1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 47 #include <linux/mlx4/device.h> 48 #include <linux/mlx4/driver.h> 49 #include <linux/mlx4/doorbell.h> 50 #include <linux/mlx4/cmd.h> 51 52 #define DRV_NAME "mlx4_core" 53 #define PFX DRV_NAME ": " 54 #define DRV_VERSION "2.2-1" 55 #define DRV_RELDATE "Feb, 2014" 56 57 #define MLX4_FS_UDP_UC_EN (1 << 1) 58 #define MLX4_FS_TCP_UC_EN (1 << 2) 59 #define MLX4_FS_NUM_OF_L2_ADDR 8 60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 61 #define MLX4_FS_NUM_MCG (1 << 17) 62 63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 64 65 struct mlx4_set_port_prio2tc_context { 66 u8 prio2tc[4]; 67 }; 68 69 struct mlx4_port_scheduler_tc_cfg_be { 70 __be16 pg; 71 __be16 bw_precentage; 72 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ 73 __be16 max_bw_value; 74 }; 75 76 struct mlx4_set_port_scheduler_context { 77 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 78 }; 79 80 enum { 81 MLX4_HCR_BASE = 0x80680, 82 MLX4_HCR_SIZE = 0x0001c, 83 MLX4_CLR_INT_SIZE = 0x00008, 84 MLX4_SLAVE_COMM_BASE = 0x0, 85 MLX4_COMM_PAGESIZE = 0x1000, 86 MLX4_CLOCK_SIZE = 0x00008 87 }; 88 89 enum { 90 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 91 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 92 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 93 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 94 MLX4_MTT_ENTRY_PER_SEG = 8, 95 }; 96 97 enum { 98 MLX4_NUM_PDS = 1 << 15 99 }; 100 101 enum { 102 MLX4_CMPT_TYPE_QP = 0, 103 MLX4_CMPT_TYPE_SRQ = 1, 104 MLX4_CMPT_TYPE_CQ = 2, 105 MLX4_CMPT_TYPE_EQ = 3, 106 MLX4_CMPT_NUM_TYPE 107 }; 108 109 enum { 110 MLX4_CMPT_SHIFT = 24, 111 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 112 }; 113 114 enum mlx4_mpt_state { 115 MLX4_MPT_DISABLED = 0, 116 MLX4_MPT_EN_HW, 117 MLX4_MPT_EN_SW 118 }; 119 120 #define MLX4_COMM_TIME 10000 121 enum { 122 MLX4_COMM_CMD_RESET, 123 MLX4_COMM_CMD_VHCR0, 124 MLX4_COMM_CMD_VHCR1, 125 MLX4_COMM_CMD_VHCR2, 126 MLX4_COMM_CMD_VHCR_EN, 127 MLX4_COMM_CMD_VHCR_POST, 128 MLX4_COMM_CMD_FLR = 254 129 }; 130 131 enum { 132 MLX4_VF_SMI_DISABLED, 133 MLX4_VF_SMI_ENABLED 134 }; 135 136 /*The flag indicates that the slave should delay the RESET cmd*/ 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 138 /*indicates how many retries will be done if we are in the middle of FLR*/ 139 #define NUM_OF_RESET_RETRIES 10 140 #define SLEEP_TIME_IN_RESET (2 * 1000) 141 enum mlx4_resource { 142 RES_QP, 143 RES_CQ, 144 RES_SRQ, 145 RES_XRCD, 146 RES_MPT, 147 RES_MTT, 148 RES_MAC, 149 RES_VLAN, 150 RES_EQ, 151 RES_COUNTER, 152 RES_FS_RULE, 153 MLX4_NUM_OF_RESOURCE_TYPE 154 }; 155 156 enum mlx4_alloc_mode { 157 RES_OP_RESERVE, 158 RES_OP_RESERVE_AND_MAP, 159 RES_OP_MAP_ICM, 160 }; 161 162 enum mlx4_res_tracker_free_type { 163 RES_TR_FREE_ALL, 164 RES_TR_FREE_SLAVES_ONLY, 165 RES_TR_FREE_STRUCTS_ONLY, 166 }; 167 168 /* 169 *Virtual HCR structures. 170 * mlx4_vhcr is the sw representation, in machine endianess 171 * 172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 173 * to FW to go through communication channel. 174 * It is big endian, and has the same structure as the physical HCR 175 * used by command interface 176 */ 177 struct mlx4_vhcr { 178 u64 in_param; 179 u64 out_param; 180 u32 in_modifier; 181 u32 errno; 182 u16 op; 183 u16 token; 184 u8 op_modifier; 185 u8 e_bit; 186 }; 187 188 struct mlx4_vhcr_cmd { 189 __be64 in_param; 190 __be32 in_modifier; 191 __be64 out_param; 192 __be16 token; 193 u16 reserved; 194 u8 status; 195 u8 flags; 196 __be16 opcode; 197 }; 198 199 struct mlx4_cmd_info { 200 u16 opcode; 201 bool has_inbox; 202 bool has_outbox; 203 bool out_is_imm; 204 bool encode_slave_id; 205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox); 207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 208 struct mlx4_cmd_mailbox *inbox, 209 struct mlx4_cmd_mailbox *outbox, 210 struct mlx4_cmd_info *cmd); 211 }; 212 213 #ifdef CONFIG_MLX4_DEBUG 214 extern int mlx4_debug_level; 215 #else /* CONFIG_MLX4_DEBUG */ 216 #define mlx4_debug_level (0) 217 #endif /* CONFIG_MLX4_DEBUG */ 218 219 #define mlx4_dbg(mdev, format, ...) \ 220 do { \ 221 if (mlx4_debug_level) \ 222 dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \ 223 ##__VA_ARGS__); \ 224 } while (0) 225 226 #define mlx4_err(mdev, format, ...) \ 227 dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__) 228 #define mlx4_info(mdev, format, ...) \ 229 dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__) 230 #define mlx4_warn(mdev, format, ...) \ 231 dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__) 232 233 extern int mlx4_log_num_mgm_entry_size; 234 extern int log_mtts_per_seg; 235 236 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 237 #define ALL_SLAVES 0xff 238 239 struct mlx4_bitmap { 240 u32 last; 241 u32 top; 242 u32 max; 243 u32 reserved_top; 244 u32 mask; 245 u32 avail; 246 spinlock_t lock; 247 unsigned long *table; 248 }; 249 250 struct mlx4_buddy { 251 unsigned long **bits; 252 unsigned int *num_free; 253 u32 max_order; 254 spinlock_t lock; 255 }; 256 257 struct mlx4_icm; 258 259 struct mlx4_icm_table { 260 u64 virt; 261 int num_icm; 262 u32 num_obj; 263 int obj_size; 264 int lowmem; 265 int coherent; 266 struct mutex mutex; 267 struct mlx4_icm **icm; 268 }; 269 270 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 271 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 272 #define MLX4_MPT_FLAG_MIO (1 << 17) 273 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 274 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 275 #define MLX4_MPT_FLAG_REGION (1 << 8) 276 277 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 278 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 279 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 280 281 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 282 283 #define MLX4_MPT_STATUS_SW 0xF0 284 #define MLX4_MPT_STATUS_HW 0x00 285 286 /* 287 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 288 */ 289 struct mlx4_mpt_entry { 290 __be32 flags; 291 __be32 qpn; 292 __be32 key; 293 __be32 pd_flags; 294 __be64 start; 295 __be64 length; 296 __be32 lkey; 297 __be32 win_cnt; 298 u8 reserved1[3]; 299 u8 mtt_rep; 300 __be64 mtt_addr; 301 __be32 mtt_sz; 302 __be32 entity_size; 303 __be32 first_byte_offset; 304 } __packed; 305 306 /* 307 * Must be packed because start is 64 bits but only aligned to 32 bits. 308 */ 309 struct mlx4_eq_context { 310 __be32 flags; 311 u16 reserved1[3]; 312 __be16 page_offset; 313 u8 log_eq_size; 314 u8 reserved2[4]; 315 u8 eq_period; 316 u8 reserved3; 317 u8 eq_max_count; 318 u8 reserved4[3]; 319 u8 intr; 320 u8 log_page_size; 321 u8 reserved5[2]; 322 u8 mtt_base_addr_h; 323 __be32 mtt_base_addr_l; 324 u32 reserved6[2]; 325 __be32 consumer_index; 326 __be32 producer_index; 327 u32 reserved7[4]; 328 }; 329 330 struct mlx4_cq_context { 331 __be32 flags; 332 u16 reserved1[3]; 333 __be16 page_offset; 334 __be32 logsize_usrpage; 335 __be16 cq_period; 336 __be16 cq_max_count; 337 u8 reserved2[3]; 338 u8 comp_eqn; 339 u8 log_page_size; 340 u8 reserved3[2]; 341 u8 mtt_base_addr_h; 342 __be32 mtt_base_addr_l; 343 __be32 last_notified_index; 344 __be32 solicit_producer_index; 345 __be32 consumer_index; 346 __be32 producer_index; 347 u32 reserved4[2]; 348 __be64 db_rec_addr; 349 }; 350 351 struct mlx4_srq_context { 352 __be32 state_logsize_srqn; 353 u8 logstride; 354 u8 reserved1; 355 __be16 xrcd; 356 __be32 pg_offset_cqn; 357 u32 reserved2; 358 u8 log_page_size; 359 u8 reserved3[2]; 360 u8 mtt_base_addr_h; 361 __be32 mtt_base_addr_l; 362 __be32 pd; 363 __be16 limit_watermark; 364 __be16 wqe_cnt; 365 u16 reserved4; 366 __be16 wqe_counter; 367 u32 reserved5; 368 __be64 db_rec_addr; 369 }; 370 371 struct mlx4_eq { 372 struct mlx4_dev *dev; 373 void __iomem *doorbell; 374 int eqn; 375 u32 cons_index; 376 u16 irq; 377 u16 have_irq; 378 int nent; 379 struct mlx4_buf_list *page_list; 380 struct mlx4_mtt mtt; 381 }; 382 383 struct mlx4_slave_eqe { 384 u8 type; 385 u8 port; 386 u32 param; 387 }; 388 389 struct mlx4_slave_event_eq_info { 390 int eqn; 391 u16 token; 392 }; 393 394 struct mlx4_profile { 395 int num_qp; 396 int rdmarc_per_qp; 397 int num_srq; 398 int num_cq; 399 int num_mcg; 400 int num_mpt; 401 unsigned num_mtt; 402 }; 403 404 struct mlx4_fw { 405 u64 clr_int_base; 406 u64 catas_offset; 407 u64 comm_base; 408 u64 clock_offset; 409 struct mlx4_icm *fw_icm; 410 struct mlx4_icm *aux_icm; 411 u32 catas_size; 412 u16 fw_pages; 413 u8 clr_int_bar; 414 u8 catas_bar; 415 u8 comm_bar; 416 u8 clock_bar; 417 }; 418 419 struct mlx4_comm { 420 u32 slave_write; 421 u32 slave_read; 422 }; 423 424 enum { 425 MLX4_MCAST_CONFIG = 0, 426 MLX4_MCAST_DISABLE = 1, 427 MLX4_MCAST_ENABLE = 2, 428 }; 429 430 #define VLAN_FLTR_SIZE 128 431 432 struct mlx4_vlan_fltr { 433 __be32 entry[VLAN_FLTR_SIZE]; 434 }; 435 436 struct mlx4_mcast_entry { 437 struct list_head list; 438 u64 addr; 439 }; 440 441 struct mlx4_promisc_qp { 442 struct list_head list; 443 u32 qpn; 444 }; 445 446 struct mlx4_steer_index { 447 struct list_head list; 448 unsigned int index; 449 struct list_head duplicates; 450 }; 451 452 #define MLX4_EVENT_TYPES_NUM 64 453 454 struct mlx4_slave_state { 455 u8 comm_toggle; 456 u8 last_cmd; 457 u8 init_port_mask; 458 bool active; 459 bool old_vlan_api; 460 u8 function; 461 dma_addr_t vhcr_dma; 462 u16 mtu[MLX4_MAX_PORTS + 1]; 463 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 464 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 465 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 466 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 467 /* event type to eq number lookup */ 468 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 469 u16 eq_pi; 470 u16 eq_ci; 471 spinlock_t lock; 472 /*initialized via the kzalloc*/ 473 u8 is_slave_going_down; 474 u32 cookie; 475 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 476 }; 477 478 #define MLX4_VGT 4095 479 #define NO_INDX (-1) 480 481 struct mlx4_vport_state { 482 u64 mac; 483 u16 default_vlan; 484 u8 default_qos; 485 u32 tx_rate; 486 bool spoofchk; 487 u32 link_state; 488 }; 489 490 struct mlx4_vf_admin_state { 491 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 492 u8 enable_smi[MLX4_MAX_PORTS + 1]; 493 }; 494 495 struct mlx4_vport_oper_state { 496 struct mlx4_vport_state state; 497 int mac_idx; 498 int vlan_idx; 499 }; 500 501 struct mlx4_vf_oper_state { 502 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 503 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 504 }; 505 506 struct slave_list { 507 struct mutex mutex; 508 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 509 }; 510 511 struct resource_allocator { 512 spinlock_t alloc_lock; /* protect quotas */ 513 union { 514 int res_reserved; 515 int res_port_rsvd[MLX4_MAX_PORTS]; 516 }; 517 union { 518 int res_free; 519 int res_port_free[MLX4_MAX_PORTS]; 520 }; 521 int *quota; 522 int *allocated; 523 int *guaranteed; 524 }; 525 526 struct mlx4_resource_tracker { 527 spinlock_t lock; 528 /* tree for each resources */ 529 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 530 /* num_of_slave's lists, one per slave */ 531 struct slave_list *slave_list; 532 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 533 }; 534 535 #define SLAVE_EVENT_EQ_SIZE 128 536 struct mlx4_slave_event_eq { 537 u32 eqn; 538 u32 cons; 539 u32 prod; 540 spinlock_t event_lock; 541 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 542 }; 543 544 struct mlx4_master_qp0_state { 545 int proxy_qp0_active; 546 int qp0_active; 547 int port_active; 548 }; 549 550 struct mlx4_mfunc_master_ctx { 551 struct mlx4_slave_state *slave_state; 552 struct mlx4_vf_admin_state *vf_admin; 553 struct mlx4_vf_oper_state *vf_oper; 554 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 555 int init_port_ref[MLX4_MAX_PORTS + 1]; 556 u16 max_mtu[MLX4_MAX_PORTS + 1]; 557 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 558 struct mlx4_resource_tracker res_tracker; 559 struct workqueue_struct *comm_wq; 560 struct work_struct comm_work; 561 struct work_struct slave_event_work; 562 struct work_struct slave_flr_event_work; 563 spinlock_t slave_state_lock; 564 __be32 comm_arm_bit_vector[4]; 565 struct mlx4_eqe cmd_eqe; 566 struct mlx4_slave_event_eq slave_eq; 567 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 568 }; 569 570 struct mlx4_mfunc { 571 struct mlx4_comm __iomem *comm; 572 struct mlx4_vhcr_cmd *vhcr; 573 dma_addr_t vhcr_dma; 574 575 struct mlx4_mfunc_master_ctx master; 576 }; 577 578 #define MGM_QPN_MASK 0x00FFFFFF 579 #define MGM_BLCK_LB_BIT 30 580 581 struct mlx4_mgm { 582 __be32 next_gid_index; 583 __be32 members_count; 584 u32 reserved[2]; 585 u8 gid[16]; 586 __be32 qp[MLX4_MAX_QP_PER_MGM]; 587 }; 588 589 struct mlx4_cmd { 590 struct pci_pool *pool; 591 void __iomem *hcr; 592 struct mutex hcr_mutex; 593 struct mutex slave_cmd_mutex; 594 struct semaphore poll_sem; 595 struct semaphore event_sem; 596 int max_cmds; 597 spinlock_t context_lock; 598 int free_head; 599 struct mlx4_cmd_context *context; 600 u16 token_mask; 601 u8 use_events; 602 u8 toggle; 603 u8 comm_toggle; 604 }; 605 606 enum { 607 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 608 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 609 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 610 }; 611 struct mlx4_vf_immed_vlan_work { 612 struct work_struct work; 613 struct mlx4_priv *priv; 614 int flags; 615 int slave; 616 int vlan_ix; 617 int orig_vlan_ix; 618 u8 port; 619 u8 qos; 620 u16 vlan_id; 621 u16 orig_vlan_id; 622 }; 623 624 625 struct mlx4_uar_table { 626 struct mlx4_bitmap bitmap; 627 }; 628 629 struct mlx4_mr_table { 630 struct mlx4_bitmap mpt_bitmap; 631 struct mlx4_buddy mtt_buddy; 632 u64 mtt_base; 633 u64 mpt_base; 634 struct mlx4_icm_table mtt_table; 635 struct mlx4_icm_table dmpt_table; 636 }; 637 638 struct mlx4_cq_table { 639 struct mlx4_bitmap bitmap; 640 spinlock_t lock; 641 struct radix_tree_root tree; 642 struct mlx4_icm_table table; 643 struct mlx4_icm_table cmpt_table; 644 }; 645 646 struct mlx4_eq_table { 647 struct mlx4_bitmap bitmap; 648 char *irq_names; 649 void __iomem *clr_int; 650 void __iomem **uar_map; 651 u32 clr_mask; 652 struct mlx4_eq *eq; 653 struct mlx4_icm_table table; 654 struct mlx4_icm_table cmpt_table; 655 int have_irq; 656 u8 inta_pin; 657 }; 658 659 struct mlx4_srq_table { 660 struct mlx4_bitmap bitmap; 661 spinlock_t lock; 662 struct radix_tree_root tree; 663 struct mlx4_icm_table table; 664 struct mlx4_icm_table cmpt_table; 665 }; 666 667 struct mlx4_qp_table { 668 struct mlx4_bitmap bitmap; 669 u32 rdmarc_base; 670 int rdmarc_shift; 671 spinlock_t lock; 672 struct mlx4_icm_table qp_table; 673 struct mlx4_icm_table auxc_table; 674 struct mlx4_icm_table altc_table; 675 struct mlx4_icm_table rdmarc_table; 676 struct mlx4_icm_table cmpt_table; 677 }; 678 679 struct mlx4_mcg_table { 680 struct mutex mutex; 681 struct mlx4_bitmap bitmap; 682 struct mlx4_icm_table table; 683 }; 684 685 struct mlx4_catas_err { 686 u32 __iomem *map; 687 struct timer_list timer; 688 struct list_head list; 689 }; 690 691 #define MLX4_MAX_MAC_NUM 128 692 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 693 694 struct mlx4_mac_table { 695 __be64 entries[MLX4_MAX_MAC_NUM]; 696 int refs[MLX4_MAX_MAC_NUM]; 697 struct mutex mutex; 698 int total; 699 int max; 700 }; 701 702 #define MLX4_ROCE_GID_ENTRY_SIZE 16 703 704 struct mlx4_roce_gid_entry { 705 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 706 }; 707 708 struct mlx4_roce_gid_table { 709 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 710 struct mutex mutex; 711 }; 712 713 #define MLX4_MAX_VLAN_NUM 128 714 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 715 716 struct mlx4_vlan_table { 717 __be32 entries[MLX4_MAX_VLAN_NUM]; 718 int refs[MLX4_MAX_VLAN_NUM]; 719 struct mutex mutex; 720 int total; 721 int max; 722 }; 723 724 #define SET_PORT_GEN_ALL_VALID 0x7 725 #define SET_PORT_PROMISC_SHIFT 31 726 #define SET_PORT_MC_PROMISC_SHIFT 30 727 728 enum { 729 MCAST_DIRECT_ONLY = 0, 730 MCAST_DIRECT = 1, 731 MCAST_DEFAULT = 2 732 }; 733 734 735 struct mlx4_set_port_general_context { 736 u8 reserved[3]; 737 u8 flags; 738 u16 reserved2; 739 __be16 mtu; 740 u8 pptx; 741 u8 pfctx; 742 u16 reserved3; 743 u8 pprx; 744 u8 pfcrx; 745 u16 reserved4; 746 }; 747 748 struct mlx4_set_port_rqp_calc_context { 749 __be32 base_qpn; 750 u8 rererved; 751 u8 n_mac; 752 u8 n_vlan; 753 u8 n_prio; 754 u8 reserved2[3]; 755 u8 mac_miss; 756 u8 intra_no_vlan; 757 u8 no_vlan; 758 u8 intra_vlan_miss; 759 u8 vlan_miss; 760 u8 reserved3[3]; 761 u8 no_vlan_prio; 762 __be32 promisc; 763 __be32 mcast; 764 }; 765 766 struct mlx4_port_info { 767 struct mlx4_dev *dev; 768 int port; 769 char dev_name[16]; 770 struct device_attribute port_attr; 771 enum mlx4_port_type tmp_type; 772 char dev_mtu_name[16]; 773 struct device_attribute port_mtu_attr; 774 struct mlx4_mac_table mac_table; 775 struct mlx4_vlan_table vlan_table; 776 struct mlx4_roce_gid_table gid_table; 777 int base_qpn; 778 }; 779 780 struct mlx4_sense { 781 struct mlx4_dev *dev; 782 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 783 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 784 struct delayed_work sense_poll; 785 }; 786 787 struct mlx4_msix_ctl { 788 u64 pool_bm; 789 struct mutex pool_lock; 790 }; 791 792 struct mlx4_steer { 793 struct list_head promisc_qps[MLX4_NUM_STEERS]; 794 struct list_head steer_entries[MLX4_NUM_STEERS]; 795 }; 796 797 enum { 798 MLX4_PCI_DEV_IS_VF = 1 << 0, 799 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 800 }; 801 802 enum { 803 MLX4_NO_RR = 0, 804 MLX4_USE_RR = 1, 805 }; 806 807 struct mlx4_priv { 808 struct mlx4_dev dev; 809 810 struct list_head dev_list; 811 struct list_head ctx_list; 812 spinlock_t ctx_lock; 813 814 int pci_dev_data; 815 int removed; 816 817 struct list_head pgdir_list; 818 struct mutex pgdir_mutex; 819 820 struct mlx4_fw fw; 821 struct mlx4_cmd cmd; 822 struct mlx4_mfunc mfunc; 823 824 struct mlx4_bitmap pd_bitmap; 825 struct mlx4_bitmap xrcd_bitmap; 826 struct mlx4_uar_table uar_table; 827 struct mlx4_mr_table mr_table; 828 struct mlx4_cq_table cq_table; 829 struct mlx4_eq_table eq_table; 830 struct mlx4_srq_table srq_table; 831 struct mlx4_qp_table qp_table; 832 struct mlx4_mcg_table mcg_table; 833 struct mlx4_bitmap counters_bitmap; 834 835 struct mlx4_catas_err catas_err; 836 837 void __iomem *clr_base; 838 839 struct mlx4_uar driver_uar; 840 void __iomem *kar; 841 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 842 struct mlx4_sense sense; 843 struct mutex port_mutex; 844 struct mlx4_msix_ctl msix_ctl; 845 struct mlx4_steer *steer; 846 struct list_head bf_list; 847 struct mutex bf_mutex; 848 struct io_mapping *bf_mapping; 849 void __iomem *clock_mapping; 850 int reserved_mtts; 851 int fs_hash_mode; 852 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 853 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 854 855 atomic_t opreq_count; 856 struct work_struct opreq_task; 857 }; 858 859 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 860 { 861 return container_of(dev, struct mlx4_priv, dev); 862 } 863 864 #define MLX4_SENSE_RANGE (HZ * 3) 865 866 extern struct workqueue_struct *mlx4_wq; 867 868 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 869 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 870 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 871 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 872 int use_rr); 873 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 874 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 875 u32 reserved_bot, u32 resetrved_top); 876 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 877 878 int mlx4_reset(struct mlx4_dev *dev); 879 880 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 881 void mlx4_free_eq_table(struct mlx4_dev *dev); 882 883 int mlx4_init_pd_table(struct mlx4_dev *dev); 884 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 885 int mlx4_init_uar_table(struct mlx4_dev *dev); 886 int mlx4_init_mr_table(struct mlx4_dev *dev); 887 int mlx4_init_eq_table(struct mlx4_dev *dev); 888 int mlx4_init_cq_table(struct mlx4_dev *dev); 889 int mlx4_init_qp_table(struct mlx4_dev *dev); 890 int mlx4_init_srq_table(struct mlx4_dev *dev); 891 int mlx4_init_mcg_table(struct mlx4_dev *dev); 892 893 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 894 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 895 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 896 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 897 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 898 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 899 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 900 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 901 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 902 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 903 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 904 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 905 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 906 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 907 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 908 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 909 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 910 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 911 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 912 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 913 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 914 915 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 916 struct mlx4_vhcr *vhcr, 917 struct mlx4_cmd_mailbox *inbox, 918 struct mlx4_cmd_mailbox *outbox, 919 struct mlx4_cmd_info *cmd); 920 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 921 struct mlx4_vhcr *vhcr, 922 struct mlx4_cmd_mailbox *inbox, 923 struct mlx4_cmd_mailbox *outbox, 924 struct mlx4_cmd_info *cmd); 925 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 926 struct mlx4_vhcr *vhcr, 927 struct mlx4_cmd_mailbox *inbox, 928 struct mlx4_cmd_mailbox *outbox, 929 struct mlx4_cmd_info *cmd); 930 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 931 struct mlx4_vhcr *vhcr, 932 struct mlx4_cmd_mailbox *inbox, 933 struct mlx4_cmd_mailbox *outbox, 934 struct mlx4_cmd_info *cmd); 935 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 936 struct mlx4_vhcr *vhcr, 937 struct mlx4_cmd_mailbox *inbox, 938 struct mlx4_cmd_mailbox *outbox, 939 struct mlx4_cmd_info *cmd); 940 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 941 struct mlx4_vhcr *vhcr, 942 struct mlx4_cmd_mailbox *inbox, 943 struct mlx4_cmd_mailbox *outbox, 944 struct mlx4_cmd_info *cmd); 945 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 946 struct mlx4_vhcr *vhcr, 947 struct mlx4_cmd_mailbox *inbox, 948 struct mlx4_cmd_mailbox *outbox, 949 struct mlx4_cmd_info *cmd); 950 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 951 int *base); 952 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 953 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 954 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 955 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 956 int start_index, int npages, u64 *page_list); 957 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 958 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 959 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 960 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 961 962 void mlx4_start_catas_poll(struct mlx4_dev *dev); 963 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 964 void mlx4_catas_init(void); 965 int mlx4_restart_one(struct pci_dev *pdev); 966 int mlx4_register_device(struct mlx4_dev *dev); 967 void mlx4_unregister_device(struct mlx4_dev *dev); 968 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 969 unsigned long param); 970 971 struct mlx4_dev_cap; 972 struct mlx4_init_hca_param; 973 974 u64 mlx4_make_profile(struct mlx4_dev *dev, 975 struct mlx4_profile *request, 976 struct mlx4_dev_cap *dev_cap, 977 struct mlx4_init_hca_param *init_hca); 978 void mlx4_master_comm_channel(struct work_struct *work); 979 void mlx4_gen_slave_eqe(struct work_struct *work); 980 void mlx4_master_handle_slave_flr(struct work_struct *work); 981 982 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 983 struct mlx4_vhcr *vhcr, 984 struct mlx4_cmd_mailbox *inbox, 985 struct mlx4_cmd_mailbox *outbox, 986 struct mlx4_cmd_info *cmd); 987 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 988 struct mlx4_vhcr *vhcr, 989 struct mlx4_cmd_mailbox *inbox, 990 struct mlx4_cmd_mailbox *outbox, 991 struct mlx4_cmd_info *cmd); 992 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 993 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 994 struct mlx4_cmd_mailbox *outbox, 995 struct mlx4_cmd_info *cmd); 996 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 997 struct mlx4_vhcr *vhcr, 998 struct mlx4_cmd_mailbox *inbox, 999 struct mlx4_cmd_mailbox *outbox, 1000 struct mlx4_cmd_info *cmd); 1001 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1002 struct mlx4_vhcr *vhcr, 1003 struct mlx4_cmd_mailbox *inbox, 1004 struct mlx4_cmd_mailbox *outbox, 1005 struct mlx4_cmd_info *cmd); 1006 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1007 struct mlx4_vhcr *vhcr, 1008 struct mlx4_cmd_mailbox *inbox, 1009 struct mlx4_cmd_mailbox *outbox, 1010 struct mlx4_cmd_info *cmd); 1011 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1012 struct mlx4_vhcr *vhcr, 1013 struct mlx4_cmd_mailbox *inbox, 1014 struct mlx4_cmd_mailbox *outbox, 1015 struct mlx4_cmd_info *cmd); 1016 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1017 struct mlx4_vhcr *vhcr, 1018 struct mlx4_cmd_mailbox *inbox, 1019 struct mlx4_cmd_mailbox *outbox, 1020 struct mlx4_cmd_info *cmd); 1021 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1022 struct mlx4_vhcr *vhcr, 1023 struct mlx4_cmd_mailbox *inbox, 1024 struct mlx4_cmd_mailbox *outbox, 1025 struct mlx4_cmd_info *cmd); 1026 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1027 struct mlx4_vhcr *vhcr, 1028 struct mlx4_cmd_mailbox *inbox, 1029 struct mlx4_cmd_mailbox *outbox, 1030 struct mlx4_cmd_info *cmd); 1031 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1032 struct mlx4_vhcr *vhcr, 1033 struct mlx4_cmd_mailbox *inbox, 1034 struct mlx4_cmd_mailbox *outbox, 1035 struct mlx4_cmd_info *cmd); 1036 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1037 struct mlx4_vhcr *vhcr, 1038 struct mlx4_cmd_mailbox *inbox, 1039 struct mlx4_cmd_mailbox *outbox, 1040 struct mlx4_cmd_info *cmd); 1041 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1047 struct mlx4_vhcr *vhcr, 1048 struct mlx4_cmd_mailbox *inbox, 1049 struct mlx4_cmd_mailbox *outbox, 1050 struct mlx4_cmd_info *cmd); 1051 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1077 struct mlx4_vhcr *vhcr, 1078 struct mlx4_cmd_mailbox *inbox, 1079 struct mlx4_cmd_mailbox *outbox, 1080 struct mlx4_cmd_info *cmd); 1081 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1082 struct mlx4_vhcr *vhcr, 1083 struct mlx4_cmd_mailbox *inbox, 1084 struct mlx4_cmd_mailbox *outbox, 1085 struct mlx4_cmd_info *cmd); 1086 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1087 struct mlx4_vhcr *vhcr, 1088 struct mlx4_cmd_mailbox *inbox, 1089 struct mlx4_cmd_mailbox *outbox, 1090 struct mlx4_cmd_info *cmd); 1091 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1092 struct mlx4_vhcr *vhcr, 1093 struct mlx4_cmd_mailbox *inbox, 1094 struct mlx4_cmd_mailbox *outbox, 1095 struct mlx4_cmd_info *cmd); 1096 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1097 struct mlx4_vhcr *vhcr, 1098 struct mlx4_cmd_mailbox *inbox, 1099 struct mlx4_cmd_mailbox *outbox, 1100 struct mlx4_cmd_info *cmd); 1101 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1102 struct mlx4_vhcr *vhcr, 1103 struct mlx4_cmd_mailbox *inbox, 1104 struct mlx4_cmd_mailbox *outbox, 1105 struct mlx4_cmd_info *cmd); 1106 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1107 struct mlx4_vhcr *vhcr, 1108 struct mlx4_cmd_mailbox *inbox, 1109 struct mlx4_cmd_mailbox *outbox, 1110 struct mlx4_cmd_info *cmd); 1111 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1112 struct mlx4_vhcr *vhcr, 1113 struct mlx4_cmd_mailbox *inbox, 1114 struct mlx4_cmd_mailbox *outbox, 1115 struct mlx4_cmd_info *cmd); 1116 1117 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1118 1119 int mlx4_cmd_init(struct mlx4_dev *dev); 1120 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 1121 int mlx4_multi_func_init(struct mlx4_dev *dev); 1122 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1123 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1124 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1125 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1126 1127 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1128 unsigned long timeout); 1129 1130 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1131 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1132 1133 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1134 1135 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1136 1137 void mlx4_handle_catas_err(struct mlx4_dev *dev); 1138 1139 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1140 enum mlx4_port_type *type); 1141 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1142 enum mlx4_port_type *stype, 1143 enum mlx4_port_type *defaults); 1144 void mlx4_start_sense(struct mlx4_dev *dev); 1145 void mlx4_stop_sense(struct mlx4_dev *dev); 1146 void mlx4_sense_init(struct mlx4_dev *dev); 1147 int mlx4_check_port_params(struct mlx4_dev *dev, 1148 enum mlx4_port_type *port_type); 1149 int mlx4_change_port_types(struct mlx4_dev *dev, 1150 enum mlx4_port_type *port_types); 1151 1152 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1153 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1154 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1155 struct mlx4_roce_gid_table *table); 1156 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1157 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1158 1159 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1160 /* resource tracker functions*/ 1161 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1162 enum mlx4_resource resource_type, 1163 u64 resource_id, int *slave); 1164 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1165 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1166 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1167 1168 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1169 enum mlx4_res_tracker_free_type type); 1170 1171 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1172 struct mlx4_vhcr *vhcr, 1173 struct mlx4_cmd_mailbox *inbox, 1174 struct mlx4_cmd_mailbox *outbox, 1175 struct mlx4_cmd_info *cmd); 1176 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1177 struct mlx4_vhcr *vhcr, 1178 struct mlx4_cmd_mailbox *inbox, 1179 struct mlx4_cmd_mailbox *outbox, 1180 struct mlx4_cmd_info *cmd); 1181 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1182 struct mlx4_vhcr *vhcr, 1183 struct mlx4_cmd_mailbox *inbox, 1184 struct mlx4_cmd_mailbox *outbox, 1185 struct mlx4_cmd_info *cmd); 1186 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1187 struct mlx4_vhcr *vhcr, 1188 struct mlx4_cmd_mailbox *inbox, 1189 struct mlx4_cmd_mailbox *outbox, 1190 struct mlx4_cmd_info *cmd); 1191 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1192 struct mlx4_vhcr *vhcr, 1193 struct mlx4_cmd_mailbox *inbox, 1194 struct mlx4_cmd_mailbox *outbox, 1195 struct mlx4_cmd_info *cmd); 1196 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1197 struct mlx4_vhcr *vhcr, 1198 struct mlx4_cmd_mailbox *inbox, 1199 struct mlx4_cmd_mailbox *outbox, 1200 struct mlx4_cmd_info *cmd); 1201 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1202 1203 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1204 int *gid_tbl_len, int *pkey_tbl_len); 1205 1206 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1207 struct mlx4_vhcr *vhcr, 1208 struct mlx4_cmd_mailbox *inbox, 1209 struct mlx4_cmd_mailbox *outbox, 1210 struct mlx4_cmd_info *cmd); 1211 1212 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1213 struct mlx4_vhcr *vhcr, 1214 struct mlx4_cmd_mailbox *inbox, 1215 struct mlx4_cmd_mailbox *outbox, 1216 struct mlx4_cmd_info *cmd); 1217 1218 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1219 struct mlx4_vhcr *vhcr, 1220 struct mlx4_cmd_mailbox *inbox, 1221 struct mlx4_cmd_mailbox *outbox, 1222 struct mlx4_cmd_info *cmd); 1223 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1224 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1225 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1226 int block_mcast_loopback, enum mlx4_protocol prot, 1227 enum mlx4_steer_type steer); 1228 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1229 u8 gid[16], u8 port, 1230 int block_mcast_loopback, 1231 enum mlx4_protocol prot, u64 *reg_id); 1232 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1233 struct mlx4_vhcr *vhcr, 1234 struct mlx4_cmd_mailbox *inbox, 1235 struct mlx4_cmd_mailbox *outbox, 1236 struct mlx4_cmd_info *cmd); 1237 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1238 struct mlx4_vhcr *vhcr, 1239 struct mlx4_cmd_mailbox *inbox, 1240 struct mlx4_cmd_mailbox *outbox, 1241 struct mlx4_cmd_info *cmd); 1242 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1243 int port, void *buf); 1244 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1245 struct mlx4_cmd_mailbox *outbox); 1246 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1247 struct mlx4_vhcr *vhcr, 1248 struct mlx4_cmd_mailbox *inbox, 1249 struct mlx4_cmd_mailbox *outbox, 1250 struct mlx4_cmd_info *cmd); 1251 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1252 struct mlx4_vhcr *vhcr, 1253 struct mlx4_cmd_mailbox *inbox, 1254 struct mlx4_cmd_mailbox *outbox, 1255 struct mlx4_cmd_info *cmd); 1256 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1257 struct mlx4_vhcr *vhcr, 1258 struct mlx4_cmd_mailbox *inbox, 1259 struct mlx4_cmd_mailbox *outbox, 1260 struct mlx4_cmd_info *cmd); 1261 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1262 struct mlx4_vhcr *vhcr, 1263 struct mlx4_cmd_mailbox *inbox, 1264 struct mlx4_cmd_mailbox *outbox, 1265 struct mlx4_cmd_info *cmd); 1266 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1267 struct mlx4_vhcr *vhcr, 1268 struct mlx4_cmd_mailbox *inbox, 1269 struct mlx4_cmd_mailbox *outbox, 1270 struct mlx4_cmd_info *cmd); 1271 1272 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1273 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1274 1275 static inline void set_param_l(u64 *arg, u32 val) 1276 { 1277 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1278 } 1279 1280 static inline void set_param_h(u64 *arg, u32 val) 1281 { 1282 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1283 } 1284 1285 static inline u32 get_param_l(u64 *arg) 1286 { 1287 return (u32) (*arg & 0xffffffff); 1288 } 1289 1290 static inline u32 get_param_h(u64 *arg) 1291 { 1292 return (u32)(*arg >> 32); 1293 } 1294 1295 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1296 { 1297 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1298 } 1299 1300 #define NOT_MASKED_PD_BITS 17 1301 1302 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1303 1304 void mlx4_init_quotas(struct mlx4_dev *dev); 1305 1306 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1307 /* Returns the VF index of slave */ 1308 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1309 1310 #endif /* MLX4_H */ 1311