1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 49 #include <linux/mlx4/device.h> 50 #include <linux/mlx4/driver.h> 51 #include <linux/mlx4/doorbell.h> 52 #include <linux/mlx4/cmd.h> 53 #include "fw_qos.h" 54 55 #define DRV_NAME "mlx4_core" 56 #define PFX DRV_NAME ": " 57 #define DRV_VERSION "2.2-1" 58 #define DRV_RELDATE "Feb, 2014" 59 60 #define MLX4_FS_UDP_UC_EN (1 << 1) 61 #define MLX4_FS_TCP_UC_EN (1 << 2) 62 #define MLX4_FS_NUM_OF_L2_ADDR 8 63 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 64 #define MLX4_FS_NUM_MCG (1 << 17) 65 66 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 67 68 enum { 69 MLX4_HCR_BASE = 0x80680, 70 MLX4_HCR_SIZE = 0x0001c, 71 MLX4_CLR_INT_SIZE = 0x00008, 72 MLX4_SLAVE_COMM_BASE = 0x0, 73 MLX4_COMM_PAGESIZE = 0x1000, 74 MLX4_CLOCK_SIZE = 0x00008, 75 MLX4_COMM_CHAN_CAPS = 0x8, 76 MLX4_COMM_CHAN_FLAGS = 0xc 77 }; 78 79 enum { 80 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 81 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 82 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 83 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 84 MLX4_MTT_ENTRY_PER_SEG = 8, 85 }; 86 87 enum { 88 MLX4_NUM_PDS = 1 << 15 89 }; 90 91 enum { 92 MLX4_CMPT_TYPE_QP = 0, 93 MLX4_CMPT_TYPE_SRQ = 1, 94 MLX4_CMPT_TYPE_CQ = 2, 95 MLX4_CMPT_TYPE_EQ = 3, 96 MLX4_CMPT_NUM_TYPE 97 }; 98 99 enum { 100 MLX4_CMPT_SHIFT = 24, 101 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 102 }; 103 104 enum mlx4_mpt_state { 105 MLX4_MPT_DISABLED = 0, 106 MLX4_MPT_EN_HW, 107 MLX4_MPT_EN_SW 108 }; 109 110 #define MLX4_COMM_TIME 10000 111 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 112 #define MLX4_COMM_CMD_NA_OP 0x0 113 114 115 enum { 116 MLX4_COMM_CMD_RESET, 117 MLX4_COMM_CMD_VHCR0, 118 MLX4_COMM_CMD_VHCR1, 119 MLX4_COMM_CMD_VHCR2, 120 MLX4_COMM_CMD_VHCR_EN, 121 MLX4_COMM_CMD_VHCR_POST, 122 MLX4_COMM_CMD_FLR = 254 123 }; 124 125 enum { 126 MLX4_VF_SMI_DISABLED, 127 MLX4_VF_SMI_ENABLED 128 }; 129 130 /*The flag indicates that the slave should delay the RESET cmd*/ 131 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 132 /*indicates how many retries will be done if we are in the middle of FLR*/ 133 #define NUM_OF_RESET_RETRIES 10 134 #define SLEEP_TIME_IN_RESET (2 * 1000) 135 enum mlx4_resource { 136 RES_QP, 137 RES_CQ, 138 RES_SRQ, 139 RES_XRCD, 140 RES_MPT, 141 RES_MTT, 142 RES_MAC, 143 RES_VLAN, 144 RES_EQ, 145 RES_COUNTER, 146 RES_FS_RULE, 147 MLX4_NUM_OF_RESOURCE_TYPE 148 }; 149 150 enum mlx4_alloc_mode { 151 RES_OP_RESERVE, 152 RES_OP_RESERVE_AND_MAP, 153 RES_OP_MAP_ICM, 154 }; 155 156 enum mlx4_res_tracker_free_type { 157 RES_TR_FREE_ALL, 158 RES_TR_FREE_SLAVES_ONLY, 159 RES_TR_FREE_STRUCTS_ONLY, 160 }; 161 162 /* 163 *Virtual HCR structures. 164 * mlx4_vhcr is the sw representation, in machine endianness 165 * 166 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 167 * to FW to go through communication channel. 168 * It is big endian, and has the same structure as the physical HCR 169 * used by command interface 170 */ 171 struct mlx4_vhcr { 172 u64 in_param; 173 u64 out_param; 174 u32 in_modifier; 175 u32 errno; 176 u16 op; 177 u16 token; 178 u8 op_modifier; 179 u8 e_bit; 180 }; 181 182 struct mlx4_vhcr_cmd { 183 __be64 in_param; 184 __be32 in_modifier; 185 u32 reserved1; 186 __be64 out_param; 187 __be16 token; 188 u16 reserved; 189 u8 status; 190 u8 flags; 191 __be16 opcode; 192 }; 193 194 struct mlx4_cmd_info { 195 u16 opcode; 196 bool has_inbox; 197 bool has_outbox; 198 bool out_is_imm; 199 bool encode_slave_id; 200 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 201 struct mlx4_cmd_mailbox *inbox); 202 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 203 struct mlx4_cmd_mailbox *inbox, 204 struct mlx4_cmd_mailbox *outbox, 205 struct mlx4_cmd_info *cmd); 206 }; 207 208 #ifdef CONFIG_MLX4_DEBUG 209 extern int mlx4_debug_level; 210 #else /* CONFIG_MLX4_DEBUG */ 211 #define mlx4_debug_level (0) 212 #endif /* CONFIG_MLX4_DEBUG */ 213 214 #define mlx4_dbg(mdev, format, ...) \ 215 do { \ 216 if (mlx4_debug_level) \ 217 dev_printk(KERN_DEBUG, \ 218 &(mdev)->persist->pdev->dev, format, \ 219 ##__VA_ARGS__); \ 220 } while (0) 221 222 #define mlx4_err(mdev, format, ...) \ 223 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 224 #define mlx4_info(mdev, format, ...) \ 225 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 226 #define mlx4_warn(mdev, format, ...) \ 227 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 228 229 extern int mlx4_log_num_mgm_entry_size; 230 extern int log_mtts_per_seg; 231 extern int mlx4_internal_err_reset; 232 233 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 234 MLX4_MFUNC_MAX)) 235 #define ALL_SLAVES 0xff 236 237 struct mlx4_bitmap { 238 u32 last; 239 u32 top; 240 u32 max; 241 u32 reserved_top; 242 u32 mask; 243 u32 avail; 244 u32 effective_len; 245 spinlock_t lock; 246 unsigned long *table; 247 }; 248 249 struct mlx4_buddy { 250 unsigned long **bits; 251 unsigned int *num_free; 252 u32 max_order; 253 spinlock_t lock; 254 }; 255 256 struct mlx4_icm; 257 258 struct mlx4_icm_table { 259 u64 virt; 260 int num_icm; 261 u32 num_obj; 262 int obj_size; 263 int lowmem; 264 int coherent; 265 struct mutex mutex; 266 struct mlx4_icm **icm; 267 }; 268 269 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 270 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 271 #define MLX4_MPT_FLAG_MIO (1 << 17) 272 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 273 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 274 #define MLX4_MPT_FLAG_REGION (1 << 8) 275 276 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 277 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 278 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 279 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 280 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 281 282 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 283 284 #define MLX4_MPT_STATUS_SW 0xF0 285 #define MLX4_MPT_STATUS_HW 0x00 286 287 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 288 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 289 290 /* 291 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 292 */ 293 struct mlx4_mpt_entry { 294 __be32 flags; 295 __be32 qpn; 296 __be32 key; 297 __be32 pd_flags; 298 __be64 start; 299 __be64 length; 300 __be32 lkey; 301 __be32 win_cnt; 302 u8 reserved1[3]; 303 u8 mtt_rep; 304 __be64 mtt_addr; 305 __be32 mtt_sz; 306 __be32 entity_size; 307 __be32 first_byte_offset; 308 } __packed; 309 310 /* 311 * Must be packed because start is 64 bits but only aligned to 32 bits. 312 */ 313 struct mlx4_eq_context { 314 __be32 flags; 315 u16 reserved1[3]; 316 __be16 page_offset; 317 u8 log_eq_size; 318 u8 reserved2[4]; 319 u8 eq_period; 320 u8 reserved3; 321 u8 eq_max_count; 322 u8 reserved4[3]; 323 u8 intr; 324 u8 log_page_size; 325 u8 reserved5[2]; 326 u8 mtt_base_addr_h; 327 __be32 mtt_base_addr_l; 328 u32 reserved6[2]; 329 __be32 consumer_index; 330 __be32 producer_index; 331 u32 reserved7[4]; 332 }; 333 334 struct mlx4_cq_context { 335 __be32 flags; 336 u16 reserved1[3]; 337 __be16 page_offset; 338 __be32 logsize_usrpage; 339 __be16 cq_period; 340 __be16 cq_max_count; 341 u8 reserved2[3]; 342 u8 comp_eqn; 343 u8 log_page_size; 344 u8 reserved3[2]; 345 u8 mtt_base_addr_h; 346 __be32 mtt_base_addr_l; 347 __be32 last_notified_index; 348 __be32 solicit_producer_index; 349 __be32 consumer_index; 350 __be32 producer_index; 351 u32 reserved4[2]; 352 __be64 db_rec_addr; 353 }; 354 355 struct mlx4_srq_context { 356 __be32 state_logsize_srqn; 357 u8 logstride; 358 u8 reserved1; 359 __be16 xrcd; 360 __be32 pg_offset_cqn; 361 u32 reserved2; 362 u8 log_page_size; 363 u8 reserved3[2]; 364 u8 mtt_base_addr_h; 365 __be32 mtt_base_addr_l; 366 __be32 pd; 367 __be16 limit_watermark; 368 __be16 wqe_cnt; 369 u16 reserved4; 370 __be16 wqe_counter; 371 u32 reserved5; 372 __be64 db_rec_addr; 373 }; 374 375 struct mlx4_eq_tasklet { 376 struct list_head list; 377 struct list_head process_list; 378 struct tasklet_struct task; 379 /* lock on completion tasklet list */ 380 spinlock_t lock; 381 }; 382 383 struct mlx4_eq { 384 struct mlx4_dev *dev; 385 void __iomem *doorbell; 386 int eqn; 387 u32 cons_index; 388 u16 irq; 389 u16 have_irq; 390 int nent; 391 struct mlx4_buf_list *page_list; 392 struct mlx4_mtt mtt; 393 struct mlx4_eq_tasklet tasklet_ctx; 394 }; 395 396 struct mlx4_slave_eqe { 397 u8 type; 398 u8 port; 399 u32 param; 400 }; 401 402 struct mlx4_slave_event_eq_info { 403 int eqn; 404 u16 token; 405 }; 406 407 struct mlx4_profile { 408 int num_qp; 409 int rdmarc_per_qp; 410 int num_srq; 411 int num_cq; 412 int num_mcg; 413 int num_mpt; 414 unsigned num_mtt; 415 }; 416 417 struct mlx4_fw { 418 u64 clr_int_base; 419 u64 catas_offset; 420 u64 comm_base; 421 u64 clock_offset; 422 struct mlx4_icm *fw_icm; 423 struct mlx4_icm *aux_icm; 424 u32 catas_size; 425 u16 fw_pages; 426 u8 clr_int_bar; 427 u8 catas_bar; 428 u8 comm_bar; 429 u8 clock_bar; 430 }; 431 432 struct mlx4_comm { 433 u32 slave_write; 434 u32 slave_read; 435 }; 436 437 enum { 438 MLX4_MCAST_CONFIG = 0, 439 MLX4_MCAST_DISABLE = 1, 440 MLX4_MCAST_ENABLE = 2, 441 }; 442 443 #define VLAN_FLTR_SIZE 128 444 445 struct mlx4_vlan_fltr { 446 __be32 entry[VLAN_FLTR_SIZE]; 447 }; 448 449 struct mlx4_mcast_entry { 450 struct list_head list; 451 u64 addr; 452 }; 453 454 struct mlx4_promisc_qp { 455 struct list_head list; 456 u32 qpn; 457 }; 458 459 struct mlx4_steer_index { 460 struct list_head list; 461 unsigned int index; 462 struct list_head duplicates; 463 }; 464 465 #define MLX4_EVENT_TYPES_NUM 64 466 467 struct mlx4_slave_state { 468 u8 comm_toggle; 469 u8 last_cmd; 470 u8 init_port_mask; 471 bool active; 472 bool old_vlan_api; 473 u8 function; 474 dma_addr_t vhcr_dma; 475 u16 mtu[MLX4_MAX_PORTS + 1]; 476 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 477 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 478 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 479 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 480 /* event type to eq number lookup */ 481 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 482 u16 eq_pi; 483 u16 eq_ci; 484 spinlock_t lock; 485 /*initialized via the kzalloc*/ 486 u8 is_slave_going_down; 487 u32 cookie; 488 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 489 }; 490 491 #define MLX4_VGT 4095 492 #define NO_INDX (-1) 493 494 struct mlx4_vport_state { 495 u64 mac; 496 u16 default_vlan; 497 u8 default_qos; 498 u32 tx_rate; 499 bool spoofchk; 500 u32 link_state; 501 u8 qos_vport; 502 }; 503 504 struct mlx4_vf_admin_state { 505 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 506 u8 enable_smi[MLX4_MAX_PORTS + 1]; 507 }; 508 509 struct mlx4_vport_oper_state { 510 struct mlx4_vport_state state; 511 int mac_idx; 512 int vlan_idx; 513 }; 514 515 struct mlx4_vf_oper_state { 516 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 517 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 518 }; 519 520 struct slave_list { 521 struct mutex mutex; 522 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 523 }; 524 525 struct resource_allocator { 526 spinlock_t alloc_lock; /* protect quotas */ 527 union { 528 int res_reserved; 529 int res_port_rsvd[MLX4_MAX_PORTS]; 530 }; 531 union { 532 int res_free; 533 int res_port_free[MLX4_MAX_PORTS]; 534 }; 535 int *quota; 536 int *allocated; 537 int *guaranteed; 538 }; 539 540 struct mlx4_resource_tracker { 541 spinlock_t lock; 542 /* tree for each resources */ 543 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 544 /* num_of_slave's lists, one per slave */ 545 struct slave_list *slave_list; 546 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 547 }; 548 549 #define SLAVE_EVENT_EQ_SIZE 128 550 struct mlx4_slave_event_eq { 551 u32 eqn; 552 u32 cons; 553 u32 prod; 554 spinlock_t event_lock; 555 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 556 }; 557 558 struct mlx4_qos_manager { 559 int num_of_qos_vfs; 560 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 561 }; 562 563 struct mlx4_master_qp0_state { 564 int proxy_qp0_active; 565 int qp0_active; 566 int port_active; 567 }; 568 569 struct mlx4_mfunc_master_ctx { 570 struct mlx4_slave_state *slave_state; 571 struct mlx4_vf_admin_state *vf_admin; 572 struct mlx4_vf_oper_state *vf_oper; 573 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 574 int init_port_ref[MLX4_MAX_PORTS + 1]; 575 u16 max_mtu[MLX4_MAX_PORTS + 1]; 576 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 577 struct mlx4_resource_tracker res_tracker; 578 struct workqueue_struct *comm_wq; 579 struct work_struct comm_work; 580 struct work_struct slave_event_work; 581 struct work_struct slave_flr_event_work; 582 spinlock_t slave_state_lock; 583 __be32 comm_arm_bit_vector[4]; 584 struct mlx4_eqe cmd_eqe; 585 struct mlx4_slave_event_eq slave_eq; 586 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 587 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 588 }; 589 590 struct mlx4_mfunc { 591 struct mlx4_comm __iomem *comm; 592 struct mlx4_vhcr_cmd *vhcr; 593 dma_addr_t vhcr_dma; 594 595 struct mlx4_mfunc_master_ctx master; 596 }; 597 598 #define MGM_QPN_MASK 0x00FFFFFF 599 #define MGM_BLCK_LB_BIT 30 600 601 struct mlx4_mgm { 602 __be32 next_gid_index; 603 __be32 members_count; 604 u32 reserved[2]; 605 u8 gid[16]; 606 __be32 qp[MLX4_MAX_QP_PER_MGM]; 607 }; 608 609 struct mlx4_cmd { 610 struct pci_pool *pool; 611 void __iomem *hcr; 612 struct mutex slave_cmd_mutex; 613 struct semaphore poll_sem; 614 struct semaphore event_sem; 615 int max_cmds; 616 spinlock_t context_lock; 617 int free_head; 618 struct mlx4_cmd_context *context; 619 u16 token_mask; 620 u8 use_events; 621 u8 toggle; 622 u8 comm_toggle; 623 u8 initialized; 624 }; 625 626 enum { 627 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 628 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 629 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 630 }; 631 struct mlx4_vf_immed_vlan_work { 632 struct work_struct work; 633 struct mlx4_priv *priv; 634 int flags; 635 int slave; 636 int vlan_ix; 637 int orig_vlan_ix; 638 u8 port; 639 u8 qos; 640 u8 qos_vport; 641 u16 vlan_id; 642 u16 orig_vlan_id; 643 }; 644 645 646 struct mlx4_uar_table { 647 struct mlx4_bitmap bitmap; 648 }; 649 650 struct mlx4_mr_table { 651 struct mlx4_bitmap mpt_bitmap; 652 struct mlx4_buddy mtt_buddy; 653 u64 mtt_base; 654 u64 mpt_base; 655 struct mlx4_icm_table mtt_table; 656 struct mlx4_icm_table dmpt_table; 657 }; 658 659 struct mlx4_cq_table { 660 struct mlx4_bitmap bitmap; 661 spinlock_t lock; 662 struct radix_tree_root tree; 663 struct mlx4_icm_table table; 664 struct mlx4_icm_table cmpt_table; 665 }; 666 667 struct mlx4_eq_table { 668 struct mlx4_bitmap bitmap; 669 char *irq_names; 670 void __iomem *clr_int; 671 void __iomem **uar_map; 672 u32 clr_mask; 673 struct mlx4_eq *eq; 674 struct mlx4_icm_table table; 675 struct mlx4_icm_table cmpt_table; 676 int have_irq; 677 u8 inta_pin; 678 }; 679 680 struct mlx4_srq_table { 681 struct mlx4_bitmap bitmap; 682 spinlock_t lock; 683 struct radix_tree_root tree; 684 struct mlx4_icm_table table; 685 struct mlx4_icm_table cmpt_table; 686 }; 687 688 enum mlx4_qp_table_zones { 689 MLX4_QP_TABLE_ZONE_GENERAL, 690 MLX4_QP_TABLE_ZONE_RSS, 691 MLX4_QP_TABLE_ZONE_RAW_ETH, 692 MLX4_QP_TABLE_ZONE_NUM 693 }; 694 695 struct mlx4_qp_table { 696 struct mlx4_bitmap *bitmap_gen; 697 struct mlx4_zone_allocator *zones; 698 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 699 u32 rdmarc_base; 700 int rdmarc_shift; 701 spinlock_t lock; 702 struct mlx4_icm_table qp_table; 703 struct mlx4_icm_table auxc_table; 704 struct mlx4_icm_table altc_table; 705 struct mlx4_icm_table rdmarc_table; 706 struct mlx4_icm_table cmpt_table; 707 }; 708 709 struct mlx4_mcg_table { 710 struct mutex mutex; 711 struct mlx4_bitmap bitmap; 712 struct mlx4_icm_table table; 713 }; 714 715 struct mlx4_catas_err { 716 u32 __iomem *map; 717 struct timer_list timer; 718 struct list_head list; 719 }; 720 721 #define MLX4_MAX_MAC_NUM 128 722 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 723 724 struct mlx4_mac_table { 725 __be64 entries[MLX4_MAX_MAC_NUM]; 726 int refs[MLX4_MAX_MAC_NUM]; 727 struct mutex mutex; 728 int total; 729 int max; 730 }; 731 732 #define MLX4_ROCE_GID_ENTRY_SIZE 16 733 734 struct mlx4_roce_gid_entry { 735 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 736 }; 737 738 struct mlx4_roce_gid_table { 739 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 740 struct mutex mutex; 741 }; 742 743 #define MLX4_MAX_VLAN_NUM 128 744 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 745 746 struct mlx4_vlan_table { 747 __be32 entries[MLX4_MAX_VLAN_NUM]; 748 int refs[MLX4_MAX_VLAN_NUM]; 749 struct mutex mutex; 750 int total; 751 int max; 752 }; 753 754 #define SET_PORT_GEN_ALL_VALID 0x7 755 #define SET_PORT_PROMISC_SHIFT 31 756 #define SET_PORT_MC_PROMISC_SHIFT 30 757 758 enum { 759 MCAST_DIRECT_ONLY = 0, 760 MCAST_DIRECT = 1, 761 MCAST_DEFAULT = 2 762 }; 763 764 765 struct mlx4_set_port_general_context { 766 u16 reserved1; 767 u8 v_ignore_fcs; 768 u8 flags; 769 u8 ignore_fcs; 770 u8 reserved2; 771 __be16 mtu; 772 u8 pptx; 773 u8 pfctx; 774 u16 reserved3; 775 u8 pprx; 776 u8 pfcrx; 777 u16 reserved4; 778 }; 779 780 struct mlx4_set_port_rqp_calc_context { 781 __be32 base_qpn; 782 u8 rererved; 783 u8 n_mac; 784 u8 n_vlan; 785 u8 n_prio; 786 u8 reserved2[3]; 787 u8 mac_miss; 788 u8 intra_no_vlan; 789 u8 no_vlan; 790 u8 intra_vlan_miss; 791 u8 vlan_miss; 792 u8 reserved3[3]; 793 u8 no_vlan_prio; 794 __be32 promisc; 795 __be32 mcast; 796 }; 797 798 struct mlx4_port_info { 799 struct mlx4_dev *dev; 800 int port; 801 char dev_name[16]; 802 struct device_attribute port_attr; 803 enum mlx4_port_type tmp_type; 804 char dev_mtu_name[16]; 805 struct device_attribute port_mtu_attr; 806 struct mlx4_mac_table mac_table; 807 struct mlx4_vlan_table vlan_table; 808 struct mlx4_roce_gid_table gid_table; 809 int base_qpn; 810 }; 811 812 struct mlx4_sense { 813 struct mlx4_dev *dev; 814 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 815 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 816 struct delayed_work sense_poll; 817 }; 818 819 struct mlx4_msix_ctl { 820 u64 pool_bm; 821 struct mutex pool_lock; 822 }; 823 824 struct mlx4_steer { 825 struct list_head promisc_qps[MLX4_NUM_STEERS]; 826 struct list_head steer_entries[MLX4_NUM_STEERS]; 827 }; 828 829 enum { 830 MLX4_PCI_DEV_IS_VF = 1 << 0, 831 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 832 }; 833 834 enum { 835 MLX4_NO_RR = 0, 836 MLX4_USE_RR = 1, 837 }; 838 839 struct mlx4_priv { 840 struct mlx4_dev dev; 841 842 struct list_head dev_list; 843 struct list_head ctx_list; 844 spinlock_t ctx_lock; 845 846 int pci_dev_data; 847 int removed; 848 849 struct list_head pgdir_list; 850 struct mutex pgdir_mutex; 851 852 struct mlx4_fw fw; 853 struct mlx4_cmd cmd; 854 struct mlx4_mfunc mfunc; 855 856 struct mlx4_bitmap pd_bitmap; 857 struct mlx4_bitmap xrcd_bitmap; 858 struct mlx4_uar_table uar_table; 859 struct mlx4_mr_table mr_table; 860 struct mlx4_cq_table cq_table; 861 struct mlx4_eq_table eq_table; 862 struct mlx4_srq_table srq_table; 863 struct mlx4_qp_table qp_table; 864 struct mlx4_mcg_table mcg_table; 865 struct mlx4_bitmap counters_bitmap; 866 867 struct mlx4_catas_err catas_err; 868 869 void __iomem *clr_base; 870 871 struct mlx4_uar driver_uar; 872 void __iomem *kar; 873 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 874 struct mlx4_sense sense; 875 struct mutex port_mutex; 876 struct mlx4_msix_ctl msix_ctl; 877 struct mlx4_steer *steer; 878 struct list_head bf_list; 879 struct mutex bf_mutex; 880 struct io_mapping *bf_mapping; 881 void __iomem *clock_mapping; 882 int reserved_mtts; 883 int fs_hash_mode; 884 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 885 struct mlx4_port_map v2p; /* cached port mapping configuration */ 886 struct mutex bond_mutex; /* for bond mode */ 887 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 888 889 atomic_t opreq_count; 890 struct work_struct opreq_task; 891 }; 892 893 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 894 { 895 return container_of(dev, struct mlx4_priv, dev); 896 } 897 898 #define MLX4_SENSE_RANGE (HZ * 3) 899 900 extern struct workqueue_struct *mlx4_wq; 901 902 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 903 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 904 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 905 int align, u32 skip_mask); 906 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 907 int use_rr); 908 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 909 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 910 u32 reserved_bot, u32 resetrved_top); 911 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 912 913 int mlx4_reset(struct mlx4_dev *dev); 914 915 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 916 void mlx4_free_eq_table(struct mlx4_dev *dev); 917 918 int mlx4_init_pd_table(struct mlx4_dev *dev); 919 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 920 int mlx4_init_uar_table(struct mlx4_dev *dev); 921 int mlx4_init_mr_table(struct mlx4_dev *dev); 922 int mlx4_init_eq_table(struct mlx4_dev *dev); 923 int mlx4_init_cq_table(struct mlx4_dev *dev); 924 int mlx4_init_qp_table(struct mlx4_dev *dev); 925 int mlx4_init_srq_table(struct mlx4_dev *dev); 926 int mlx4_init_mcg_table(struct mlx4_dev *dev); 927 928 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 929 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 930 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 931 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 932 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 933 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 934 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 935 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 936 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 937 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 938 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 939 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 940 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 941 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 942 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 943 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 944 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 945 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 946 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 947 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 948 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 949 950 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 951 struct mlx4_vhcr *vhcr, 952 struct mlx4_cmd_mailbox *inbox, 953 struct mlx4_cmd_mailbox *outbox, 954 struct mlx4_cmd_info *cmd); 955 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 956 struct mlx4_vhcr *vhcr, 957 struct mlx4_cmd_mailbox *inbox, 958 struct mlx4_cmd_mailbox *outbox, 959 struct mlx4_cmd_info *cmd); 960 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 961 struct mlx4_vhcr *vhcr, 962 struct mlx4_cmd_mailbox *inbox, 963 struct mlx4_cmd_mailbox *outbox, 964 struct mlx4_cmd_info *cmd); 965 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 966 struct mlx4_vhcr *vhcr, 967 struct mlx4_cmd_mailbox *inbox, 968 struct mlx4_cmd_mailbox *outbox, 969 struct mlx4_cmd_info *cmd); 970 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 971 struct mlx4_vhcr *vhcr, 972 struct mlx4_cmd_mailbox *inbox, 973 struct mlx4_cmd_mailbox *outbox, 974 struct mlx4_cmd_info *cmd); 975 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 976 struct mlx4_vhcr *vhcr, 977 struct mlx4_cmd_mailbox *inbox, 978 struct mlx4_cmd_mailbox *outbox, 979 struct mlx4_cmd_info *cmd); 980 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 981 struct mlx4_vhcr *vhcr, 982 struct mlx4_cmd_mailbox *inbox, 983 struct mlx4_cmd_mailbox *outbox, 984 struct mlx4_cmd_info *cmd); 985 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 986 struct mlx4_vhcr *vhcr, 987 struct mlx4_cmd_mailbox *inbox, 988 struct mlx4_cmd_mailbox *outbox, 989 struct mlx4_cmd_info *cmd); 990 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 991 int *base, u8 flags); 992 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 993 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 994 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 995 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 996 int start_index, int npages, u64 *page_list); 997 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 998 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 999 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1000 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1001 1002 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1003 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1004 int mlx4_catas_init(struct mlx4_dev *dev); 1005 void mlx4_catas_end(struct mlx4_dev *dev); 1006 int mlx4_restart_one(struct pci_dev *pdev); 1007 int mlx4_register_device(struct mlx4_dev *dev); 1008 void mlx4_unregister_device(struct mlx4_dev *dev); 1009 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1010 unsigned long param); 1011 1012 struct mlx4_dev_cap; 1013 struct mlx4_init_hca_param; 1014 1015 u64 mlx4_make_profile(struct mlx4_dev *dev, 1016 struct mlx4_profile *request, 1017 struct mlx4_dev_cap *dev_cap, 1018 struct mlx4_init_hca_param *init_hca); 1019 void mlx4_master_comm_channel(struct work_struct *work); 1020 void mlx4_gen_slave_eqe(struct work_struct *work); 1021 void mlx4_master_handle_slave_flr(struct work_struct *work); 1022 1023 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1024 struct mlx4_vhcr *vhcr, 1025 struct mlx4_cmd_mailbox *inbox, 1026 struct mlx4_cmd_mailbox *outbox, 1027 struct mlx4_cmd_info *cmd); 1028 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1029 struct mlx4_vhcr *vhcr, 1030 struct mlx4_cmd_mailbox *inbox, 1031 struct mlx4_cmd_mailbox *outbox, 1032 struct mlx4_cmd_info *cmd); 1033 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1034 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1035 struct mlx4_cmd_mailbox *outbox, 1036 struct mlx4_cmd_info *cmd); 1037 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, 1039 struct mlx4_cmd_mailbox *inbox, 1040 struct mlx4_cmd_mailbox *outbox, 1041 struct mlx4_cmd_info *cmd); 1042 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1043 struct mlx4_vhcr *vhcr, 1044 struct mlx4_cmd_mailbox *inbox, 1045 struct mlx4_cmd_mailbox *outbox, 1046 struct mlx4_cmd_info *cmd); 1047 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1048 struct mlx4_vhcr *vhcr, 1049 struct mlx4_cmd_mailbox *inbox, 1050 struct mlx4_cmd_mailbox *outbox, 1051 struct mlx4_cmd_info *cmd); 1052 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1053 struct mlx4_vhcr *vhcr, 1054 struct mlx4_cmd_mailbox *inbox, 1055 struct mlx4_cmd_mailbox *outbox, 1056 struct mlx4_cmd_info *cmd); 1057 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1058 struct mlx4_vhcr *vhcr, 1059 struct mlx4_cmd_mailbox *inbox, 1060 struct mlx4_cmd_mailbox *outbox, 1061 struct mlx4_cmd_info *cmd); 1062 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1063 struct mlx4_vhcr *vhcr, 1064 struct mlx4_cmd_mailbox *inbox, 1065 struct mlx4_cmd_mailbox *outbox, 1066 struct mlx4_cmd_info *cmd); 1067 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1068 struct mlx4_vhcr *vhcr, 1069 struct mlx4_cmd_mailbox *inbox, 1070 struct mlx4_cmd_mailbox *outbox, 1071 struct mlx4_cmd_info *cmd); 1072 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1073 struct mlx4_vhcr *vhcr, 1074 struct mlx4_cmd_mailbox *inbox, 1075 struct mlx4_cmd_mailbox *outbox, 1076 struct mlx4_cmd_info *cmd); 1077 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1078 struct mlx4_vhcr *vhcr, 1079 struct mlx4_cmd_mailbox *inbox, 1080 struct mlx4_cmd_mailbox *outbox, 1081 struct mlx4_cmd_info *cmd); 1082 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1083 struct mlx4_vhcr *vhcr, 1084 struct mlx4_cmd_mailbox *inbox, 1085 struct mlx4_cmd_mailbox *outbox, 1086 struct mlx4_cmd_info *cmd); 1087 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1088 struct mlx4_vhcr *vhcr, 1089 struct mlx4_cmd_mailbox *inbox, 1090 struct mlx4_cmd_mailbox *outbox, 1091 struct mlx4_cmd_info *cmd); 1092 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1093 struct mlx4_vhcr *vhcr, 1094 struct mlx4_cmd_mailbox *inbox, 1095 struct mlx4_cmd_mailbox *outbox, 1096 struct mlx4_cmd_info *cmd); 1097 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1098 struct mlx4_vhcr *vhcr, 1099 struct mlx4_cmd_mailbox *inbox, 1100 struct mlx4_cmd_mailbox *outbox, 1101 struct mlx4_cmd_info *cmd); 1102 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1103 struct mlx4_vhcr *vhcr, 1104 struct mlx4_cmd_mailbox *inbox, 1105 struct mlx4_cmd_mailbox *outbox, 1106 struct mlx4_cmd_info *cmd); 1107 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1108 struct mlx4_vhcr *vhcr, 1109 struct mlx4_cmd_mailbox *inbox, 1110 struct mlx4_cmd_mailbox *outbox, 1111 struct mlx4_cmd_info *cmd); 1112 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1113 struct mlx4_vhcr *vhcr, 1114 struct mlx4_cmd_mailbox *inbox, 1115 struct mlx4_cmd_mailbox *outbox, 1116 struct mlx4_cmd_info *cmd); 1117 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1118 struct mlx4_vhcr *vhcr, 1119 struct mlx4_cmd_mailbox *inbox, 1120 struct mlx4_cmd_mailbox *outbox, 1121 struct mlx4_cmd_info *cmd); 1122 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1123 struct mlx4_vhcr *vhcr, 1124 struct mlx4_cmd_mailbox *inbox, 1125 struct mlx4_cmd_mailbox *outbox, 1126 struct mlx4_cmd_info *cmd); 1127 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1128 struct mlx4_vhcr *vhcr, 1129 struct mlx4_cmd_mailbox *inbox, 1130 struct mlx4_cmd_mailbox *outbox, 1131 struct mlx4_cmd_info *cmd); 1132 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1133 struct mlx4_vhcr *vhcr, 1134 struct mlx4_cmd_mailbox *inbox, 1135 struct mlx4_cmd_mailbox *outbox, 1136 struct mlx4_cmd_info *cmd); 1137 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1138 struct mlx4_vhcr *vhcr, 1139 struct mlx4_cmd_mailbox *inbox, 1140 struct mlx4_cmd_mailbox *outbox, 1141 struct mlx4_cmd_info *cmd); 1142 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1143 struct mlx4_vhcr *vhcr, 1144 struct mlx4_cmd_mailbox *inbox, 1145 struct mlx4_cmd_mailbox *outbox, 1146 struct mlx4_cmd_info *cmd); 1147 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1148 struct mlx4_vhcr *vhcr, 1149 struct mlx4_cmd_mailbox *inbox, 1150 struct mlx4_cmd_mailbox *outbox, 1151 struct mlx4_cmd_info *cmd); 1152 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1153 struct mlx4_vhcr *vhcr, 1154 struct mlx4_cmd_mailbox *inbox, 1155 struct mlx4_cmd_mailbox *outbox, 1156 struct mlx4_cmd_info *cmd); 1157 1158 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1159 1160 enum { 1161 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1162 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1163 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1164 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1165 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1166 }; 1167 1168 int mlx4_cmd_init(struct mlx4_dev *dev); 1169 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1170 int mlx4_multi_func_init(struct mlx4_dev *dev); 1171 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1172 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1173 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1174 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1175 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1176 1177 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1178 u16 op, unsigned long timeout); 1179 1180 void mlx4_cq_tasklet_cb(unsigned long data); 1181 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1182 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1183 1184 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1185 1186 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1187 1188 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1189 1190 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1191 enum mlx4_port_type *type); 1192 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1193 enum mlx4_port_type *stype, 1194 enum mlx4_port_type *defaults); 1195 void mlx4_start_sense(struct mlx4_dev *dev); 1196 void mlx4_stop_sense(struct mlx4_dev *dev); 1197 void mlx4_sense_init(struct mlx4_dev *dev); 1198 int mlx4_check_port_params(struct mlx4_dev *dev, 1199 enum mlx4_port_type *port_type); 1200 int mlx4_change_port_types(struct mlx4_dev *dev, 1201 enum mlx4_port_type *port_types); 1202 1203 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1204 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1205 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1206 struct mlx4_roce_gid_table *table); 1207 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1208 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1209 1210 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1211 /* resource tracker functions*/ 1212 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1213 enum mlx4_resource resource_type, 1214 u64 resource_id, int *slave); 1215 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1216 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1217 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1218 1219 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1220 enum mlx4_res_tracker_free_type type); 1221 1222 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1223 struct mlx4_vhcr *vhcr, 1224 struct mlx4_cmd_mailbox *inbox, 1225 struct mlx4_cmd_mailbox *outbox, 1226 struct mlx4_cmd_info *cmd); 1227 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1228 struct mlx4_vhcr *vhcr, 1229 struct mlx4_cmd_mailbox *inbox, 1230 struct mlx4_cmd_mailbox *outbox, 1231 struct mlx4_cmd_info *cmd); 1232 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1233 struct mlx4_vhcr *vhcr, 1234 struct mlx4_cmd_mailbox *inbox, 1235 struct mlx4_cmd_mailbox *outbox, 1236 struct mlx4_cmd_info *cmd); 1237 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1238 struct mlx4_vhcr *vhcr, 1239 struct mlx4_cmd_mailbox *inbox, 1240 struct mlx4_cmd_mailbox *outbox, 1241 struct mlx4_cmd_info *cmd); 1242 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1243 struct mlx4_vhcr *vhcr, 1244 struct mlx4_cmd_mailbox *inbox, 1245 struct mlx4_cmd_mailbox *outbox, 1246 struct mlx4_cmd_info *cmd); 1247 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1248 struct mlx4_vhcr *vhcr, 1249 struct mlx4_cmd_mailbox *inbox, 1250 struct mlx4_cmd_mailbox *outbox, 1251 struct mlx4_cmd_info *cmd); 1252 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1253 1254 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1255 int *gid_tbl_len, int *pkey_tbl_len); 1256 1257 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1258 struct mlx4_vhcr *vhcr, 1259 struct mlx4_cmd_mailbox *inbox, 1260 struct mlx4_cmd_mailbox *outbox, 1261 struct mlx4_cmd_info *cmd); 1262 1263 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1264 struct mlx4_vhcr *vhcr, 1265 struct mlx4_cmd_mailbox *inbox, 1266 struct mlx4_cmd_mailbox *outbox, 1267 struct mlx4_cmd_info *cmd); 1268 1269 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1270 struct mlx4_vhcr *vhcr, 1271 struct mlx4_cmd_mailbox *inbox, 1272 struct mlx4_cmd_mailbox *outbox, 1273 struct mlx4_cmd_info *cmd); 1274 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1275 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1276 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1277 int block_mcast_loopback, enum mlx4_protocol prot, 1278 enum mlx4_steer_type steer); 1279 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1280 u8 gid[16], u8 port, 1281 int block_mcast_loopback, 1282 enum mlx4_protocol prot, u64 *reg_id); 1283 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1284 struct mlx4_vhcr *vhcr, 1285 struct mlx4_cmd_mailbox *inbox, 1286 struct mlx4_cmd_mailbox *outbox, 1287 struct mlx4_cmd_info *cmd); 1288 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1289 struct mlx4_vhcr *vhcr, 1290 struct mlx4_cmd_mailbox *inbox, 1291 struct mlx4_cmd_mailbox *outbox, 1292 struct mlx4_cmd_info *cmd); 1293 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1294 int port, void *buf); 1295 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1296 struct mlx4_cmd_mailbox *outbox); 1297 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1298 struct mlx4_vhcr *vhcr, 1299 struct mlx4_cmd_mailbox *inbox, 1300 struct mlx4_cmd_mailbox *outbox, 1301 struct mlx4_cmd_info *cmd); 1302 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1303 struct mlx4_vhcr *vhcr, 1304 struct mlx4_cmd_mailbox *inbox, 1305 struct mlx4_cmd_mailbox *outbox, 1306 struct mlx4_cmd_info *cmd); 1307 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1308 struct mlx4_vhcr *vhcr, 1309 struct mlx4_cmd_mailbox *inbox, 1310 struct mlx4_cmd_mailbox *outbox, 1311 struct mlx4_cmd_info *cmd); 1312 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1313 struct mlx4_vhcr *vhcr, 1314 struct mlx4_cmd_mailbox *inbox, 1315 struct mlx4_cmd_mailbox *outbox, 1316 struct mlx4_cmd_info *cmd); 1317 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1318 struct mlx4_vhcr *vhcr, 1319 struct mlx4_cmd_mailbox *inbox, 1320 struct mlx4_cmd_mailbox *outbox, 1321 struct mlx4_cmd_info *cmd); 1322 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1323 struct mlx4_vhcr *vhcr, 1324 struct mlx4_cmd_mailbox *inbox, 1325 struct mlx4_cmd_mailbox *outbox, 1326 struct mlx4_cmd_info *cmd); 1327 1328 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1329 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1330 1331 static inline void set_param_l(u64 *arg, u32 val) 1332 { 1333 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1334 } 1335 1336 static inline void set_param_h(u64 *arg, u32 val) 1337 { 1338 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1339 } 1340 1341 static inline u32 get_param_l(u64 *arg) 1342 { 1343 return (u32) (*arg & 0xffffffff); 1344 } 1345 1346 static inline u32 get_param_h(u64 *arg) 1347 { 1348 return (u32)(*arg >> 32); 1349 } 1350 1351 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1352 { 1353 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1354 } 1355 1356 #define NOT_MASKED_PD_BITS 17 1357 1358 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1359 1360 void mlx4_init_quotas(struct mlx4_dev *dev); 1361 1362 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1363 /* Returns the VF index of slave */ 1364 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1365 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1366 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1367 1368 enum mlx4_zone_flags { 1369 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1370 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1371 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1372 MLX4_ZONE_USE_RR = 1UL << 3, 1373 }; 1374 1375 enum mlx4_zone_alloc_flags { 1376 /* No two objects could overlap between zones. UID 1377 * could be left unused. If this flag is given and 1378 * two overlapped zones are used, an object will be free'd 1379 * from the smallest possible matching zone. 1380 */ 1381 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1382 }; 1383 1384 struct mlx4_zone_allocator; 1385 1386 /* Create a new zone allocator */ 1387 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1388 1389 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1390 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1391 * Similarly, when searching for an object to free, this offset it taken into 1392 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1393 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1394 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1395 * according to the policy set by <flags>. <puid> is the unique identifier 1396 * received to this zone. 1397 */ 1398 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1399 struct mlx4_bitmap *bitmap, 1400 u32 flags, 1401 int priority, 1402 int offset, 1403 u32 *puid); 1404 1405 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1406 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1407 1408 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1409 * the attached bitmaps. 1410 */ 1411 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1412 1413 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1414 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1415 * allocated from is returned in <puid>. If the allocation fails, a negative 1416 * number is returned. Otherwise, the offset of the first object is returned. 1417 */ 1418 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1419 int align, u32 skip_mask, u32 *puid); 1420 1421 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1422 * <zones>. 1423 */ 1424 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1425 u32 uid, u32 obj, u32 count); 1426 1427 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1428 * specifying the uid when freeing an object, zone allocator could figure it by 1429 * itself. Other parameters are similar to mlx4_zone_free. 1430 */ 1431 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1432 1433 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1434 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1435 1436 #endif /* MLX4_H */ 1437