1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 47 #include <linux/mlx4/device.h> 48 #include <linux/mlx4/driver.h> 49 #include <linux/mlx4/doorbell.h> 50 #include <linux/mlx4/cmd.h> 51 52 #define DRV_NAME "mlx4_core" 53 #define PFX DRV_NAME ": " 54 #define DRV_VERSION "1.1" 55 #define DRV_RELDATE "Dec, 2011" 56 57 #define MLX4_FS_UDP_UC_EN (1 << 1) 58 #define MLX4_FS_TCP_UC_EN (1 << 2) 59 #define MLX4_FS_NUM_OF_L2_ADDR 8 60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 61 #define MLX4_FS_NUM_MCG (1 << 17) 62 63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 64 65 #define MLX4_NUM_UP 8 66 #define MLX4_NUM_TC 8 67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */ 68 #define MLX4_RATELIMIT_DEFAULT 0xffff 69 70 struct mlx4_set_port_prio2tc_context { 71 u8 prio2tc[4]; 72 }; 73 74 struct mlx4_port_scheduler_tc_cfg_be { 75 __be16 pg; 76 __be16 bw_precentage; 77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ 78 __be16 max_bw_value; 79 }; 80 81 struct mlx4_set_port_scheduler_context { 82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 83 }; 84 85 enum { 86 MLX4_HCR_BASE = 0x80680, 87 MLX4_HCR_SIZE = 0x0001c, 88 MLX4_CLR_INT_SIZE = 0x00008, 89 MLX4_SLAVE_COMM_BASE = 0x0, 90 MLX4_COMM_PAGESIZE = 0x1000, 91 MLX4_CLOCK_SIZE = 0x00008 92 }; 93 94 enum { 95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 99 MLX4_MTT_ENTRY_PER_SEG = 8, 100 }; 101 102 enum { 103 MLX4_NUM_PDS = 1 << 15 104 }; 105 106 enum { 107 MLX4_CMPT_TYPE_QP = 0, 108 MLX4_CMPT_TYPE_SRQ = 1, 109 MLX4_CMPT_TYPE_CQ = 2, 110 MLX4_CMPT_TYPE_EQ = 3, 111 MLX4_CMPT_NUM_TYPE 112 }; 113 114 enum { 115 MLX4_CMPT_SHIFT = 24, 116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 117 }; 118 119 enum mlx4_mpt_state { 120 MLX4_MPT_DISABLED = 0, 121 MLX4_MPT_EN_HW, 122 MLX4_MPT_EN_SW 123 }; 124 125 #define MLX4_COMM_TIME 10000 126 enum { 127 MLX4_COMM_CMD_RESET, 128 MLX4_COMM_CMD_VHCR0, 129 MLX4_COMM_CMD_VHCR1, 130 MLX4_COMM_CMD_VHCR2, 131 MLX4_COMM_CMD_VHCR_EN, 132 MLX4_COMM_CMD_VHCR_POST, 133 MLX4_COMM_CMD_FLR = 254 134 }; 135 136 /*The flag indicates that the slave should delay the RESET cmd*/ 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 138 /*indicates how many retries will be done if we are in the middle of FLR*/ 139 #define NUM_OF_RESET_RETRIES 10 140 #define SLEEP_TIME_IN_RESET (2 * 1000) 141 enum mlx4_resource { 142 RES_QP, 143 RES_CQ, 144 RES_SRQ, 145 RES_XRCD, 146 RES_MPT, 147 RES_MTT, 148 RES_MAC, 149 RES_VLAN, 150 RES_EQ, 151 RES_COUNTER, 152 RES_FS_RULE, 153 MLX4_NUM_OF_RESOURCE_TYPE 154 }; 155 156 enum mlx4_alloc_mode { 157 RES_OP_RESERVE, 158 RES_OP_RESERVE_AND_MAP, 159 RES_OP_MAP_ICM, 160 }; 161 162 enum mlx4_res_tracker_free_type { 163 RES_TR_FREE_ALL, 164 RES_TR_FREE_SLAVES_ONLY, 165 RES_TR_FREE_STRUCTS_ONLY, 166 }; 167 168 /* 169 *Virtual HCR structures. 170 * mlx4_vhcr is the sw representation, in machine endianess 171 * 172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 173 * to FW to go through communication channel. 174 * It is big endian, and has the same structure as the physical HCR 175 * used by command interface 176 */ 177 struct mlx4_vhcr { 178 u64 in_param; 179 u64 out_param; 180 u32 in_modifier; 181 u32 errno; 182 u16 op; 183 u16 token; 184 u8 op_modifier; 185 u8 e_bit; 186 }; 187 188 struct mlx4_vhcr_cmd { 189 __be64 in_param; 190 __be32 in_modifier; 191 __be64 out_param; 192 __be16 token; 193 u16 reserved; 194 u8 status; 195 u8 flags; 196 __be16 opcode; 197 }; 198 199 struct mlx4_cmd_info { 200 u16 opcode; 201 bool has_inbox; 202 bool has_outbox; 203 bool out_is_imm; 204 bool encode_slave_id; 205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox); 207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 208 struct mlx4_cmd_mailbox *inbox, 209 struct mlx4_cmd_mailbox *outbox, 210 struct mlx4_cmd_info *cmd); 211 }; 212 213 #ifdef CONFIG_MLX4_DEBUG 214 extern int mlx4_debug_level; 215 #else /* CONFIG_MLX4_DEBUG */ 216 #define mlx4_debug_level (0) 217 #endif /* CONFIG_MLX4_DEBUG */ 218 219 #define mlx4_dbg(mdev, format, arg...) \ 220 do { \ 221 if (mlx4_debug_level) \ 222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 223 } while (0) 224 225 #define mlx4_err(mdev, format, arg...) \ 226 dev_err(&mdev->pdev->dev, format, ##arg) 227 #define mlx4_info(mdev, format, arg...) \ 228 dev_info(&mdev->pdev->dev, format, ##arg) 229 #define mlx4_warn(mdev, format, arg...) \ 230 dev_warn(&mdev->pdev->dev, format, ##arg) 231 232 extern int mlx4_log_num_mgm_entry_size; 233 extern int log_mtts_per_seg; 234 235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 236 #define ALL_SLAVES 0xff 237 238 struct mlx4_bitmap { 239 u32 last; 240 u32 top; 241 u32 max; 242 u32 reserved_top; 243 u32 mask; 244 u32 avail; 245 spinlock_t lock; 246 unsigned long *table; 247 }; 248 249 struct mlx4_buddy { 250 unsigned long **bits; 251 unsigned int *num_free; 252 u32 max_order; 253 spinlock_t lock; 254 }; 255 256 struct mlx4_icm; 257 258 struct mlx4_icm_table { 259 u64 virt; 260 int num_icm; 261 u32 num_obj; 262 int obj_size; 263 int lowmem; 264 int coherent; 265 struct mutex mutex; 266 struct mlx4_icm **icm; 267 }; 268 269 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 270 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 271 #define MLX4_MPT_FLAG_MIO (1 << 17) 272 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 273 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 274 #define MLX4_MPT_FLAG_REGION (1 << 8) 275 276 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 277 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 278 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 279 280 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 281 282 #define MLX4_MPT_STATUS_SW 0xF0 283 #define MLX4_MPT_STATUS_HW 0x00 284 285 /* 286 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 287 */ 288 struct mlx4_mpt_entry { 289 __be32 flags; 290 __be32 qpn; 291 __be32 key; 292 __be32 pd_flags; 293 __be64 start; 294 __be64 length; 295 __be32 lkey; 296 __be32 win_cnt; 297 u8 reserved1[3]; 298 u8 mtt_rep; 299 __be64 mtt_addr; 300 __be32 mtt_sz; 301 __be32 entity_size; 302 __be32 first_byte_offset; 303 } __packed; 304 305 /* 306 * Must be packed because start is 64 bits but only aligned to 32 bits. 307 */ 308 struct mlx4_eq_context { 309 __be32 flags; 310 u16 reserved1[3]; 311 __be16 page_offset; 312 u8 log_eq_size; 313 u8 reserved2[4]; 314 u8 eq_period; 315 u8 reserved3; 316 u8 eq_max_count; 317 u8 reserved4[3]; 318 u8 intr; 319 u8 log_page_size; 320 u8 reserved5[2]; 321 u8 mtt_base_addr_h; 322 __be32 mtt_base_addr_l; 323 u32 reserved6[2]; 324 __be32 consumer_index; 325 __be32 producer_index; 326 u32 reserved7[4]; 327 }; 328 329 struct mlx4_cq_context { 330 __be32 flags; 331 u16 reserved1[3]; 332 __be16 page_offset; 333 __be32 logsize_usrpage; 334 __be16 cq_period; 335 __be16 cq_max_count; 336 u8 reserved2[3]; 337 u8 comp_eqn; 338 u8 log_page_size; 339 u8 reserved3[2]; 340 u8 mtt_base_addr_h; 341 __be32 mtt_base_addr_l; 342 __be32 last_notified_index; 343 __be32 solicit_producer_index; 344 __be32 consumer_index; 345 __be32 producer_index; 346 u32 reserved4[2]; 347 __be64 db_rec_addr; 348 }; 349 350 struct mlx4_srq_context { 351 __be32 state_logsize_srqn; 352 u8 logstride; 353 u8 reserved1; 354 __be16 xrcd; 355 __be32 pg_offset_cqn; 356 u32 reserved2; 357 u8 log_page_size; 358 u8 reserved3[2]; 359 u8 mtt_base_addr_h; 360 __be32 mtt_base_addr_l; 361 __be32 pd; 362 __be16 limit_watermark; 363 __be16 wqe_cnt; 364 u16 reserved4; 365 __be16 wqe_counter; 366 u32 reserved5; 367 __be64 db_rec_addr; 368 }; 369 370 struct mlx4_eq { 371 struct mlx4_dev *dev; 372 void __iomem *doorbell; 373 int eqn; 374 u32 cons_index; 375 u16 irq; 376 u16 have_irq; 377 int nent; 378 struct mlx4_buf_list *page_list; 379 struct mlx4_mtt mtt; 380 }; 381 382 struct mlx4_slave_eqe { 383 u8 type; 384 u8 port; 385 u32 param; 386 }; 387 388 struct mlx4_slave_event_eq_info { 389 int eqn; 390 u16 token; 391 }; 392 393 struct mlx4_profile { 394 int num_qp; 395 int rdmarc_per_qp; 396 int num_srq; 397 int num_cq; 398 int num_mcg; 399 int num_mpt; 400 unsigned num_mtt; 401 }; 402 403 struct mlx4_fw { 404 u64 clr_int_base; 405 u64 catas_offset; 406 u64 comm_base; 407 u64 clock_offset; 408 struct mlx4_icm *fw_icm; 409 struct mlx4_icm *aux_icm; 410 u32 catas_size; 411 u16 fw_pages; 412 u8 clr_int_bar; 413 u8 catas_bar; 414 u8 comm_bar; 415 u8 clock_bar; 416 }; 417 418 struct mlx4_comm { 419 u32 slave_write; 420 u32 slave_read; 421 }; 422 423 enum { 424 MLX4_MCAST_CONFIG = 0, 425 MLX4_MCAST_DISABLE = 1, 426 MLX4_MCAST_ENABLE = 2, 427 }; 428 429 #define VLAN_FLTR_SIZE 128 430 431 struct mlx4_vlan_fltr { 432 __be32 entry[VLAN_FLTR_SIZE]; 433 }; 434 435 struct mlx4_mcast_entry { 436 struct list_head list; 437 u64 addr; 438 }; 439 440 struct mlx4_promisc_qp { 441 struct list_head list; 442 u32 qpn; 443 }; 444 445 struct mlx4_steer_index { 446 struct list_head list; 447 unsigned int index; 448 struct list_head duplicates; 449 }; 450 451 #define MLX4_EVENT_TYPES_NUM 64 452 453 struct mlx4_slave_state { 454 u8 comm_toggle; 455 u8 last_cmd; 456 u8 init_port_mask; 457 bool active; 458 u8 function; 459 dma_addr_t vhcr_dma; 460 u16 mtu[MLX4_MAX_PORTS + 1]; 461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 465 /* event type to eq number lookup */ 466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 467 u16 eq_pi; 468 u16 eq_ci; 469 spinlock_t lock; 470 /*initialized via the kzalloc*/ 471 u8 is_slave_going_down; 472 u32 cookie; 473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 474 }; 475 476 #define MLX4_VGT 4095 477 #define NO_INDX (-1) 478 479 struct mlx4_vport_state { 480 u64 mac; 481 u16 default_vlan; 482 u8 default_qos; 483 u32 tx_rate; 484 bool spoofchk; 485 u32 link_state; 486 }; 487 488 struct mlx4_vf_admin_state { 489 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 490 }; 491 492 struct mlx4_vport_oper_state { 493 struct mlx4_vport_state state; 494 int mac_idx; 495 int vlan_idx; 496 }; 497 struct mlx4_vf_oper_state { 498 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 499 }; 500 501 struct slave_list { 502 struct mutex mutex; 503 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 504 }; 505 506 struct mlx4_resource_tracker { 507 spinlock_t lock; 508 /* tree for each resources */ 509 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 510 /* num_of_slave's lists, one per slave */ 511 struct slave_list *slave_list; 512 }; 513 514 #define SLAVE_EVENT_EQ_SIZE 128 515 struct mlx4_slave_event_eq { 516 u32 eqn; 517 u32 cons; 518 u32 prod; 519 spinlock_t event_lock; 520 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 521 }; 522 523 struct mlx4_master_qp0_state { 524 int proxy_qp0_active; 525 int qp0_active; 526 int port_active; 527 }; 528 529 struct mlx4_mfunc_master_ctx { 530 struct mlx4_slave_state *slave_state; 531 struct mlx4_vf_admin_state *vf_admin; 532 struct mlx4_vf_oper_state *vf_oper; 533 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 534 int init_port_ref[MLX4_MAX_PORTS + 1]; 535 u16 max_mtu[MLX4_MAX_PORTS + 1]; 536 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 537 struct mlx4_resource_tracker res_tracker; 538 struct workqueue_struct *comm_wq; 539 struct work_struct comm_work; 540 struct work_struct slave_event_work; 541 struct work_struct slave_flr_event_work; 542 spinlock_t slave_state_lock; 543 __be32 comm_arm_bit_vector[4]; 544 struct mlx4_eqe cmd_eqe; 545 struct mlx4_slave_event_eq slave_eq; 546 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 547 }; 548 549 struct mlx4_mfunc { 550 struct mlx4_comm __iomem *comm; 551 struct mlx4_vhcr_cmd *vhcr; 552 dma_addr_t vhcr_dma; 553 554 struct mlx4_mfunc_master_ctx master; 555 }; 556 557 #define MGM_QPN_MASK 0x00FFFFFF 558 #define MGM_BLCK_LB_BIT 30 559 560 struct mlx4_mgm { 561 __be32 next_gid_index; 562 __be32 members_count; 563 u32 reserved[2]; 564 u8 gid[16]; 565 __be32 qp[MLX4_MAX_QP_PER_MGM]; 566 }; 567 568 struct mlx4_cmd { 569 struct pci_pool *pool; 570 void __iomem *hcr; 571 struct mutex hcr_mutex; 572 struct mutex slave_cmd_mutex; 573 struct semaphore poll_sem; 574 struct semaphore event_sem; 575 int max_cmds; 576 spinlock_t context_lock; 577 int free_head; 578 struct mlx4_cmd_context *context; 579 u16 token_mask; 580 u8 use_events; 581 u8 toggle; 582 u8 comm_toggle; 583 }; 584 585 enum { 586 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 587 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 588 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 589 }; 590 struct mlx4_vf_immed_vlan_work { 591 struct work_struct work; 592 struct mlx4_priv *priv; 593 int flags; 594 int slave; 595 int vlan_ix; 596 int orig_vlan_ix; 597 u8 port; 598 u8 qos; 599 u16 vlan_id; 600 u16 orig_vlan_id; 601 }; 602 603 604 struct mlx4_uar_table { 605 struct mlx4_bitmap bitmap; 606 }; 607 608 struct mlx4_mr_table { 609 struct mlx4_bitmap mpt_bitmap; 610 struct mlx4_buddy mtt_buddy; 611 u64 mtt_base; 612 u64 mpt_base; 613 struct mlx4_icm_table mtt_table; 614 struct mlx4_icm_table dmpt_table; 615 }; 616 617 struct mlx4_cq_table { 618 struct mlx4_bitmap bitmap; 619 spinlock_t lock; 620 struct radix_tree_root tree; 621 struct mlx4_icm_table table; 622 struct mlx4_icm_table cmpt_table; 623 }; 624 625 struct mlx4_eq_table { 626 struct mlx4_bitmap bitmap; 627 char *irq_names; 628 void __iomem *clr_int; 629 void __iomem **uar_map; 630 u32 clr_mask; 631 struct mlx4_eq *eq; 632 struct mlx4_icm_table table; 633 struct mlx4_icm_table cmpt_table; 634 int have_irq; 635 u8 inta_pin; 636 }; 637 638 struct mlx4_srq_table { 639 struct mlx4_bitmap bitmap; 640 spinlock_t lock; 641 struct radix_tree_root tree; 642 struct mlx4_icm_table table; 643 struct mlx4_icm_table cmpt_table; 644 }; 645 646 struct mlx4_qp_table { 647 struct mlx4_bitmap bitmap; 648 u32 rdmarc_base; 649 int rdmarc_shift; 650 spinlock_t lock; 651 struct mlx4_icm_table qp_table; 652 struct mlx4_icm_table auxc_table; 653 struct mlx4_icm_table altc_table; 654 struct mlx4_icm_table rdmarc_table; 655 struct mlx4_icm_table cmpt_table; 656 }; 657 658 struct mlx4_mcg_table { 659 struct mutex mutex; 660 struct mlx4_bitmap bitmap; 661 struct mlx4_icm_table table; 662 }; 663 664 struct mlx4_catas_err { 665 u32 __iomem *map; 666 struct timer_list timer; 667 struct list_head list; 668 }; 669 670 #define MLX4_MAX_MAC_NUM 128 671 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 672 673 struct mlx4_mac_table { 674 __be64 entries[MLX4_MAX_MAC_NUM]; 675 int refs[MLX4_MAX_MAC_NUM]; 676 struct mutex mutex; 677 int total; 678 int max; 679 }; 680 681 #define MLX4_MAX_VLAN_NUM 128 682 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 683 684 struct mlx4_vlan_table { 685 __be32 entries[MLX4_MAX_VLAN_NUM]; 686 int refs[MLX4_MAX_VLAN_NUM]; 687 struct mutex mutex; 688 int total; 689 int max; 690 }; 691 692 #define SET_PORT_GEN_ALL_VALID 0x7 693 #define SET_PORT_PROMISC_SHIFT 31 694 #define SET_PORT_MC_PROMISC_SHIFT 30 695 696 enum { 697 MCAST_DIRECT_ONLY = 0, 698 MCAST_DIRECT = 1, 699 MCAST_DEFAULT = 2 700 }; 701 702 703 struct mlx4_set_port_general_context { 704 u8 reserved[3]; 705 u8 flags; 706 u16 reserved2; 707 __be16 mtu; 708 u8 pptx; 709 u8 pfctx; 710 u16 reserved3; 711 u8 pprx; 712 u8 pfcrx; 713 u16 reserved4; 714 }; 715 716 struct mlx4_set_port_rqp_calc_context { 717 __be32 base_qpn; 718 u8 rererved; 719 u8 n_mac; 720 u8 n_vlan; 721 u8 n_prio; 722 u8 reserved2[3]; 723 u8 mac_miss; 724 u8 intra_no_vlan; 725 u8 no_vlan; 726 u8 intra_vlan_miss; 727 u8 vlan_miss; 728 u8 reserved3[3]; 729 u8 no_vlan_prio; 730 __be32 promisc; 731 __be32 mcast; 732 }; 733 734 struct mlx4_port_info { 735 struct mlx4_dev *dev; 736 int port; 737 char dev_name[16]; 738 struct device_attribute port_attr; 739 enum mlx4_port_type tmp_type; 740 char dev_mtu_name[16]; 741 struct device_attribute port_mtu_attr; 742 struct mlx4_mac_table mac_table; 743 struct mlx4_vlan_table vlan_table; 744 int base_qpn; 745 }; 746 747 struct mlx4_sense { 748 struct mlx4_dev *dev; 749 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 750 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 751 struct delayed_work sense_poll; 752 }; 753 754 struct mlx4_msix_ctl { 755 u64 pool_bm; 756 struct mutex pool_lock; 757 }; 758 759 struct mlx4_steer { 760 struct list_head promisc_qps[MLX4_NUM_STEERS]; 761 struct list_head steer_entries[MLX4_NUM_STEERS]; 762 }; 763 764 enum { 765 MLX4_PCI_DEV_IS_VF = 1 << 0, 766 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 767 }; 768 769 struct mlx4_priv { 770 struct mlx4_dev dev; 771 772 struct list_head dev_list; 773 struct list_head ctx_list; 774 spinlock_t ctx_lock; 775 776 int pci_dev_data; 777 778 struct list_head pgdir_list; 779 struct mutex pgdir_mutex; 780 781 struct mlx4_fw fw; 782 struct mlx4_cmd cmd; 783 struct mlx4_mfunc mfunc; 784 785 struct mlx4_bitmap pd_bitmap; 786 struct mlx4_bitmap xrcd_bitmap; 787 struct mlx4_uar_table uar_table; 788 struct mlx4_mr_table mr_table; 789 struct mlx4_cq_table cq_table; 790 struct mlx4_eq_table eq_table; 791 struct mlx4_srq_table srq_table; 792 struct mlx4_qp_table qp_table; 793 struct mlx4_mcg_table mcg_table; 794 struct mlx4_bitmap counters_bitmap; 795 796 struct mlx4_catas_err catas_err; 797 798 void __iomem *clr_base; 799 800 struct mlx4_uar driver_uar; 801 void __iomem *kar; 802 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 803 struct mlx4_sense sense; 804 struct mutex port_mutex; 805 struct mlx4_msix_ctl msix_ctl; 806 struct mlx4_steer *steer; 807 struct list_head bf_list; 808 struct mutex bf_mutex; 809 struct io_mapping *bf_mapping; 810 void __iomem *clock_mapping; 811 int reserved_mtts; 812 int fs_hash_mode; 813 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 814 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 815 816 atomic_t opreq_count; 817 struct work_struct opreq_task; 818 }; 819 820 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 821 { 822 return container_of(dev, struct mlx4_priv, dev); 823 } 824 825 #define MLX4_SENSE_RANGE (HZ * 3) 826 827 extern struct workqueue_struct *mlx4_wq; 828 829 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 830 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 831 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 832 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 833 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 834 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 835 u32 reserved_bot, u32 resetrved_top); 836 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 837 838 int mlx4_reset(struct mlx4_dev *dev); 839 840 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 841 void mlx4_free_eq_table(struct mlx4_dev *dev); 842 843 int mlx4_init_pd_table(struct mlx4_dev *dev); 844 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 845 int mlx4_init_uar_table(struct mlx4_dev *dev); 846 int mlx4_init_mr_table(struct mlx4_dev *dev); 847 int mlx4_init_eq_table(struct mlx4_dev *dev); 848 int mlx4_init_cq_table(struct mlx4_dev *dev); 849 int mlx4_init_qp_table(struct mlx4_dev *dev); 850 int mlx4_init_srq_table(struct mlx4_dev *dev); 851 int mlx4_init_mcg_table(struct mlx4_dev *dev); 852 853 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 854 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 855 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 856 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 857 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 858 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 859 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 860 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 861 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 862 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 863 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 864 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 865 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 866 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 867 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 868 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 869 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 870 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index); 871 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 872 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 873 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 874 875 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 876 struct mlx4_vhcr *vhcr, 877 struct mlx4_cmd_mailbox *inbox, 878 struct mlx4_cmd_mailbox *outbox, 879 struct mlx4_cmd_info *cmd); 880 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 881 struct mlx4_vhcr *vhcr, 882 struct mlx4_cmd_mailbox *inbox, 883 struct mlx4_cmd_mailbox *outbox, 884 struct mlx4_cmd_info *cmd); 885 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 886 struct mlx4_vhcr *vhcr, 887 struct mlx4_cmd_mailbox *inbox, 888 struct mlx4_cmd_mailbox *outbox, 889 struct mlx4_cmd_info *cmd); 890 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 891 struct mlx4_vhcr *vhcr, 892 struct mlx4_cmd_mailbox *inbox, 893 struct mlx4_cmd_mailbox *outbox, 894 struct mlx4_cmd_info *cmd); 895 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 896 struct mlx4_vhcr *vhcr, 897 struct mlx4_cmd_mailbox *inbox, 898 struct mlx4_cmd_mailbox *outbox, 899 struct mlx4_cmd_info *cmd); 900 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 901 struct mlx4_vhcr *vhcr, 902 struct mlx4_cmd_mailbox *inbox, 903 struct mlx4_cmd_mailbox *outbox, 904 struct mlx4_cmd_info *cmd); 905 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 906 struct mlx4_vhcr *vhcr, 907 struct mlx4_cmd_mailbox *inbox, 908 struct mlx4_cmd_mailbox *outbox, 909 struct mlx4_cmd_info *cmd); 910 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 911 int *base); 912 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 913 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 914 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 915 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 916 int start_index, int npages, u64 *page_list); 917 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 918 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 919 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 920 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 921 922 void mlx4_start_catas_poll(struct mlx4_dev *dev); 923 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 924 void mlx4_catas_init(void); 925 int mlx4_restart_one(struct pci_dev *pdev); 926 int mlx4_register_device(struct mlx4_dev *dev); 927 void mlx4_unregister_device(struct mlx4_dev *dev); 928 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 929 unsigned long param); 930 931 struct mlx4_dev_cap; 932 struct mlx4_init_hca_param; 933 934 u64 mlx4_make_profile(struct mlx4_dev *dev, 935 struct mlx4_profile *request, 936 struct mlx4_dev_cap *dev_cap, 937 struct mlx4_init_hca_param *init_hca); 938 void mlx4_master_comm_channel(struct work_struct *work); 939 void mlx4_gen_slave_eqe(struct work_struct *work); 940 void mlx4_master_handle_slave_flr(struct work_struct *work); 941 942 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 943 struct mlx4_vhcr *vhcr, 944 struct mlx4_cmd_mailbox *inbox, 945 struct mlx4_cmd_mailbox *outbox, 946 struct mlx4_cmd_info *cmd); 947 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 948 struct mlx4_vhcr *vhcr, 949 struct mlx4_cmd_mailbox *inbox, 950 struct mlx4_cmd_mailbox *outbox, 951 struct mlx4_cmd_info *cmd); 952 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 953 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 954 struct mlx4_cmd_mailbox *outbox, 955 struct mlx4_cmd_info *cmd); 956 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 957 struct mlx4_vhcr *vhcr, 958 struct mlx4_cmd_mailbox *inbox, 959 struct mlx4_cmd_mailbox *outbox, 960 struct mlx4_cmd_info *cmd); 961 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 962 struct mlx4_vhcr *vhcr, 963 struct mlx4_cmd_mailbox *inbox, 964 struct mlx4_cmd_mailbox *outbox, 965 struct mlx4_cmd_info *cmd); 966 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 967 struct mlx4_vhcr *vhcr, 968 struct mlx4_cmd_mailbox *inbox, 969 struct mlx4_cmd_mailbox *outbox, 970 struct mlx4_cmd_info *cmd); 971 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 972 struct mlx4_vhcr *vhcr, 973 struct mlx4_cmd_mailbox *inbox, 974 struct mlx4_cmd_mailbox *outbox, 975 struct mlx4_cmd_info *cmd); 976 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 977 struct mlx4_vhcr *vhcr, 978 struct mlx4_cmd_mailbox *inbox, 979 struct mlx4_cmd_mailbox *outbox, 980 struct mlx4_cmd_info *cmd); 981 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 982 struct mlx4_vhcr *vhcr, 983 struct mlx4_cmd_mailbox *inbox, 984 struct mlx4_cmd_mailbox *outbox, 985 struct mlx4_cmd_info *cmd); 986 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 987 struct mlx4_vhcr *vhcr, 988 struct mlx4_cmd_mailbox *inbox, 989 struct mlx4_cmd_mailbox *outbox, 990 struct mlx4_cmd_info *cmd); 991 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 992 struct mlx4_vhcr *vhcr, 993 struct mlx4_cmd_mailbox *inbox, 994 struct mlx4_cmd_mailbox *outbox, 995 struct mlx4_cmd_info *cmd); 996 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 997 struct mlx4_vhcr *vhcr, 998 struct mlx4_cmd_mailbox *inbox, 999 struct mlx4_cmd_mailbox *outbox, 1000 struct mlx4_cmd_info *cmd); 1001 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1002 struct mlx4_vhcr *vhcr, 1003 struct mlx4_cmd_mailbox *inbox, 1004 struct mlx4_cmd_mailbox *outbox, 1005 struct mlx4_cmd_info *cmd); 1006 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1007 struct mlx4_vhcr *vhcr, 1008 struct mlx4_cmd_mailbox *inbox, 1009 struct mlx4_cmd_mailbox *outbox, 1010 struct mlx4_cmd_info *cmd); 1011 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1012 struct mlx4_vhcr *vhcr, 1013 struct mlx4_cmd_mailbox *inbox, 1014 struct mlx4_cmd_mailbox *outbox, 1015 struct mlx4_cmd_info *cmd); 1016 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1017 struct mlx4_vhcr *vhcr, 1018 struct mlx4_cmd_mailbox *inbox, 1019 struct mlx4_cmd_mailbox *outbox, 1020 struct mlx4_cmd_info *cmd); 1021 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1022 struct mlx4_vhcr *vhcr, 1023 struct mlx4_cmd_mailbox *inbox, 1024 struct mlx4_cmd_mailbox *outbox, 1025 struct mlx4_cmd_info *cmd); 1026 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1027 struct mlx4_vhcr *vhcr, 1028 struct mlx4_cmd_mailbox *inbox, 1029 struct mlx4_cmd_mailbox *outbox, 1030 struct mlx4_cmd_info *cmd); 1031 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1032 struct mlx4_vhcr *vhcr, 1033 struct mlx4_cmd_mailbox *inbox, 1034 struct mlx4_cmd_mailbox *outbox, 1035 struct mlx4_cmd_info *cmd); 1036 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1037 struct mlx4_vhcr *vhcr, 1038 struct mlx4_cmd_mailbox *inbox, 1039 struct mlx4_cmd_mailbox *outbox, 1040 struct mlx4_cmd_info *cmd); 1041 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1047 struct mlx4_vhcr *vhcr, 1048 struct mlx4_cmd_mailbox *inbox, 1049 struct mlx4_cmd_mailbox *outbox, 1050 struct mlx4_cmd_info *cmd); 1051 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 1077 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1078 1079 int mlx4_cmd_init(struct mlx4_dev *dev); 1080 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 1081 int mlx4_multi_func_init(struct mlx4_dev *dev); 1082 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1083 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1084 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1085 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1086 1087 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1088 unsigned long timeout); 1089 1090 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1091 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1092 1093 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1094 1095 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1096 1097 void mlx4_handle_catas_err(struct mlx4_dev *dev); 1098 1099 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1100 enum mlx4_port_type *type); 1101 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1102 enum mlx4_port_type *stype, 1103 enum mlx4_port_type *defaults); 1104 void mlx4_start_sense(struct mlx4_dev *dev); 1105 void mlx4_stop_sense(struct mlx4_dev *dev); 1106 void mlx4_sense_init(struct mlx4_dev *dev); 1107 int mlx4_check_port_params(struct mlx4_dev *dev, 1108 enum mlx4_port_type *port_type); 1109 int mlx4_change_port_types(struct mlx4_dev *dev, 1110 enum mlx4_port_type *port_types); 1111 1112 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1113 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1114 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 1115 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1116 1117 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1118 /* resource tracker functions*/ 1119 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1120 enum mlx4_resource resource_type, 1121 u64 resource_id, int *slave); 1122 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1123 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1124 1125 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1126 enum mlx4_res_tracker_free_type type); 1127 1128 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1129 struct mlx4_vhcr *vhcr, 1130 struct mlx4_cmd_mailbox *inbox, 1131 struct mlx4_cmd_mailbox *outbox, 1132 struct mlx4_cmd_info *cmd); 1133 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1134 struct mlx4_vhcr *vhcr, 1135 struct mlx4_cmd_mailbox *inbox, 1136 struct mlx4_cmd_mailbox *outbox, 1137 struct mlx4_cmd_info *cmd); 1138 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1139 struct mlx4_vhcr *vhcr, 1140 struct mlx4_cmd_mailbox *inbox, 1141 struct mlx4_cmd_mailbox *outbox, 1142 struct mlx4_cmd_info *cmd); 1143 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1144 struct mlx4_vhcr *vhcr, 1145 struct mlx4_cmd_mailbox *inbox, 1146 struct mlx4_cmd_mailbox *outbox, 1147 struct mlx4_cmd_info *cmd); 1148 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1149 struct mlx4_vhcr *vhcr, 1150 struct mlx4_cmd_mailbox *inbox, 1151 struct mlx4_cmd_mailbox *outbox, 1152 struct mlx4_cmd_info *cmd); 1153 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1154 struct mlx4_vhcr *vhcr, 1155 struct mlx4_cmd_mailbox *inbox, 1156 struct mlx4_cmd_mailbox *outbox, 1157 struct mlx4_cmd_info *cmd); 1158 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1159 1160 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1161 int *gid_tbl_len, int *pkey_tbl_len); 1162 1163 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1164 struct mlx4_vhcr *vhcr, 1165 struct mlx4_cmd_mailbox *inbox, 1166 struct mlx4_cmd_mailbox *outbox, 1167 struct mlx4_cmd_info *cmd); 1168 1169 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1170 struct mlx4_vhcr *vhcr, 1171 struct mlx4_cmd_mailbox *inbox, 1172 struct mlx4_cmd_mailbox *outbox, 1173 struct mlx4_cmd_info *cmd); 1174 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1175 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1176 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1177 int block_mcast_loopback, enum mlx4_protocol prot, 1178 enum mlx4_steer_type steer); 1179 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1180 u8 gid[16], u8 port, 1181 int block_mcast_loopback, 1182 enum mlx4_protocol prot, u64 *reg_id); 1183 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1184 struct mlx4_vhcr *vhcr, 1185 struct mlx4_cmd_mailbox *inbox, 1186 struct mlx4_cmd_mailbox *outbox, 1187 struct mlx4_cmd_info *cmd); 1188 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1189 struct mlx4_vhcr *vhcr, 1190 struct mlx4_cmd_mailbox *inbox, 1191 struct mlx4_cmd_mailbox *outbox, 1192 struct mlx4_cmd_info *cmd); 1193 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1194 int port, void *buf); 1195 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1196 struct mlx4_cmd_mailbox *outbox); 1197 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1198 struct mlx4_vhcr *vhcr, 1199 struct mlx4_cmd_mailbox *inbox, 1200 struct mlx4_cmd_mailbox *outbox, 1201 struct mlx4_cmd_info *cmd); 1202 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1203 struct mlx4_vhcr *vhcr, 1204 struct mlx4_cmd_mailbox *inbox, 1205 struct mlx4_cmd_mailbox *outbox, 1206 struct mlx4_cmd_info *cmd); 1207 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1208 struct mlx4_vhcr *vhcr, 1209 struct mlx4_cmd_mailbox *inbox, 1210 struct mlx4_cmd_mailbox *outbox, 1211 struct mlx4_cmd_info *cmd); 1212 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1213 struct mlx4_vhcr *vhcr, 1214 struct mlx4_cmd_mailbox *inbox, 1215 struct mlx4_cmd_mailbox *outbox, 1216 struct mlx4_cmd_info *cmd); 1217 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1218 struct mlx4_vhcr *vhcr, 1219 struct mlx4_cmd_mailbox *inbox, 1220 struct mlx4_cmd_mailbox *outbox, 1221 struct mlx4_cmd_info *cmd); 1222 1223 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1224 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1225 1226 static inline void set_param_l(u64 *arg, u32 val) 1227 { 1228 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1229 } 1230 1231 static inline void set_param_h(u64 *arg, u32 val) 1232 { 1233 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1234 } 1235 1236 static inline u32 get_param_l(u64 *arg) 1237 { 1238 return (u32) (*arg & 0xffffffff); 1239 } 1240 1241 static inline u32 get_param_h(u64 *arg) 1242 { 1243 return (u32)(*arg >> 32); 1244 } 1245 1246 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1247 { 1248 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1249 } 1250 1251 #define NOT_MASKED_PD_BITS 17 1252 1253 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1254 1255 #endif /* MLX4_H */ 1256