1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 #include <net/devlink.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/driver.h> 52 #include <linux/mlx4/doorbell.h> 53 #include <linux/mlx4/cmd.h> 54 #include "fw_qos.h" 55 56 #define DRV_NAME "mlx4_core" 57 #define PFX DRV_NAME ": " 58 #define DRV_VERSION "2.2-1" 59 #define DRV_RELDATE "Feb, 2014" 60 61 #define MLX4_FS_UDP_UC_EN (1 << 1) 62 #define MLX4_FS_TCP_UC_EN (1 << 2) 63 #define MLX4_FS_NUM_OF_L2_ADDR 8 64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 65 #define MLX4_FS_NUM_MCG (1 << 17) 66 67 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 68 69 #define MLX4_QUERY_IF_STAT_RESET BIT(31) 70 71 enum { 72 MLX4_HCR_BASE = 0x80680, 73 MLX4_HCR_SIZE = 0x0001c, 74 MLX4_CLR_INT_SIZE = 0x00008, 75 MLX4_SLAVE_COMM_BASE = 0x0, 76 MLX4_COMM_PAGESIZE = 0x1000, 77 MLX4_CLOCK_SIZE = 0x00008, 78 MLX4_COMM_CHAN_CAPS = 0x8, 79 MLX4_COMM_CHAN_FLAGS = 0xc 80 }; 81 82 enum { 83 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 84 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 85 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 86 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 87 MLX4_MTT_ENTRY_PER_SEG = 8, 88 }; 89 90 enum { 91 MLX4_NUM_PDS = 1 << 15 92 }; 93 94 enum { 95 MLX4_CMPT_TYPE_QP = 0, 96 MLX4_CMPT_TYPE_SRQ = 1, 97 MLX4_CMPT_TYPE_CQ = 2, 98 MLX4_CMPT_TYPE_EQ = 3, 99 MLX4_CMPT_NUM_TYPE 100 }; 101 102 enum { 103 MLX4_CMPT_SHIFT = 24, 104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 105 }; 106 107 enum mlx4_mpt_state { 108 MLX4_MPT_DISABLED = 0, 109 MLX4_MPT_EN_HW, 110 MLX4_MPT_EN_SW 111 }; 112 113 #define MLX4_COMM_TIME 10000 114 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 115 #define MLX4_COMM_CMD_NA_OP 0x0 116 117 118 enum { 119 MLX4_COMM_CMD_RESET, 120 MLX4_COMM_CMD_VHCR0, 121 MLX4_COMM_CMD_VHCR1, 122 MLX4_COMM_CMD_VHCR2, 123 MLX4_COMM_CMD_VHCR_EN, 124 MLX4_COMM_CMD_VHCR_POST, 125 MLX4_COMM_CMD_FLR = 254 126 }; 127 128 enum { 129 MLX4_VF_SMI_DISABLED, 130 MLX4_VF_SMI_ENABLED 131 }; 132 133 /*The flag indicates that the slave should delay the RESET cmd*/ 134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 135 /*indicates how many retries will be done if we are in the middle of FLR*/ 136 #define NUM_OF_RESET_RETRIES 10 137 #define SLEEP_TIME_IN_RESET (2 * 1000) 138 enum mlx4_resource { 139 RES_QP, 140 RES_CQ, 141 RES_SRQ, 142 RES_XRCD, 143 RES_MPT, 144 RES_MTT, 145 RES_MAC, 146 RES_VLAN, 147 RES_EQ, 148 RES_COUNTER, 149 RES_FS_RULE, 150 MLX4_NUM_OF_RESOURCE_TYPE 151 }; 152 153 enum mlx4_alloc_mode { 154 RES_OP_RESERVE, 155 RES_OP_RESERVE_AND_MAP, 156 RES_OP_MAP_ICM, 157 }; 158 159 enum mlx4_res_tracker_free_type { 160 RES_TR_FREE_ALL, 161 RES_TR_FREE_SLAVES_ONLY, 162 RES_TR_FREE_STRUCTS_ONLY, 163 }; 164 165 /* 166 *Virtual HCR structures. 167 * mlx4_vhcr is the sw representation, in machine endianness 168 * 169 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 170 * to FW to go through communication channel. 171 * It is big endian, and has the same structure as the physical HCR 172 * used by command interface 173 */ 174 struct mlx4_vhcr { 175 u64 in_param; 176 u64 out_param; 177 u32 in_modifier; 178 u32 errno; 179 u16 op; 180 u16 token; 181 u8 op_modifier; 182 u8 e_bit; 183 }; 184 185 struct mlx4_vhcr_cmd { 186 __be64 in_param; 187 __be32 in_modifier; 188 u32 reserved1; 189 __be64 out_param; 190 __be16 token; 191 u16 reserved; 192 u8 status; 193 u8 flags; 194 __be16 opcode; 195 }; 196 197 struct mlx4_cmd_info { 198 u16 opcode; 199 bool has_inbox; 200 bool has_outbox; 201 bool out_is_imm; 202 bool encode_slave_id; 203 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 204 struct mlx4_cmd_mailbox *inbox); 205 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox, 207 struct mlx4_cmd_mailbox *outbox, 208 struct mlx4_cmd_info *cmd); 209 }; 210 211 #ifdef CONFIG_MLX4_DEBUG 212 extern int mlx4_debug_level; 213 #else /* CONFIG_MLX4_DEBUG */ 214 #define mlx4_debug_level (0) 215 #endif /* CONFIG_MLX4_DEBUG */ 216 217 #define mlx4_dbg(mdev, format, ...) \ 218 do { \ 219 if (mlx4_debug_level) \ 220 dev_printk(KERN_DEBUG, \ 221 &(mdev)->persist->pdev->dev, format, \ 222 ##__VA_ARGS__); \ 223 } while (0) 224 225 #define mlx4_err(mdev, format, ...) \ 226 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 227 #define mlx4_info(mdev, format, ...) \ 228 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 229 #define mlx4_warn(mdev, format, ...) \ 230 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 231 232 extern int mlx4_log_num_mgm_entry_size; 233 extern int log_mtts_per_seg; 234 extern int mlx4_internal_err_reset; 235 236 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 237 MLX4_MFUNC_MAX)) 238 #define ALL_SLAVES 0xff 239 240 struct mlx4_bitmap { 241 u32 last; 242 u32 top; 243 u32 max; 244 u32 reserved_top; 245 u32 mask; 246 u32 avail; 247 u32 effective_len; 248 spinlock_t lock; 249 unsigned long *table; 250 }; 251 252 struct mlx4_buddy { 253 unsigned long **bits; 254 unsigned int *num_free; 255 u32 max_order; 256 spinlock_t lock; 257 }; 258 259 struct mlx4_icm; 260 261 struct mlx4_icm_table { 262 u64 virt; 263 int num_icm; 264 u32 num_obj; 265 int obj_size; 266 int lowmem; 267 int coherent; 268 struct mutex mutex; 269 struct mlx4_icm **icm; 270 }; 271 272 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 273 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 274 #define MLX4_MPT_FLAG_MIO (1 << 17) 275 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 276 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 277 #define MLX4_MPT_FLAG_REGION (1 << 8) 278 279 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 280 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 284 285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 286 287 #define MLX4_MPT_STATUS_SW 0xF0 288 #define MLX4_MPT_STATUS_HW 0x00 289 290 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 291 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 292 293 #define MLX4_EQ_ASYNC 0 294 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ 295 !!((int)(vector) >= MLX4_EQ_ASYNC)) 296 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ 297 !!((int)(vector) >= MLX4_EQ_ASYNC)) 298 299 /* 300 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 301 */ 302 struct mlx4_mpt_entry { 303 __be32 flags; 304 __be32 qpn; 305 __be32 key; 306 __be32 pd_flags; 307 __be64 start; 308 __be64 length; 309 __be32 lkey; 310 __be32 win_cnt; 311 u8 reserved1[3]; 312 u8 mtt_rep; 313 __be64 mtt_addr; 314 __be32 mtt_sz; 315 __be32 entity_size; 316 __be32 first_byte_offset; 317 } __packed; 318 319 /* 320 * Must be packed because start is 64 bits but only aligned to 32 bits. 321 */ 322 struct mlx4_eq_context { 323 __be32 flags; 324 u16 reserved1[3]; 325 __be16 page_offset; 326 u8 log_eq_size; 327 u8 reserved2[4]; 328 u8 eq_period; 329 u8 reserved3; 330 u8 eq_max_count; 331 u8 reserved4[3]; 332 u8 intr; 333 u8 log_page_size; 334 u8 reserved5[2]; 335 u8 mtt_base_addr_h; 336 __be32 mtt_base_addr_l; 337 u32 reserved6[2]; 338 __be32 consumer_index; 339 __be32 producer_index; 340 u32 reserved7[4]; 341 }; 342 343 struct mlx4_cq_context { 344 __be32 flags; 345 u16 reserved1[3]; 346 __be16 page_offset; 347 __be32 logsize_usrpage; 348 __be16 cq_period; 349 __be16 cq_max_count; 350 u8 reserved2[3]; 351 u8 comp_eqn; 352 u8 log_page_size; 353 u8 reserved3[2]; 354 u8 mtt_base_addr_h; 355 __be32 mtt_base_addr_l; 356 __be32 last_notified_index; 357 __be32 solicit_producer_index; 358 __be32 consumer_index; 359 __be32 producer_index; 360 u32 reserved4[2]; 361 __be64 db_rec_addr; 362 }; 363 364 struct mlx4_srq_context { 365 __be32 state_logsize_srqn; 366 u8 logstride; 367 u8 reserved1; 368 __be16 xrcd; 369 __be32 pg_offset_cqn; 370 u32 reserved2; 371 u8 log_page_size; 372 u8 reserved3[2]; 373 u8 mtt_base_addr_h; 374 __be32 mtt_base_addr_l; 375 __be32 pd; 376 __be16 limit_watermark; 377 __be16 wqe_cnt; 378 u16 reserved4; 379 __be16 wqe_counter; 380 u32 reserved5; 381 __be64 db_rec_addr; 382 }; 383 384 struct mlx4_eq_tasklet { 385 struct list_head list; 386 struct list_head process_list; 387 struct tasklet_struct task; 388 /* lock on completion tasklet list */ 389 spinlock_t lock; 390 }; 391 392 struct mlx4_eq { 393 struct mlx4_dev *dev; 394 void __iomem *doorbell; 395 int eqn; 396 u32 cons_index; 397 u16 irq; 398 u16 have_irq; 399 int nent; 400 struct mlx4_buf_list *page_list; 401 struct mlx4_mtt mtt; 402 struct mlx4_eq_tasklet tasklet_ctx; 403 struct mlx4_active_ports actv_ports; 404 u32 ref_count; 405 cpumask_var_t affinity_mask; 406 }; 407 408 struct mlx4_slave_eqe { 409 u8 type; 410 u8 port; 411 u32 param; 412 }; 413 414 struct mlx4_slave_event_eq_info { 415 int eqn; 416 u16 token; 417 }; 418 419 struct mlx4_profile { 420 int num_qp; 421 int rdmarc_per_qp; 422 int num_srq; 423 int num_cq; 424 int num_mcg; 425 int num_mpt; 426 unsigned num_mtt; 427 }; 428 429 struct mlx4_fw { 430 u64 clr_int_base; 431 u64 catas_offset; 432 u64 comm_base; 433 u64 clock_offset; 434 struct mlx4_icm *fw_icm; 435 struct mlx4_icm *aux_icm; 436 u32 catas_size; 437 u16 fw_pages; 438 u8 clr_int_bar; 439 u8 catas_bar; 440 u8 comm_bar; 441 u8 clock_bar; 442 }; 443 444 struct mlx4_comm { 445 u32 slave_write; 446 u32 slave_read; 447 }; 448 449 enum { 450 MLX4_MCAST_CONFIG = 0, 451 MLX4_MCAST_DISABLE = 1, 452 MLX4_MCAST_ENABLE = 2, 453 }; 454 455 #define VLAN_FLTR_SIZE 128 456 457 struct mlx4_vlan_fltr { 458 __be32 entry[VLAN_FLTR_SIZE]; 459 }; 460 461 struct mlx4_mcast_entry { 462 struct list_head list; 463 u64 addr; 464 }; 465 466 struct mlx4_promisc_qp { 467 struct list_head list; 468 u32 qpn; 469 }; 470 471 struct mlx4_steer_index { 472 struct list_head list; 473 unsigned int index; 474 struct list_head duplicates; 475 }; 476 477 #define MLX4_EVENT_TYPES_NUM 64 478 479 struct mlx4_slave_state { 480 u8 comm_toggle; 481 u8 last_cmd; 482 u8 init_port_mask; 483 bool active; 484 bool old_vlan_api; 485 u8 function; 486 dma_addr_t vhcr_dma; 487 u16 mtu[MLX4_MAX_PORTS + 1]; 488 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 489 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 490 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 491 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 492 /* event type to eq number lookup */ 493 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 494 u16 eq_pi; 495 u16 eq_ci; 496 spinlock_t lock; 497 /*initialized via the kzalloc*/ 498 u8 is_slave_going_down; 499 u32 cookie; 500 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 501 }; 502 503 #define MLX4_VGT 4095 504 #define NO_INDX (-1) 505 506 struct mlx4_vport_state { 507 u64 mac; 508 u16 default_vlan; 509 u8 default_qos; 510 u32 tx_rate; 511 bool spoofchk; 512 u32 link_state; 513 u8 qos_vport; 514 __be64 guid; 515 }; 516 517 struct mlx4_vf_admin_state { 518 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 519 u8 enable_smi[MLX4_MAX_PORTS + 1]; 520 }; 521 522 struct mlx4_vport_oper_state { 523 struct mlx4_vport_state state; 524 int mac_idx; 525 int vlan_idx; 526 }; 527 528 struct mlx4_vf_oper_state { 529 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 530 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 531 }; 532 533 struct slave_list { 534 struct mutex mutex; 535 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 536 }; 537 538 struct resource_allocator { 539 spinlock_t alloc_lock; /* protect quotas */ 540 union { 541 int res_reserved; 542 int res_port_rsvd[MLX4_MAX_PORTS]; 543 }; 544 union { 545 int res_free; 546 int res_port_free[MLX4_MAX_PORTS]; 547 }; 548 int *quota; 549 int *allocated; 550 int *guaranteed; 551 }; 552 553 struct mlx4_resource_tracker { 554 spinlock_t lock; 555 /* tree for each resources */ 556 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 557 /* num_of_slave's lists, one per slave */ 558 struct slave_list *slave_list; 559 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 560 }; 561 562 #define SLAVE_EVENT_EQ_SIZE 128 563 struct mlx4_slave_event_eq { 564 u32 eqn; 565 u32 cons; 566 u32 prod; 567 spinlock_t event_lock; 568 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 569 }; 570 571 struct mlx4_qos_manager { 572 int num_of_qos_vfs; 573 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 574 }; 575 576 struct mlx4_master_qp0_state { 577 int proxy_qp0_active; 578 int qp0_active; 579 int port_active; 580 }; 581 582 struct mlx4_mfunc_master_ctx { 583 struct mlx4_slave_state *slave_state; 584 struct mlx4_vf_admin_state *vf_admin; 585 struct mlx4_vf_oper_state *vf_oper; 586 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 587 int init_port_ref[MLX4_MAX_PORTS + 1]; 588 u16 max_mtu[MLX4_MAX_PORTS + 1]; 589 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 590 struct mlx4_resource_tracker res_tracker; 591 struct workqueue_struct *comm_wq; 592 struct work_struct comm_work; 593 struct work_struct slave_event_work; 594 struct work_struct slave_flr_event_work; 595 spinlock_t slave_state_lock; 596 __be32 comm_arm_bit_vector[4]; 597 struct mlx4_eqe cmd_eqe; 598 struct mlx4_slave_event_eq slave_eq; 599 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 600 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 601 }; 602 603 struct mlx4_mfunc { 604 struct mlx4_comm __iomem *comm; 605 struct mlx4_vhcr_cmd *vhcr; 606 dma_addr_t vhcr_dma; 607 608 struct mlx4_mfunc_master_ctx master; 609 }; 610 611 #define MGM_QPN_MASK 0x00FFFFFF 612 #define MGM_BLCK_LB_BIT 30 613 614 struct mlx4_mgm { 615 __be32 next_gid_index; 616 __be32 members_count; 617 u32 reserved[2]; 618 u8 gid[16]; 619 __be32 qp[MLX4_MAX_QP_PER_MGM]; 620 }; 621 622 struct mlx4_cmd { 623 struct pci_pool *pool; 624 void __iomem *hcr; 625 struct mutex slave_cmd_mutex; 626 struct semaphore poll_sem; 627 struct semaphore event_sem; 628 int max_cmds; 629 spinlock_t context_lock; 630 int free_head; 631 struct mlx4_cmd_context *context; 632 u16 token_mask; 633 u8 use_events; 634 u8 toggle; 635 u8 comm_toggle; 636 u8 initialized; 637 }; 638 639 enum { 640 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 641 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 642 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 643 }; 644 struct mlx4_vf_immed_vlan_work { 645 struct work_struct work; 646 struct mlx4_priv *priv; 647 int flags; 648 int slave; 649 int vlan_ix; 650 int orig_vlan_ix; 651 u8 port; 652 u8 qos; 653 u8 qos_vport; 654 u16 vlan_id; 655 u16 orig_vlan_id; 656 }; 657 658 659 struct mlx4_uar_table { 660 struct mlx4_bitmap bitmap; 661 }; 662 663 struct mlx4_mr_table { 664 struct mlx4_bitmap mpt_bitmap; 665 struct mlx4_buddy mtt_buddy; 666 u64 mtt_base; 667 u64 mpt_base; 668 struct mlx4_icm_table mtt_table; 669 struct mlx4_icm_table dmpt_table; 670 }; 671 672 struct mlx4_cq_table { 673 struct mlx4_bitmap bitmap; 674 spinlock_t lock; 675 struct radix_tree_root tree; 676 struct mlx4_icm_table table; 677 struct mlx4_icm_table cmpt_table; 678 }; 679 680 struct mlx4_eq_table { 681 struct mlx4_bitmap bitmap; 682 char *irq_names; 683 void __iomem *clr_int; 684 void __iomem **uar_map; 685 u32 clr_mask; 686 struct mlx4_eq *eq; 687 struct mlx4_icm_table table; 688 struct mlx4_icm_table cmpt_table; 689 int have_irq; 690 u8 inta_pin; 691 }; 692 693 struct mlx4_srq_table { 694 struct mlx4_bitmap bitmap; 695 spinlock_t lock; 696 struct radix_tree_root tree; 697 struct mlx4_icm_table table; 698 struct mlx4_icm_table cmpt_table; 699 }; 700 701 enum mlx4_qp_table_zones { 702 MLX4_QP_TABLE_ZONE_GENERAL, 703 MLX4_QP_TABLE_ZONE_RSS, 704 MLX4_QP_TABLE_ZONE_RAW_ETH, 705 MLX4_QP_TABLE_ZONE_NUM 706 }; 707 708 struct mlx4_qp_table { 709 struct mlx4_bitmap *bitmap_gen; 710 struct mlx4_zone_allocator *zones; 711 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 712 u32 rdmarc_base; 713 int rdmarc_shift; 714 spinlock_t lock; 715 struct mlx4_icm_table qp_table; 716 struct mlx4_icm_table auxc_table; 717 struct mlx4_icm_table altc_table; 718 struct mlx4_icm_table rdmarc_table; 719 struct mlx4_icm_table cmpt_table; 720 }; 721 722 struct mlx4_mcg_table { 723 struct mutex mutex; 724 struct mlx4_bitmap bitmap; 725 struct mlx4_icm_table table; 726 }; 727 728 struct mlx4_catas_err { 729 u32 __iomem *map; 730 struct timer_list timer; 731 struct list_head list; 732 }; 733 734 #define MLX4_MAX_MAC_NUM 128 735 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 736 737 struct mlx4_mac_table { 738 __be64 entries[MLX4_MAX_MAC_NUM]; 739 int refs[MLX4_MAX_MAC_NUM]; 740 bool is_dup[MLX4_MAX_MAC_NUM]; 741 struct mutex mutex; 742 int total; 743 int max; 744 }; 745 746 #define MLX4_ROCE_GID_ENTRY_SIZE 16 747 748 struct mlx4_roce_gid_entry { 749 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 750 }; 751 752 struct mlx4_roce_gid_table { 753 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 754 struct mutex mutex; 755 }; 756 757 #define MLX4_MAX_VLAN_NUM 128 758 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 759 760 struct mlx4_vlan_table { 761 __be32 entries[MLX4_MAX_VLAN_NUM]; 762 int refs[MLX4_MAX_VLAN_NUM]; 763 int is_dup[MLX4_MAX_VLAN_NUM]; 764 struct mutex mutex; 765 int total; 766 int max; 767 }; 768 769 #define SET_PORT_GEN_ALL_VALID 0x7 770 #define SET_PORT_PROMISC_SHIFT 31 771 #define SET_PORT_MC_PROMISC_SHIFT 30 772 773 enum { 774 MCAST_DIRECT_ONLY = 0, 775 MCAST_DIRECT = 1, 776 MCAST_DEFAULT = 2 777 }; 778 779 780 struct mlx4_set_port_general_context { 781 u16 reserved1; 782 u8 v_ignore_fcs; 783 u8 flags; 784 union { 785 u8 ignore_fcs; 786 u8 roce_mode; 787 }; 788 u8 reserved2; 789 __be16 mtu; 790 u8 pptx; 791 u8 pfctx; 792 u16 reserved3; 793 u8 pprx; 794 u8 pfcrx; 795 u16 reserved4; 796 u32 reserved5; 797 u8 phv_en; 798 u8 reserved6[3]; 799 }; 800 801 struct mlx4_set_port_rqp_calc_context { 802 __be32 base_qpn; 803 u8 rererved; 804 u8 n_mac; 805 u8 n_vlan; 806 u8 n_prio; 807 u8 reserved2[3]; 808 u8 mac_miss; 809 u8 intra_no_vlan; 810 u8 no_vlan; 811 u8 intra_vlan_miss; 812 u8 vlan_miss; 813 u8 reserved3[3]; 814 u8 no_vlan_prio; 815 __be32 promisc; 816 __be32 mcast; 817 }; 818 819 struct mlx4_port_info { 820 struct mlx4_dev *dev; 821 int port; 822 char dev_name[16]; 823 struct device_attribute port_attr; 824 enum mlx4_port_type tmp_type; 825 char dev_mtu_name[16]; 826 struct device_attribute port_mtu_attr; 827 struct mlx4_mac_table mac_table; 828 struct mlx4_vlan_table vlan_table; 829 struct mlx4_roce_gid_table gid_table; 830 int base_qpn; 831 struct cpu_rmap *rmap; 832 struct devlink_port devlink_port; 833 }; 834 835 struct mlx4_sense { 836 struct mlx4_dev *dev; 837 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 838 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 839 struct delayed_work sense_poll; 840 }; 841 842 struct mlx4_msix_ctl { 843 DECLARE_BITMAP(pool_bm, MAX_MSIX); 844 struct mutex pool_lock; 845 }; 846 847 struct mlx4_steer { 848 struct list_head promisc_qps[MLX4_NUM_STEERS]; 849 struct list_head steer_entries[MLX4_NUM_STEERS]; 850 }; 851 852 enum { 853 MLX4_PCI_DEV_IS_VF = 1 << 0, 854 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 855 }; 856 857 enum { 858 MLX4_NO_RR = 0, 859 MLX4_USE_RR = 1, 860 }; 861 862 struct mlx4_priv { 863 struct mlx4_dev dev; 864 865 struct list_head dev_list; 866 struct list_head ctx_list; 867 spinlock_t ctx_lock; 868 869 int pci_dev_data; 870 int removed; 871 872 struct list_head pgdir_list; 873 struct mutex pgdir_mutex; 874 875 struct mlx4_fw fw; 876 struct mlx4_cmd cmd; 877 struct mlx4_mfunc mfunc; 878 879 struct mlx4_bitmap pd_bitmap; 880 struct mlx4_bitmap xrcd_bitmap; 881 struct mlx4_uar_table uar_table; 882 struct mlx4_mr_table mr_table; 883 struct mlx4_cq_table cq_table; 884 struct mlx4_eq_table eq_table; 885 struct mlx4_srq_table srq_table; 886 struct mlx4_qp_table qp_table; 887 struct mlx4_mcg_table mcg_table; 888 struct mlx4_bitmap counters_bitmap; 889 int def_counter[MLX4_MAX_PORTS]; 890 891 struct mlx4_catas_err catas_err; 892 893 void __iomem *clr_base; 894 895 struct mlx4_uar driver_uar; 896 void __iomem *kar; 897 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 898 struct mlx4_sense sense; 899 struct mutex port_mutex; 900 struct mlx4_msix_ctl msix_ctl; 901 struct mlx4_steer *steer; 902 struct list_head bf_list; 903 struct mutex bf_mutex; 904 struct io_mapping *bf_mapping; 905 void __iomem *clock_mapping; 906 int reserved_mtts; 907 int fs_hash_mode; 908 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 909 struct mlx4_port_map v2p; /* cached port mapping configuration */ 910 struct mutex bond_mutex; /* for bond mode */ 911 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 912 913 atomic_t opreq_count; 914 struct work_struct opreq_task; 915 }; 916 917 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 918 { 919 return container_of(dev, struct mlx4_priv, dev); 920 } 921 922 #define MLX4_SENSE_RANGE (HZ * 3) 923 924 extern struct workqueue_struct *mlx4_wq; 925 926 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 927 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 928 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 929 int align, u32 skip_mask); 930 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 931 int use_rr); 932 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 933 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 934 u32 reserved_bot, u32 resetrved_top); 935 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 936 937 int mlx4_reset(struct mlx4_dev *dev); 938 939 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 940 void mlx4_free_eq_table(struct mlx4_dev *dev); 941 942 int mlx4_init_pd_table(struct mlx4_dev *dev); 943 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 944 int mlx4_init_uar_table(struct mlx4_dev *dev); 945 int mlx4_init_mr_table(struct mlx4_dev *dev); 946 int mlx4_init_eq_table(struct mlx4_dev *dev); 947 int mlx4_init_cq_table(struct mlx4_dev *dev); 948 int mlx4_init_qp_table(struct mlx4_dev *dev); 949 int mlx4_init_srq_table(struct mlx4_dev *dev); 950 int mlx4_init_mcg_table(struct mlx4_dev *dev); 951 952 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 953 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 954 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 955 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 956 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 957 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 958 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 959 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 960 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 961 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 962 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 963 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 964 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 965 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 966 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 967 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 968 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 969 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 970 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 971 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 972 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 973 974 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 975 struct mlx4_vhcr *vhcr, 976 struct mlx4_cmd_mailbox *inbox, 977 struct mlx4_cmd_mailbox *outbox, 978 struct mlx4_cmd_info *cmd); 979 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 980 struct mlx4_vhcr *vhcr, 981 struct mlx4_cmd_mailbox *inbox, 982 struct mlx4_cmd_mailbox *outbox, 983 struct mlx4_cmd_info *cmd); 984 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 985 struct mlx4_vhcr *vhcr, 986 struct mlx4_cmd_mailbox *inbox, 987 struct mlx4_cmd_mailbox *outbox, 988 struct mlx4_cmd_info *cmd); 989 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 990 struct mlx4_vhcr *vhcr, 991 struct mlx4_cmd_mailbox *inbox, 992 struct mlx4_cmd_mailbox *outbox, 993 struct mlx4_cmd_info *cmd); 994 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 995 struct mlx4_vhcr *vhcr, 996 struct mlx4_cmd_mailbox *inbox, 997 struct mlx4_cmd_mailbox *outbox, 998 struct mlx4_cmd_info *cmd); 999 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1000 struct mlx4_vhcr *vhcr, 1001 struct mlx4_cmd_mailbox *inbox, 1002 struct mlx4_cmd_mailbox *outbox, 1003 struct mlx4_cmd_info *cmd); 1004 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 1005 struct mlx4_vhcr *vhcr, 1006 struct mlx4_cmd_mailbox *inbox, 1007 struct mlx4_cmd_mailbox *outbox, 1008 struct mlx4_cmd_info *cmd); 1009 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 1010 struct mlx4_vhcr *vhcr, 1011 struct mlx4_cmd_mailbox *inbox, 1012 struct mlx4_cmd_mailbox *outbox, 1013 struct mlx4_cmd_info *cmd); 1014 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1015 int *base, u8 flags); 1016 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1017 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1018 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1019 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1020 int start_index, int npages, u64 *page_list); 1021 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1022 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1023 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1024 struct mlx4_counter *data); 1025 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1026 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1027 1028 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1029 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1030 int mlx4_catas_init(struct mlx4_dev *dev); 1031 void mlx4_catas_end(struct mlx4_dev *dev); 1032 int mlx4_restart_one(struct pci_dev *pdev); 1033 int mlx4_register_device(struct mlx4_dev *dev); 1034 void mlx4_unregister_device(struct mlx4_dev *dev); 1035 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1036 unsigned long param); 1037 1038 struct mlx4_dev_cap; 1039 struct mlx4_init_hca_param; 1040 1041 u64 mlx4_make_profile(struct mlx4_dev *dev, 1042 struct mlx4_profile *request, 1043 struct mlx4_dev_cap *dev_cap, 1044 struct mlx4_init_hca_param *init_hca); 1045 void mlx4_master_comm_channel(struct work_struct *work); 1046 void mlx4_gen_slave_eqe(struct work_struct *work); 1047 void mlx4_master_handle_slave_flr(struct work_struct *work); 1048 1049 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1050 struct mlx4_vhcr *vhcr, 1051 struct mlx4_cmd_mailbox *inbox, 1052 struct mlx4_cmd_mailbox *outbox, 1053 struct mlx4_cmd_info *cmd); 1054 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1055 struct mlx4_vhcr *vhcr, 1056 struct mlx4_cmd_mailbox *inbox, 1057 struct mlx4_cmd_mailbox *outbox, 1058 struct mlx4_cmd_info *cmd); 1059 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1060 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1061 struct mlx4_cmd_mailbox *outbox, 1062 struct mlx4_cmd_info *cmd); 1063 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1064 struct mlx4_vhcr *vhcr, 1065 struct mlx4_cmd_mailbox *inbox, 1066 struct mlx4_cmd_mailbox *outbox, 1067 struct mlx4_cmd_info *cmd); 1068 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1069 struct mlx4_vhcr *vhcr, 1070 struct mlx4_cmd_mailbox *inbox, 1071 struct mlx4_cmd_mailbox *outbox, 1072 struct mlx4_cmd_info *cmd); 1073 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1074 struct mlx4_vhcr *vhcr, 1075 struct mlx4_cmd_mailbox *inbox, 1076 struct mlx4_cmd_mailbox *outbox, 1077 struct mlx4_cmd_info *cmd); 1078 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1079 struct mlx4_vhcr *vhcr, 1080 struct mlx4_cmd_mailbox *inbox, 1081 struct mlx4_cmd_mailbox *outbox, 1082 struct mlx4_cmd_info *cmd); 1083 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1084 struct mlx4_vhcr *vhcr, 1085 struct mlx4_cmd_mailbox *inbox, 1086 struct mlx4_cmd_mailbox *outbox, 1087 struct mlx4_cmd_info *cmd); 1088 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1089 struct mlx4_vhcr *vhcr, 1090 struct mlx4_cmd_mailbox *inbox, 1091 struct mlx4_cmd_mailbox *outbox, 1092 struct mlx4_cmd_info *cmd); 1093 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1094 struct mlx4_vhcr *vhcr, 1095 struct mlx4_cmd_mailbox *inbox, 1096 struct mlx4_cmd_mailbox *outbox, 1097 struct mlx4_cmd_info *cmd); 1098 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1099 struct mlx4_vhcr *vhcr, 1100 struct mlx4_cmd_mailbox *inbox, 1101 struct mlx4_cmd_mailbox *outbox, 1102 struct mlx4_cmd_info *cmd); 1103 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1104 struct mlx4_vhcr *vhcr, 1105 struct mlx4_cmd_mailbox *inbox, 1106 struct mlx4_cmd_mailbox *outbox, 1107 struct mlx4_cmd_info *cmd); 1108 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1109 struct mlx4_vhcr *vhcr, 1110 struct mlx4_cmd_mailbox *inbox, 1111 struct mlx4_cmd_mailbox *outbox, 1112 struct mlx4_cmd_info *cmd); 1113 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1114 struct mlx4_vhcr *vhcr, 1115 struct mlx4_cmd_mailbox *inbox, 1116 struct mlx4_cmd_mailbox *outbox, 1117 struct mlx4_cmd_info *cmd); 1118 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1119 struct mlx4_vhcr *vhcr, 1120 struct mlx4_cmd_mailbox *inbox, 1121 struct mlx4_cmd_mailbox *outbox, 1122 struct mlx4_cmd_info *cmd); 1123 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1124 struct mlx4_vhcr *vhcr, 1125 struct mlx4_cmd_mailbox *inbox, 1126 struct mlx4_cmd_mailbox *outbox, 1127 struct mlx4_cmd_info *cmd); 1128 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1129 struct mlx4_vhcr *vhcr, 1130 struct mlx4_cmd_mailbox *inbox, 1131 struct mlx4_cmd_mailbox *outbox, 1132 struct mlx4_cmd_info *cmd); 1133 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1134 struct mlx4_vhcr *vhcr, 1135 struct mlx4_cmd_mailbox *inbox, 1136 struct mlx4_cmd_mailbox *outbox, 1137 struct mlx4_cmd_info *cmd); 1138 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1139 struct mlx4_vhcr *vhcr, 1140 struct mlx4_cmd_mailbox *inbox, 1141 struct mlx4_cmd_mailbox *outbox, 1142 struct mlx4_cmd_info *cmd); 1143 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1144 struct mlx4_vhcr *vhcr, 1145 struct mlx4_cmd_mailbox *inbox, 1146 struct mlx4_cmd_mailbox *outbox, 1147 struct mlx4_cmd_info *cmd); 1148 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1149 struct mlx4_vhcr *vhcr, 1150 struct mlx4_cmd_mailbox *inbox, 1151 struct mlx4_cmd_mailbox *outbox, 1152 struct mlx4_cmd_info *cmd); 1153 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1154 struct mlx4_vhcr *vhcr, 1155 struct mlx4_cmd_mailbox *inbox, 1156 struct mlx4_cmd_mailbox *outbox, 1157 struct mlx4_cmd_info *cmd); 1158 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1159 struct mlx4_vhcr *vhcr, 1160 struct mlx4_cmd_mailbox *inbox, 1161 struct mlx4_cmd_mailbox *outbox, 1162 struct mlx4_cmd_info *cmd); 1163 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1164 struct mlx4_vhcr *vhcr, 1165 struct mlx4_cmd_mailbox *inbox, 1166 struct mlx4_cmd_mailbox *outbox, 1167 struct mlx4_cmd_info *cmd); 1168 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1169 struct mlx4_vhcr *vhcr, 1170 struct mlx4_cmd_mailbox *inbox, 1171 struct mlx4_cmd_mailbox *outbox, 1172 struct mlx4_cmd_info *cmd); 1173 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1174 struct mlx4_vhcr *vhcr, 1175 struct mlx4_cmd_mailbox *inbox, 1176 struct mlx4_cmd_mailbox *outbox, 1177 struct mlx4_cmd_info *cmd); 1178 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1179 struct mlx4_vhcr *vhcr, 1180 struct mlx4_cmd_mailbox *inbox, 1181 struct mlx4_cmd_mailbox *outbox, 1182 struct mlx4_cmd_info *cmd); 1183 1184 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1185 1186 enum { 1187 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1188 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1189 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1190 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1191 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1192 }; 1193 1194 int mlx4_cmd_init(struct mlx4_dev *dev); 1195 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1196 int mlx4_multi_func_init(struct mlx4_dev *dev); 1197 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1198 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1199 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1200 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1201 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1202 1203 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1204 u16 op, unsigned long timeout); 1205 1206 void mlx4_cq_tasklet_cb(unsigned long data); 1207 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1208 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1209 1210 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1211 1212 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1213 1214 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1215 1216 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1217 enum mlx4_port_type *type); 1218 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1219 enum mlx4_port_type *stype, 1220 enum mlx4_port_type *defaults); 1221 void mlx4_start_sense(struct mlx4_dev *dev); 1222 void mlx4_stop_sense(struct mlx4_dev *dev); 1223 void mlx4_sense_init(struct mlx4_dev *dev); 1224 int mlx4_check_port_params(struct mlx4_dev *dev, 1225 enum mlx4_port_type *port_type); 1226 int mlx4_change_port_types(struct mlx4_dev *dev, 1227 enum mlx4_port_type *port_types); 1228 1229 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1230 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1231 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1232 struct mlx4_roce_gid_table *table); 1233 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1234 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1235 int mlx4_bond_vlan_table(struct mlx4_dev *dev); 1236 int mlx4_unbond_vlan_table(struct mlx4_dev *dev); 1237 int mlx4_bond_mac_table(struct mlx4_dev *dev); 1238 int mlx4_unbond_mac_table(struct mlx4_dev *dev); 1239 1240 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1241 /* resource tracker functions*/ 1242 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1243 enum mlx4_resource resource_type, 1244 u64 resource_id, int *slave); 1245 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1246 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1247 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1248 1249 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1250 enum mlx4_res_tracker_free_type type); 1251 1252 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1253 struct mlx4_vhcr *vhcr, 1254 struct mlx4_cmd_mailbox *inbox, 1255 struct mlx4_cmd_mailbox *outbox, 1256 struct mlx4_cmd_info *cmd); 1257 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1258 struct mlx4_vhcr *vhcr, 1259 struct mlx4_cmd_mailbox *inbox, 1260 struct mlx4_cmd_mailbox *outbox, 1261 struct mlx4_cmd_info *cmd); 1262 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1263 struct mlx4_vhcr *vhcr, 1264 struct mlx4_cmd_mailbox *inbox, 1265 struct mlx4_cmd_mailbox *outbox, 1266 struct mlx4_cmd_info *cmd); 1267 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1268 struct mlx4_vhcr *vhcr, 1269 struct mlx4_cmd_mailbox *inbox, 1270 struct mlx4_cmd_mailbox *outbox, 1271 struct mlx4_cmd_info *cmd); 1272 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1273 struct mlx4_vhcr *vhcr, 1274 struct mlx4_cmd_mailbox *inbox, 1275 struct mlx4_cmd_mailbox *outbox, 1276 struct mlx4_cmd_info *cmd); 1277 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1278 struct mlx4_vhcr *vhcr, 1279 struct mlx4_cmd_mailbox *inbox, 1280 struct mlx4_cmd_mailbox *outbox, 1281 struct mlx4_cmd_info *cmd); 1282 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1283 1284 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1285 int *gid_tbl_len, int *pkey_tbl_len); 1286 1287 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1288 struct mlx4_vhcr *vhcr, 1289 struct mlx4_cmd_mailbox *inbox, 1290 struct mlx4_cmd_mailbox *outbox, 1291 struct mlx4_cmd_info *cmd); 1292 1293 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1294 struct mlx4_vhcr *vhcr, 1295 struct mlx4_cmd_mailbox *inbox, 1296 struct mlx4_cmd_mailbox *outbox, 1297 struct mlx4_cmd_info *cmd); 1298 1299 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1300 struct mlx4_vhcr *vhcr, 1301 struct mlx4_cmd_mailbox *inbox, 1302 struct mlx4_cmd_mailbox *outbox, 1303 struct mlx4_cmd_info *cmd); 1304 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1305 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1306 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1307 int block_mcast_loopback, enum mlx4_protocol prot, 1308 enum mlx4_steer_type steer); 1309 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1310 u8 gid[16], u8 port, 1311 int block_mcast_loopback, 1312 enum mlx4_protocol prot, u64 *reg_id); 1313 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1314 struct mlx4_vhcr *vhcr, 1315 struct mlx4_cmd_mailbox *inbox, 1316 struct mlx4_cmd_mailbox *outbox, 1317 struct mlx4_cmd_info *cmd); 1318 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1319 struct mlx4_vhcr *vhcr, 1320 struct mlx4_cmd_mailbox *inbox, 1321 struct mlx4_cmd_mailbox *outbox, 1322 struct mlx4_cmd_info *cmd); 1323 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1324 int port, void *buf); 1325 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1326 struct mlx4_cmd_mailbox *outbox); 1327 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1328 struct mlx4_vhcr *vhcr, 1329 struct mlx4_cmd_mailbox *inbox, 1330 struct mlx4_cmd_mailbox *outbox, 1331 struct mlx4_cmd_info *cmd); 1332 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1333 struct mlx4_vhcr *vhcr, 1334 struct mlx4_cmd_mailbox *inbox, 1335 struct mlx4_cmd_mailbox *outbox, 1336 struct mlx4_cmd_info *cmd); 1337 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1338 struct mlx4_vhcr *vhcr, 1339 struct mlx4_cmd_mailbox *inbox, 1340 struct mlx4_cmd_mailbox *outbox, 1341 struct mlx4_cmd_info *cmd); 1342 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1343 struct mlx4_vhcr *vhcr, 1344 struct mlx4_cmd_mailbox *inbox, 1345 struct mlx4_cmd_mailbox *outbox, 1346 struct mlx4_cmd_info *cmd); 1347 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1348 struct mlx4_vhcr *vhcr, 1349 struct mlx4_cmd_mailbox *inbox, 1350 struct mlx4_cmd_mailbox *outbox, 1351 struct mlx4_cmd_info *cmd); 1352 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1353 struct mlx4_vhcr *vhcr, 1354 struct mlx4_cmd_mailbox *inbox, 1355 struct mlx4_cmd_mailbox *outbox, 1356 struct mlx4_cmd_info *cmd); 1357 1358 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1359 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1360 1361 static inline void set_param_l(u64 *arg, u32 val) 1362 { 1363 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1364 } 1365 1366 static inline void set_param_h(u64 *arg, u32 val) 1367 { 1368 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1369 } 1370 1371 static inline u32 get_param_l(u64 *arg) 1372 { 1373 return (u32) (*arg & 0xffffffff); 1374 } 1375 1376 static inline u32 get_param_h(u64 *arg) 1377 { 1378 return (u32)(*arg >> 32); 1379 } 1380 1381 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1382 { 1383 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1384 } 1385 1386 #define NOT_MASKED_PD_BITS 17 1387 1388 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1389 1390 void mlx4_init_quotas(struct mlx4_dev *dev); 1391 1392 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */ 1393 void mlx4_replace_zero_macs(struct mlx4_dev *dev); 1394 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1395 /* Returns the VF index of slave */ 1396 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1397 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1398 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1399 int mlx4_bond_fs_rules(struct mlx4_dev *dev); 1400 int mlx4_unbond_fs_rules(struct mlx4_dev *dev); 1401 1402 enum mlx4_zone_flags { 1403 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1404 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1405 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1406 MLX4_ZONE_USE_RR = 1UL << 3, 1407 }; 1408 1409 enum mlx4_zone_alloc_flags { 1410 /* No two objects could overlap between zones. UID 1411 * could be left unused. If this flag is given and 1412 * two overlapped zones are used, an object will be free'd 1413 * from the smallest possible matching zone. 1414 */ 1415 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1416 }; 1417 1418 struct mlx4_zone_allocator; 1419 1420 /* Create a new zone allocator */ 1421 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1422 1423 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1424 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1425 * Similarly, when searching for an object to free, this offset it taken into 1426 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1427 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1428 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1429 * according to the policy set by <flags>. <puid> is the unique identifier 1430 * received to this zone. 1431 */ 1432 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1433 struct mlx4_bitmap *bitmap, 1434 u32 flags, 1435 int priority, 1436 int offset, 1437 u32 *puid); 1438 1439 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1440 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1441 1442 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1443 * the attached bitmaps. 1444 */ 1445 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1446 1447 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1448 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1449 * allocated from is returned in <puid>. If the allocation fails, a negative 1450 * number is returned. Otherwise, the offset of the first object is returned. 1451 */ 1452 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1453 int align, u32 skip_mask, u32 *puid); 1454 1455 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1456 * <zones>. 1457 */ 1458 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1459 u32 uid, u32 obj, u32 count); 1460 1461 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1462 * specifying the uid when freeing an object, zone allocator could figure it by 1463 * itself. Other parameters are similar to mlx4_zone_free. 1464 */ 1465 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1466 1467 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1468 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1469 1470 #endif /* MLX4_H */ 1471