1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 #include <net/devlink.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/driver.h> 52 #include <linux/mlx4/doorbell.h> 53 #include <linux/mlx4/cmd.h> 54 #include "fw_qos.h" 55 56 #define DRV_NAME "mlx4_core" 57 #define PFX DRV_NAME ": " 58 #define DRV_VERSION "2.2-1" 59 #define DRV_RELDATE "Feb, 2014" 60 61 #define MLX4_FS_UDP_UC_EN (1 << 1) 62 #define MLX4_FS_TCP_UC_EN (1 << 2) 63 #define MLX4_FS_NUM_OF_L2_ADDR 8 64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 65 #define MLX4_FS_NUM_MCG (1 << 17) 66 67 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 68 69 #define MLX4_QUERY_IF_STAT_RESET BIT(31) 70 71 enum { 72 MLX4_HCR_BASE = 0x80680, 73 MLX4_HCR_SIZE = 0x0001c, 74 MLX4_CLR_INT_SIZE = 0x00008, 75 MLX4_SLAVE_COMM_BASE = 0x0, 76 MLX4_COMM_PAGESIZE = 0x1000, 77 MLX4_CLOCK_SIZE = 0x00008, 78 MLX4_COMM_CHAN_CAPS = 0x8, 79 MLX4_COMM_CHAN_FLAGS = 0xc 80 }; 81 82 enum { 83 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 84 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 85 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 86 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 87 MLX4_MTT_ENTRY_PER_SEG = 8, 88 }; 89 90 enum { 91 MLX4_NUM_PDS = 1 << 15 92 }; 93 94 enum { 95 MLX4_CMPT_TYPE_QP = 0, 96 MLX4_CMPT_TYPE_SRQ = 1, 97 MLX4_CMPT_TYPE_CQ = 2, 98 MLX4_CMPT_TYPE_EQ = 3, 99 MLX4_CMPT_NUM_TYPE 100 }; 101 102 enum { 103 MLX4_CMPT_SHIFT = 24, 104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 105 }; 106 107 enum mlx4_mpt_state { 108 MLX4_MPT_DISABLED = 0, 109 MLX4_MPT_EN_HW, 110 MLX4_MPT_EN_SW 111 }; 112 113 #define MLX4_COMM_TIME 10000 114 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 115 #define MLX4_COMM_CMD_NA_OP 0x0 116 117 118 enum { 119 MLX4_COMM_CMD_RESET, 120 MLX4_COMM_CMD_VHCR0, 121 MLX4_COMM_CMD_VHCR1, 122 MLX4_COMM_CMD_VHCR2, 123 MLX4_COMM_CMD_VHCR_EN, 124 MLX4_COMM_CMD_VHCR_POST, 125 MLX4_COMM_CMD_FLR = 254 126 }; 127 128 enum { 129 MLX4_VF_SMI_DISABLED, 130 MLX4_VF_SMI_ENABLED 131 }; 132 133 /*The flag indicates that the slave should delay the RESET cmd*/ 134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 135 /*indicates how many retries will be done if we are in the middle of FLR*/ 136 #define NUM_OF_RESET_RETRIES 10 137 #define SLEEP_TIME_IN_RESET (2 * 1000) 138 enum mlx4_resource { 139 RES_QP, 140 RES_CQ, 141 RES_SRQ, 142 RES_XRCD, 143 RES_MPT, 144 RES_MTT, 145 RES_MAC, 146 RES_VLAN, 147 RES_EQ, 148 RES_COUNTER, 149 RES_FS_RULE, 150 MLX4_NUM_OF_RESOURCE_TYPE 151 }; 152 153 enum mlx4_alloc_mode { 154 RES_OP_RESERVE, 155 RES_OP_RESERVE_AND_MAP, 156 RES_OP_MAP_ICM, 157 }; 158 159 enum mlx4_res_tracker_free_type { 160 RES_TR_FREE_ALL, 161 RES_TR_FREE_SLAVES_ONLY, 162 RES_TR_FREE_STRUCTS_ONLY, 163 }; 164 165 /* 166 *Virtual HCR structures. 167 * mlx4_vhcr is the sw representation, in machine endianness 168 * 169 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 170 * to FW to go through communication channel. 171 * It is big endian, and has the same structure as the physical HCR 172 * used by command interface 173 */ 174 struct mlx4_vhcr { 175 u64 in_param; 176 u64 out_param; 177 u32 in_modifier; 178 u32 errno; 179 u16 op; 180 u16 token; 181 u8 op_modifier; 182 u8 e_bit; 183 }; 184 185 struct mlx4_vhcr_cmd { 186 __be64 in_param; 187 __be32 in_modifier; 188 u32 reserved1; 189 __be64 out_param; 190 __be16 token; 191 u16 reserved; 192 u8 status; 193 u8 flags; 194 __be16 opcode; 195 }; 196 197 struct mlx4_cmd_info { 198 u16 opcode; 199 bool has_inbox; 200 bool has_outbox; 201 bool out_is_imm; 202 bool encode_slave_id; 203 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 204 struct mlx4_cmd_mailbox *inbox); 205 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox, 207 struct mlx4_cmd_mailbox *outbox, 208 struct mlx4_cmd_info *cmd); 209 }; 210 211 #ifdef CONFIG_MLX4_DEBUG 212 extern int mlx4_debug_level; 213 #else /* CONFIG_MLX4_DEBUG */ 214 #define mlx4_debug_level (0) 215 #endif /* CONFIG_MLX4_DEBUG */ 216 217 #define mlx4_dbg(mdev, format, ...) \ 218 do { \ 219 if (mlx4_debug_level) \ 220 dev_printk(KERN_DEBUG, \ 221 &(mdev)->persist->pdev->dev, format, \ 222 ##__VA_ARGS__); \ 223 } while (0) 224 225 #define mlx4_err(mdev, format, ...) \ 226 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 227 #define mlx4_info(mdev, format, ...) \ 228 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 229 #define mlx4_warn(mdev, format, ...) \ 230 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 231 232 extern int mlx4_log_num_mgm_entry_size; 233 extern int log_mtts_per_seg; 234 extern int mlx4_internal_err_reset; 235 236 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 237 MLX4_MFUNC_MAX)) 238 #define ALL_SLAVES 0xff 239 240 struct mlx4_bitmap { 241 u32 last; 242 u32 top; 243 u32 max; 244 u32 reserved_top; 245 u32 mask; 246 u32 avail; 247 u32 effective_len; 248 spinlock_t lock; 249 unsigned long *table; 250 }; 251 252 struct mlx4_buddy { 253 unsigned long **bits; 254 unsigned int *num_free; 255 u32 max_order; 256 spinlock_t lock; 257 }; 258 259 struct mlx4_icm; 260 261 struct mlx4_icm_table { 262 u64 virt; 263 int num_icm; 264 u32 num_obj; 265 int obj_size; 266 int lowmem; 267 int coherent; 268 struct mutex mutex; 269 struct mlx4_icm **icm; 270 }; 271 272 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 273 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 274 #define MLX4_MPT_FLAG_MIO (1 << 17) 275 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 276 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 277 #define MLX4_MPT_FLAG_REGION (1 << 8) 278 279 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 280 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 284 285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 286 287 #define MLX4_MPT_STATUS_SW 0xF0 288 #define MLX4_MPT_STATUS_HW 0x00 289 290 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 291 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 292 293 #define MLX4_EQ_ASYNC 0 294 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ 295 !!((int)(vector) >= MLX4_EQ_ASYNC)) 296 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ 297 !!((int)(vector) >= MLX4_EQ_ASYNC)) 298 299 /* 300 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 301 */ 302 struct mlx4_mpt_entry { 303 __be32 flags; 304 __be32 qpn; 305 __be32 key; 306 __be32 pd_flags; 307 __be64 start; 308 __be64 length; 309 __be32 lkey; 310 __be32 win_cnt; 311 u8 reserved1[3]; 312 u8 mtt_rep; 313 __be64 mtt_addr; 314 __be32 mtt_sz; 315 __be32 entity_size; 316 __be32 first_byte_offset; 317 } __packed; 318 319 /* 320 * Must be packed because start is 64 bits but only aligned to 32 bits. 321 */ 322 struct mlx4_eq_context { 323 __be32 flags; 324 u16 reserved1[3]; 325 __be16 page_offset; 326 u8 log_eq_size; 327 u8 reserved2[4]; 328 u8 eq_period; 329 u8 reserved3; 330 u8 eq_max_count; 331 u8 reserved4[3]; 332 u8 intr; 333 u8 log_page_size; 334 u8 reserved5[2]; 335 u8 mtt_base_addr_h; 336 __be32 mtt_base_addr_l; 337 u32 reserved6[2]; 338 __be32 consumer_index; 339 __be32 producer_index; 340 u32 reserved7[4]; 341 }; 342 343 struct mlx4_cq_context { 344 __be32 flags; 345 u16 reserved1[3]; 346 __be16 page_offset; 347 __be32 logsize_usrpage; 348 __be16 cq_period; 349 __be16 cq_max_count; 350 u8 reserved2[3]; 351 u8 comp_eqn; 352 u8 log_page_size; 353 u8 reserved3[2]; 354 u8 mtt_base_addr_h; 355 __be32 mtt_base_addr_l; 356 __be32 last_notified_index; 357 __be32 solicit_producer_index; 358 __be32 consumer_index; 359 __be32 producer_index; 360 u32 reserved4[2]; 361 __be64 db_rec_addr; 362 }; 363 364 struct mlx4_srq_context { 365 __be32 state_logsize_srqn; 366 u8 logstride; 367 u8 reserved1; 368 __be16 xrcd; 369 __be32 pg_offset_cqn; 370 u32 reserved2; 371 u8 log_page_size; 372 u8 reserved3[2]; 373 u8 mtt_base_addr_h; 374 __be32 mtt_base_addr_l; 375 __be32 pd; 376 __be16 limit_watermark; 377 __be16 wqe_cnt; 378 u16 reserved4; 379 __be16 wqe_counter; 380 u32 reserved5; 381 __be64 db_rec_addr; 382 }; 383 384 struct mlx4_eq_tasklet { 385 struct list_head list; 386 struct list_head process_list; 387 struct tasklet_struct task; 388 /* lock on completion tasklet list */ 389 spinlock_t lock; 390 }; 391 392 struct mlx4_eq { 393 struct mlx4_dev *dev; 394 void __iomem *doorbell; 395 int eqn; 396 u32 cons_index; 397 u16 irq; 398 u16 have_irq; 399 int nent; 400 struct mlx4_buf_list *page_list; 401 struct mlx4_mtt mtt; 402 struct mlx4_eq_tasklet tasklet_ctx; 403 struct mlx4_active_ports actv_ports; 404 u32 ref_count; 405 cpumask_var_t affinity_mask; 406 }; 407 408 struct mlx4_slave_eqe { 409 u8 type; 410 u8 port; 411 u32 param; 412 }; 413 414 struct mlx4_slave_event_eq_info { 415 int eqn; 416 u16 token; 417 }; 418 419 struct mlx4_profile { 420 int num_qp; 421 int rdmarc_per_qp; 422 int num_srq; 423 int num_cq; 424 int num_mcg; 425 int num_mpt; 426 unsigned num_mtt; 427 }; 428 429 struct mlx4_fw { 430 u64 clr_int_base; 431 u64 catas_offset; 432 u64 comm_base; 433 u64 clock_offset; 434 struct mlx4_icm *fw_icm; 435 struct mlx4_icm *aux_icm; 436 u32 catas_size; 437 u16 fw_pages; 438 u8 clr_int_bar; 439 u8 catas_bar; 440 u8 comm_bar; 441 u8 clock_bar; 442 }; 443 444 struct mlx4_comm { 445 u32 slave_write; 446 u32 slave_read; 447 }; 448 449 enum { 450 MLX4_MCAST_CONFIG = 0, 451 MLX4_MCAST_DISABLE = 1, 452 MLX4_MCAST_ENABLE = 2, 453 }; 454 455 #define VLAN_FLTR_SIZE 128 456 457 struct mlx4_vlan_fltr { 458 __be32 entry[VLAN_FLTR_SIZE]; 459 }; 460 461 struct mlx4_mcast_entry { 462 struct list_head list; 463 u64 addr; 464 }; 465 466 struct mlx4_promisc_qp { 467 struct list_head list; 468 u32 qpn; 469 }; 470 471 struct mlx4_steer_index { 472 struct list_head list; 473 unsigned int index; 474 struct list_head duplicates; 475 }; 476 477 #define MLX4_EVENT_TYPES_NUM 64 478 479 struct mlx4_slave_state { 480 u8 comm_toggle; 481 u8 last_cmd; 482 u8 init_port_mask; 483 bool active; 484 bool old_vlan_api; 485 u8 function; 486 dma_addr_t vhcr_dma; 487 u16 mtu[MLX4_MAX_PORTS + 1]; 488 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 489 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 490 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 491 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 492 /* event type to eq number lookup */ 493 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 494 u16 eq_pi; 495 u16 eq_ci; 496 spinlock_t lock; 497 /*initialized via the kzalloc*/ 498 u8 is_slave_going_down; 499 u32 cookie; 500 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 501 }; 502 503 #define MLX4_VGT 4095 504 #define NO_INDX (-1) 505 506 struct mlx4_vport_state { 507 u64 mac; 508 u16 default_vlan; 509 u8 default_qos; 510 u32 tx_rate; 511 bool spoofchk; 512 u32 link_state; 513 u8 qos_vport; 514 __be64 guid; 515 }; 516 517 struct mlx4_vf_admin_state { 518 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 519 u8 enable_smi[MLX4_MAX_PORTS + 1]; 520 }; 521 522 struct mlx4_vport_oper_state { 523 struct mlx4_vport_state state; 524 int mac_idx; 525 int vlan_idx; 526 }; 527 528 struct mlx4_vf_oper_state { 529 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 530 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 531 }; 532 533 struct slave_list { 534 struct mutex mutex; 535 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 536 }; 537 538 struct resource_allocator { 539 spinlock_t alloc_lock; /* protect quotas */ 540 union { 541 int res_reserved; 542 int res_port_rsvd[MLX4_MAX_PORTS]; 543 }; 544 union { 545 int res_free; 546 int res_port_free[MLX4_MAX_PORTS]; 547 }; 548 int *quota; 549 int *allocated; 550 int *guaranteed; 551 }; 552 553 struct mlx4_resource_tracker { 554 spinlock_t lock; 555 /* tree for each resources */ 556 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 557 /* num_of_slave's lists, one per slave */ 558 struct slave_list *slave_list; 559 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 560 }; 561 562 #define SLAVE_EVENT_EQ_SIZE 128 563 struct mlx4_slave_event_eq { 564 u32 eqn; 565 u32 cons; 566 u32 prod; 567 spinlock_t event_lock; 568 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 569 }; 570 571 struct mlx4_qos_manager { 572 int num_of_qos_vfs; 573 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 574 }; 575 576 struct mlx4_master_qp0_state { 577 int proxy_qp0_active; 578 int qp0_active; 579 int port_active; 580 }; 581 582 struct mlx4_mfunc_master_ctx { 583 struct mlx4_slave_state *slave_state; 584 struct mlx4_vf_admin_state *vf_admin; 585 struct mlx4_vf_oper_state *vf_oper; 586 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 587 int init_port_ref[MLX4_MAX_PORTS + 1]; 588 u16 max_mtu[MLX4_MAX_PORTS + 1]; 589 u8 pptx; 590 u8 pprx; 591 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 592 struct mlx4_resource_tracker res_tracker; 593 struct workqueue_struct *comm_wq; 594 struct work_struct comm_work; 595 struct work_struct slave_event_work; 596 struct work_struct slave_flr_event_work; 597 spinlock_t slave_state_lock; 598 __be32 comm_arm_bit_vector[4]; 599 struct mlx4_eqe cmd_eqe; 600 struct mlx4_slave_event_eq slave_eq; 601 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 602 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 603 }; 604 605 struct mlx4_mfunc { 606 struct mlx4_comm __iomem *comm; 607 struct mlx4_vhcr_cmd *vhcr; 608 dma_addr_t vhcr_dma; 609 610 struct mlx4_mfunc_master_ctx master; 611 }; 612 613 #define MGM_QPN_MASK 0x00FFFFFF 614 #define MGM_BLCK_LB_BIT 30 615 616 struct mlx4_mgm { 617 __be32 next_gid_index; 618 __be32 members_count; 619 u32 reserved[2]; 620 u8 gid[16]; 621 __be32 qp[MLX4_MAX_QP_PER_MGM]; 622 }; 623 624 struct mlx4_cmd { 625 struct pci_pool *pool; 626 void __iomem *hcr; 627 struct mutex slave_cmd_mutex; 628 struct semaphore poll_sem; 629 struct semaphore event_sem; 630 int max_cmds; 631 spinlock_t context_lock; 632 int free_head; 633 struct mlx4_cmd_context *context; 634 u16 token_mask; 635 u8 use_events; 636 u8 toggle; 637 u8 comm_toggle; 638 u8 initialized; 639 }; 640 641 enum { 642 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 643 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 644 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 645 }; 646 struct mlx4_vf_immed_vlan_work { 647 struct work_struct work; 648 struct mlx4_priv *priv; 649 int flags; 650 int slave; 651 int vlan_ix; 652 int orig_vlan_ix; 653 u8 port; 654 u8 qos; 655 u8 qos_vport; 656 u16 vlan_id; 657 u16 orig_vlan_id; 658 }; 659 660 661 struct mlx4_uar_table { 662 struct mlx4_bitmap bitmap; 663 }; 664 665 struct mlx4_mr_table { 666 struct mlx4_bitmap mpt_bitmap; 667 struct mlx4_buddy mtt_buddy; 668 u64 mtt_base; 669 u64 mpt_base; 670 struct mlx4_icm_table mtt_table; 671 struct mlx4_icm_table dmpt_table; 672 }; 673 674 struct mlx4_cq_table { 675 struct mlx4_bitmap bitmap; 676 spinlock_t lock; 677 struct radix_tree_root tree; 678 struct mlx4_icm_table table; 679 struct mlx4_icm_table cmpt_table; 680 }; 681 682 struct mlx4_eq_table { 683 struct mlx4_bitmap bitmap; 684 char *irq_names; 685 void __iomem *clr_int; 686 void __iomem **uar_map; 687 u32 clr_mask; 688 struct mlx4_eq *eq; 689 struct mlx4_icm_table table; 690 struct mlx4_icm_table cmpt_table; 691 int have_irq; 692 u8 inta_pin; 693 }; 694 695 struct mlx4_srq_table { 696 struct mlx4_bitmap bitmap; 697 spinlock_t lock; 698 struct radix_tree_root tree; 699 struct mlx4_icm_table table; 700 struct mlx4_icm_table cmpt_table; 701 }; 702 703 enum mlx4_qp_table_zones { 704 MLX4_QP_TABLE_ZONE_GENERAL, 705 MLX4_QP_TABLE_ZONE_RSS, 706 MLX4_QP_TABLE_ZONE_RAW_ETH, 707 MLX4_QP_TABLE_ZONE_NUM 708 }; 709 710 struct mlx4_qp_table { 711 struct mlx4_bitmap *bitmap_gen; 712 struct mlx4_zone_allocator *zones; 713 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 714 u32 rdmarc_base; 715 int rdmarc_shift; 716 spinlock_t lock; 717 struct mlx4_icm_table qp_table; 718 struct mlx4_icm_table auxc_table; 719 struct mlx4_icm_table altc_table; 720 struct mlx4_icm_table rdmarc_table; 721 struct mlx4_icm_table cmpt_table; 722 }; 723 724 struct mlx4_mcg_table { 725 struct mutex mutex; 726 struct mlx4_bitmap bitmap; 727 struct mlx4_icm_table table; 728 }; 729 730 struct mlx4_catas_err { 731 u32 __iomem *map; 732 struct timer_list timer; 733 struct list_head list; 734 }; 735 736 #define MLX4_MAX_MAC_NUM 128 737 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 738 739 struct mlx4_mac_table { 740 __be64 entries[MLX4_MAX_MAC_NUM]; 741 int refs[MLX4_MAX_MAC_NUM]; 742 bool is_dup[MLX4_MAX_MAC_NUM]; 743 struct mutex mutex; 744 int total; 745 int max; 746 }; 747 748 #define MLX4_ROCE_GID_ENTRY_SIZE 16 749 750 struct mlx4_roce_gid_entry { 751 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 752 }; 753 754 struct mlx4_roce_gid_table { 755 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 756 struct mutex mutex; 757 }; 758 759 #define MLX4_MAX_VLAN_NUM 128 760 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 761 762 struct mlx4_vlan_table { 763 __be32 entries[MLX4_MAX_VLAN_NUM]; 764 int refs[MLX4_MAX_VLAN_NUM]; 765 int is_dup[MLX4_MAX_VLAN_NUM]; 766 struct mutex mutex; 767 int total; 768 int max; 769 }; 770 771 #define SET_PORT_GEN_ALL_VALID 0x7 772 #define SET_PORT_PROMISC_SHIFT 31 773 #define SET_PORT_MC_PROMISC_SHIFT 30 774 775 enum { 776 MCAST_DIRECT_ONLY = 0, 777 MCAST_DIRECT = 1, 778 MCAST_DEFAULT = 2 779 }; 780 781 782 struct mlx4_set_port_general_context { 783 u16 reserved1; 784 u8 v_ignore_fcs; 785 u8 flags; 786 union { 787 u8 ignore_fcs; 788 u8 roce_mode; 789 }; 790 u8 reserved2; 791 __be16 mtu; 792 u8 pptx; 793 u8 pfctx; 794 u16 reserved3; 795 u8 pprx; 796 u8 pfcrx; 797 u16 reserved4; 798 u32 reserved5; 799 u8 phv_en; 800 u8 reserved6[3]; 801 }; 802 803 struct mlx4_set_port_rqp_calc_context { 804 __be32 base_qpn; 805 u8 rererved; 806 u8 n_mac; 807 u8 n_vlan; 808 u8 n_prio; 809 u8 reserved2[3]; 810 u8 mac_miss; 811 u8 intra_no_vlan; 812 u8 no_vlan; 813 u8 intra_vlan_miss; 814 u8 vlan_miss; 815 u8 reserved3[3]; 816 u8 no_vlan_prio; 817 __be32 promisc; 818 __be32 mcast; 819 }; 820 821 struct mlx4_port_info { 822 struct mlx4_dev *dev; 823 int port; 824 char dev_name[16]; 825 struct device_attribute port_attr; 826 enum mlx4_port_type tmp_type; 827 char dev_mtu_name[16]; 828 struct device_attribute port_mtu_attr; 829 struct mlx4_mac_table mac_table; 830 struct mlx4_vlan_table vlan_table; 831 struct mlx4_roce_gid_table gid_table; 832 int base_qpn; 833 struct cpu_rmap *rmap; 834 struct devlink_port devlink_port; 835 }; 836 837 struct mlx4_sense { 838 struct mlx4_dev *dev; 839 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 840 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 841 struct delayed_work sense_poll; 842 }; 843 844 struct mlx4_msix_ctl { 845 DECLARE_BITMAP(pool_bm, MAX_MSIX); 846 struct mutex pool_lock; 847 }; 848 849 struct mlx4_steer { 850 struct list_head promisc_qps[MLX4_NUM_STEERS]; 851 struct list_head steer_entries[MLX4_NUM_STEERS]; 852 }; 853 854 enum { 855 MLX4_PCI_DEV_IS_VF = 1 << 0, 856 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 857 }; 858 859 enum { 860 MLX4_NO_RR = 0, 861 MLX4_USE_RR = 1, 862 }; 863 864 struct mlx4_priv { 865 struct mlx4_dev dev; 866 867 struct list_head dev_list; 868 struct list_head ctx_list; 869 spinlock_t ctx_lock; 870 871 int pci_dev_data; 872 int removed; 873 874 struct list_head pgdir_list; 875 struct mutex pgdir_mutex; 876 877 struct mlx4_fw fw; 878 struct mlx4_cmd cmd; 879 struct mlx4_mfunc mfunc; 880 881 struct mlx4_bitmap pd_bitmap; 882 struct mlx4_bitmap xrcd_bitmap; 883 struct mlx4_uar_table uar_table; 884 struct mlx4_mr_table mr_table; 885 struct mlx4_cq_table cq_table; 886 struct mlx4_eq_table eq_table; 887 struct mlx4_srq_table srq_table; 888 struct mlx4_qp_table qp_table; 889 struct mlx4_mcg_table mcg_table; 890 struct mlx4_bitmap counters_bitmap; 891 int def_counter[MLX4_MAX_PORTS]; 892 893 struct mlx4_catas_err catas_err; 894 895 void __iomem *clr_base; 896 897 struct mlx4_uar driver_uar; 898 void __iomem *kar; 899 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 900 struct mlx4_sense sense; 901 struct mutex port_mutex; 902 struct mlx4_msix_ctl msix_ctl; 903 struct mlx4_steer *steer; 904 struct list_head bf_list; 905 struct mutex bf_mutex; 906 struct io_mapping *bf_mapping; 907 void __iomem *clock_mapping; 908 int reserved_mtts; 909 int fs_hash_mode; 910 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 911 struct mlx4_port_map v2p; /* cached port mapping configuration */ 912 struct mutex bond_mutex; /* for bond mode */ 913 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 914 915 atomic_t opreq_count; 916 struct work_struct opreq_task; 917 }; 918 919 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 920 { 921 return container_of(dev, struct mlx4_priv, dev); 922 } 923 924 #define MLX4_SENSE_RANGE (HZ * 3) 925 926 extern struct workqueue_struct *mlx4_wq; 927 928 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 929 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 930 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 931 int align, u32 skip_mask); 932 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 933 int use_rr); 934 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 935 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 936 u32 reserved_bot, u32 resetrved_top); 937 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 938 939 int mlx4_reset(struct mlx4_dev *dev); 940 941 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 942 void mlx4_free_eq_table(struct mlx4_dev *dev); 943 944 int mlx4_init_pd_table(struct mlx4_dev *dev); 945 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 946 int mlx4_init_uar_table(struct mlx4_dev *dev); 947 int mlx4_init_mr_table(struct mlx4_dev *dev); 948 int mlx4_init_eq_table(struct mlx4_dev *dev); 949 int mlx4_init_cq_table(struct mlx4_dev *dev); 950 int mlx4_init_qp_table(struct mlx4_dev *dev); 951 int mlx4_init_srq_table(struct mlx4_dev *dev); 952 int mlx4_init_mcg_table(struct mlx4_dev *dev); 953 954 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 955 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 956 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 957 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 958 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 959 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 960 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 961 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 962 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 963 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 964 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 965 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 966 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 967 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 968 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 969 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 970 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 971 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 972 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 973 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 974 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 975 976 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 977 struct mlx4_vhcr *vhcr, 978 struct mlx4_cmd_mailbox *inbox, 979 struct mlx4_cmd_mailbox *outbox, 980 struct mlx4_cmd_info *cmd); 981 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 982 struct mlx4_vhcr *vhcr, 983 struct mlx4_cmd_mailbox *inbox, 984 struct mlx4_cmd_mailbox *outbox, 985 struct mlx4_cmd_info *cmd); 986 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 987 struct mlx4_vhcr *vhcr, 988 struct mlx4_cmd_mailbox *inbox, 989 struct mlx4_cmd_mailbox *outbox, 990 struct mlx4_cmd_info *cmd); 991 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 992 struct mlx4_vhcr *vhcr, 993 struct mlx4_cmd_mailbox *inbox, 994 struct mlx4_cmd_mailbox *outbox, 995 struct mlx4_cmd_info *cmd); 996 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 997 struct mlx4_vhcr *vhcr, 998 struct mlx4_cmd_mailbox *inbox, 999 struct mlx4_cmd_mailbox *outbox, 1000 struct mlx4_cmd_info *cmd); 1001 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1002 struct mlx4_vhcr *vhcr, 1003 struct mlx4_cmd_mailbox *inbox, 1004 struct mlx4_cmd_mailbox *outbox, 1005 struct mlx4_cmd_info *cmd); 1006 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 1007 struct mlx4_vhcr *vhcr, 1008 struct mlx4_cmd_mailbox *inbox, 1009 struct mlx4_cmd_mailbox *outbox, 1010 struct mlx4_cmd_info *cmd); 1011 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 1012 struct mlx4_vhcr *vhcr, 1013 struct mlx4_cmd_mailbox *inbox, 1014 struct mlx4_cmd_mailbox *outbox, 1015 struct mlx4_cmd_info *cmd); 1016 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1017 int *base, u8 flags); 1018 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1019 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1020 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1021 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1022 int start_index, int npages, u64 *page_list); 1023 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1024 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1025 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1026 struct mlx4_counter *data); 1027 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1028 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1029 1030 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1031 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1032 int mlx4_catas_init(struct mlx4_dev *dev); 1033 void mlx4_catas_end(struct mlx4_dev *dev); 1034 int mlx4_restart_one(struct pci_dev *pdev); 1035 int mlx4_register_device(struct mlx4_dev *dev); 1036 void mlx4_unregister_device(struct mlx4_dev *dev); 1037 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1038 unsigned long param); 1039 1040 struct mlx4_dev_cap; 1041 struct mlx4_init_hca_param; 1042 1043 u64 mlx4_make_profile(struct mlx4_dev *dev, 1044 struct mlx4_profile *request, 1045 struct mlx4_dev_cap *dev_cap, 1046 struct mlx4_init_hca_param *init_hca); 1047 void mlx4_master_comm_channel(struct work_struct *work); 1048 void mlx4_gen_slave_eqe(struct work_struct *work); 1049 void mlx4_master_handle_slave_flr(struct work_struct *work); 1050 1051 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1063 struct mlx4_cmd_mailbox *outbox, 1064 struct mlx4_cmd_info *cmd); 1065 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1066 struct mlx4_vhcr *vhcr, 1067 struct mlx4_cmd_mailbox *inbox, 1068 struct mlx4_cmd_mailbox *outbox, 1069 struct mlx4_cmd_info *cmd); 1070 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1071 struct mlx4_vhcr *vhcr, 1072 struct mlx4_cmd_mailbox *inbox, 1073 struct mlx4_cmd_mailbox *outbox, 1074 struct mlx4_cmd_info *cmd); 1075 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1076 struct mlx4_vhcr *vhcr, 1077 struct mlx4_cmd_mailbox *inbox, 1078 struct mlx4_cmd_mailbox *outbox, 1079 struct mlx4_cmd_info *cmd); 1080 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1081 struct mlx4_vhcr *vhcr, 1082 struct mlx4_cmd_mailbox *inbox, 1083 struct mlx4_cmd_mailbox *outbox, 1084 struct mlx4_cmd_info *cmd); 1085 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1086 struct mlx4_vhcr *vhcr, 1087 struct mlx4_cmd_mailbox *inbox, 1088 struct mlx4_cmd_mailbox *outbox, 1089 struct mlx4_cmd_info *cmd); 1090 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1091 struct mlx4_vhcr *vhcr, 1092 struct mlx4_cmd_mailbox *inbox, 1093 struct mlx4_cmd_mailbox *outbox, 1094 struct mlx4_cmd_info *cmd); 1095 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1096 struct mlx4_vhcr *vhcr, 1097 struct mlx4_cmd_mailbox *inbox, 1098 struct mlx4_cmd_mailbox *outbox, 1099 struct mlx4_cmd_info *cmd); 1100 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1101 struct mlx4_vhcr *vhcr, 1102 struct mlx4_cmd_mailbox *inbox, 1103 struct mlx4_cmd_mailbox *outbox, 1104 struct mlx4_cmd_info *cmd); 1105 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1106 struct mlx4_vhcr *vhcr, 1107 struct mlx4_cmd_mailbox *inbox, 1108 struct mlx4_cmd_mailbox *outbox, 1109 struct mlx4_cmd_info *cmd); 1110 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1111 struct mlx4_vhcr *vhcr, 1112 struct mlx4_cmd_mailbox *inbox, 1113 struct mlx4_cmd_mailbox *outbox, 1114 struct mlx4_cmd_info *cmd); 1115 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1116 struct mlx4_vhcr *vhcr, 1117 struct mlx4_cmd_mailbox *inbox, 1118 struct mlx4_cmd_mailbox *outbox, 1119 struct mlx4_cmd_info *cmd); 1120 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1121 struct mlx4_vhcr *vhcr, 1122 struct mlx4_cmd_mailbox *inbox, 1123 struct mlx4_cmd_mailbox *outbox, 1124 struct mlx4_cmd_info *cmd); 1125 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1126 struct mlx4_vhcr *vhcr, 1127 struct mlx4_cmd_mailbox *inbox, 1128 struct mlx4_cmd_mailbox *outbox, 1129 struct mlx4_cmd_info *cmd); 1130 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1131 struct mlx4_vhcr *vhcr, 1132 struct mlx4_cmd_mailbox *inbox, 1133 struct mlx4_cmd_mailbox *outbox, 1134 struct mlx4_cmd_info *cmd); 1135 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1136 struct mlx4_vhcr *vhcr, 1137 struct mlx4_cmd_mailbox *inbox, 1138 struct mlx4_cmd_mailbox *outbox, 1139 struct mlx4_cmd_info *cmd); 1140 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1141 struct mlx4_vhcr *vhcr, 1142 struct mlx4_cmd_mailbox *inbox, 1143 struct mlx4_cmd_mailbox *outbox, 1144 struct mlx4_cmd_info *cmd); 1145 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1146 struct mlx4_vhcr *vhcr, 1147 struct mlx4_cmd_mailbox *inbox, 1148 struct mlx4_cmd_mailbox *outbox, 1149 struct mlx4_cmd_info *cmd); 1150 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1151 struct mlx4_vhcr *vhcr, 1152 struct mlx4_cmd_mailbox *inbox, 1153 struct mlx4_cmd_mailbox *outbox, 1154 struct mlx4_cmd_info *cmd); 1155 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1156 struct mlx4_vhcr *vhcr, 1157 struct mlx4_cmd_mailbox *inbox, 1158 struct mlx4_cmd_mailbox *outbox, 1159 struct mlx4_cmd_info *cmd); 1160 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1161 struct mlx4_vhcr *vhcr, 1162 struct mlx4_cmd_mailbox *inbox, 1163 struct mlx4_cmd_mailbox *outbox, 1164 struct mlx4_cmd_info *cmd); 1165 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1166 struct mlx4_vhcr *vhcr, 1167 struct mlx4_cmd_mailbox *inbox, 1168 struct mlx4_cmd_mailbox *outbox, 1169 struct mlx4_cmd_info *cmd); 1170 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1171 struct mlx4_vhcr *vhcr, 1172 struct mlx4_cmd_mailbox *inbox, 1173 struct mlx4_cmd_mailbox *outbox, 1174 struct mlx4_cmd_info *cmd); 1175 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1176 struct mlx4_vhcr *vhcr, 1177 struct mlx4_cmd_mailbox *inbox, 1178 struct mlx4_cmd_mailbox *outbox, 1179 struct mlx4_cmd_info *cmd); 1180 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1181 struct mlx4_vhcr *vhcr, 1182 struct mlx4_cmd_mailbox *inbox, 1183 struct mlx4_cmd_mailbox *outbox, 1184 struct mlx4_cmd_info *cmd); 1185 1186 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1187 1188 enum { 1189 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1190 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1191 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1192 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1193 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1194 }; 1195 1196 int mlx4_cmd_init(struct mlx4_dev *dev); 1197 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1198 int mlx4_multi_func_init(struct mlx4_dev *dev); 1199 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1200 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1201 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1202 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1203 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1204 1205 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1206 u16 op, unsigned long timeout); 1207 1208 void mlx4_cq_tasklet_cb(unsigned long data); 1209 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1210 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1211 1212 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1213 1214 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1215 1216 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1217 1218 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1219 enum mlx4_port_type *type); 1220 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1221 enum mlx4_port_type *stype, 1222 enum mlx4_port_type *defaults); 1223 void mlx4_start_sense(struct mlx4_dev *dev); 1224 void mlx4_stop_sense(struct mlx4_dev *dev); 1225 void mlx4_sense_init(struct mlx4_dev *dev); 1226 int mlx4_check_port_params(struct mlx4_dev *dev, 1227 enum mlx4_port_type *port_type); 1228 int mlx4_change_port_types(struct mlx4_dev *dev, 1229 enum mlx4_port_type *port_types); 1230 1231 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1232 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1233 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1234 struct mlx4_roce_gid_table *table); 1235 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1236 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1237 int mlx4_bond_vlan_table(struct mlx4_dev *dev); 1238 int mlx4_unbond_vlan_table(struct mlx4_dev *dev); 1239 int mlx4_bond_mac_table(struct mlx4_dev *dev); 1240 int mlx4_unbond_mac_table(struct mlx4_dev *dev); 1241 1242 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1243 /* resource tracker functions*/ 1244 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1245 enum mlx4_resource resource_type, 1246 u64 resource_id, int *slave); 1247 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1248 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1249 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1250 1251 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1252 enum mlx4_res_tracker_free_type type); 1253 1254 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1255 struct mlx4_vhcr *vhcr, 1256 struct mlx4_cmd_mailbox *inbox, 1257 struct mlx4_cmd_mailbox *outbox, 1258 struct mlx4_cmd_info *cmd); 1259 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1260 struct mlx4_vhcr *vhcr, 1261 struct mlx4_cmd_mailbox *inbox, 1262 struct mlx4_cmd_mailbox *outbox, 1263 struct mlx4_cmd_info *cmd); 1264 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1265 struct mlx4_vhcr *vhcr, 1266 struct mlx4_cmd_mailbox *inbox, 1267 struct mlx4_cmd_mailbox *outbox, 1268 struct mlx4_cmd_info *cmd); 1269 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1270 struct mlx4_vhcr *vhcr, 1271 struct mlx4_cmd_mailbox *inbox, 1272 struct mlx4_cmd_mailbox *outbox, 1273 struct mlx4_cmd_info *cmd); 1274 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1275 struct mlx4_vhcr *vhcr, 1276 struct mlx4_cmd_mailbox *inbox, 1277 struct mlx4_cmd_mailbox *outbox, 1278 struct mlx4_cmd_info *cmd); 1279 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1280 struct mlx4_vhcr *vhcr, 1281 struct mlx4_cmd_mailbox *inbox, 1282 struct mlx4_cmd_mailbox *outbox, 1283 struct mlx4_cmd_info *cmd); 1284 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1285 1286 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1287 int *gid_tbl_len, int *pkey_tbl_len); 1288 1289 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1290 struct mlx4_vhcr *vhcr, 1291 struct mlx4_cmd_mailbox *inbox, 1292 struct mlx4_cmd_mailbox *outbox, 1293 struct mlx4_cmd_info *cmd); 1294 1295 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1296 struct mlx4_vhcr *vhcr, 1297 struct mlx4_cmd_mailbox *inbox, 1298 struct mlx4_cmd_mailbox *outbox, 1299 struct mlx4_cmd_info *cmd); 1300 1301 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1302 struct mlx4_vhcr *vhcr, 1303 struct mlx4_cmd_mailbox *inbox, 1304 struct mlx4_cmd_mailbox *outbox, 1305 struct mlx4_cmd_info *cmd); 1306 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1307 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1308 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1309 int block_mcast_loopback, enum mlx4_protocol prot, 1310 enum mlx4_steer_type steer); 1311 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1312 u8 gid[16], u8 port, 1313 int block_mcast_loopback, 1314 enum mlx4_protocol prot, u64 *reg_id); 1315 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1316 struct mlx4_vhcr *vhcr, 1317 struct mlx4_cmd_mailbox *inbox, 1318 struct mlx4_cmd_mailbox *outbox, 1319 struct mlx4_cmd_info *cmd); 1320 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1321 struct mlx4_vhcr *vhcr, 1322 struct mlx4_cmd_mailbox *inbox, 1323 struct mlx4_cmd_mailbox *outbox, 1324 struct mlx4_cmd_info *cmd); 1325 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1326 int port, void *buf); 1327 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1328 struct mlx4_cmd_mailbox *outbox); 1329 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1330 struct mlx4_vhcr *vhcr, 1331 struct mlx4_cmd_mailbox *inbox, 1332 struct mlx4_cmd_mailbox *outbox, 1333 struct mlx4_cmd_info *cmd); 1334 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1335 struct mlx4_vhcr *vhcr, 1336 struct mlx4_cmd_mailbox *inbox, 1337 struct mlx4_cmd_mailbox *outbox, 1338 struct mlx4_cmd_info *cmd); 1339 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1340 struct mlx4_vhcr *vhcr, 1341 struct mlx4_cmd_mailbox *inbox, 1342 struct mlx4_cmd_mailbox *outbox, 1343 struct mlx4_cmd_info *cmd); 1344 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1345 struct mlx4_vhcr *vhcr, 1346 struct mlx4_cmd_mailbox *inbox, 1347 struct mlx4_cmd_mailbox *outbox, 1348 struct mlx4_cmd_info *cmd); 1349 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1350 struct mlx4_vhcr *vhcr, 1351 struct mlx4_cmd_mailbox *inbox, 1352 struct mlx4_cmd_mailbox *outbox, 1353 struct mlx4_cmd_info *cmd); 1354 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1355 struct mlx4_vhcr *vhcr, 1356 struct mlx4_cmd_mailbox *inbox, 1357 struct mlx4_cmd_mailbox *outbox, 1358 struct mlx4_cmd_info *cmd); 1359 1360 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1361 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1362 1363 static inline void set_param_l(u64 *arg, u32 val) 1364 { 1365 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1366 } 1367 1368 static inline void set_param_h(u64 *arg, u32 val) 1369 { 1370 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1371 } 1372 1373 static inline u32 get_param_l(u64 *arg) 1374 { 1375 return (u32) (*arg & 0xffffffff); 1376 } 1377 1378 static inline u32 get_param_h(u64 *arg) 1379 { 1380 return (u32)(*arg >> 32); 1381 } 1382 1383 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1384 { 1385 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1386 } 1387 1388 #define NOT_MASKED_PD_BITS 17 1389 1390 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1391 1392 void mlx4_init_quotas(struct mlx4_dev *dev); 1393 1394 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */ 1395 void mlx4_replace_zero_macs(struct mlx4_dev *dev); 1396 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1397 /* Returns the VF index of slave */ 1398 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1399 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1400 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1401 int mlx4_bond_fs_rules(struct mlx4_dev *dev); 1402 int mlx4_unbond_fs_rules(struct mlx4_dev *dev); 1403 1404 enum mlx4_zone_flags { 1405 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1406 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1407 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1408 MLX4_ZONE_USE_RR = 1UL << 3, 1409 }; 1410 1411 enum mlx4_zone_alloc_flags { 1412 /* No two objects could overlap between zones. UID 1413 * could be left unused. If this flag is given and 1414 * two overlapped zones are used, an object will be free'd 1415 * from the smallest possible matching zone. 1416 */ 1417 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1418 }; 1419 1420 struct mlx4_zone_allocator; 1421 1422 /* Create a new zone allocator */ 1423 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1424 1425 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1426 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1427 * Similarly, when searching for an object to free, this offset it taken into 1428 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1429 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1430 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1431 * according to the policy set by <flags>. <puid> is the unique identifier 1432 * received to this zone. 1433 */ 1434 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1435 struct mlx4_bitmap *bitmap, 1436 u32 flags, 1437 int priority, 1438 int offset, 1439 u32 *puid); 1440 1441 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1442 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1443 1444 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1445 * the attached bitmaps. 1446 */ 1447 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1448 1449 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1450 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1451 * allocated from is returned in <puid>. If the allocation fails, a negative 1452 * number is returned. Otherwise, the offset of the first object is returned. 1453 */ 1454 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1455 int align, u32 skip_mask, u32 *puid); 1456 1457 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1458 * <zones>. 1459 */ 1460 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1461 u32 uid, u32 obj, u32 count); 1462 1463 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1464 * specifying the uid when freeing an object, zone allocator could figure it by 1465 * itself. Other parameters are similar to mlx4_zone_free. 1466 */ 1467 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1468 1469 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1470 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1471 1472 #endif /* MLX4_H */ 1473