1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 #include <net/devlink.h> 49 #include <linux/rwsem.h> 50 51 #include <linux/mlx4/device.h> 52 #include <linux/mlx4/driver.h> 53 #include <linux/mlx4/doorbell.h> 54 #include <linux/mlx4/cmd.h> 55 #include "fw_qos.h" 56 57 #define DRV_NAME "mlx4_core" 58 #define PFX DRV_NAME ": " 59 #define DRV_VERSION "2.2-1" 60 #define DRV_RELDATE "Feb, 2014" 61 62 #define MLX4_FS_UDP_UC_EN (1 << 1) 63 #define MLX4_FS_TCP_UC_EN (1 << 2) 64 #define MLX4_FS_NUM_OF_L2_ADDR 8 65 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 66 #define MLX4_FS_NUM_MCG (1 << 17) 67 68 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 69 70 #define MLX4_QUERY_IF_STAT_RESET BIT(31) 71 72 enum { 73 MLX4_HCR_BASE = 0x80680, 74 MLX4_HCR_SIZE = 0x0001c, 75 MLX4_CLR_INT_SIZE = 0x00008, 76 MLX4_SLAVE_COMM_BASE = 0x0, 77 MLX4_COMM_PAGESIZE = 0x1000, 78 MLX4_CLOCK_SIZE = 0x00008, 79 MLX4_COMM_CHAN_CAPS = 0x8, 80 MLX4_COMM_CHAN_FLAGS = 0xc 81 }; 82 83 enum { 84 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 85 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 86 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 87 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 88 MLX4_MTT_ENTRY_PER_SEG = 8, 89 }; 90 91 enum { 92 MLX4_NUM_PDS = 1 << 15 93 }; 94 95 enum { 96 MLX4_CMPT_TYPE_QP = 0, 97 MLX4_CMPT_TYPE_SRQ = 1, 98 MLX4_CMPT_TYPE_CQ = 2, 99 MLX4_CMPT_TYPE_EQ = 3, 100 MLX4_CMPT_NUM_TYPE 101 }; 102 103 enum { 104 MLX4_CMPT_SHIFT = 24, 105 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 106 }; 107 108 enum mlx4_mpt_state { 109 MLX4_MPT_DISABLED = 0, 110 MLX4_MPT_EN_HW, 111 MLX4_MPT_EN_SW 112 }; 113 114 #define MLX4_COMM_TIME 10000 115 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 116 #define MLX4_COMM_CMD_NA_OP 0x0 117 118 119 enum { 120 MLX4_COMM_CMD_RESET, 121 MLX4_COMM_CMD_VHCR0, 122 MLX4_COMM_CMD_VHCR1, 123 MLX4_COMM_CMD_VHCR2, 124 MLX4_COMM_CMD_VHCR_EN, 125 MLX4_COMM_CMD_VHCR_POST, 126 MLX4_COMM_CMD_FLR = 254 127 }; 128 129 enum { 130 MLX4_VF_SMI_DISABLED, 131 MLX4_VF_SMI_ENABLED 132 }; 133 134 /*The flag indicates that the slave should delay the RESET cmd*/ 135 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 136 /*indicates how many retries will be done if we are in the middle of FLR*/ 137 #define NUM_OF_RESET_RETRIES 10 138 #define SLEEP_TIME_IN_RESET (2 * 1000) 139 enum mlx4_resource { 140 RES_QP, 141 RES_CQ, 142 RES_SRQ, 143 RES_XRCD, 144 RES_MPT, 145 RES_MTT, 146 RES_MAC, 147 RES_VLAN, 148 RES_NPORT_ID, 149 RES_COUNTER, 150 RES_FS_RULE, 151 RES_EQ, 152 MLX4_NUM_OF_RESOURCE_TYPE 153 }; 154 155 enum mlx4_alloc_mode { 156 RES_OP_RESERVE, 157 RES_OP_RESERVE_AND_MAP, 158 RES_OP_MAP_ICM, 159 }; 160 161 enum mlx4_res_tracker_free_type { 162 RES_TR_FREE_ALL, 163 RES_TR_FREE_SLAVES_ONLY, 164 RES_TR_FREE_STRUCTS_ONLY, 165 }; 166 167 /* 168 *Virtual HCR structures. 169 * mlx4_vhcr is the sw representation, in machine endianness 170 * 171 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 172 * to FW to go through communication channel. 173 * It is big endian, and has the same structure as the physical HCR 174 * used by command interface 175 */ 176 struct mlx4_vhcr { 177 u64 in_param; 178 u64 out_param; 179 u32 in_modifier; 180 u32 errno; 181 u16 op; 182 u16 token; 183 u8 op_modifier; 184 u8 e_bit; 185 }; 186 187 struct mlx4_vhcr_cmd { 188 __be64 in_param; 189 __be32 in_modifier; 190 u32 reserved1; 191 __be64 out_param; 192 __be16 token; 193 u16 reserved; 194 u8 status; 195 u8 flags; 196 __be16 opcode; 197 }; 198 199 struct mlx4_cmd_info { 200 u16 opcode; 201 bool has_inbox; 202 bool has_outbox; 203 bool out_is_imm; 204 bool encode_slave_id; 205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox); 207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 208 struct mlx4_cmd_mailbox *inbox, 209 struct mlx4_cmd_mailbox *outbox, 210 struct mlx4_cmd_info *cmd); 211 }; 212 213 #ifdef CONFIG_MLX4_DEBUG 214 extern int mlx4_debug_level; 215 #else /* CONFIG_MLX4_DEBUG */ 216 #define mlx4_debug_level (0) 217 #endif /* CONFIG_MLX4_DEBUG */ 218 219 #define mlx4_dbg(mdev, format, ...) \ 220 do { \ 221 if (mlx4_debug_level) \ 222 dev_printk(KERN_DEBUG, \ 223 &(mdev)->persist->pdev->dev, format, \ 224 ##__VA_ARGS__); \ 225 } while (0) 226 227 #define mlx4_err(mdev, format, ...) \ 228 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 229 #define mlx4_info(mdev, format, ...) \ 230 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 231 #define mlx4_warn(mdev, format, ...) \ 232 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 233 234 extern int mlx4_log_num_mgm_entry_size; 235 extern int log_mtts_per_seg; 236 extern int mlx4_internal_err_reset; 237 238 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 239 MLX4_MFUNC_MAX)) 240 #define ALL_SLAVES 0xff 241 242 struct mlx4_bitmap { 243 u32 last; 244 u32 top; 245 u32 max; 246 u32 reserved_top; 247 u32 mask; 248 u32 avail; 249 u32 effective_len; 250 spinlock_t lock; 251 unsigned long *table; 252 }; 253 254 struct mlx4_buddy { 255 unsigned long **bits; 256 unsigned int *num_free; 257 u32 max_order; 258 spinlock_t lock; 259 }; 260 261 struct mlx4_icm; 262 263 struct mlx4_icm_table { 264 u64 virt; 265 int num_icm; 266 u32 num_obj; 267 int obj_size; 268 int lowmem; 269 int coherent; 270 struct mutex mutex; 271 struct mlx4_icm **icm; 272 }; 273 274 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 275 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 276 #define MLX4_MPT_FLAG_MIO (1 << 17) 277 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 278 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 279 #define MLX4_MPT_FLAG_REGION (1 << 8) 280 281 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 282 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 283 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 284 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 285 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 286 287 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 288 289 #define MLX4_MPT_STATUS_SW 0xF0 290 #define MLX4_MPT_STATUS_HW 0x00 291 292 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 293 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 294 295 #define MLX4_EQ_ASYNC 0 296 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ 297 !!((int)(vector) >= MLX4_EQ_ASYNC)) 298 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ 299 !!((int)(vector) >= MLX4_EQ_ASYNC)) 300 301 /* 302 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 303 */ 304 struct mlx4_mpt_entry { 305 __be32 flags; 306 __be32 qpn; 307 __be32 key; 308 __be32 pd_flags; 309 __be64 start; 310 __be64 length; 311 __be32 lkey; 312 __be32 win_cnt; 313 u8 reserved1[3]; 314 u8 mtt_rep; 315 __be64 mtt_addr; 316 __be32 mtt_sz; 317 __be32 entity_size; 318 __be32 first_byte_offset; 319 } __packed; 320 321 /* 322 * Must be packed because start is 64 bits but only aligned to 32 bits. 323 */ 324 struct mlx4_eq_context { 325 __be32 flags; 326 u16 reserved1[3]; 327 __be16 page_offset; 328 u8 log_eq_size; 329 u8 reserved2[4]; 330 u8 eq_period; 331 u8 reserved3; 332 u8 eq_max_count; 333 u8 reserved4[3]; 334 u8 intr; 335 u8 log_page_size; 336 u8 reserved5[2]; 337 u8 mtt_base_addr_h; 338 __be32 mtt_base_addr_l; 339 u32 reserved6[2]; 340 __be32 consumer_index; 341 __be32 producer_index; 342 u32 reserved7[4]; 343 }; 344 345 struct mlx4_cq_context { 346 __be32 flags; 347 u16 reserved1[3]; 348 __be16 page_offset; 349 __be32 logsize_usrpage; 350 __be16 cq_period; 351 __be16 cq_max_count; 352 u8 reserved2[3]; 353 u8 comp_eqn; 354 u8 log_page_size; 355 u8 reserved3[2]; 356 u8 mtt_base_addr_h; 357 __be32 mtt_base_addr_l; 358 __be32 last_notified_index; 359 __be32 solicit_producer_index; 360 __be32 consumer_index; 361 __be32 producer_index; 362 u32 reserved4[2]; 363 __be64 db_rec_addr; 364 }; 365 366 struct mlx4_srq_context { 367 __be32 state_logsize_srqn; 368 u8 logstride; 369 u8 reserved1; 370 __be16 xrcd; 371 __be32 pg_offset_cqn; 372 u32 reserved2; 373 u8 log_page_size; 374 u8 reserved3[2]; 375 u8 mtt_base_addr_h; 376 __be32 mtt_base_addr_l; 377 __be32 pd; 378 __be16 limit_watermark; 379 __be16 wqe_cnt; 380 u16 reserved4; 381 __be16 wqe_counter; 382 u32 reserved5; 383 __be64 db_rec_addr; 384 }; 385 386 struct mlx4_eq_tasklet { 387 struct list_head list; 388 struct list_head process_list; 389 struct tasklet_struct task; 390 /* lock on completion tasklet list */ 391 spinlock_t lock; 392 }; 393 394 struct mlx4_eq { 395 struct mlx4_dev *dev; 396 void __iomem *doorbell; 397 int eqn; 398 u32 cons_index; 399 u16 irq; 400 u16 have_irq; 401 int nent; 402 struct mlx4_buf_list *page_list; 403 struct mlx4_mtt mtt; 404 struct mlx4_eq_tasklet tasklet_ctx; 405 struct mlx4_active_ports actv_ports; 406 u32 ref_count; 407 cpumask_var_t affinity_mask; 408 }; 409 410 struct mlx4_slave_eqe { 411 u8 type; 412 u8 port; 413 u32 param; 414 }; 415 416 struct mlx4_slave_event_eq_info { 417 int eqn; 418 u16 token; 419 }; 420 421 struct mlx4_profile { 422 int num_qp; 423 int rdmarc_per_qp; 424 int num_srq; 425 int num_cq; 426 int num_mcg; 427 int num_mpt; 428 unsigned num_mtt; 429 }; 430 431 struct mlx4_fw { 432 u64 clr_int_base; 433 u64 catas_offset; 434 u64 comm_base; 435 u64 clock_offset; 436 struct mlx4_icm *fw_icm; 437 struct mlx4_icm *aux_icm; 438 u32 catas_size; 439 u16 fw_pages; 440 u8 clr_int_bar; 441 u8 catas_bar; 442 u8 comm_bar; 443 u8 clock_bar; 444 }; 445 446 struct mlx4_comm { 447 u32 slave_write; 448 u32 slave_read; 449 }; 450 451 enum { 452 MLX4_MCAST_CONFIG = 0, 453 MLX4_MCAST_DISABLE = 1, 454 MLX4_MCAST_ENABLE = 2, 455 }; 456 457 #define VLAN_FLTR_SIZE 128 458 459 struct mlx4_vlan_fltr { 460 __be32 entry[VLAN_FLTR_SIZE]; 461 }; 462 463 struct mlx4_mcast_entry { 464 struct list_head list; 465 u64 addr; 466 }; 467 468 struct mlx4_promisc_qp { 469 struct list_head list; 470 u32 qpn; 471 }; 472 473 struct mlx4_steer_index { 474 struct list_head list; 475 unsigned int index; 476 struct list_head duplicates; 477 }; 478 479 #define MLX4_EVENT_TYPES_NUM 64 480 481 struct mlx4_slave_state { 482 u8 comm_toggle; 483 u8 last_cmd; 484 u8 init_port_mask; 485 bool active; 486 bool old_vlan_api; 487 bool vst_qinq_supported; 488 u8 function; 489 dma_addr_t vhcr_dma; 490 u16 user_mtu[MLX4_MAX_PORTS + 1]; 491 u16 mtu[MLX4_MAX_PORTS + 1]; 492 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 493 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 494 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 495 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 496 /* event type to eq number lookup */ 497 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 498 u16 eq_pi; 499 u16 eq_ci; 500 spinlock_t lock; 501 /*initialized via the kzalloc*/ 502 u8 is_slave_going_down; 503 u32 cookie; 504 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 505 }; 506 507 #define MLX4_VGT 4095 508 #define NO_INDX (-1) 509 510 struct mlx4_vport_state { 511 u64 mac; 512 u16 default_vlan; 513 u8 default_qos; 514 __be16 vlan_proto; 515 u32 tx_rate; 516 bool spoofchk; 517 u32 link_state; 518 u8 qos_vport; 519 __be64 guid; 520 }; 521 522 struct mlx4_vf_admin_state { 523 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 524 u8 enable_smi[MLX4_MAX_PORTS + 1]; 525 }; 526 527 struct mlx4_vport_oper_state { 528 struct mlx4_vport_state state; 529 int mac_idx; 530 int vlan_idx; 531 }; 532 533 struct mlx4_vf_oper_state { 534 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 535 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 536 }; 537 538 struct slave_list { 539 struct mutex mutex; 540 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 541 }; 542 543 struct resource_allocator { 544 spinlock_t alloc_lock; /* protect quotas */ 545 union { 546 int res_reserved; 547 int res_port_rsvd[MLX4_MAX_PORTS]; 548 }; 549 union { 550 int res_free; 551 int res_port_free[MLX4_MAX_PORTS]; 552 }; 553 int *quota; 554 int *allocated; 555 int *guaranteed; 556 }; 557 558 struct mlx4_resource_tracker { 559 spinlock_t lock; 560 /* tree for each resources */ 561 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 562 /* num_of_slave's lists, one per slave */ 563 struct slave_list *slave_list; 564 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 565 }; 566 567 #define SLAVE_EVENT_EQ_SIZE 128 568 struct mlx4_slave_event_eq { 569 u32 eqn; 570 u32 cons; 571 u32 prod; 572 spinlock_t event_lock; 573 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 574 }; 575 576 struct mlx4_qos_manager { 577 int num_of_qos_vfs; 578 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 579 }; 580 581 struct mlx4_master_qp0_state { 582 int proxy_qp0_active; 583 int qp0_active; 584 int port_active; 585 }; 586 587 struct mlx4_mfunc_master_ctx { 588 struct mlx4_slave_state *slave_state; 589 struct mlx4_vf_admin_state *vf_admin; 590 struct mlx4_vf_oper_state *vf_oper; 591 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 592 int init_port_ref[MLX4_MAX_PORTS + 1]; 593 u16 max_mtu[MLX4_MAX_PORTS + 1]; 594 u16 max_user_mtu[MLX4_MAX_PORTS + 1]; 595 u8 pptx; 596 u8 pprx; 597 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 598 struct mlx4_resource_tracker res_tracker; 599 struct workqueue_struct *comm_wq; 600 struct work_struct comm_work; 601 struct work_struct slave_event_work; 602 struct work_struct slave_flr_event_work; 603 spinlock_t slave_state_lock; 604 __be32 comm_arm_bit_vector[4]; 605 struct mlx4_eqe cmd_eqe; 606 struct mlx4_slave_event_eq slave_eq; 607 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 608 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 609 }; 610 611 struct mlx4_mfunc { 612 struct mlx4_comm __iomem *comm; 613 struct mlx4_vhcr_cmd *vhcr; 614 dma_addr_t vhcr_dma; 615 616 struct mlx4_mfunc_master_ctx master; 617 }; 618 619 #define MGM_QPN_MASK 0x00FFFFFF 620 #define MGM_BLCK_LB_BIT 30 621 622 struct mlx4_mgm { 623 __be32 next_gid_index; 624 __be32 members_count; 625 u32 reserved[2]; 626 u8 gid[16]; 627 __be32 qp[MLX4_MAX_QP_PER_MGM]; 628 }; 629 630 struct mlx4_cmd { 631 struct pci_pool *pool; 632 void __iomem *hcr; 633 struct mutex slave_cmd_mutex; 634 struct semaphore poll_sem; 635 struct semaphore event_sem; 636 struct rw_semaphore switch_sem; 637 int max_cmds; 638 spinlock_t context_lock; 639 int free_head; 640 struct mlx4_cmd_context *context; 641 u16 token_mask; 642 u8 use_events; 643 u8 toggle; 644 u8 comm_toggle; 645 u8 initialized; 646 }; 647 648 enum { 649 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 650 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 651 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 652 }; 653 struct mlx4_vf_immed_vlan_work { 654 struct work_struct work; 655 struct mlx4_priv *priv; 656 int flags; 657 int slave; 658 int vlan_ix; 659 int orig_vlan_ix; 660 u8 port; 661 u8 qos; 662 u8 qos_vport; 663 u16 vlan_id; 664 u16 orig_vlan_id; 665 __be16 vlan_proto; 666 }; 667 668 669 struct mlx4_uar_table { 670 struct mlx4_bitmap bitmap; 671 }; 672 673 struct mlx4_mr_table { 674 struct mlx4_bitmap mpt_bitmap; 675 struct mlx4_buddy mtt_buddy; 676 u64 mtt_base; 677 u64 mpt_base; 678 struct mlx4_icm_table mtt_table; 679 struct mlx4_icm_table dmpt_table; 680 }; 681 682 struct mlx4_cq_table { 683 struct mlx4_bitmap bitmap; 684 spinlock_t lock; 685 struct radix_tree_root tree; 686 struct mlx4_icm_table table; 687 struct mlx4_icm_table cmpt_table; 688 }; 689 690 struct mlx4_eq_table { 691 struct mlx4_bitmap bitmap; 692 char *irq_names; 693 void __iomem *clr_int; 694 void __iomem **uar_map; 695 u32 clr_mask; 696 struct mlx4_eq *eq; 697 struct mlx4_icm_table table; 698 struct mlx4_icm_table cmpt_table; 699 int have_irq; 700 u8 inta_pin; 701 }; 702 703 struct mlx4_srq_table { 704 struct mlx4_bitmap bitmap; 705 spinlock_t lock; 706 struct radix_tree_root tree; 707 struct mlx4_icm_table table; 708 struct mlx4_icm_table cmpt_table; 709 }; 710 711 enum mlx4_qp_table_zones { 712 MLX4_QP_TABLE_ZONE_GENERAL, 713 MLX4_QP_TABLE_ZONE_RSS, 714 MLX4_QP_TABLE_ZONE_RAW_ETH, 715 MLX4_QP_TABLE_ZONE_NUM 716 }; 717 718 struct mlx4_qp_table { 719 struct mlx4_bitmap *bitmap_gen; 720 struct mlx4_zone_allocator *zones; 721 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 722 u32 rdmarc_base; 723 int rdmarc_shift; 724 spinlock_t lock; 725 struct mlx4_icm_table qp_table; 726 struct mlx4_icm_table auxc_table; 727 struct mlx4_icm_table altc_table; 728 struct mlx4_icm_table rdmarc_table; 729 struct mlx4_icm_table cmpt_table; 730 }; 731 732 struct mlx4_mcg_table { 733 struct mutex mutex; 734 struct mlx4_bitmap bitmap; 735 struct mlx4_icm_table table; 736 }; 737 738 struct mlx4_catas_err { 739 u32 __iomem *map; 740 struct timer_list timer; 741 struct list_head list; 742 }; 743 744 #define MLX4_MAX_MAC_NUM 128 745 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 746 747 struct mlx4_mac_table { 748 __be64 entries[MLX4_MAX_MAC_NUM]; 749 int refs[MLX4_MAX_MAC_NUM]; 750 bool is_dup[MLX4_MAX_MAC_NUM]; 751 struct mutex mutex; 752 int total; 753 int max; 754 }; 755 756 #define MLX4_ROCE_GID_ENTRY_SIZE 16 757 758 struct mlx4_roce_gid_entry { 759 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 760 }; 761 762 struct mlx4_roce_gid_table { 763 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 764 struct mutex mutex; 765 }; 766 767 #define MLX4_MAX_VLAN_NUM 128 768 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 769 770 struct mlx4_vlan_table { 771 __be32 entries[MLX4_MAX_VLAN_NUM]; 772 int refs[MLX4_MAX_VLAN_NUM]; 773 int is_dup[MLX4_MAX_VLAN_NUM]; 774 struct mutex mutex; 775 int total; 776 int max; 777 }; 778 779 #define SET_PORT_GEN_ALL_VALID (MLX4_FLAG_V_MTU_MASK | \ 780 MLX4_FLAG_V_PPRX_MASK | \ 781 MLX4_FLAG_V_PPTX_MASK) 782 #define SET_PORT_PROMISC_SHIFT 31 783 #define SET_PORT_MC_PROMISC_SHIFT 30 784 785 enum { 786 MCAST_DIRECT_ONLY = 0, 787 MCAST_DIRECT = 1, 788 MCAST_DEFAULT = 2 789 }; 790 791 792 struct mlx4_set_port_general_context { 793 u16 reserved1; 794 u8 flags2; 795 u8 flags; 796 union { 797 u8 ignore_fcs; 798 u8 roce_mode; 799 }; 800 u8 reserved2; 801 __be16 mtu; 802 u8 pptx; 803 u8 pfctx; 804 u16 reserved3; 805 u8 pprx; 806 u8 pfcrx; 807 u16 reserved4; 808 u32 reserved5; 809 u8 phv_en; 810 u8 reserved6[5]; 811 __be16 user_mtu; 812 }; 813 814 struct mlx4_set_port_rqp_calc_context { 815 __be32 base_qpn; 816 u8 rererved; 817 u8 n_mac; 818 u8 n_vlan; 819 u8 n_prio; 820 u8 reserved2[3]; 821 u8 mac_miss; 822 u8 intra_no_vlan; 823 u8 no_vlan; 824 u8 intra_vlan_miss; 825 u8 vlan_miss; 826 u8 reserved3[3]; 827 u8 no_vlan_prio; 828 __be32 promisc; 829 __be32 mcast; 830 }; 831 832 struct mlx4_port_info { 833 struct mlx4_dev *dev; 834 int port; 835 char dev_name[16]; 836 struct device_attribute port_attr; 837 enum mlx4_port_type tmp_type; 838 char dev_mtu_name[16]; 839 struct device_attribute port_mtu_attr; 840 struct mlx4_mac_table mac_table; 841 struct mlx4_vlan_table vlan_table; 842 struct mlx4_roce_gid_table gid_table; 843 int base_qpn; 844 struct cpu_rmap *rmap; 845 struct devlink_port devlink_port; 846 }; 847 848 struct mlx4_sense { 849 struct mlx4_dev *dev; 850 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 851 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 852 struct delayed_work sense_poll; 853 }; 854 855 struct mlx4_msix_ctl { 856 DECLARE_BITMAP(pool_bm, MAX_MSIX); 857 struct mutex pool_lock; 858 }; 859 860 struct mlx4_steer { 861 struct list_head promisc_qps[MLX4_NUM_STEERS]; 862 struct list_head steer_entries[MLX4_NUM_STEERS]; 863 }; 864 865 enum { 866 MLX4_PCI_DEV_IS_VF = 1 << 0, 867 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 868 }; 869 870 enum { 871 MLX4_NO_RR = 0, 872 MLX4_USE_RR = 1, 873 }; 874 875 struct mlx4_priv { 876 struct mlx4_dev dev; 877 878 struct list_head dev_list; 879 struct list_head ctx_list; 880 spinlock_t ctx_lock; 881 882 int pci_dev_data; 883 int removed; 884 885 struct list_head pgdir_list; 886 struct mutex pgdir_mutex; 887 888 struct mlx4_fw fw; 889 struct mlx4_cmd cmd; 890 struct mlx4_mfunc mfunc; 891 892 struct mlx4_bitmap pd_bitmap; 893 struct mlx4_bitmap xrcd_bitmap; 894 struct mlx4_uar_table uar_table; 895 struct mlx4_mr_table mr_table; 896 struct mlx4_cq_table cq_table; 897 struct mlx4_eq_table eq_table; 898 struct mlx4_srq_table srq_table; 899 struct mlx4_qp_table qp_table; 900 struct mlx4_mcg_table mcg_table; 901 struct mlx4_bitmap counters_bitmap; 902 int def_counter[MLX4_MAX_PORTS]; 903 904 struct mlx4_catas_err catas_err; 905 906 void __iomem *clr_base; 907 908 struct mlx4_uar driver_uar; 909 void __iomem *kar; 910 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 911 struct mlx4_sense sense; 912 struct mutex port_mutex; 913 struct mlx4_msix_ctl msix_ctl; 914 struct mlx4_steer *steer; 915 struct list_head bf_list; 916 struct mutex bf_mutex; 917 struct io_mapping *bf_mapping; 918 void __iomem *clock_mapping; 919 int reserved_mtts; 920 int fs_hash_mode; 921 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 922 struct mlx4_port_map v2p; /* cached port mapping configuration */ 923 struct mutex bond_mutex; /* for bond mode */ 924 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 925 926 atomic_t opreq_count; 927 struct work_struct opreq_task; 928 }; 929 930 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 931 { 932 return container_of(dev, struct mlx4_priv, dev); 933 } 934 935 #define MLX4_SENSE_RANGE (HZ * 3) 936 937 extern struct workqueue_struct *mlx4_wq; 938 939 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 940 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 941 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 942 int align, u32 skip_mask); 943 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 944 int use_rr); 945 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 946 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 947 u32 reserved_bot, u32 resetrved_top); 948 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 949 950 int mlx4_reset(struct mlx4_dev *dev); 951 952 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 953 void mlx4_free_eq_table(struct mlx4_dev *dev); 954 955 int mlx4_init_pd_table(struct mlx4_dev *dev); 956 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 957 int mlx4_init_uar_table(struct mlx4_dev *dev); 958 int mlx4_init_mr_table(struct mlx4_dev *dev); 959 int mlx4_init_eq_table(struct mlx4_dev *dev); 960 int mlx4_init_cq_table(struct mlx4_dev *dev); 961 int mlx4_init_qp_table(struct mlx4_dev *dev); 962 int mlx4_init_srq_table(struct mlx4_dev *dev); 963 int mlx4_init_mcg_table(struct mlx4_dev *dev); 964 965 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 966 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 967 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 968 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 969 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 970 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 971 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 972 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 973 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 974 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 975 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 976 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 977 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 978 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 979 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 980 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 981 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 982 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 983 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 984 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 985 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 986 987 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 988 struct mlx4_vhcr *vhcr, 989 struct mlx4_cmd_mailbox *inbox, 990 struct mlx4_cmd_mailbox *outbox, 991 struct mlx4_cmd_info *cmd); 992 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 993 struct mlx4_vhcr *vhcr, 994 struct mlx4_cmd_mailbox *inbox, 995 struct mlx4_cmd_mailbox *outbox, 996 struct mlx4_cmd_info *cmd); 997 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 998 struct mlx4_vhcr *vhcr, 999 struct mlx4_cmd_mailbox *inbox, 1000 struct mlx4_cmd_mailbox *outbox, 1001 struct mlx4_cmd_info *cmd); 1002 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 1003 struct mlx4_vhcr *vhcr, 1004 struct mlx4_cmd_mailbox *inbox, 1005 struct mlx4_cmd_mailbox *outbox, 1006 struct mlx4_cmd_info *cmd); 1007 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 1008 struct mlx4_vhcr *vhcr, 1009 struct mlx4_cmd_mailbox *inbox, 1010 struct mlx4_cmd_mailbox *outbox, 1011 struct mlx4_cmd_info *cmd); 1012 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1013 struct mlx4_vhcr *vhcr, 1014 struct mlx4_cmd_mailbox *inbox, 1015 struct mlx4_cmd_mailbox *outbox, 1016 struct mlx4_cmd_info *cmd); 1017 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 1018 struct mlx4_vhcr *vhcr, 1019 struct mlx4_cmd_mailbox *inbox, 1020 struct mlx4_cmd_mailbox *outbox, 1021 struct mlx4_cmd_info *cmd); 1022 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 1023 struct mlx4_vhcr *vhcr, 1024 struct mlx4_cmd_mailbox *inbox, 1025 struct mlx4_cmd_mailbox *outbox, 1026 struct mlx4_cmd_info *cmd); 1027 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1028 int *base, u8 flags); 1029 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1030 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1031 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1032 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1033 int start_index, int npages, u64 *page_list); 1034 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1035 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1036 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1037 struct mlx4_counter *data); 1038 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1039 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1040 1041 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1042 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1043 int mlx4_catas_init(struct mlx4_dev *dev); 1044 void mlx4_catas_end(struct mlx4_dev *dev); 1045 int mlx4_restart_one(struct pci_dev *pdev); 1046 int mlx4_register_device(struct mlx4_dev *dev); 1047 void mlx4_unregister_device(struct mlx4_dev *dev); 1048 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1049 unsigned long param); 1050 1051 struct mlx4_dev_cap; 1052 struct mlx4_init_hca_param; 1053 1054 u64 mlx4_make_profile(struct mlx4_dev *dev, 1055 struct mlx4_profile *request, 1056 struct mlx4_dev_cap *dev_cap, 1057 struct mlx4_init_hca_param *init_hca); 1058 void mlx4_master_comm_channel(struct work_struct *work); 1059 void mlx4_gen_slave_eqe(struct work_struct *work); 1060 void mlx4_master_handle_slave_flr(struct work_struct *work); 1061 1062 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1063 struct mlx4_vhcr *vhcr, 1064 struct mlx4_cmd_mailbox *inbox, 1065 struct mlx4_cmd_mailbox *outbox, 1066 struct mlx4_cmd_info *cmd); 1067 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1068 struct mlx4_vhcr *vhcr, 1069 struct mlx4_cmd_mailbox *inbox, 1070 struct mlx4_cmd_mailbox *outbox, 1071 struct mlx4_cmd_info *cmd); 1072 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1073 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1077 struct mlx4_vhcr *vhcr, 1078 struct mlx4_cmd_mailbox *inbox, 1079 struct mlx4_cmd_mailbox *outbox, 1080 struct mlx4_cmd_info *cmd); 1081 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1082 struct mlx4_vhcr *vhcr, 1083 struct mlx4_cmd_mailbox *inbox, 1084 struct mlx4_cmd_mailbox *outbox, 1085 struct mlx4_cmd_info *cmd); 1086 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1087 struct mlx4_vhcr *vhcr, 1088 struct mlx4_cmd_mailbox *inbox, 1089 struct mlx4_cmd_mailbox *outbox, 1090 struct mlx4_cmd_info *cmd); 1091 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1092 struct mlx4_vhcr *vhcr, 1093 struct mlx4_cmd_mailbox *inbox, 1094 struct mlx4_cmd_mailbox *outbox, 1095 struct mlx4_cmd_info *cmd); 1096 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1097 struct mlx4_vhcr *vhcr, 1098 struct mlx4_cmd_mailbox *inbox, 1099 struct mlx4_cmd_mailbox *outbox, 1100 struct mlx4_cmd_info *cmd); 1101 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1102 struct mlx4_vhcr *vhcr, 1103 struct mlx4_cmd_mailbox *inbox, 1104 struct mlx4_cmd_mailbox *outbox, 1105 struct mlx4_cmd_info *cmd); 1106 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1107 struct mlx4_vhcr *vhcr, 1108 struct mlx4_cmd_mailbox *inbox, 1109 struct mlx4_cmd_mailbox *outbox, 1110 struct mlx4_cmd_info *cmd); 1111 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1112 struct mlx4_vhcr *vhcr, 1113 struct mlx4_cmd_mailbox *inbox, 1114 struct mlx4_cmd_mailbox *outbox, 1115 struct mlx4_cmd_info *cmd); 1116 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1117 struct mlx4_vhcr *vhcr, 1118 struct mlx4_cmd_mailbox *inbox, 1119 struct mlx4_cmd_mailbox *outbox, 1120 struct mlx4_cmd_info *cmd); 1121 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1122 struct mlx4_vhcr *vhcr, 1123 struct mlx4_cmd_mailbox *inbox, 1124 struct mlx4_cmd_mailbox *outbox, 1125 struct mlx4_cmd_info *cmd); 1126 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1127 struct mlx4_vhcr *vhcr, 1128 struct mlx4_cmd_mailbox *inbox, 1129 struct mlx4_cmd_mailbox *outbox, 1130 struct mlx4_cmd_info *cmd); 1131 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1132 struct mlx4_vhcr *vhcr, 1133 struct mlx4_cmd_mailbox *inbox, 1134 struct mlx4_cmd_mailbox *outbox, 1135 struct mlx4_cmd_info *cmd); 1136 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1137 struct mlx4_vhcr *vhcr, 1138 struct mlx4_cmd_mailbox *inbox, 1139 struct mlx4_cmd_mailbox *outbox, 1140 struct mlx4_cmd_info *cmd); 1141 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1142 struct mlx4_vhcr *vhcr, 1143 struct mlx4_cmd_mailbox *inbox, 1144 struct mlx4_cmd_mailbox *outbox, 1145 struct mlx4_cmd_info *cmd); 1146 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1147 struct mlx4_vhcr *vhcr, 1148 struct mlx4_cmd_mailbox *inbox, 1149 struct mlx4_cmd_mailbox *outbox, 1150 struct mlx4_cmd_info *cmd); 1151 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1152 struct mlx4_vhcr *vhcr, 1153 struct mlx4_cmd_mailbox *inbox, 1154 struct mlx4_cmd_mailbox *outbox, 1155 struct mlx4_cmd_info *cmd); 1156 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1157 struct mlx4_vhcr *vhcr, 1158 struct mlx4_cmd_mailbox *inbox, 1159 struct mlx4_cmd_mailbox *outbox, 1160 struct mlx4_cmd_info *cmd); 1161 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1162 struct mlx4_vhcr *vhcr, 1163 struct mlx4_cmd_mailbox *inbox, 1164 struct mlx4_cmd_mailbox *outbox, 1165 struct mlx4_cmd_info *cmd); 1166 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1167 struct mlx4_vhcr *vhcr, 1168 struct mlx4_cmd_mailbox *inbox, 1169 struct mlx4_cmd_mailbox *outbox, 1170 struct mlx4_cmd_info *cmd); 1171 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1172 struct mlx4_vhcr *vhcr, 1173 struct mlx4_cmd_mailbox *inbox, 1174 struct mlx4_cmd_mailbox *outbox, 1175 struct mlx4_cmd_info *cmd); 1176 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1177 struct mlx4_vhcr *vhcr, 1178 struct mlx4_cmd_mailbox *inbox, 1179 struct mlx4_cmd_mailbox *outbox, 1180 struct mlx4_cmd_info *cmd); 1181 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1182 struct mlx4_vhcr *vhcr, 1183 struct mlx4_cmd_mailbox *inbox, 1184 struct mlx4_cmd_mailbox *outbox, 1185 struct mlx4_cmd_info *cmd); 1186 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1187 struct mlx4_vhcr *vhcr, 1188 struct mlx4_cmd_mailbox *inbox, 1189 struct mlx4_cmd_mailbox *outbox, 1190 struct mlx4_cmd_info *cmd); 1191 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1192 struct mlx4_vhcr *vhcr, 1193 struct mlx4_cmd_mailbox *inbox, 1194 struct mlx4_cmd_mailbox *outbox, 1195 struct mlx4_cmd_info *cmd); 1196 1197 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1198 1199 enum { 1200 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1201 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1202 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1203 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1204 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1205 }; 1206 1207 int mlx4_cmd_init(struct mlx4_dev *dev); 1208 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1209 int mlx4_multi_func_init(struct mlx4_dev *dev); 1210 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1211 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1212 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1213 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1214 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1215 1216 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1217 u16 op, unsigned long timeout); 1218 1219 void mlx4_cq_tasklet_cb(unsigned long data); 1220 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1221 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1222 1223 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1224 1225 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1226 1227 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1228 int mlx4_comm_internal_err(u32 slave_read); 1229 1230 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1231 enum mlx4_port_type *type); 1232 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1233 enum mlx4_port_type *stype, 1234 enum mlx4_port_type *defaults); 1235 void mlx4_start_sense(struct mlx4_dev *dev); 1236 void mlx4_stop_sense(struct mlx4_dev *dev); 1237 void mlx4_sense_init(struct mlx4_dev *dev); 1238 int mlx4_check_port_params(struct mlx4_dev *dev, 1239 enum mlx4_port_type *port_type); 1240 int mlx4_change_port_types(struct mlx4_dev *dev, 1241 enum mlx4_port_type *port_types); 1242 1243 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1244 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1245 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1246 struct mlx4_roce_gid_table *table); 1247 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1248 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1249 int mlx4_bond_vlan_table(struct mlx4_dev *dev); 1250 int mlx4_unbond_vlan_table(struct mlx4_dev *dev); 1251 int mlx4_bond_mac_table(struct mlx4_dev *dev); 1252 int mlx4_unbond_mac_table(struct mlx4_dev *dev); 1253 1254 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1255 /* resource tracker functions*/ 1256 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1257 enum mlx4_resource resource_type, 1258 u64 resource_id, int *slave); 1259 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1260 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1261 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1262 1263 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1264 enum mlx4_res_tracker_free_type type); 1265 1266 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1267 struct mlx4_vhcr *vhcr, 1268 struct mlx4_cmd_mailbox *inbox, 1269 struct mlx4_cmd_mailbox *outbox, 1270 struct mlx4_cmd_info *cmd); 1271 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1272 struct mlx4_vhcr *vhcr, 1273 struct mlx4_cmd_mailbox *inbox, 1274 struct mlx4_cmd_mailbox *outbox, 1275 struct mlx4_cmd_info *cmd); 1276 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1277 struct mlx4_vhcr *vhcr, 1278 struct mlx4_cmd_mailbox *inbox, 1279 struct mlx4_cmd_mailbox *outbox, 1280 struct mlx4_cmd_info *cmd); 1281 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1282 struct mlx4_vhcr *vhcr, 1283 struct mlx4_cmd_mailbox *inbox, 1284 struct mlx4_cmd_mailbox *outbox, 1285 struct mlx4_cmd_info *cmd); 1286 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1287 struct mlx4_vhcr *vhcr, 1288 struct mlx4_cmd_mailbox *inbox, 1289 struct mlx4_cmd_mailbox *outbox, 1290 struct mlx4_cmd_info *cmd); 1291 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1292 struct mlx4_vhcr *vhcr, 1293 struct mlx4_cmd_mailbox *inbox, 1294 struct mlx4_cmd_mailbox *outbox, 1295 struct mlx4_cmd_info *cmd); 1296 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1297 1298 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1299 int *gid_tbl_len, int *pkey_tbl_len); 1300 1301 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1302 struct mlx4_vhcr *vhcr, 1303 struct mlx4_cmd_mailbox *inbox, 1304 struct mlx4_cmd_mailbox *outbox, 1305 struct mlx4_cmd_info *cmd); 1306 1307 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1308 struct mlx4_vhcr *vhcr, 1309 struct mlx4_cmd_mailbox *inbox, 1310 struct mlx4_cmd_mailbox *outbox, 1311 struct mlx4_cmd_info *cmd); 1312 1313 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1314 struct mlx4_vhcr *vhcr, 1315 struct mlx4_cmd_mailbox *inbox, 1316 struct mlx4_cmd_mailbox *outbox, 1317 struct mlx4_cmd_info *cmd); 1318 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1319 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1320 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1321 int block_mcast_loopback, enum mlx4_protocol prot, 1322 enum mlx4_steer_type steer); 1323 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1324 u8 gid[16], u8 port, 1325 int block_mcast_loopback, 1326 enum mlx4_protocol prot, u64 *reg_id); 1327 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1328 struct mlx4_vhcr *vhcr, 1329 struct mlx4_cmd_mailbox *inbox, 1330 struct mlx4_cmd_mailbox *outbox, 1331 struct mlx4_cmd_info *cmd); 1332 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1333 struct mlx4_vhcr *vhcr, 1334 struct mlx4_cmd_mailbox *inbox, 1335 struct mlx4_cmd_mailbox *outbox, 1336 struct mlx4_cmd_info *cmd); 1337 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1338 int port, void *buf); 1339 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1340 struct mlx4_vhcr *vhcr, 1341 struct mlx4_cmd_mailbox *inbox, 1342 struct mlx4_cmd_mailbox *outbox, 1343 struct mlx4_cmd_info *cmd); 1344 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1345 struct mlx4_vhcr *vhcr, 1346 struct mlx4_cmd_mailbox *inbox, 1347 struct mlx4_cmd_mailbox *outbox, 1348 struct mlx4_cmd_info *cmd); 1349 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1350 struct mlx4_vhcr *vhcr, 1351 struct mlx4_cmd_mailbox *inbox, 1352 struct mlx4_cmd_mailbox *outbox, 1353 struct mlx4_cmd_info *cmd); 1354 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1355 struct mlx4_vhcr *vhcr, 1356 struct mlx4_cmd_mailbox *inbox, 1357 struct mlx4_cmd_mailbox *outbox, 1358 struct mlx4_cmd_info *cmd); 1359 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1360 struct mlx4_vhcr *vhcr, 1361 struct mlx4_cmd_mailbox *inbox, 1362 struct mlx4_cmd_mailbox *outbox, 1363 struct mlx4_cmd_info *cmd); 1364 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1365 struct mlx4_vhcr *vhcr, 1366 struct mlx4_cmd_mailbox *inbox, 1367 struct mlx4_cmd_mailbox *outbox, 1368 struct mlx4_cmd_info *cmd); 1369 1370 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1371 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1372 1373 static inline void set_param_l(u64 *arg, u32 val) 1374 { 1375 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1376 } 1377 1378 static inline void set_param_h(u64 *arg, u32 val) 1379 { 1380 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1381 } 1382 1383 static inline u32 get_param_l(u64 *arg) 1384 { 1385 return (u32) (*arg & 0xffffffff); 1386 } 1387 1388 static inline u32 get_param_h(u64 *arg) 1389 { 1390 return (u32)(*arg >> 32); 1391 } 1392 1393 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1394 { 1395 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1396 } 1397 1398 #define NOT_MASKED_PD_BITS 17 1399 1400 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1401 1402 void mlx4_init_quotas(struct mlx4_dev *dev); 1403 1404 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */ 1405 void mlx4_replace_zero_macs(struct mlx4_dev *dev); 1406 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1407 /* Returns the VF index of slave */ 1408 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1409 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1410 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1411 int mlx4_bond_fs_rules(struct mlx4_dev *dev); 1412 int mlx4_unbond_fs_rules(struct mlx4_dev *dev); 1413 1414 enum mlx4_zone_flags { 1415 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1416 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1417 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1418 MLX4_ZONE_USE_RR = 1UL << 3, 1419 }; 1420 1421 enum mlx4_zone_alloc_flags { 1422 /* No two objects could overlap between zones. UID 1423 * could be left unused. If this flag is given and 1424 * two overlapped zones are used, an object will be free'd 1425 * from the smallest possible matching zone. 1426 */ 1427 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1428 }; 1429 1430 struct mlx4_zone_allocator; 1431 1432 /* Create a new zone allocator */ 1433 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1434 1435 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1436 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1437 * Similarly, when searching for an object to free, this offset it taken into 1438 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1439 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1440 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1441 * according to the policy set by <flags>. <puid> is the unique identifier 1442 * received to this zone. 1443 */ 1444 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1445 struct mlx4_bitmap *bitmap, 1446 u32 flags, 1447 int priority, 1448 int offset, 1449 u32 *puid); 1450 1451 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1452 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1453 1454 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1455 * the attached bitmaps. 1456 */ 1457 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1458 1459 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1460 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1461 * allocated from is returned in <puid>. If the allocation fails, a negative 1462 * number is returned. Otherwise, the offset of the first object is returned. 1463 */ 1464 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1465 int align, u32 skip_mask, u32 *puid); 1466 1467 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1468 * <zones>. 1469 */ 1470 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1471 u32 uid, u32 obj, u32 count); 1472 1473 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1474 * specifying the uid when freeing an object, zone allocator could figure it by 1475 * itself. Other parameters are similar to mlx4_zone_free. 1476 */ 1477 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1478 1479 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1480 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1481 1482 #endif /* MLX4_H */ 1483