1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static uint8_t num_vfs[3] = {0, 0, 0}; 81 static int num_vfs_argc; 82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 84 "num_vfs=port1,port2,port1+2"); 85 86 static uint8_t probe_vf[3] = {0, 0, 0}; 87 static int probe_vfs_argc; 88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 90 "probe_vf=port1,port2,port1+2"); 91 92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 93 module_param_named(log_num_mgm_entry_size, 94 mlx4_log_num_mgm_entry_size, int, 0444); 95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 96 " of qp per mcg, for example:" 97 " 10 gives 248.range: 7 <=" 98 " log_num_mgm_entry_size <= 12." 99 " To activate device managed" 100 " flow steering when available, set to -1"); 101 102 static bool enable_64b_cqe_eqe = true; 103 module_param(enable_64b_cqe_eqe, bool, 0444); 104 MODULE_PARM_DESC(enable_64b_cqe_eqe, 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 106 107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 109 MLX4_FUNC_CAP_DMFS_A0_STATIC) 110 111 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 112 113 static char mlx4_version[] = 114 DRV_NAME ": Mellanox ConnectX core driver v" 115 DRV_VERSION " (" DRV_RELDATE ")\n"; 116 117 static struct mlx4_profile default_profile = { 118 .num_qp = 1 << 18, 119 .num_srq = 1 << 16, 120 .rdmarc_per_qp = 1 << 4, 121 .num_cq = 1 << 16, 122 .num_mcg = 1 << 13, 123 .num_mpt = 1 << 19, 124 .num_mtt = 1 << 20, /* It is really num mtt segements */ 125 }; 126 127 static struct mlx4_profile low_mem_profile = { 128 .num_qp = 1 << 17, 129 .num_srq = 1 << 6, 130 .rdmarc_per_qp = 1 << 4, 131 .num_cq = 1 << 8, 132 .num_mcg = 1 << 8, 133 .num_mpt = 1 << 9, 134 .num_mtt = 1 << 7, 135 }; 136 137 static int log_num_mac = 7; 138 module_param_named(log_num_mac, log_num_mac, int, 0444); 139 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 140 141 static int log_num_vlan; 142 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 143 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 144 /* Log2 max number of VLANs per ETH port (0-7) */ 145 #define MLX4_LOG_NUM_VLANS 7 146 #define MLX4_MIN_LOG_NUM_VLANS 0 147 #define MLX4_MIN_LOG_NUM_MAC 1 148 149 static bool use_prio; 150 module_param_named(use_prio, use_prio, bool, 0444); 151 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 152 153 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 154 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 155 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 156 157 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 158 static int arr_argc = 2; 159 module_param_array(port_type_array, int, &arr_argc, 0444); 160 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 161 "1 for IB, 2 for Ethernet"); 162 163 struct mlx4_port_config { 164 struct list_head list; 165 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 166 struct pci_dev *pdev; 167 }; 168 169 static atomic_t pf_loading = ATOMIC_INIT(0); 170 171 int mlx4_check_port_params(struct mlx4_dev *dev, 172 enum mlx4_port_type *port_type) 173 { 174 int i; 175 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 177 for (i = 0; i < dev->caps.num_ports - 1; i++) { 178 if (port_type[i] != port_type[i + 1]) { 179 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 180 return -EINVAL; 181 } 182 } 183 } 184 185 for (i = 0; i < dev->caps.num_ports; i++) { 186 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 187 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 188 i + 1); 189 return -EINVAL; 190 } 191 } 192 return 0; 193 } 194 195 static void mlx4_set_port_mask(struct mlx4_dev *dev) 196 { 197 int i; 198 199 for (i = 1; i <= dev->caps.num_ports; ++i) 200 dev->caps.port_mask[i] = dev->caps.port_type[i]; 201 } 202 203 enum { 204 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 205 }; 206 207 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 208 { 209 int err = 0; 210 struct mlx4_func func; 211 212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 213 err = mlx4_QUERY_FUNC(dev, &func, 0); 214 if (err) { 215 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 216 return err; 217 } 218 dev_cap->max_eqs = func.max_eq; 219 dev_cap->reserved_eqs = func.rsvd_eqs; 220 dev_cap->reserved_uars = func.rsvd_uars; 221 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 222 } 223 return err; 224 } 225 226 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 227 { 228 struct mlx4_caps *dev_cap = &dev->caps; 229 230 /* FW not supporting or cancelled by user */ 231 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 232 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 233 return; 234 235 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 236 * When FW has NCSI it may decide not to report 64B CQE/EQEs 237 */ 238 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 239 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 240 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 241 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 242 return; 243 } 244 245 if (cache_line_size() == 128 || cache_line_size() == 256) { 246 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 247 /* Changing the real data inside CQE size to 32B */ 248 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 249 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 250 251 if (mlx4_is_master(dev)) 252 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 253 } else { 254 if (cache_line_size() != 32 && cache_line_size() != 64) 255 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 257 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 258 } 259 } 260 261 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 262 struct mlx4_port_cap *port_cap) 263 { 264 dev->caps.vl_cap[port] = port_cap->max_vl; 265 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 266 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 267 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 268 /* set gid and pkey table operating lengths by default 269 * to non-sriov values 270 */ 271 dev->caps.gid_table_len[port] = port_cap->max_gids; 272 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 273 dev->caps.port_width_cap[port] = port_cap->max_port_width; 274 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 275 dev->caps.def_mac[port] = port_cap->def_mac; 276 dev->caps.supported_type[port] = port_cap->supported_port_types; 277 dev->caps.suggested_type[port] = port_cap->suggested_type; 278 dev->caps.default_sense[port] = port_cap->default_sense; 279 dev->caps.trans_type[port] = port_cap->trans_type; 280 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 281 dev->caps.wavelength[port] = port_cap->wavelength; 282 dev->caps.trans_code[port] = port_cap->trans_code; 283 284 return 0; 285 } 286 287 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 288 struct mlx4_port_cap *port_cap) 289 { 290 int err = 0; 291 292 err = mlx4_QUERY_PORT(dev, port, port_cap); 293 294 if (err) 295 mlx4_err(dev, "QUERY_PORT command failed.\n"); 296 297 return err; 298 } 299 300 #define MLX4_A0_STEERING_TABLE_SIZE 256 301 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 302 { 303 int err; 304 int i; 305 306 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 307 if (err) { 308 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 309 return err; 310 } 311 mlx4_dev_cap_dump(dev, dev_cap); 312 313 if (dev_cap->min_page_sz > PAGE_SIZE) { 314 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 315 dev_cap->min_page_sz, PAGE_SIZE); 316 return -ENODEV; 317 } 318 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 319 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 320 dev_cap->num_ports, MLX4_MAX_PORTS); 321 return -ENODEV; 322 } 323 324 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 325 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 326 dev_cap->uar_size, 327 (unsigned long long) 328 pci_resource_len(dev->persist->pdev, 2)); 329 return -ENODEV; 330 } 331 332 dev->caps.num_ports = dev_cap->num_ports; 333 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 334 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 335 dev->caps.num_sys_eqs : 336 MLX4_MAX_EQ_NUM; 337 for (i = 1; i <= dev->caps.num_ports; ++i) { 338 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 339 if (err) { 340 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 341 return err; 342 } 343 } 344 345 dev->caps.uar_page_size = PAGE_SIZE; 346 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 347 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 348 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 349 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 350 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 351 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 352 dev->caps.max_wqes = dev_cap->max_qp_sz; 353 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 354 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 355 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 356 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 357 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 358 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 359 /* 360 * Subtract 1 from the limit because we need to allocate a 361 * spare CQE so the HCA HW can tell the difference between an 362 * empty CQ and a full CQ. 363 */ 364 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 365 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 366 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 367 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 368 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 369 370 /* The first 128 UARs are used for EQ doorbells */ 371 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 372 dev->caps.reserved_pds = dev_cap->reserved_pds; 373 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 374 dev_cap->reserved_xrcds : 0; 375 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 376 dev_cap->max_xrcds : 0; 377 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 378 379 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 380 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 381 dev->caps.flags = dev_cap->flags; 382 dev->caps.flags2 = dev_cap->flags2; 383 dev->caps.bmme_flags = dev_cap->bmme_flags; 384 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 385 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 386 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 387 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 388 389 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 390 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 391 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 392 /* Don't do sense port on multifunction devices (for now at least) */ 393 if (mlx4_is_mfunc(dev)) 394 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 395 396 if (mlx4_low_memory_profile()) { 397 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 398 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 399 } else { 400 dev->caps.log_num_macs = log_num_mac; 401 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 402 } 403 404 for (i = 1; i <= dev->caps.num_ports; ++i) { 405 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 406 if (dev->caps.supported_type[i]) { 407 /* if only ETH is supported - assign ETH */ 408 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 409 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 410 /* if only IB is supported, assign IB */ 411 else if (dev->caps.supported_type[i] == 412 MLX4_PORT_TYPE_IB) 413 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 414 else { 415 /* if IB and ETH are supported, we set the port 416 * type according to user selection of port type; 417 * if user selected none, take the FW hint */ 418 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 419 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 420 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 421 else 422 dev->caps.port_type[i] = port_type_array[i - 1]; 423 } 424 } 425 /* 426 * Link sensing is allowed on the port if 3 conditions are true: 427 * 1. Both protocols are supported on the port. 428 * 2. Different types are supported on the port 429 * 3. FW declared that it supports link sensing 430 */ 431 mlx4_priv(dev)->sense.sense_allowed[i] = 432 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 433 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 434 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 435 436 /* 437 * If "default_sense" bit is set, we move the port to "AUTO" mode 438 * and perform sense_port FW command to try and set the correct 439 * port type from beginning 440 */ 441 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 442 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 443 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 444 mlx4_SENSE_PORT(dev, i, &sensed_port); 445 if (sensed_port != MLX4_PORT_TYPE_NONE) 446 dev->caps.port_type[i] = sensed_port; 447 } else { 448 dev->caps.possible_type[i] = dev->caps.port_type[i]; 449 } 450 451 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 452 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 453 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 454 i, 1 << dev->caps.log_num_macs); 455 } 456 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 457 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 458 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 459 i, 1 << dev->caps.log_num_vlans); 460 } 461 } 462 463 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 464 465 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 467 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 468 (1 << dev->caps.log_num_macs) * 469 (1 << dev->caps.log_num_vlans) * 470 dev->caps.num_ports; 471 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 472 473 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 474 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 475 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 476 else 477 dev->caps.dmfs_high_rate_qpn_base = 478 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 479 480 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 481 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 482 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 483 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 484 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 485 } else { 486 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 487 dev->caps.dmfs_high_rate_qpn_base = 488 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 489 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 490 } 491 492 dev->caps.rl_caps = dev_cap->rl_caps; 493 494 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 495 dev->caps.dmfs_high_rate_qpn_range; 496 497 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 498 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 499 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 500 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 501 502 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 503 504 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 505 if (dev_cap->flags & 506 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 507 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 508 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 509 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 510 } 511 512 if (dev_cap->flags2 & 513 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 514 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 515 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 516 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 517 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 518 } 519 } 520 521 if ((dev->caps.flags & 522 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 523 mlx4_is_master(dev)) 524 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 525 526 if (!mlx4_is_slave(dev)) { 527 mlx4_enable_cqe_eqe_stride(dev); 528 dev->caps.alloc_res_qp_mask = 529 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 530 MLX4_RESERVE_A0_QP; 531 } else { 532 dev->caps.alloc_res_qp_mask = 0; 533 } 534 535 return 0; 536 } 537 538 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 539 enum pci_bus_speed *speed, 540 enum pcie_link_width *width) 541 { 542 u32 lnkcap1, lnkcap2; 543 int err1, err2; 544 545 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 546 547 *speed = PCI_SPEED_UNKNOWN; 548 *width = PCIE_LNK_WIDTH_UNKNOWN; 549 550 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP, 551 &lnkcap1); 552 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2, 553 &lnkcap2); 554 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 555 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 556 *speed = PCIE_SPEED_8_0GT; 557 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 558 *speed = PCIE_SPEED_5_0GT; 559 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 560 *speed = PCIE_SPEED_2_5GT; 561 } 562 if (!err1) { 563 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 564 if (!lnkcap2) { /* pre-r3.0 */ 565 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 566 *speed = PCIE_SPEED_5_0GT; 567 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 568 *speed = PCIE_SPEED_2_5GT; 569 } 570 } 571 572 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 573 return err1 ? err1 : 574 err2 ? err2 : -EINVAL; 575 } 576 return 0; 577 } 578 579 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 580 { 581 enum pcie_link_width width, width_cap; 582 enum pci_bus_speed speed, speed_cap; 583 int err; 584 585 #define PCIE_SPEED_STR(speed) \ 586 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 587 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 588 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 589 "Unknown") 590 591 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 592 if (err) { 593 mlx4_warn(dev, 594 "Unable to determine PCIe device BW capabilities\n"); 595 return; 596 } 597 598 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width); 599 if (err || speed == PCI_SPEED_UNKNOWN || 600 width == PCIE_LNK_WIDTH_UNKNOWN) { 601 mlx4_warn(dev, 602 "Unable to determine PCI device chain minimum BW\n"); 603 return; 604 } 605 606 if (width != width_cap || speed != speed_cap) 607 mlx4_warn(dev, 608 "PCIe BW is different than device's capability\n"); 609 610 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 611 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 612 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 613 width, width_cap); 614 return; 615 } 616 617 /*The function checks if there are live vf, return the num of them*/ 618 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 619 { 620 struct mlx4_priv *priv = mlx4_priv(dev); 621 struct mlx4_slave_state *s_state; 622 int i; 623 int ret = 0; 624 625 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 626 s_state = &priv->mfunc.master.slave_state[i]; 627 if (s_state->active && s_state->last_cmd != 628 MLX4_COMM_CMD_RESET) { 629 mlx4_warn(dev, "%s: slave: %d is still active\n", 630 __func__, i); 631 ret++; 632 } 633 } 634 return ret; 635 } 636 637 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 638 { 639 u32 qk = MLX4_RESERVED_QKEY_BASE; 640 641 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 642 qpn < dev->phys_caps.base_proxy_sqpn) 643 return -EINVAL; 644 645 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 646 /* tunnel qp */ 647 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 648 else 649 qk += qpn - dev->phys_caps.base_proxy_sqpn; 650 *qkey = qk; 651 return 0; 652 } 653 EXPORT_SYMBOL(mlx4_get_parav_qkey); 654 655 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 656 { 657 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 658 659 if (!mlx4_is_master(dev)) 660 return; 661 662 priv->virt2phys_pkey[slave][port - 1][i] = val; 663 } 664 EXPORT_SYMBOL(mlx4_sync_pkey_table); 665 666 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 667 { 668 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 669 670 if (!mlx4_is_master(dev)) 671 return; 672 673 priv->slave_node_guids[slave] = guid; 674 } 675 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 676 677 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 678 { 679 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 680 681 if (!mlx4_is_master(dev)) 682 return 0; 683 684 return priv->slave_node_guids[slave]; 685 } 686 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 687 688 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 689 { 690 struct mlx4_priv *priv = mlx4_priv(dev); 691 struct mlx4_slave_state *s_slave; 692 693 if (!mlx4_is_master(dev)) 694 return 0; 695 696 s_slave = &priv->mfunc.master.slave_state[slave]; 697 return !!s_slave->active; 698 } 699 EXPORT_SYMBOL(mlx4_is_slave_active); 700 701 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 702 struct mlx4_dev_cap *dev_cap, 703 struct mlx4_init_hca_param *hca_param) 704 { 705 dev->caps.steering_mode = hca_param->steering_mode; 706 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 707 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 708 dev->caps.fs_log_max_ucast_qp_range_size = 709 dev_cap->fs_log_max_ucast_qp_range_size; 710 } else 711 dev->caps.num_qp_per_mgm = 712 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 713 714 mlx4_dbg(dev, "Steering mode is: %s\n", 715 mlx4_steering_mode_str(dev->caps.steering_mode)); 716 } 717 718 static int mlx4_slave_cap(struct mlx4_dev *dev) 719 { 720 int err; 721 u32 page_size; 722 struct mlx4_dev_cap dev_cap; 723 struct mlx4_func_cap func_cap; 724 struct mlx4_init_hca_param hca_param; 725 u8 i; 726 727 memset(&hca_param, 0, sizeof(hca_param)); 728 err = mlx4_QUERY_HCA(dev, &hca_param); 729 if (err) { 730 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 731 return err; 732 } 733 734 /* fail if the hca has an unknown global capability 735 * at this time global_caps should be always zeroed 736 */ 737 if (hca_param.global_caps) { 738 mlx4_err(dev, "Unknown hca global capabilities\n"); 739 return -ENOSYS; 740 } 741 742 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 743 744 dev->caps.hca_core_clock = hca_param.hca_core_clock; 745 746 memset(&dev_cap, 0, sizeof(dev_cap)); 747 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 748 err = mlx4_dev_cap(dev, &dev_cap); 749 if (err) { 750 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 751 return err; 752 } 753 754 err = mlx4_QUERY_FW(dev); 755 if (err) 756 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 757 758 page_size = ~dev->caps.page_size_cap + 1; 759 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 760 if (page_size > PAGE_SIZE) { 761 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 762 page_size, PAGE_SIZE); 763 return -ENODEV; 764 } 765 766 /* slave gets uar page size from QUERY_HCA fw command */ 767 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 768 769 /* TODO: relax this assumption */ 770 if (dev->caps.uar_page_size != PAGE_SIZE) { 771 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 772 dev->caps.uar_page_size, PAGE_SIZE); 773 return -ENODEV; 774 } 775 776 memset(&func_cap, 0, sizeof(func_cap)); 777 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 778 if (err) { 779 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 780 err); 781 return err; 782 } 783 784 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 785 PF_CONTEXT_BEHAVIOUR_MASK) { 786 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 787 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK); 788 return -ENOSYS; 789 } 790 791 dev->caps.num_ports = func_cap.num_ports; 792 dev->quotas.qp = func_cap.qp_quota; 793 dev->quotas.srq = func_cap.srq_quota; 794 dev->quotas.cq = func_cap.cq_quota; 795 dev->quotas.mpt = func_cap.mpt_quota; 796 dev->quotas.mtt = func_cap.mtt_quota; 797 dev->caps.num_qps = 1 << hca_param.log_num_qps; 798 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 799 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 800 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 801 dev->caps.num_eqs = func_cap.max_eq; 802 dev->caps.reserved_eqs = func_cap.reserved_eq; 803 dev->caps.reserved_lkey = func_cap.reserved_lkey; 804 dev->caps.num_pds = MLX4_NUM_PDS; 805 dev->caps.num_mgms = 0; 806 dev->caps.num_amgms = 0; 807 808 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 809 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 810 dev->caps.num_ports, MLX4_MAX_PORTS); 811 return -ENODEV; 812 } 813 814 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); 815 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 816 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 817 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 818 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 819 820 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 821 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || 822 !dev->caps.qp0_qkey) { 823 err = -ENOMEM; 824 goto err_mem; 825 } 826 827 for (i = 1; i <= dev->caps.num_ports; ++i) { 828 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap); 829 if (err) { 830 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 831 i, err); 832 goto err_mem; 833 } 834 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; 835 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 836 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 837 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 838 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 839 dev->caps.port_mask[i] = dev->caps.port_type[i]; 840 dev->caps.phys_port_id[i] = func_cap.phys_port_id; 841 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 842 &dev->caps.gid_table_len[i], 843 &dev->caps.pkey_table_len[i])) 844 goto err_mem; 845 } 846 847 if (dev->caps.uar_page_size * (dev->caps.num_uars - 848 dev->caps.reserved_uars) > 849 pci_resource_len(dev->persist->pdev, 850 2)) { 851 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 852 dev->caps.uar_page_size * dev->caps.num_uars, 853 (unsigned long long) 854 pci_resource_len(dev->persist->pdev, 2)); 855 goto err_mem; 856 } 857 858 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 859 dev->caps.eqe_size = 64; 860 dev->caps.eqe_factor = 1; 861 } else { 862 dev->caps.eqe_size = 32; 863 dev->caps.eqe_factor = 0; 864 } 865 866 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 867 dev->caps.cqe_size = 64; 868 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 869 } else { 870 dev->caps.cqe_size = 32; 871 } 872 873 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 874 dev->caps.eqe_size = hca_param.eqe_size; 875 dev->caps.eqe_factor = 0; 876 } 877 878 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 879 dev->caps.cqe_size = hca_param.cqe_size; 880 /* User still need to know when CQE > 32B */ 881 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 882 } 883 884 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 885 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 886 887 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 888 889 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 890 dev->caps.bf_reg_size) 891 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 892 893 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 894 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 895 896 return 0; 897 898 err_mem: 899 kfree(dev->caps.qp0_qkey); 900 kfree(dev->caps.qp0_tunnel); 901 kfree(dev->caps.qp0_proxy); 902 kfree(dev->caps.qp1_tunnel); 903 kfree(dev->caps.qp1_proxy); 904 dev->caps.qp0_qkey = NULL; 905 dev->caps.qp0_tunnel = NULL; 906 dev->caps.qp0_proxy = NULL; 907 dev->caps.qp1_tunnel = NULL; 908 dev->caps.qp1_proxy = NULL; 909 910 return err; 911 } 912 913 static void mlx4_request_modules(struct mlx4_dev *dev) 914 { 915 int port; 916 int has_ib_port = false; 917 int has_eth_port = false; 918 #define EN_DRV_NAME "mlx4_en" 919 #define IB_DRV_NAME "mlx4_ib" 920 921 for (port = 1; port <= dev->caps.num_ports; port++) { 922 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 923 has_ib_port = true; 924 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 925 has_eth_port = true; 926 } 927 928 if (has_eth_port) 929 request_module_nowait(EN_DRV_NAME); 930 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 931 request_module_nowait(IB_DRV_NAME); 932 } 933 934 /* 935 * Change the port configuration of the device. 936 * Every user of this function must hold the port mutex. 937 */ 938 int mlx4_change_port_types(struct mlx4_dev *dev, 939 enum mlx4_port_type *port_types) 940 { 941 int err = 0; 942 int change = 0; 943 int port; 944 945 for (port = 0; port < dev->caps.num_ports; port++) { 946 /* Change the port type only if the new type is different 947 * from the current, and not set to Auto */ 948 if (port_types[port] != dev->caps.port_type[port + 1]) 949 change = 1; 950 } 951 if (change) { 952 mlx4_unregister_device(dev); 953 for (port = 1; port <= dev->caps.num_ports; port++) { 954 mlx4_CLOSE_PORT(dev, port); 955 dev->caps.port_type[port] = port_types[port - 1]; 956 err = mlx4_SET_PORT(dev, port, -1); 957 if (err) { 958 mlx4_err(dev, "Failed to set port %d, aborting\n", 959 port); 960 goto out; 961 } 962 } 963 mlx4_set_port_mask(dev); 964 err = mlx4_register_device(dev); 965 if (err) { 966 mlx4_err(dev, "Failed to register device\n"); 967 goto out; 968 } 969 mlx4_request_modules(dev); 970 } 971 972 out: 973 return err; 974 } 975 976 static ssize_t show_port_type(struct device *dev, 977 struct device_attribute *attr, 978 char *buf) 979 { 980 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 981 port_attr); 982 struct mlx4_dev *mdev = info->dev; 983 char type[8]; 984 985 sprintf(type, "%s", 986 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 987 "ib" : "eth"); 988 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 989 sprintf(buf, "auto (%s)\n", type); 990 else 991 sprintf(buf, "%s\n", type); 992 993 return strlen(buf); 994 } 995 996 static ssize_t set_port_type(struct device *dev, 997 struct device_attribute *attr, 998 const char *buf, size_t count) 999 { 1000 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1001 port_attr); 1002 struct mlx4_dev *mdev = info->dev; 1003 struct mlx4_priv *priv = mlx4_priv(mdev); 1004 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1005 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1006 static DEFINE_MUTEX(set_port_type_mutex); 1007 int i; 1008 int err = 0; 1009 1010 mutex_lock(&set_port_type_mutex); 1011 1012 if (!strcmp(buf, "ib\n")) 1013 info->tmp_type = MLX4_PORT_TYPE_IB; 1014 else if (!strcmp(buf, "eth\n")) 1015 info->tmp_type = MLX4_PORT_TYPE_ETH; 1016 else if (!strcmp(buf, "auto\n")) 1017 info->tmp_type = MLX4_PORT_TYPE_AUTO; 1018 else { 1019 mlx4_err(mdev, "%s is not supported port type\n", buf); 1020 err = -EINVAL; 1021 goto err_out; 1022 } 1023 1024 mlx4_stop_sense(mdev); 1025 mutex_lock(&priv->port_mutex); 1026 /* Possible type is always the one that was delivered */ 1027 mdev->caps.possible_type[info->port] = info->tmp_type; 1028 1029 for (i = 0; i < mdev->caps.num_ports; i++) { 1030 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1031 mdev->caps.possible_type[i+1]; 1032 if (types[i] == MLX4_PORT_TYPE_AUTO) 1033 types[i] = mdev->caps.port_type[i+1]; 1034 } 1035 1036 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1037 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1038 for (i = 1; i <= mdev->caps.num_ports; i++) { 1039 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1040 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1041 err = -EINVAL; 1042 } 1043 } 1044 } 1045 if (err) { 1046 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1047 goto out; 1048 } 1049 1050 mlx4_do_sense_ports(mdev, new_types, types); 1051 1052 err = mlx4_check_port_params(mdev, new_types); 1053 if (err) 1054 goto out; 1055 1056 /* We are about to apply the changes after the configuration 1057 * was verified, no need to remember the temporary types 1058 * any more */ 1059 for (i = 0; i < mdev->caps.num_ports; i++) 1060 priv->port[i + 1].tmp_type = 0; 1061 1062 err = mlx4_change_port_types(mdev, new_types); 1063 1064 out: 1065 mlx4_start_sense(mdev); 1066 mutex_unlock(&priv->port_mutex); 1067 err_out: 1068 mutex_unlock(&set_port_type_mutex); 1069 1070 return err ? err : count; 1071 } 1072 1073 enum ibta_mtu { 1074 IB_MTU_256 = 1, 1075 IB_MTU_512 = 2, 1076 IB_MTU_1024 = 3, 1077 IB_MTU_2048 = 4, 1078 IB_MTU_4096 = 5 1079 }; 1080 1081 static inline int int_to_ibta_mtu(int mtu) 1082 { 1083 switch (mtu) { 1084 case 256: return IB_MTU_256; 1085 case 512: return IB_MTU_512; 1086 case 1024: return IB_MTU_1024; 1087 case 2048: return IB_MTU_2048; 1088 case 4096: return IB_MTU_4096; 1089 default: return -1; 1090 } 1091 } 1092 1093 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1094 { 1095 switch (mtu) { 1096 case IB_MTU_256: return 256; 1097 case IB_MTU_512: return 512; 1098 case IB_MTU_1024: return 1024; 1099 case IB_MTU_2048: return 2048; 1100 case IB_MTU_4096: return 4096; 1101 default: return -1; 1102 } 1103 } 1104 1105 static ssize_t show_port_ib_mtu(struct device *dev, 1106 struct device_attribute *attr, 1107 char *buf) 1108 { 1109 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1110 port_mtu_attr); 1111 struct mlx4_dev *mdev = info->dev; 1112 1113 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1114 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1115 1116 sprintf(buf, "%d\n", 1117 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1118 return strlen(buf); 1119 } 1120 1121 static ssize_t set_port_ib_mtu(struct device *dev, 1122 struct device_attribute *attr, 1123 const char *buf, size_t count) 1124 { 1125 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1126 port_mtu_attr); 1127 struct mlx4_dev *mdev = info->dev; 1128 struct mlx4_priv *priv = mlx4_priv(mdev); 1129 int err, port, mtu, ibta_mtu = -1; 1130 1131 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1132 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1133 return -EINVAL; 1134 } 1135 1136 err = kstrtoint(buf, 0, &mtu); 1137 if (!err) 1138 ibta_mtu = int_to_ibta_mtu(mtu); 1139 1140 if (err || ibta_mtu < 0) { 1141 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1142 return -EINVAL; 1143 } 1144 1145 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1146 1147 mlx4_stop_sense(mdev); 1148 mutex_lock(&priv->port_mutex); 1149 mlx4_unregister_device(mdev); 1150 for (port = 1; port <= mdev->caps.num_ports; port++) { 1151 mlx4_CLOSE_PORT(mdev, port); 1152 err = mlx4_SET_PORT(mdev, port, -1); 1153 if (err) { 1154 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1155 port); 1156 goto err_set_port; 1157 } 1158 } 1159 err = mlx4_register_device(mdev); 1160 err_set_port: 1161 mutex_unlock(&priv->port_mutex); 1162 mlx4_start_sense(mdev); 1163 return err ? err : count; 1164 } 1165 1166 int mlx4_bond(struct mlx4_dev *dev) 1167 { 1168 int ret = 0; 1169 struct mlx4_priv *priv = mlx4_priv(dev); 1170 1171 mutex_lock(&priv->bond_mutex); 1172 1173 if (!mlx4_is_bonded(dev)) 1174 ret = mlx4_do_bond(dev, true); 1175 else 1176 ret = 0; 1177 1178 mutex_unlock(&priv->bond_mutex); 1179 if (ret) 1180 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1181 else 1182 mlx4_dbg(dev, "Device is bonded\n"); 1183 return ret; 1184 } 1185 EXPORT_SYMBOL_GPL(mlx4_bond); 1186 1187 int mlx4_unbond(struct mlx4_dev *dev) 1188 { 1189 int ret = 0; 1190 struct mlx4_priv *priv = mlx4_priv(dev); 1191 1192 mutex_lock(&priv->bond_mutex); 1193 1194 if (mlx4_is_bonded(dev)) 1195 ret = mlx4_do_bond(dev, false); 1196 1197 mutex_unlock(&priv->bond_mutex); 1198 if (ret) 1199 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1200 else 1201 mlx4_dbg(dev, "Device is unbonded\n"); 1202 return ret; 1203 } 1204 EXPORT_SYMBOL_GPL(mlx4_unbond); 1205 1206 1207 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1208 { 1209 u8 port1 = v2p->port1; 1210 u8 port2 = v2p->port2; 1211 struct mlx4_priv *priv = mlx4_priv(dev); 1212 int err; 1213 1214 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1215 return -ENOTSUPP; 1216 1217 mutex_lock(&priv->bond_mutex); 1218 1219 /* zero means keep current mapping for this port */ 1220 if (port1 == 0) 1221 port1 = priv->v2p.port1; 1222 if (port2 == 0) 1223 port2 = priv->v2p.port2; 1224 1225 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1226 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1227 (port1 == 2 && port2 == 1)) { 1228 /* besides boundary checks cross mapping makes 1229 * no sense and therefore not allowed */ 1230 err = -EINVAL; 1231 } else if ((port1 == priv->v2p.port1) && 1232 (port2 == priv->v2p.port2)) { 1233 err = 0; 1234 } else { 1235 err = mlx4_virt2phy_port_map(dev, port1, port2); 1236 if (!err) { 1237 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1238 port1, port2); 1239 priv->v2p.port1 = port1; 1240 priv->v2p.port2 = port2; 1241 } else { 1242 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1243 } 1244 } 1245 1246 mutex_unlock(&priv->bond_mutex); 1247 return err; 1248 } 1249 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1250 1251 static int mlx4_load_fw(struct mlx4_dev *dev) 1252 { 1253 struct mlx4_priv *priv = mlx4_priv(dev); 1254 int err; 1255 1256 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1257 GFP_HIGHUSER | __GFP_NOWARN, 0); 1258 if (!priv->fw.fw_icm) { 1259 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1260 return -ENOMEM; 1261 } 1262 1263 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1264 if (err) { 1265 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1266 goto err_free; 1267 } 1268 1269 err = mlx4_RUN_FW(dev); 1270 if (err) { 1271 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1272 goto err_unmap_fa; 1273 } 1274 1275 return 0; 1276 1277 err_unmap_fa: 1278 mlx4_UNMAP_FA(dev); 1279 1280 err_free: 1281 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1282 return err; 1283 } 1284 1285 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1286 int cmpt_entry_sz) 1287 { 1288 struct mlx4_priv *priv = mlx4_priv(dev); 1289 int err; 1290 int num_eqs; 1291 1292 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1293 cmpt_base + 1294 ((u64) (MLX4_CMPT_TYPE_QP * 1295 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1296 cmpt_entry_sz, dev->caps.num_qps, 1297 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1298 0, 0); 1299 if (err) 1300 goto err; 1301 1302 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1303 cmpt_base + 1304 ((u64) (MLX4_CMPT_TYPE_SRQ * 1305 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1306 cmpt_entry_sz, dev->caps.num_srqs, 1307 dev->caps.reserved_srqs, 0, 0); 1308 if (err) 1309 goto err_qp; 1310 1311 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1312 cmpt_base + 1313 ((u64) (MLX4_CMPT_TYPE_CQ * 1314 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1315 cmpt_entry_sz, dev->caps.num_cqs, 1316 dev->caps.reserved_cqs, 0, 0); 1317 if (err) 1318 goto err_srq; 1319 1320 num_eqs = dev->phys_caps.num_phys_eqs; 1321 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1322 cmpt_base + 1323 ((u64) (MLX4_CMPT_TYPE_EQ * 1324 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1325 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1326 if (err) 1327 goto err_cq; 1328 1329 return 0; 1330 1331 err_cq: 1332 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1333 1334 err_srq: 1335 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1336 1337 err_qp: 1338 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1339 1340 err: 1341 return err; 1342 } 1343 1344 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1345 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1346 { 1347 struct mlx4_priv *priv = mlx4_priv(dev); 1348 u64 aux_pages; 1349 int num_eqs; 1350 int err; 1351 1352 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1353 if (err) { 1354 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1355 return err; 1356 } 1357 1358 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1359 (unsigned long long) icm_size >> 10, 1360 (unsigned long long) aux_pages << 2); 1361 1362 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1363 GFP_HIGHUSER | __GFP_NOWARN, 0); 1364 if (!priv->fw.aux_icm) { 1365 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1366 return -ENOMEM; 1367 } 1368 1369 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1370 if (err) { 1371 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1372 goto err_free_aux; 1373 } 1374 1375 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1376 if (err) { 1377 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1378 goto err_unmap_aux; 1379 } 1380 1381 1382 num_eqs = dev->phys_caps.num_phys_eqs; 1383 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1384 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1385 num_eqs, num_eqs, 0, 0); 1386 if (err) { 1387 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1388 goto err_unmap_cmpt; 1389 } 1390 1391 /* 1392 * Reserved MTT entries must be aligned up to a cacheline 1393 * boundary, since the FW will write to them, while the driver 1394 * writes to all other MTT entries. (The variable 1395 * dev->caps.mtt_entry_sz below is really the MTT segment 1396 * size, not the raw entry size) 1397 */ 1398 dev->caps.reserved_mtts = 1399 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1400 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1401 1402 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1403 init_hca->mtt_base, 1404 dev->caps.mtt_entry_sz, 1405 dev->caps.num_mtts, 1406 dev->caps.reserved_mtts, 1, 0); 1407 if (err) { 1408 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1409 goto err_unmap_eq; 1410 } 1411 1412 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1413 init_hca->dmpt_base, 1414 dev_cap->dmpt_entry_sz, 1415 dev->caps.num_mpts, 1416 dev->caps.reserved_mrws, 1, 1); 1417 if (err) { 1418 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1419 goto err_unmap_mtt; 1420 } 1421 1422 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1423 init_hca->qpc_base, 1424 dev_cap->qpc_entry_sz, 1425 dev->caps.num_qps, 1426 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1427 0, 0); 1428 if (err) { 1429 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1430 goto err_unmap_dmpt; 1431 } 1432 1433 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1434 init_hca->auxc_base, 1435 dev_cap->aux_entry_sz, 1436 dev->caps.num_qps, 1437 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1438 0, 0); 1439 if (err) { 1440 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1441 goto err_unmap_qp; 1442 } 1443 1444 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1445 init_hca->altc_base, 1446 dev_cap->altc_entry_sz, 1447 dev->caps.num_qps, 1448 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1449 0, 0); 1450 if (err) { 1451 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1452 goto err_unmap_auxc; 1453 } 1454 1455 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1456 init_hca->rdmarc_base, 1457 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1458 dev->caps.num_qps, 1459 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1460 0, 0); 1461 if (err) { 1462 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1463 goto err_unmap_altc; 1464 } 1465 1466 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1467 init_hca->cqc_base, 1468 dev_cap->cqc_entry_sz, 1469 dev->caps.num_cqs, 1470 dev->caps.reserved_cqs, 0, 0); 1471 if (err) { 1472 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1473 goto err_unmap_rdmarc; 1474 } 1475 1476 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1477 init_hca->srqc_base, 1478 dev_cap->srq_entry_sz, 1479 dev->caps.num_srqs, 1480 dev->caps.reserved_srqs, 0, 0); 1481 if (err) { 1482 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1483 goto err_unmap_cq; 1484 } 1485 1486 /* 1487 * For flow steering device managed mode it is required to use 1488 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1489 * required, but for simplicity just map the whole multicast 1490 * group table now. The table isn't very big and it's a lot 1491 * easier than trying to track ref counts. 1492 */ 1493 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1494 init_hca->mc_base, 1495 mlx4_get_mgm_entry_size(dev), 1496 dev->caps.num_mgms + dev->caps.num_amgms, 1497 dev->caps.num_mgms + dev->caps.num_amgms, 1498 0, 0); 1499 if (err) { 1500 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1501 goto err_unmap_srq; 1502 } 1503 1504 return 0; 1505 1506 err_unmap_srq: 1507 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1508 1509 err_unmap_cq: 1510 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1511 1512 err_unmap_rdmarc: 1513 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1514 1515 err_unmap_altc: 1516 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1517 1518 err_unmap_auxc: 1519 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1520 1521 err_unmap_qp: 1522 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1523 1524 err_unmap_dmpt: 1525 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1526 1527 err_unmap_mtt: 1528 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1529 1530 err_unmap_eq: 1531 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1532 1533 err_unmap_cmpt: 1534 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1535 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1536 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1537 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1538 1539 err_unmap_aux: 1540 mlx4_UNMAP_ICM_AUX(dev); 1541 1542 err_free_aux: 1543 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1544 1545 return err; 1546 } 1547 1548 static void mlx4_free_icms(struct mlx4_dev *dev) 1549 { 1550 struct mlx4_priv *priv = mlx4_priv(dev); 1551 1552 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1553 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1554 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1555 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1556 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1557 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1558 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1559 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1560 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1561 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1562 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1563 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1564 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1565 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1566 1567 mlx4_UNMAP_ICM_AUX(dev); 1568 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1569 } 1570 1571 static void mlx4_slave_exit(struct mlx4_dev *dev) 1572 { 1573 struct mlx4_priv *priv = mlx4_priv(dev); 1574 1575 mutex_lock(&priv->cmd.slave_cmd_mutex); 1576 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1577 MLX4_COMM_TIME)) 1578 mlx4_warn(dev, "Failed to close slave function\n"); 1579 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1580 } 1581 1582 static int map_bf_area(struct mlx4_dev *dev) 1583 { 1584 struct mlx4_priv *priv = mlx4_priv(dev); 1585 resource_size_t bf_start; 1586 resource_size_t bf_len; 1587 int err = 0; 1588 1589 if (!dev->caps.bf_reg_size) 1590 return -ENXIO; 1591 1592 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1593 (dev->caps.num_uars << PAGE_SHIFT); 1594 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1595 (dev->caps.num_uars << PAGE_SHIFT); 1596 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1597 if (!priv->bf_mapping) 1598 err = -ENOMEM; 1599 1600 return err; 1601 } 1602 1603 static void unmap_bf_area(struct mlx4_dev *dev) 1604 { 1605 if (mlx4_priv(dev)->bf_mapping) 1606 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1607 } 1608 1609 cycle_t mlx4_read_clock(struct mlx4_dev *dev) 1610 { 1611 u32 clockhi, clocklo, clockhi1; 1612 cycle_t cycles; 1613 int i; 1614 struct mlx4_priv *priv = mlx4_priv(dev); 1615 1616 for (i = 0; i < 10; i++) { 1617 clockhi = swab32(readl(priv->clock_mapping)); 1618 clocklo = swab32(readl(priv->clock_mapping + 4)); 1619 clockhi1 = swab32(readl(priv->clock_mapping)); 1620 if (clockhi == clockhi1) 1621 break; 1622 } 1623 1624 cycles = (u64) clockhi << 32 | (u64) clocklo; 1625 1626 return cycles; 1627 } 1628 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1629 1630 1631 static int map_internal_clock(struct mlx4_dev *dev) 1632 { 1633 struct mlx4_priv *priv = mlx4_priv(dev); 1634 1635 priv->clock_mapping = 1636 ioremap(pci_resource_start(dev->persist->pdev, 1637 priv->fw.clock_bar) + 1638 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1639 1640 if (!priv->clock_mapping) 1641 return -ENOMEM; 1642 1643 return 0; 1644 } 1645 1646 static void unmap_internal_clock(struct mlx4_dev *dev) 1647 { 1648 struct mlx4_priv *priv = mlx4_priv(dev); 1649 1650 if (priv->clock_mapping) 1651 iounmap(priv->clock_mapping); 1652 } 1653 1654 static void mlx4_close_hca(struct mlx4_dev *dev) 1655 { 1656 unmap_internal_clock(dev); 1657 unmap_bf_area(dev); 1658 if (mlx4_is_slave(dev)) 1659 mlx4_slave_exit(dev); 1660 else { 1661 mlx4_CLOSE_HCA(dev, 0); 1662 mlx4_free_icms(dev); 1663 } 1664 } 1665 1666 static void mlx4_close_fw(struct mlx4_dev *dev) 1667 { 1668 if (!mlx4_is_slave(dev)) { 1669 mlx4_UNMAP_FA(dev); 1670 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1671 } 1672 } 1673 1674 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1675 { 1676 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1677 1678 u32 comm_flags; 1679 u32 offline_bit; 1680 unsigned long end; 1681 struct mlx4_priv *priv = mlx4_priv(dev); 1682 1683 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 1684 while (time_before(jiffies, end)) { 1685 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 1686 MLX4_COMM_CHAN_FLAGS)); 1687 offline_bit = (comm_flags & 1688 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 1689 if (!offline_bit) 1690 return 0; 1691 /* There are cases as part of AER/Reset flow that PF needs 1692 * around 100 msec to load. We therefore sleep for 100 msec 1693 * to allow other tasks to make use of that CPU during this 1694 * time interval. 1695 */ 1696 msleep(100); 1697 } 1698 mlx4_err(dev, "Communication channel is offline.\n"); 1699 return -EIO; 1700 } 1701 1702 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 1703 { 1704 #define COMM_CHAN_RST_OFFSET 0x1e 1705 1706 struct mlx4_priv *priv = mlx4_priv(dev); 1707 u32 comm_rst; 1708 u32 comm_caps; 1709 1710 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 1711 MLX4_COMM_CHAN_CAPS)); 1712 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 1713 1714 if (comm_rst) 1715 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 1716 } 1717 1718 static int mlx4_init_slave(struct mlx4_dev *dev) 1719 { 1720 struct mlx4_priv *priv = mlx4_priv(dev); 1721 u64 dma = (u64) priv->mfunc.vhcr_dma; 1722 int ret_from_reset = 0; 1723 u32 slave_read; 1724 u32 cmd_channel_ver; 1725 1726 if (atomic_read(&pf_loading)) { 1727 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 1728 return -EPROBE_DEFER; 1729 } 1730 1731 mutex_lock(&priv->cmd.slave_cmd_mutex); 1732 priv->cmd.max_cmds = 1; 1733 if (mlx4_comm_check_offline(dev)) { 1734 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 1735 goto err_offline; 1736 } 1737 1738 mlx4_reset_vf_support(dev); 1739 mlx4_warn(dev, "Sending reset\n"); 1740 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1741 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 1742 /* if we are in the middle of flr the slave will try 1743 * NUM_OF_RESET_RETRIES times before leaving.*/ 1744 if (ret_from_reset) { 1745 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1746 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 1747 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1748 return -EPROBE_DEFER; 1749 } else 1750 goto err; 1751 } 1752 1753 /* check the driver version - the slave I/F revision 1754 * must match the master's */ 1755 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1756 cmd_channel_ver = mlx4_comm_get_version(); 1757 1758 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1759 MLX4_COMM_GET_IF_REV(slave_read)) { 1760 mlx4_err(dev, "slave driver version is not supported by the master\n"); 1761 goto err; 1762 } 1763 1764 mlx4_warn(dev, "Sending vhcr0\n"); 1765 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1766 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1767 goto err; 1768 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1769 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1770 goto err; 1771 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1772 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1773 goto err; 1774 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 1775 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1776 goto err; 1777 1778 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1779 return 0; 1780 1781 err: 1782 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 1783 err_offline: 1784 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1785 return -EIO; 1786 } 1787 1788 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1789 { 1790 int i; 1791 1792 for (i = 1; i <= dev->caps.num_ports; i++) { 1793 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1794 dev->caps.gid_table_len[i] = 1795 mlx4_get_slave_num_gids(dev, 0, i); 1796 else 1797 dev->caps.gid_table_len[i] = 1; 1798 dev->caps.pkey_table_len[i] = 1799 dev->phys_caps.pkey_phys_table_len[i] - 1; 1800 } 1801 } 1802 1803 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1804 { 1805 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1806 1807 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1808 i++) { 1809 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1810 break; 1811 } 1812 1813 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1814 } 1815 1816 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 1817 { 1818 switch (dmfs_high_steer_mode) { 1819 case MLX4_STEERING_DMFS_A0_DEFAULT: 1820 return "default performance"; 1821 1822 case MLX4_STEERING_DMFS_A0_DYNAMIC: 1823 return "dynamic hybrid mode"; 1824 1825 case MLX4_STEERING_DMFS_A0_STATIC: 1826 return "performance optimized for limited rule configuration (static)"; 1827 1828 case MLX4_STEERING_DMFS_A0_DISABLE: 1829 return "disabled performance optimized steering"; 1830 1831 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 1832 return "performance optimized steering not supported"; 1833 1834 default: 1835 return "Unrecognized mode"; 1836 } 1837 } 1838 1839 #define MLX4_DMFS_A0_STEERING (1UL << 2) 1840 1841 static void choose_steering_mode(struct mlx4_dev *dev, 1842 struct mlx4_dev_cap *dev_cap) 1843 { 1844 if (mlx4_log_num_mgm_entry_size <= 0) { 1845 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 1846 if (dev->caps.dmfs_high_steer_mode == 1847 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1848 mlx4_err(dev, "DMFS high rate mode not supported\n"); 1849 else 1850 dev->caps.dmfs_high_steer_mode = 1851 MLX4_STEERING_DMFS_A0_STATIC; 1852 } 1853 } 1854 1855 if (mlx4_log_num_mgm_entry_size <= 0 && 1856 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1857 (!mlx4_is_mfunc(dev) || 1858 (dev_cap->fs_max_num_qp_per_entry >= 1859 (dev->persist->num_vfs + 1))) && 1860 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1861 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1862 dev->oper_log_mgm_entry_size = 1863 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1864 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1865 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1866 dev->caps.fs_log_max_ucast_qp_range_size = 1867 dev_cap->fs_log_max_ucast_qp_range_size; 1868 } else { 1869 if (dev->caps.dmfs_high_steer_mode != 1870 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1871 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 1872 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1873 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1874 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1875 else { 1876 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1877 1878 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1879 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1880 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 1881 } 1882 dev->oper_log_mgm_entry_size = 1883 mlx4_log_num_mgm_entry_size > 0 ? 1884 mlx4_log_num_mgm_entry_size : 1885 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1886 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1887 } 1888 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 1889 mlx4_steering_mode_str(dev->caps.steering_mode), 1890 dev->oper_log_mgm_entry_size, 1891 mlx4_log_num_mgm_entry_size); 1892 } 1893 1894 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 1895 struct mlx4_dev_cap *dev_cap) 1896 { 1897 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 1898 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 1899 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 1900 else 1901 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 1902 1903 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 1904 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 1905 } 1906 1907 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 1908 { 1909 int i; 1910 struct mlx4_port_cap port_cap; 1911 1912 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1913 return -EINVAL; 1914 1915 for (i = 1; i <= dev->caps.num_ports; i++) { 1916 if (mlx4_dev_port(dev, i, &port_cap)) { 1917 mlx4_err(dev, 1918 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 1919 } else if ((dev->caps.dmfs_high_steer_mode != 1920 MLX4_STEERING_DMFS_A0_DEFAULT) && 1921 (port_cap.dmfs_optimized_state == 1922 !!(dev->caps.dmfs_high_steer_mode == 1923 MLX4_STEERING_DMFS_A0_DISABLE))) { 1924 mlx4_err(dev, 1925 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 1926 dmfs_high_rate_steering_mode_str( 1927 dev->caps.dmfs_high_steer_mode), 1928 (port_cap.dmfs_optimized_state ? 1929 "enabled" : "disabled")); 1930 } 1931 } 1932 1933 return 0; 1934 } 1935 1936 static int mlx4_init_fw(struct mlx4_dev *dev) 1937 { 1938 struct mlx4_mod_stat_cfg mlx4_cfg; 1939 int err = 0; 1940 1941 if (!mlx4_is_slave(dev)) { 1942 err = mlx4_QUERY_FW(dev); 1943 if (err) { 1944 if (err == -EACCES) 1945 mlx4_info(dev, "non-primary physical function, skipping\n"); 1946 else 1947 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 1948 return err; 1949 } 1950 1951 err = mlx4_load_fw(dev); 1952 if (err) { 1953 mlx4_err(dev, "Failed to start FW, aborting\n"); 1954 return err; 1955 } 1956 1957 mlx4_cfg.log_pg_sz_m = 1; 1958 mlx4_cfg.log_pg_sz = 0; 1959 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1960 if (err) 1961 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1962 } 1963 1964 return err; 1965 } 1966 1967 static int mlx4_init_hca(struct mlx4_dev *dev) 1968 { 1969 struct mlx4_priv *priv = mlx4_priv(dev); 1970 struct mlx4_adapter adapter; 1971 struct mlx4_dev_cap dev_cap; 1972 struct mlx4_profile profile; 1973 struct mlx4_init_hca_param init_hca; 1974 u64 icm_size; 1975 struct mlx4_config_dev_params params; 1976 int err; 1977 1978 if (!mlx4_is_slave(dev)) { 1979 err = mlx4_dev_cap(dev, &dev_cap); 1980 if (err) { 1981 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 1982 return err; 1983 } 1984 1985 choose_steering_mode(dev, &dev_cap); 1986 choose_tunnel_offload_mode(dev, &dev_cap); 1987 1988 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 1989 mlx4_is_master(dev)) 1990 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 1991 1992 err = mlx4_get_phys_port_id(dev); 1993 if (err) 1994 mlx4_err(dev, "Fail to get physical port id\n"); 1995 1996 if (mlx4_is_master(dev)) 1997 mlx4_parav_master_pf_caps(dev); 1998 1999 if (mlx4_low_memory_profile()) { 2000 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2001 profile = low_mem_profile; 2002 } else { 2003 profile = default_profile; 2004 } 2005 if (dev->caps.steering_mode == 2006 MLX4_STEERING_MODE_DEVICE_MANAGED) 2007 profile.num_mcg = MLX4_FS_NUM_MCG; 2008 2009 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2010 &init_hca); 2011 if ((long long) icm_size < 0) { 2012 err = icm_size; 2013 return err; 2014 } 2015 2016 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2017 2018 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2019 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2020 init_hca.mw_enabled = 0; 2021 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2022 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2023 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2024 2025 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2026 if (err) 2027 return err; 2028 2029 err = mlx4_INIT_HCA(dev, &init_hca); 2030 if (err) { 2031 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2032 goto err_free_icm; 2033 } 2034 2035 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2036 err = mlx4_query_func(dev, &dev_cap); 2037 if (err < 0) { 2038 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2039 goto err_close; 2040 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2041 dev->caps.num_eqs = dev_cap.max_eqs; 2042 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2043 dev->caps.reserved_uars = dev_cap.reserved_uars; 2044 } 2045 } 2046 2047 /* 2048 * If TS is supported by FW 2049 * read HCA frequency by QUERY_HCA command 2050 */ 2051 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2052 memset(&init_hca, 0, sizeof(init_hca)); 2053 err = mlx4_QUERY_HCA(dev, &init_hca); 2054 if (err) { 2055 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2056 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2057 } else { 2058 dev->caps.hca_core_clock = 2059 init_hca.hca_core_clock; 2060 } 2061 2062 /* In case we got HCA frequency 0 - disable timestamping 2063 * to avoid dividing by zero 2064 */ 2065 if (!dev->caps.hca_core_clock) { 2066 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2067 mlx4_err(dev, 2068 "HCA frequency is 0 - timestamping is not supported\n"); 2069 } else if (map_internal_clock(dev)) { 2070 /* 2071 * Map internal clock, 2072 * in case of failure disable timestamping 2073 */ 2074 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2075 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2076 } 2077 } 2078 2079 if (dev->caps.dmfs_high_steer_mode != 2080 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2081 if (mlx4_validate_optimized_steering(dev)) 2082 mlx4_warn(dev, "Optimized steering validation failed\n"); 2083 2084 if (dev->caps.dmfs_high_steer_mode == 2085 MLX4_STEERING_DMFS_A0_DISABLE) { 2086 dev->caps.dmfs_high_rate_qpn_base = 2087 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2088 dev->caps.dmfs_high_rate_qpn_range = 2089 MLX4_A0_STEERING_TABLE_SIZE; 2090 } 2091 2092 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n", 2093 dmfs_high_rate_steering_mode_str( 2094 dev->caps.dmfs_high_steer_mode)); 2095 } 2096 } else { 2097 err = mlx4_init_slave(dev); 2098 if (err) { 2099 if (err != -EPROBE_DEFER) 2100 mlx4_err(dev, "Failed to initialize slave\n"); 2101 return err; 2102 } 2103 2104 err = mlx4_slave_cap(dev); 2105 if (err) { 2106 mlx4_err(dev, "Failed to obtain slave caps\n"); 2107 goto err_close; 2108 } 2109 } 2110 2111 if (map_bf_area(dev)) 2112 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2113 2114 /*Only the master set the ports, all the rest got it from it.*/ 2115 if (!mlx4_is_slave(dev)) 2116 mlx4_set_port_mask(dev); 2117 2118 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2119 if (err) { 2120 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2121 goto unmap_bf; 2122 } 2123 2124 /* Query CONFIG_DEV parameters */ 2125 err = mlx4_config_dev_retrieval(dev, ¶ms); 2126 if (err && err != -ENOTSUPP) { 2127 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2128 } else if (!err) { 2129 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2130 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2131 } 2132 priv->eq_table.inta_pin = adapter.inta_pin; 2133 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 2134 2135 return 0; 2136 2137 unmap_bf: 2138 unmap_internal_clock(dev); 2139 unmap_bf_area(dev); 2140 2141 if (mlx4_is_slave(dev)) { 2142 kfree(dev->caps.qp0_qkey); 2143 kfree(dev->caps.qp0_tunnel); 2144 kfree(dev->caps.qp0_proxy); 2145 kfree(dev->caps.qp1_tunnel); 2146 kfree(dev->caps.qp1_proxy); 2147 } 2148 2149 err_close: 2150 if (mlx4_is_slave(dev)) 2151 mlx4_slave_exit(dev); 2152 else 2153 mlx4_CLOSE_HCA(dev, 0); 2154 2155 err_free_icm: 2156 if (!mlx4_is_slave(dev)) 2157 mlx4_free_icms(dev); 2158 2159 return err; 2160 } 2161 2162 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2163 { 2164 struct mlx4_priv *priv = mlx4_priv(dev); 2165 int nent; 2166 2167 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2168 return -ENOENT; 2169 2170 nent = dev->caps.max_counters; 2171 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 2172 } 2173 2174 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2175 { 2176 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2177 } 2178 2179 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2180 { 2181 struct mlx4_priv *priv = mlx4_priv(dev); 2182 2183 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2184 return -ENOENT; 2185 2186 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2187 if (*idx == -1) 2188 return -ENOMEM; 2189 2190 return 0; 2191 } 2192 2193 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2194 { 2195 u64 out_param; 2196 int err; 2197 2198 if (mlx4_is_mfunc(dev)) { 2199 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 2200 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2201 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2202 if (!err) 2203 *idx = get_param_l(&out_param); 2204 2205 return err; 2206 } 2207 return __mlx4_counter_alloc(dev, idx); 2208 } 2209 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2210 2211 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2212 { 2213 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2214 return; 2215 } 2216 2217 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2218 { 2219 u64 in_param = 0; 2220 2221 if (mlx4_is_mfunc(dev)) { 2222 set_param_l(&in_param, idx); 2223 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2224 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2225 MLX4_CMD_WRAPPED); 2226 return; 2227 } 2228 __mlx4_counter_free(dev, idx); 2229 } 2230 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2231 2232 static int mlx4_setup_hca(struct mlx4_dev *dev) 2233 { 2234 struct mlx4_priv *priv = mlx4_priv(dev); 2235 int err; 2236 int port; 2237 __be32 ib_port_default_caps; 2238 2239 err = mlx4_init_uar_table(dev); 2240 if (err) { 2241 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2242 return err; 2243 } 2244 2245 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2246 if (err) { 2247 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2248 goto err_uar_table_free; 2249 } 2250 2251 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2252 if (!priv->kar) { 2253 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2254 err = -ENOMEM; 2255 goto err_uar_free; 2256 } 2257 2258 err = mlx4_init_pd_table(dev); 2259 if (err) { 2260 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2261 goto err_kar_unmap; 2262 } 2263 2264 err = mlx4_init_xrcd_table(dev); 2265 if (err) { 2266 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2267 goto err_pd_table_free; 2268 } 2269 2270 err = mlx4_init_mr_table(dev); 2271 if (err) { 2272 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2273 goto err_xrcd_table_free; 2274 } 2275 2276 if (!mlx4_is_slave(dev)) { 2277 err = mlx4_init_mcg_table(dev); 2278 if (err) { 2279 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2280 goto err_mr_table_free; 2281 } 2282 err = mlx4_config_mad_demux(dev); 2283 if (err) { 2284 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2285 goto err_mcg_table_free; 2286 } 2287 } 2288 2289 err = mlx4_init_eq_table(dev); 2290 if (err) { 2291 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2292 goto err_mcg_table_free; 2293 } 2294 2295 err = mlx4_cmd_use_events(dev); 2296 if (err) { 2297 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2298 goto err_eq_table_free; 2299 } 2300 2301 err = mlx4_NOP(dev); 2302 if (err) { 2303 if (dev->flags & MLX4_FLAG_MSI_X) { 2304 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2305 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2306 mlx4_warn(dev, "Trying again without MSI-X\n"); 2307 } else { 2308 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2309 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2310 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2311 } 2312 2313 goto err_cmd_poll; 2314 } 2315 2316 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2317 2318 err = mlx4_init_cq_table(dev); 2319 if (err) { 2320 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2321 goto err_cmd_poll; 2322 } 2323 2324 err = mlx4_init_srq_table(dev); 2325 if (err) { 2326 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2327 goto err_cq_table_free; 2328 } 2329 2330 err = mlx4_init_qp_table(dev); 2331 if (err) { 2332 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2333 goto err_srq_table_free; 2334 } 2335 2336 err = mlx4_init_counters_table(dev); 2337 if (err && err != -ENOENT) { 2338 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2339 goto err_qp_table_free; 2340 } 2341 2342 if (!mlx4_is_slave(dev)) { 2343 for (port = 1; port <= dev->caps.num_ports; port++) { 2344 ib_port_default_caps = 0; 2345 err = mlx4_get_port_ib_caps(dev, port, 2346 &ib_port_default_caps); 2347 if (err) 2348 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2349 port, err); 2350 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2351 2352 /* initialize per-slave default ib port capabilities */ 2353 if (mlx4_is_master(dev)) { 2354 int i; 2355 for (i = 0; i < dev->num_slaves; i++) { 2356 if (i == mlx4_master_func_num(dev)) 2357 continue; 2358 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2359 ib_port_default_caps; 2360 } 2361 } 2362 2363 if (mlx4_is_mfunc(dev)) 2364 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2365 else 2366 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2367 2368 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2369 dev->caps.pkey_table_len[port] : -1); 2370 if (err) { 2371 mlx4_err(dev, "Failed to set port %d, aborting\n", 2372 port); 2373 goto err_counters_table_free; 2374 } 2375 } 2376 } 2377 2378 return 0; 2379 2380 err_counters_table_free: 2381 mlx4_cleanup_counters_table(dev); 2382 2383 err_qp_table_free: 2384 mlx4_cleanup_qp_table(dev); 2385 2386 err_srq_table_free: 2387 mlx4_cleanup_srq_table(dev); 2388 2389 err_cq_table_free: 2390 mlx4_cleanup_cq_table(dev); 2391 2392 err_cmd_poll: 2393 mlx4_cmd_use_polling(dev); 2394 2395 err_eq_table_free: 2396 mlx4_cleanup_eq_table(dev); 2397 2398 err_mcg_table_free: 2399 if (!mlx4_is_slave(dev)) 2400 mlx4_cleanup_mcg_table(dev); 2401 2402 err_mr_table_free: 2403 mlx4_cleanup_mr_table(dev); 2404 2405 err_xrcd_table_free: 2406 mlx4_cleanup_xrcd_table(dev); 2407 2408 err_pd_table_free: 2409 mlx4_cleanup_pd_table(dev); 2410 2411 err_kar_unmap: 2412 iounmap(priv->kar); 2413 2414 err_uar_free: 2415 mlx4_uar_free(dev, &priv->driver_uar); 2416 2417 err_uar_table_free: 2418 mlx4_cleanup_uar_table(dev); 2419 return err; 2420 } 2421 2422 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2423 { 2424 struct mlx4_priv *priv = mlx4_priv(dev); 2425 struct msix_entry *entries; 2426 int i; 2427 2428 if (msi_x) { 2429 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ; 2430 2431 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2432 nreq); 2433 2434 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2435 if (!entries) 2436 goto no_msi; 2437 2438 for (i = 0; i < nreq; ++i) 2439 entries[i].entry = i; 2440 2441 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2442 nreq); 2443 2444 if (nreq < 0) { 2445 kfree(entries); 2446 goto no_msi; 2447 } else if (nreq < MSIX_LEGACY_SZ + 2448 dev->caps.num_ports * MIN_MSIX_P_PORT) { 2449 /*Working in legacy mode , all EQ's shared*/ 2450 dev->caps.comp_pool = 0; 2451 dev->caps.num_comp_vectors = nreq - 1; 2452 } else { 2453 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 2454 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 2455 } 2456 for (i = 0; i < nreq; ++i) 2457 priv->eq_table.eq[i].irq = entries[i].vector; 2458 2459 dev->flags |= MLX4_FLAG_MSI_X; 2460 2461 kfree(entries); 2462 return; 2463 } 2464 2465 no_msi: 2466 dev->caps.num_comp_vectors = 1; 2467 dev->caps.comp_pool = 0; 2468 2469 for (i = 0; i < 2; ++i) 2470 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 2471 } 2472 2473 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2474 { 2475 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2476 int err = 0; 2477 2478 info->dev = dev; 2479 info->port = port; 2480 if (!mlx4_is_slave(dev)) { 2481 mlx4_init_mac_table(dev, &info->mac_table); 2482 mlx4_init_vlan_table(dev, &info->vlan_table); 2483 mlx4_init_roce_gid_table(dev, &info->gid_table); 2484 info->base_qpn = mlx4_get_base_qpn(dev, port); 2485 } 2486 2487 sprintf(info->dev_name, "mlx4_port%d", port); 2488 info->port_attr.attr.name = info->dev_name; 2489 if (mlx4_is_mfunc(dev)) 2490 info->port_attr.attr.mode = S_IRUGO; 2491 else { 2492 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2493 info->port_attr.store = set_port_type; 2494 } 2495 info->port_attr.show = show_port_type; 2496 sysfs_attr_init(&info->port_attr.attr); 2497 2498 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 2499 if (err) { 2500 mlx4_err(dev, "Failed to create file for port %d\n", port); 2501 info->port = -1; 2502 } 2503 2504 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2505 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2506 if (mlx4_is_mfunc(dev)) 2507 info->port_mtu_attr.attr.mode = S_IRUGO; 2508 else { 2509 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2510 info->port_mtu_attr.store = set_port_ib_mtu; 2511 } 2512 info->port_mtu_attr.show = show_port_ib_mtu; 2513 sysfs_attr_init(&info->port_mtu_attr.attr); 2514 2515 err = device_create_file(&dev->persist->pdev->dev, 2516 &info->port_mtu_attr); 2517 if (err) { 2518 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2519 device_remove_file(&info->dev->persist->pdev->dev, 2520 &info->port_attr); 2521 info->port = -1; 2522 } 2523 2524 return err; 2525 } 2526 2527 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 2528 { 2529 if (info->port < 0) 2530 return; 2531 2532 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 2533 device_remove_file(&info->dev->persist->pdev->dev, 2534 &info->port_mtu_attr); 2535 } 2536 2537 static int mlx4_init_steering(struct mlx4_dev *dev) 2538 { 2539 struct mlx4_priv *priv = mlx4_priv(dev); 2540 int num_entries = dev->caps.num_ports; 2541 int i, j; 2542 2543 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 2544 if (!priv->steer) 2545 return -ENOMEM; 2546 2547 for (i = 0; i < num_entries; i++) 2548 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2549 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 2550 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 2551 } 2552 return 0; 2553 } 2554 2555 static void mlx4_clear_steering(struct mlx4_dev *dev) 2556 { 2557 struct mlx4_priv *priv = mlx4_priv(dev); 2558 struct mlx4_steer_index *entry, *tmp_entry; 2559 struct mlx4_promisc_qp *pqp, *tmp_pqp; 2560 int num_entries = dev->caps.num_ports; 2561 int i, j; 2562 2563 for (i = 0; i < num_entries; i++) { 2564 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2565 list_for_each_entry_safe(pqp, tmp_pqp, 2566 &priv->steer[i].promisc_qps[j], 2567 list) { 2568 list_del(&pqp->list); 2569 kfree(pqp); 2570 } 2571 list_for_each_entry_safe(entry, tmp_entry, 2572 &priv->steer[i].steer_entries[j], 2573 list) { 2574 list_del(&entry->list); 2575 list_for_each_entry_safe(pqp, tmp_pqp, 2576 &entry->duplicates, 2577 list) { 2578 list_del(&pqp->list); 2579 kfree(pqp); 2580 } 2581 kfree(entry); 2582 } 2583 } 2584 } 2585 kfree(priv->steer); 2586 } 2587 2588 static int extended_func_num(struct pci_dev *pdev) 2589 { 2590 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 2591 } 2592 2593 #define MLX4_OWNER_BASE 0x8069c 2594 #define MLX4_OWNER_SIZE 4 2595 2596 static int mlx4_get_ownership(struct mlx4_dev *dev) 2597 { 2598 void __iomem *owner; 2599 u32 ret; 2600 2601 if (pci_channel_offline(dev->persist->pdev)) 2602 return -EIO; 2603 2604 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 2605 MLX4_OWNER_BASE, 2606 MLX4_OWNER_SIZE); 2607 if (!owner) { 2608 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2609 return -ENOMEM; 2610 } 2611 2612 ret = readl(owner); 2613 iounmap(owner); 2614 return (int) !!ret; 2615 } 2616 2617 static void mlx4_free_ownership(struct mlx4_dev *dev) 2618 { 2619 void __iomem *owner; 2620 2621 if (pci_channel_offline(dev->persist->pdev)) 2622 return; 2623 2624 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 2625 MLX4_OWNER_BASE, 2626 MLX4_OWNER_SIZE); 2627 if (!owner) { 2628 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2629 return; 2630 } 2631 writel(0, owner); 2632 msleep(1000); 2633 iounmap(owner); 2634 } 2635 2636 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 2637 !!((flags) & MLX4_FLAG_MASTER)) 2638 2639 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 2640 u8 total_vfs, int existing_vfs, int reset_flow) 2641 { 2642 u64 dev_flags = dev->flags; 2643 int err = 0; 2644 2645 if (reset_flow) { 2646 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 2647 GFP_KERNEL); 2648 if (!dev->dev_vfs) 2649 goto free_mem; 2650 return dev_flags; 2651 } 2652 2653 atomic_inc(&pf_loading); 2654 if (dev->flags & MLX4_FLAG_SRIOV) { 2655 if (existing_vfs != total_vfs) { 2656 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 2657 existing_vfs, total_vfs); 2658 total_vfs = existing_vfs; 2659 } 2660 } 2661 2662 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL); 2663 if (NULL == dev->dev_vfs) { 2664 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 2665 goto disable_sriov; 2666 } 2667 2668 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 2669 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 2670 err = pci_enable_sriov(pdev, total_vfs); 2671 } 2672 if (err) { 2673 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 2674 err); 2675 goto disable_sriov; 2676 } else { 2677 mlx4_warn(dev, "Running in master mode\n"); 2678 dev_flags |= MLX4_FLAG_SRIOV | 2679 MLX4_FLAG_MASTER; 2680 dev_flags &= ~MLX4_FLAG_SLAVE; 2681 dev->persist->num_vfs = total_vfs; 2682 } 2683 return dev_flags; 2684 2685 disable_sriov: 2686 atomic_dec(&pf_loading); 2687 free_mem: 2688 dev->persist->num_vfs = 0; 2689 kfree(dev->dev_vfs); 2690 return dev_flags & ~MLX4_FLAG_MASTER; 2691 } 2692 2693 enum { 2694 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 2695 }; 2696 2697 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 2698 int *nvfs) 2699 { 2700 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 2701 /* Checking for 64 VFs as a limitation of CX2 */ 2702 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 2703 requested_vfs >= 64) { 2704 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 2705 requested_vfs); 2706 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 2707 } 2708 return 0; 2709 } 2710 2711 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 2712 int total_vfs, int *nvfs, struct mlx4_priv *priv, 2713 int reset_flow) 2714 { 2715 struct mlx4_dev *dev; 2716 unsigned sum = 0; 2717 int err; 2718 int port; 2719 int i; 2720 struct mlx4_dev_cap *dev_cap = NULL; 2721 int existing_vfs = 0; 2722 2723 dev = &priv->dev; 2724 2725 INIT_LIST_HEAD(&priv->ctx_list); 2726 spin_lock_init(&priv->ctx_lock); 2727 2728 mutex_init(&priv->port_mutex); 2729 mutex_init(&priv->bond_mutex); 2730 2731 INIT_LIST_HEAD(&priv->pgdir_list); 2732 mutex_init(&priv->pgdir_mutex); 2733 2734 INIT_LIST_HEAD(&priv->bf_list); 2735 mutex_init(&priv->bf_mutex); 2736 2737 dev->rev_id = pdev->revision; 2738 dev->numa_node = dev_to_node(&pdev->dev); 2739 2740 /* Detect if this device is a virtual function */ 2741 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2742 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 2743 dev->flags |= MLX4_FLAG_SLAVE; 2744 } else { 2745 /* We reset the device and enable SRIOV only for physical 2746 * devices. Try to claim ownership on the device; 2747 * if already taken, skip -- do not allow multiple PFs */ 2748 err = mlx4_get_ownership(dev); 2749 if (err) { 2750 if (err < 0) 2751 return err; 2752 else { 2753 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 2754 return -EINVAL; 2755 } 2756 } 2757 2758 atomic_set(&priv->opreq_count, 0); 2759 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 2760 2761 /* 2762 * Now reset the HCA before we touch the PCI capabilities or 2763 * attempt a firmware command, since a boot ROM may have left 2764 * the HCA in an undefined state. 2765 */ 2766 err = mlx4_reset(dev); 2767 if (err) { 2768 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 2769 goto err_sriov; 2770 } 2771 2772 if (total_vfs) { 2773 dev->flags = MLX4_FLAG_MASTER; 2774 existing_vfs = pci_num_vf(pdev); 2775 if (existing_vfs) 2776 dev->flags |= MLX4_FLAG_SRIOV; 2777 dev->persist->num_vfs = total_vfs; 2778 } 2779 } 2780 2781 /* on load remove any previous indication of internal error, 2782 * device is up. 2783 */ 2784 dev->persist->state = MLX4_DEVICE_STATE_UP; 2785 2786 slave_start: 2787 err = mlx4_cmd_init(dev); 2788 if (err) { 2789 mlx4_err(dev, "Failed to init command interface, aborting\n"); 2790 goto err_sriov; 2791 } 2792 2793 /* In slave functions, the communication channel must be initialized 2794 * before posting commands. Also, init num_slaves before calling 2795 * mlx4_init_hca */ 2796 if (mlx4_is_mfunc(dev)) { 2797 if (mlx4_is_master(dev)) { 2798 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2799 2800 } else { 2801 dev->num_slaves = 0; 2802 err = mlx4_multi_func_init(dev); 2803 if (err) { 2804 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 2805 goto err_cmd; 2806 } 2807 } 2808 } 2809 2810 err = mlx4_init_fw(dev); 2811 if (err) { 2812 mlx4_err(dev, "Failed to init fw, aborting.\n"); 2813 goto err_mfunc; 2814 } 2815 2816 if (mlx4_is_master(dev)) { 2817 /* when we hit the goto slave_start below, dev_cap already initialized */ 2818 if (!dev_cap) { 2819 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2820 2821 if (!dev_cap) { 2822 err = -ENOMEM; 2823 goto err_fw; 2824 } 2825 2826 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 2827 if (err) { 2828 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2829 goto err_fw; 2830 } 2831 2832 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 2833 goto err_fw; 2834 2835 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 2836 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 2837 total_vfs, 2838 existing_vfs, 2839 reset_flow); 2840 2841 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 2842 dev->flags = dev_flags; 2843 if (!SRIOV_VALID_STATE(dev->flags)) { 2844 mlx4_err(dev, "Invalid SRIOV state\n"); 2845 goto err_sriov; 2846 } 2847 err = mlx4_reset(dev); 2848 if (err) { 2849 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 2850 goto err_sriov; 2851 } 2852 goto slave_start; 2853 } 2854 } else { 2855 /* Legacy mode FW requires SRIOV to be enabled before 2856 * doing QUERY_DEV_CAP, since max_eq's value is different if 2857 * SRIOV is enabled. 2858 */ 2859 memset(dev_cap, 0, sizeof(*dev_cap)); 2860 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 2861 if (err) { 2862 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2863 goto err_fw; 2864 } 2865 2866 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 2867 goto err_fw; 2868 } 2869 } 2870 2871 err = mlx4_init_hca(dev); 2872 if (err) { 2873 if (err == -EACCES) { 2874 /* Not primary Physical function 2875 * Running in slave mode */ 2876 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 2877 /* We're not a PF */ 2878 if (dev->flags & MLX4_FLAG_SRIOV) { 2879 if (!existing_vfs) 2880 pci_disable_sriov(pdev); 2881 if (mlx4_is_master(dev) && !reset_flow) 2882 atomic_dec(&pf_loading); 2883 dev->flags &= ~MLX4_FLAG_SRIOV; 2884 } 2885 if (!mlx4_is_slave(dev)) 2886 mlx4_free_ownership(dev); 2887 dev->flags |= MLX4_FLAG_SLAVE; 2888 dev->flags &= ~MLX4_FLAG_MASTER; 2889 goto slave_start; 2890 } else 2891 goto err_fw; 2892 } 2893 2894 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 2895 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 2896 existing_vfs, reset_flow); 2897 2898 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 2899 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 2900 dev->flags = dev_flags; 2901 err = mlx4_cmd_init(dev); 2902 if (err) { 2903 /* Only VHCR is cleaned up, so could still 2904 * send FW commands 2905 */ 2906 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 2907 goto err_close; 2908 } 2909 } else { 2910 dev->flags = dev_flags; 2911 } 2912 2913 if (!SRIOV_VALID_STATE(dev->flags)) { 2914 mlx4_err(dev, "Invalid SRIOV state\n"); 2915 goto err_close; 2916 } 2917 } 2918 2919 /* check if the device is functioning at its maximum possible speed. 2920 * No return code for this call, just warn the user in case of PCI 2921 * express device capabilities are under-satisfied by the bus. 2922 */ 2923 if (!mlx4_is_slave(dev)) 2924 mlx4_check_pcie_caps(dev); 2925 2926 /* In master functions, the communication channel must be initialized 2927 * after obtaining its address from fw */ 2928 if (mlx4_is_master(dev)) { 2929 int ib_ports = 0; 2930 2931 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2932 ib_ports++; 2933 2934 if (ib_ports && 2935 (num_vfs_argc > 1 || probe_vfs_argc > 1)) { 2936 mlx4_err(dev, 2937 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); 2938 err = -EINVAL; 2939 goto err_close; 2940 } 2941 if (dev->caps.num_ports < 2 && 2942 num_vfs_argc > 1) { 2943 err = -EINVAL; 2944 mlx4_err(dev, 2945 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 2946 dev->caps.num_ports); 2947 goto err_close; 2948 } 2949 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 2950 2951 for (i = 0; 2952 i < sizeof(dev->persist->nvfs)/ 2953 sizeof(dev->persist->nvfs[0]); i++) { 2954 unsigned j; 2955 2956 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 2957 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 2958 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 2959 dev->caps.num_ports; 2960 } 2961 } 2962 2963 /* In master functions, the communication channel 2964 * must be initialized after obtaining its address from fw 2965 */ 2966 err = mlx4_multi_func_init(dev); 2967 if (err) { 2968 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 2969 goto err_close; 2970 } 2971 } 2972 2973 err = mlx4_alloc_eq_table(dev); 2974 if (err) 2975 goto err_master_mfunc; 2976 2977 priv->msix_ctl.pool_bm = 0; 2978 mutex_init(&priv->msix_ctl.pool_lock); 2979 2980 mlx4_enable_msi_x(dev); 2981 if ((mlx4_is_mfunc(dev)) && 2982 !(dev->flags & MLX4_FLAG_MSI_X)) { 2983 err = -ENOSYS; 2984 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 2985 goto err_free_eq; 2986 } 2987 2988 if (!mlx4_is_slave(dev)) { 2989 err = mlx4_init_steering(dev); 2990 if (err) 2991 goto err_disable_msix; 2992 } 2993 2994 err = mlx4_setup_hca(dev); 2995 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 2996 !mlx4_is_mfunc(dev)) { 2997 dev->flags &= ~MLX4_FLAG_MSI_X; 2998 dev->caps.num_comp_vectors = 1; 2999 dev->caps.comp_pool = 0; 3000 pci_disable_msix(pdev); 3001 err = mlx4_setup_hca(dev); 3002 } 3003 3004 if (err) 3005 goto err_steer; 3006 3007 mlx4_init_quotas(dev); 3008 /* When PF resources are ready arm its comm channel to enable 3009 * getting commands 3010 */ 3011 if (mlx4_is_master(dev)) { 3012 err = mlx4_ARM_COMM_CHANNEL(dev); 3013 if (err) { 3014 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3015 err); 3016 goto err_steer; 3017 } 3018 } 3019 3020 for (port = 1; port <= dev->caps.num_ports; port++) { 3021 err = mlx4_init_port_info(dev, port); 3022 if (err) 3023 goto err_port; 3024 } 3025 3026 priv->v2p.port1 = 1; 3027 priv->v2p.port2 = 2; 3028 3029 err = mlx4_register_device(dev); 3030 if (err) 3031 goto err_port; 3032 3033 mlx4_request_modules(dev); 3034 3035 mlx4_sense_init(dev); 3036 mlx4_start_sense(dev); 3037 3038 priv->removed = 0; 3039 3040 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3041 atomic_dec(&pf_loading); 3042 3043 kfree(dev_cap); 3044 return 0; 3045 3046 err_port: 3047 for (--port; port >= 1; --port) 3048 mlx4_cleanup_port_info(&priv->port[port]); 3049 3050 mlx4_cleanup_counters_table(dev); 3051 mlx4_cleanup_qp_table(dev); 3052 mlx4_cleanup_srq_table(dev); 3053 mlx4_cleanup_cq_table(dev); 3054 mlx4_cmd_use_polling(dev); 3055 mlx4_cleanup_eq_table(dev); 3056 mlx4_cleanup_mcg_table(dev); 3057 mlx4_cleanup_mr_table(dev); 3058 mlx4_cleanup_xrcd_table(dev); 3059 mlx4_cleanup_pd_table(dev); 3060 mlx4_cleanup_uar_table(dev); 3061 3062 err_steer: 3063 if (!mlx4_is_slave(dev)) 3064 mlx4_clear_steering(dev); 3065 3066 err_disable_msix: 3067 if (dev->flags & MLX4_FLAG_MSI_X) 3068 pci_disable_msix(pdev); 3069 3070 err_free_eq: 3071 mlx4_free_eq_table(dev); 3072 3073 err_master_mfunc: 3074 if (mlx4_is_master(dev)) { 3075 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3076 mlx4_multi_func_cleanup(dev); 3077 } 3078 3079 if (mlx4_is_slave(dev)) { 3080 kfree(dev->caps.qp0_qkey); 3081 kfree(dev->caps.qp0_tunnel); 3082 kfree(dev->caps.qp0_proxy); 3083 kfree(dev->caps.qp1_tunnel); 3084 kfree(dev->caps.qp1_proxy); 3085 } 3086 3087 err_close: 3088 mlx4_close_hca(dev); 3089 3090 err_fw: 3091 mlx4_close_fw(dev); 3092 3093 err_mfunc: 3094 if (mlx4_is_slave(dev)) 3095 mlx4_multi_func_cleanup(dev); 3096 3097 err_cmd: 3098 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3099 3100 err_sriov: 3101 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3102 pci_disable_sriov(pdev); 3103 dev->flags &= ~MLX4_FLAG_SRIOV; 3104 } 3105 3106 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3107 atomic_dec(&pf_loading); 3108 3109 kfree(priv->dev.dev_vfs); 3110 3111 if (!mlx4_is_slave(dev)) 3112 mlx4_free_ownership(dev); 3113 3114 kfree(dev_cap); 3115 return err; 3116 } 3117 3118 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3119 struct mlx4_priv *priv) 3120 { 3121 int err; 3122 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3123 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3124 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3125 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3126 unsigned total_vfs = 0; 3127 unsigned int i; 3128 3129 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3130 3131 err = pci_enable_device(pdev); 3132 if (err) { 3133 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3134 return err; 3135 } 3136 3137 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3138 * per port, we must limit the number of VFs to 63 (since their are 3139 * 128 MACs) 3140 */ 3141 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 3142 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3143 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3144 if (nvfs[i] < 0) { 3145 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3146 err = -EINVAL; 3147 goto err_disable_pdev; 3148 } 3149 } 3150 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 3151 i++) { 3152 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3153 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3154 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3155 err = -EINVAL; 3156 goto err_disable_pdev; 3157 } 3158 } 3159 if (total_vfs >= MLX4_MAX_NUM_VF) { 3160 dev_err(&pdev->dev, 3161 "Requested more VF's (%d) than allowed (%d)\n", 3162 total_vfs, MLX4_MAX_NUM_VF - 1); 3163 err = -EINVAL; 3164 goto err_disable_pdev; 3165 } 3166 3167 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3168 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { 3169 dev_err(&pdev->dev, 3170 "Requested more VF's (%d) for port (%d) than allowed (%d)\n", 3171 nvfs[i] + nvfs[2], i + 1, 3172 MLX4_MAX_NUM_VF_P_PORT - 1); 3173 err = -EINVAL; 3174 goto err_disable_pdev; 3175 } 3176 } 3177 3178 /* Check for BARs. */ 3179 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3180 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3181 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3182 pci_dev_data, pci_resource_flags(pdev, 0)); 3183 err = -ENODEV; 3184 goto err_disable_pdev; 3185 } 3186 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3187 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3188 err = -ENODEV; 3189 goto err_disable_pdev; 3190 } 3191 3192 err = pci_request_regions(pdev, DRV_NAME); 3193 if (err) { 3194 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3195 goto err_disable_pdev; 3196 } 3197 3198 pci_set_master(pdev); 3199 3200 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3201 if (err) { 3202 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3203 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3204 if (err) { 3205 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3206 goto err_release_regions; 3207 } 3208 } 3209 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3210 if (err) { 3211 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3212 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3213 if (err) { 3214 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3215 goto err_release_regions; 3216 } 3217 } 3218 3219 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3220 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3221 /* Detect if this device is a virtual function */ 3222 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3223 /* When acting as pf, we normally skip vfs unless explicitly 3224 * requested to probe them. 3225 */ 3226 if (total_vfs) { 3227 unsigned vfs_offset = 0; 3228 3229 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 3230 vfs_offset + nvfs[i] < extended_func_num(pdev); 3231 vfs_offset += nvfs[i], i++) 3232 ; 3233 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 3234 err = -ENODEV; 3235 goto err_release_regions; 3236 } 3237 if ((extended_func_num(pdev) - vfs_offset) 3238 > prb_vf[i]) { 3239 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3240 extended_func_num(pdev)); 3241 err = -ENODEV; 3242 goto err_release_regions; 3243 } 3244 } 3245 } 3246 3247 err = mlx4_catas_init(&priv->dev); 3248 if (err) 3249 goto err_release_regions; 3250 3251 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3252 if (err) 3253 goto err_catas; 3254 3255 return 0; 3256 3257 err_catas: 3258 mlx4_catas_end(&priv->dev); 3259 3260 err_release_regions: 3261 pci_release_regions(pdev); 3262 3263 err_disable_pdev: 3264 pci_disable_device(pdev); 3265 pci_set_drvdata(pdev, NULL); 3266 return err; 3267 } 3268 3269 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3270 { 3271 struct mlx4_priv *priv; 3272 struct mlx4_dev *dev; 3273 int ret; 3274 3275 printk_once(KERN_INFO "%s", mlx4_version); 3276 3277 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 3278 if (!priv) 3279 return -ENOMEM; 3280 3281 dev = &priv->dev; 3282 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3283 if (!dev->persist) { 3284 kfree(priv); 3285 return -ENOMEM; 3286 } 3287 dev->persist->pdev = pdev; 3288 dev->persist->dev = dev; 3289 pci_set_drvdata(pdev, dev->persist); 3290 priv->pci_dev_data = id->driver_data; 3291 mutex_init(&dev->persist->device_state_mutex); 3292 mutex_init(&dev->persist->interface_state_mutex); 3293 3294 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3295 if (ret) { 3296 kfree(dev->persist); 3297 kfree(priv); 3298 } else { 3299 pci_save_state(pdev); 3300 } 3301 3302 return ret; 3303 } 3304 3305 static void mlx4_clean_dev(struct mlx4_dev *dev) 3306 { 3307 struct mlx4_dev_persistent *persist = dev->persist; 3308 struct mlx4_priv *priv = mlx4_priv(dev); 3309 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 3310 3311 memset(priv, 0, sizeof(*priv)); 3312 priv->dev.persist = persist; 3313 priv->dev.flags = flags; 3314 } 3315 3316 static void mlx4_unload_one(struct pci_dev *pdev) 3317 { 3318 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3319 struct mlx4_dev *dev = persist->dev; 3320 struct mlx4_priv *priv = mlx4_priv(dev); 3321 int pci_dev_data; 3322 int p, i; 3323 3324 if (priv->removed) 3325 return; 3326 3327 /* saving current ports type for further use */ 3328 for (i = 0; i < dev->caps.num_ports; i++) { 3329 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 3330 dev->persist->curr_port_poss_type[i] = dev->caps. 3331 possible_type[i + 1]; 3332 } 3333 3334 pci_dev_data = priv->pci_dev_data; 3335 3336 mlx4_stop_sense(dev); 3337 mlx4_unregister_device(dev); 3338 3339 for (p = 1; p <= dev->caps.num_ports; p++) { 3340 mlx4_cleanup_port_info(&priv->port[p]); 3341 mlx4_CLOSE_PORT(dev, p); 3342 } 3343 3344 if (mlx4_is_master(dev)) 3345 mlx4_free_resource_tracker(dev, 3346 RES_TR_FREE_SLAVES_ONLY); 3347 3348 mlx4_cleanup_counters_table(dev); 3349 mlx4_cleanup_qp_table(dev); 3350 mlx4_cleanup_srq_table(dev); 3351 mlx4_cleanup_cq_table(dev); 3352 mlx4_cmd_use_polling(dev); 3353 mlx4_cleanup_eq_table(dev); 3354 mlx4_cleanup_mcg_table(dev); 3355 mlx4_cleanup_mr_table(dev); 3356 mlx4_cleanup_xrcd_table(dev); 3357 mlx4_cleanup_pd_table(dev); 3358 3359 if (mlx4_is_master(dev)) 3360 mlx4_free_resource_tracker(dev, 3361 RES_TR_FREE_STRUCTS_ONLY); 3362 3363 iounmap(priv->kar); 3364 mlx4_uar_free(dev, &priv->driver_uar); 3365 mlx4_cleanup_uar_table(dev); 3366 if (!mlx4_is_slave(dev)) 3367 mlx4_clear_steering(dev); 3368 mlx4_free_eq_table(dev); 3369 if (mlx4_is_master(dev)) 3370 mlx4_multi_func_cleanup(dev); 3371 mlx4_close_hca(dev); 3372 mlx4_close_fw(dev); 3373 if (mlx4_is_slave(dev)) 3374 mlx4_multi_func_cleanup(dev); 3375 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3376 3377 if (dev->flags & MLX4_FLAG_MSI_X) 3378 pci_disable_msix(pdev); 3379 3380 if (!mlx4_is_slave(dev)) 3381 mlx4_free_ownership(dev); 3382 3383 kfree(dev->caps.qp0_qkey); 3384 kfree(dev->caps.qp0_tunnel); 3385 kfree(dev->caps.qp0_proxy); 3386 kfree(dev->caps.qp1_tunnel); 3387 kfree(dev->caps.qp1_proxy); 3388 kfree(dev->dev_vfs); 3389 3390 mlx4_clean_dev(dev); 3391 priv->pci_dev_data = pci_dev_data; 3392 priv->removed = 1; 3393 } 3394 3395 static void mlx4_remove_one(struct pci_dev *pdev) 3396 { 3397 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3398 struct mlx4_dev *dev = persist->dev; 3399 struct mlx4_priv *priv = mlx4_priv(dev); 3400 int active_vfs = 0; 3401 3402 mutex_lock(&persist->interface_state_mutex); 3403 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 3404 mutex_unlock(&persist->interface_state_mutex); 3405 3406 /* Disabling SR-IOV is not allowed while there are active vf's */ 3407 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 3408 active_vfs = mlx4_how_many_lives_vf(dev); 3409 if (active_vfs) { 3410 pr_warn("Removing PF when there are active VF's !!\n"); 3411 pr_warn("Will not disable SR-IOV.\n"); 3412 } 3413 } 3414 3415 /* device marked to be under deletion running now without the lock 3416 * letting other tasks to be terminated 3417 */ 3418 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3419 mlx4_unload_one(pdev); 3420 else 3421 mlx4_info(dev, "%s: interface is down\n", __func__); 3422 mlx4_catas_end(dev); 3423 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 3424 mlx4_warn(dev, "Disabling SR-IOV\n"); 3425 pci_disable_sriov(pdev); 3426 } 3427 3428 pci_release_regions(pdev); 3429 pci_disable_device(pdev); 3430 kfree(dev->persist); 3431 kfree(priv); 3432 pci_set_drvdata(pdev, NULL); 3433 } 3434 3435 static int restore_current_port_types(struct mlx4_dev *dev, 3436 enum mlx4_port_type *types, 3437 enum mlx4_port_type *poss_types) 3438 { 3439 struct mlx4_priv *priv = mlx4_priv(dev); 3440 int err, i; 3441 3442 mlx4_stop_sense(dev); 3443 3444 mutex_lock(&priv->port_mutex); 3445 for (i = 0; i < dev->caps.num_ports; i++) 3446 dev->caps.possible_type[i + 1] = poss_types[i]; 3447 err = mlx4_change_port_types(dev, types); 3448 mlx4_start_sense(dev); 3449 mutex_unlock(&priv->port_mutex); 3450 3451 return err; 3452 } 3453 3454 int mlx4_restart_one(struct pci_dev *pdev) 3455 { 3456 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3457 struct mlx4_dev *dev = persist->dev; 3458 struct mlx4_priv *priv = mlx4_priv(dev); 3459 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3460 int pci_dev_data, err, total_vfs; 3461 3462 pci_dev_data = priv->pci_dev_data; 3463 total_vfs = dev->persist->num_vfs; 3464 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 3465 3466 mlx4_unload_one(pdev); 3467 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 3468 if (err) { 3469 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 3470 __func__, pci_name(pdev), err); 3471 return err; 3472 } 3473 3474 err = restore_current_port_types(dev, dev->persist->curr_port_type, 3475 dev->persist->curr_port_poss_type); 3476 if (err) 3477 mlx4_err(dev, "could not restore original port types (%d)\n", 3478 err); 3479 3480 return err; 3481 } 3482 3483 static const struct pci_device_id mlx4_pci_table[] = { 3484 /* MT25408 "Hermon" SDR */ 3485 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3486 /* MT25408 "Hermon" DDR */ 3487 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3488 /* MT25408 "Hermon" QDR */ 3489 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3490 /* MT25408 "Hermon" DDR PCIe gen2 */ 3491 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3492 /* MT25408 "Hermon" QDR PCIe gen2 */ 3493 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3494 /* MT25408 "Hermon" EN 10GigE */ 3495 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3496 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 3497 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3498 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 3499 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3500 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 3501 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3502 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 3503 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3504 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 3505 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3506 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 3507 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3508 /* MT25400 Family [ConnectX-2 Virtual Function] */ 3509 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 3510 /* MT27500 Family [ConnectX-3] */ 3511 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 3512 /* MT27500 Family [ConnectX-3 Virtual Function] */ 3513 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 3514 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 3515 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 3516 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 3517 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 3518 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 3519 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 3520 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 3521 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 3522 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 3523 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 3524 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 3525 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 3526 { 0, } 3527 }; 3528 3529 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 3530 3531 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 3532 pci_channel_state_t state) 3533 { 3534 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3535 3536 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 3537 mlx4_enter_error_state(persist); 3538 3539 mutex_lock(&persist->interface_state_mutex); 3540 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3541 mlx4_unload_one(pdev); 3542 3543 mutex_unlock(&persist->interface_state_mutex); 3544 if (state == pci_channel_io_perm_failure) 3545 return PCI_ERS_RESULT_DISCONNECT; 3546 3547 pci_disable_device(pdev); 3548 return PCI_ERS_RESULT_NEED_RESET; 3549 } 3550 3551 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 3552 { 3553 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3554 struct mlx4_dev *dev = persist->dev; 3555 struct mlx4_priv *priv = mlx4_priv(dev); 3556 int ret; 3557 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3558 int total_vfs; 3559 3560 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 3561 ret = pci_enable_device(pdev); 3562 if (ret) { 3563 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret); 3564 return PCI_ERS_RESULT_DISCONNECT; 3565 } 3566 3567 pci_set_master(pdev); 3568 pci_restore_state(pdev); 3569 pci_save_state(pdev); 3570 3571 total_vfs = dev->persist->num_vfs; 3572 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 3573 3574 mutex_lock(&persist->interface_state_mutex); 3575 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 3576 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 3577 priv, 1); 3578 if (ret) { 3579 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n", 3580 __func__, ret); 3581 goto end; 3582 } 3583 3584 ret = restore_current_port_types(dev, dev->persist-> 3585 curr_port_type, dev->persist-> 3586 curr_port_poss_type); 3587 if (ret) 3588 mlx4_err(dev, "could not restore original port types (%d)\n", ret); 3589 } 3590 end: 3591 mutex_unlock(&persist->interface_state_mutex); 3592 3593 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 3594 } 3595 3596 static void mlx4_shutdown(struct pci_dev *pdev) 3597 { 3598 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3599 3600 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 3601 mutex_lock(&persist->interface_state_mutex); 3602 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3603 mlx4_unload_one(pdev); 3604 mutex_unlock(&persist->interface_state_mutex); 3605 } 3606 3607 static const struct pci_error_handlers mlx4_err_handler = { 3608 .error_detected = mlx4_pci_err_detected, 3609 .slot_reset = mlx4_pci_slot_reset, 3610 }; 3611 3612 static struct pci_driver mlx4_driver = { 3613 .name = DRV_NAME, 3614 .id_table = mlx4_pci_table, 3615 .probe = mlx4_init_one, 3616 .shutdown = mlx4_shutdown, 3617 .remove = mlx4_remove_one, 3618 .err_handler = &mlx4_err_handler, 3619 }; 3620 3621 static int __init mlx4_verify_params(void) 3622 { 3623 if ((log_num_mac < 0) || (log_num_mac > 7)) { 3624 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 3625 return -1; 3626 } 3627 3628 if (log_num_vlan != 0) 3629 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 3630 MLX4_LOG_NUM_VLANS); 3631 3632 if (use_prio != 0) 3633 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 3634 3635 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 3636 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 3637 log_mtts_per_seg); 3638 return -1; 3639 } 3640 3641 /* Check if module param for ports type has legal combination */ 3642 if (port_type_array[0] == false && port_type_array[1] == true) { 3643 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 3644 port_type_array[0] = true; 3645 } 3646 3647 if (mlx4_log_num_mgm_entry_size < -7 || 3648 (mlx4_log_num_mgm_entry_size > 0 && 3649 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 3650 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 3651 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 3652 mlx4_log_num_mgm_entry_size, 3653 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 3654 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 3655 return -1; 3656 } 3657 3658 return 0; 3659 } 3660 3661 static int __init mlx4_init(void) 3662 { 3663 int ret; 3664 3665 if (mlx4_verify_params()) 3666 return -EINVAL; 3667 3668 3669 mlx4_wq = create_singlethread_workqueue("mlx4"); 3670 if (!mlx4_wq) 3671 return -ENOMEM; 3672 3673 ret = pci_register_driver(&mlx4_driver); 3674 if (ret < 0) 3675 destroy_workqueue(mlx4_wq); 3676 return ret < 0 ? ret : 0; 3677 } 3678 3679 static void __exit mlx4_cleanup(void) 3680 { 3681 pci_unregister_driver(&mlx4_driver); 3682 destroy_workqueue(mlx4_wq); 3683 } 3684 3685 module_init(mlx4_init); 3686 module_exit(mlx4_cleanup); 3687