1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/errno.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/slab.h> 43 #include <linux/io-mapping.h> 44 #include <linux/delay.h> 45 #include <linux/kmod.h> 46 #include <linux/etherdevice.h> 47 #include <net/devlink.h> 48 49 #include <uapi/rdma/mlx4-abi.h> 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/doorbell.h> 52 53 #include "mlx4.h" 54 #include "fw.h" 55 #include "icm.h" 56 57 MODULE_AUTHOR("Roland Dreier"); 58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 MODULE_VERSION(DRV_VERSION); 61 62 struct workqueue_struct *mlx4_wq; 63 64 #ifdef CONFIG_MLX4_DEBUG 65 66 int mlx4_debug_level = 0; 67 module_param_named(debug_level, mlx4_debug_level, int, 0644); 68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 69 70 #endif /* CONFIG_MLX4_DEBUG */ 71 72 #ifdef CONFIG_PCI_MSI 73 74 static int msi_x = 1; 75 module_param(msi_x, int, 0444); 76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 77 78 #else /* CONFIG_PCI_MSI */ 79 80 #define msi_x (0) 81 82 #endif /* CONFIG_PCI_MSI */ 83 84 static uint8_t num_vfs[3] = {0, 0, 0}; 85 static int num_vfs_argc; 86 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 88 "num_vfs=port1,port2,port1+2"); 89 90 static uint8_t probe_vf[3] = {0, 0, 0}; 91 static int probe_vfs_argc; 92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 94 "probe_vf=port1,port2,port1+2"); 95 96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 97 module_param_named(log_num_mgm_entry_size, 98 mlx4_log_num_mgm_entry_size, int, 0444); 99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 100 " of qp per mcg, for example:" 101 " 10 gives 248.range: 7 <=" 102 " log_num_mgm_entry_size <= 12." 103 " To activate device managed" 104 " flow steering when available, set to -1"); 105 106 static bool enable_64b_cqe_eqe = true; 107 module_param(enable_64b_cqe_eqe, bool, 0444); 108 MODULE_PARM_DESC(enable_64b_cqe_eqe, 109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 110 111 static bool enable_4k_uar; 112 module_param(enable_4k_uar, bool, 0444); 113 MODULE_PARM_DESC(enable_4k_uar, 114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 115 116 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 118 MLX4_FUNC_CAP_DMFS_A0_STATIC) 119 120 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 121 122 static char mlx4_version[] = 123 DRV_NAME ": Mellanox ConnectX core driver v" 124 DRV_VERSION "\n"; 125 126 static const struct mlx4_profile default_profile = { 127 .num_qp = 1 << 18, 128 .num_srq = 1 << 16, 129 .rdmarc_per_qp = 1 << 4, 130 .num_cq = 1 << 16, 131 .num_mcg = 1 << 13, 132 .num_mpt = 1 << 19, 133 .num_mtt = 1 << 20, /* It is really num mtt segements */ 134 }; 135 136 static const struct mlx4_profile low_mem_profile = { 137 .num_qp = 1 << 17, 138 .num_srq = 1 << 6, 139 .rdmarc_per_qp = 1 << 4, 140 .num_cq = 1 << 8, 141 .num_mcg = 1 << 8, 142 .num_mpt = 1 << 9, 143 .num_mtt = 1 << 7, 144 }; 145 146 static int log_num_mac = 7; 147 module_param_named(log_num_mac, log_num_mac, int, 0444); 148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 149 150 static int log_num_vlan; 151 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 153 /* Log2 max number of VLANs per ETH port (0-7) */ 154 #define MLX4_LOG_NUM_VLANS 7 155 #define MLX4_MIN_LOG_NUM_VLANS 0 156 #define MLX4_MIN_LOG_NUM_MAC 1 157 158 static bool use_prio; 159 module_param_named(use_prio, use_prio, bool, 0444); 160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 161 162 int log_mtts_per_seg = ilog2(1); 163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 165 "(0-7) (default: 0)"); 166 167 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 168 static int arr_argc = 2; 169 module_param_array(port_type_array, int, &arr_argc, 0444); 170 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 171 "1 for IB, 2 for Ethernet"); 172 173 struct mlx4_port_config { 174 struct list_head list; 175 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 176 struct pci_dev *pdev; 177 }; 178 179 static atomic_t pf_loading = ATOMIC_INIT(0); 180 181 static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 182 struct devlink_param_gset_ctx *ctx) 183 { 184 ctx->val.vbool = !!mlx4_internal_err_reset; 185 return 0; 186 } 187 188 static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 189 struct devlink_param_gset_ctx *ctx) 190 { 191 mlx4_internal_err_reset = ctx->val.vbool; 192 return 0; 193 } 194 195 static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 196 struct devlink_param_gset_ctx *ctx) 197 { 198 struct mlx4_priv *priv = devlink_priv(devlink); 199 struct mlx4_dev *dev = &priv->dev; 200 201 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 202 return 0; 203 } 204 205 static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 206 struct devlink_param_gset_ctx *ctx) 207 { 208 struct mlx4_priv *priv = devlink_priv(devlink); 209 struct mlx4_dev *dev = &priv->dev; 210 211 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 212 return 0; 213 } 214 215 static int 216 mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 217 union devlink_param_value val, 218 struct netlink_ext_ack *extack) 219 { 220 u32 value = val.vu32; 221 222 if (value < 1 || value > 128) 223 return -ERANGE; 224 225 if (!is_power_of_2(value)) { 226 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 enum mlx4_devlink_param_id { 234 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 235 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 236 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 237 }; 238 239 static const struct devlink_param mlx4_devlink_params[] = { 240 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 241 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 242 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 243 mlx4_devlink_ierr_reset_get, 244 mlx4_devlink_ierr_reset_set, NULL), 245 DEVLINK_PARAM_GENERIC(MAX_MACS, 246 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 247 NULL, NULL, mlx4_devlink_max_macs_validate), 248 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 249 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 250 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 251 mlx4_devlink_crdump_snapshot_get, 252 mlx4_devlink_crdump_snapshot_set, NULL), 253 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 254 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 255 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 256 NULL, NULL, NULL), 257 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 258 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 259 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 260 NULL, NULL, NULL), 261 }; 262 263 static void mlx4_devlink_set_init_value(struct devlink *devlink, u32 param_id, 264 union devlink_param_value init_val) 265 { 266 struct mlx4_priv *priv = devlink_priv(devlink); 267 struct mlx4_dev *dev = &priv->dev; 268 int err; 269 270 err = devlink_param_driverinit_value_set(devlink, param_id, init_val); 271 if (err) 272 mlx4_warn(dev, 273 "devlink set parameter %u value failed (err = %d)", 274 param_id, err); 275 } 276 277 static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 278 { 279 union devlink_param_value value; 280 281 value.vbool = !!mlx4_internal_err_reset; 282 mlx4_devlink_set_init_value(devlink, 283 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 284 value); 285 286 value.vu32 = 1UL << log_num_mac; 287 mlx4_devlink_set_init_value(devlink, 288 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, value); 289 290 value.vbool = enable_64b_cqe_eqe; 291 mlx4_devlink_set_init_value(devlink, 292 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 293 value); 294 295 value.vbool = enable_4k_uar; 296 mlx4_devlink_set_init_value(devlink, 297 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 298 value); 299 300 value.vbool = false; 301 mlx4_devlink_set_init_value(devlink, 302 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 303 value); 304 } 305 306 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 307 struct mlx4_dev_cap *dev_cap) 308 { 309 /* The reserved_uars is calculated by system page size unit. 310 * Therefore, adjustment is added when the uar page size is less 311 * than the system page size 312 */ 313 dev->caps.reserved_uars = 314 max_t(int, 315 mlx4_get_num_reserved_uar(dev), 316 dev_cap->reserved_uars / 317 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 318 } 319 320 int mlx4_check_port_params(struct mlx4_dev *dev, 321 enum mlx4_port_type *port_type) 322 { 323 int i; 324 325 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 326 for (i = 0; i < dev->caps.num_ports - 1; i++) { 327 if (port_type[i] != port_type[i + 1]) { 328 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 329 return -EINVAL; 330 } 331 } 332 } 333 334 for (i = 0; i < dev->caps.num_ports; i++) { 335 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 336 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 337 i + 1); 338 return -EINVAL; 339 } 340 } 341 return 0; 342 } 343 344 static void mlx4_set_port_mask(struct mlx4_dev *dev) 345 { 346 int i; 347 348 for (i = 1; i <= dev->caps.num_ports; ++i) 349 dev->caps.port_mask[i] = dev->caps.port_type[i]; 350 } 351 352 enum { 353 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 354 }; 355 356 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 357 { 358 int err = 0; 359 struct mlx4_func func; 360 361 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 362 err = mlx4_QUERY_FUNC(dev, &func, 0); 363 if (err) { 364 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 365 return err; 366 } 367 dev_cap->max_eqs = func.max_eq; 368 dev_cap->reserved_eqs = func.rsvd_eqs; 369 dev_cap->reserved_uars = func.rsvd_uars; 370 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 371 } 372 return err; 373 } 374 375 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 376 { 377 struct mlx4_caps *dev_cap = &dev->caps; 378 379 /* FW not supporting or cancelled by user */ 380 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 381 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 382 return; 383 384 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 385 * When FW has NCSI it may decide not to report 64B CQE/EQEs 386 */ 387 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 388 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 389 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 390 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 391 return; 392 } 393 394 if (cache_line_size() == 128 || cache_line_size() == 256) { 395 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 396 /* Changing the real data inside CQE size to 32B */ 397 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 398 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 399 400 if (mlx4_is_master(dev)) 401 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 402 } else { 403 if (cache_line_size() != 32 && cache_line_size() != 64) 404 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 405 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 406 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 407 } 408 } 409 410 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 411 struct mlx4_port_cap *port_cap) 412 { 413 dev->caps.vl_cap[port] = port_cap->max_vl; 414 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 415 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 416 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 417 /* set gid and pkey table operating lengths by default 418 * to non-sriov values 419 */ 420 dev->caps.gid_table_len[port] = port_cap->max_gids; 421 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 422 dev->caps.port_width_cap[port] = port_cap->max_port_width; 423 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 424 dev->caps.max_tc_eth = port_cap->max_tc_eth; 425 dev->caps.def_mac[port] = port_cap->def_mac; 426 dev->caps.supported_type[port] = port_cap->supported_port_types; 427 dev->caps.suggested_type[port] = port_cap->suggested_type; 428 dev->caps.default_sense[port] = port_cap->default_sense; 429 dev->caps.trans_type[port] = port_cap->trans_type; 430 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 431 dev->caps.wavelength[port] = port_cap->wavelength; 432 dev->caps.trans_code[port] = port_cap->trans_code; 433 434 return 0; 435 } 436 437 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 438 struct mlx4_port_cap *port_cap) 439 { 440 int err = 0; 441 442 err = mlx4_QUERY_PORT(dev, port, port_cap); 443 444 if (err) 445 mlx4_err(dev, "QUERY_PORT command failed.\n"); 446 447 return err; 448 } 449 450 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 451 { 452 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 453 return; 454 455 if (mlx4_is_mfunc(dev)) { 456 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 457 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 458 return; 459 } 460 461 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 462 mlx4_dbg(dev, 463 "Keep FCS is not supported - Disabling Ignore FCS"); 464 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 465 return; 466 } 467 } 468 469 #define MLX4_A0_STEERING_TABLE_SIZE 256 470 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 471 { 472 int err; 473 int i; 474 475 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 476 if (err) { 477 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 478 return err; 479 } 480 mlx4_dev_cap_dump(dev, dev_cap); 481 482 if (dev_cap->min_page_sz > PAGE_SIZE) { 483 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 484 dev_cap->min_page_sz, PAGE_SIZE); 485 return -ENODEV; 486 } 487 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 488 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 489 dev_cap->num_ports, MLX4_MAX_PORTS); 490 return -ENODEV; 491 } 492 493 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 494 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 495 dev_cap->uar_size, 496 (unsigned long long) 497 pci_resource_len(dev->persist->pdev, 2)); 498 return -ENODEV; 499 } 500 501 dev->caps.num_ports = dev_cap->num_ports; 502 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 503 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 504 dev->caps.num_sys_eqs : 505 MLX4_MAX_EQ_NUM; 506 for (i = 1; i <= dev->caps.num_ports; ++i) { 507 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 508 if (err) { 509 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 510 return err; 511 } 512 } 513 514 dev->caps.uar_page_size = PAGE_SIZE; 515 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 516 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 517 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 518 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 519 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 520 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 521 dev->caps.max_wqes = dev_cap->max_qp_sz; 522 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 523 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 524 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 525 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 526 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 527 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 528 /* 529 * Subtract 1 from the limit because we need to allocate a 530 * spare CQE so the HCA HW can tell the difference between an 531 * empty CQ and a full CQ. 532 */ 533 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 534 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 535 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 536 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 537 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 538 539 dev->caps.reserved_pds = dev_cap->reserved_pds; 540 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 541 dev_cap->reserved_xrcds : 0; 542 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 543 dev_cap->max_xrcds : 0; 544 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 545 546 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 547 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 548 dev->caps.flags = dev_cap->flags; 549 dev->caps.flags2 = dev_cap->flags2; 550 dev->caps.bmme_flags = dev_cap->bmme_flags; 551 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 552 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 553 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 554 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 555 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 556 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 557 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 558 559 /* Save uar page shift */ 560 if (!mlx4_is_slave(dev)) { 561 /* Virtual PCI function needs to determine UAR page size from 562 * firmware. Only master PCI function can set the uar page size 563 */ 564 if (enable_4k_uar || !dev->persist->num_vfs) 565 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 566 else 567 dev->uar_page_shift = PAGE_SHIFT; 568 569 mlx4_set_num_reserved_uars(dev, dev_cap); 570 } 571 572 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 573 struct mlx4_init_hca_param hca_param; 574 575 memset(&hca_param, 0, sizeof(hca_param)); 576 err = mlx4_QUERY_HCA(dev, &hca_param); 577 /* Turn off PHV_EN flag in case phv_check_en is set. 578 * phv_check_en is a HW check that parse the packet and verify 579 * phv bit was reported correctly in the wqe. To allow QinQ 580 * PHV_EN flag should be set and phv_check_en must be cleared 581 * otherwise QinQ packets will be drop by the HW. 582 */ 583 if (err || hca_param.phv_check_en) 584 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 585 } 586 587 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 588 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 589 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 590 /* Don't do sense port on multifunction devices (for now at least) */ 591 if (mlx4_is_mfunc(dev)) 592 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 593 594 if (mlx4_low_memory_profile()) { 595 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 596 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 597 } else { 598 dev->caps.log_num_macs = log_num_mac; 599 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 600 } 601 602 for (i = 1; i <= dev->caps.num_ports; ++i) { 603 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 604 if (dev->caps.supported_type[i]) { 605 /* if only ETH is supported - assign ETH */ 606 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 607 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 608 /* if only IB is supported, assign IB */ 609 else if (dev->caps.supported_type[i] == 610 MLX4_PORT_TYPE_IB) 611 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 612 else { 613 /* if IB and ETH are supported, we set the port 614 * type according to user selection of port type; 615 * if user selected none, take the FW hint */ 616 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 617 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 618 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 619 else 620 dev->caps.port_type[i] = port_type_array[i - 1]; 621 } 622 } 623 /* 624 * Link sensing is allowed on the port if 3 conditions are true: 625 * 1. Both protocols are supported on the port. 626 * 2. Different types are supported on the port 627 * 3. FW declared that it supports link sensing 628 */ 629 mlx4_priv(dev)->sense.sense_allowed[i] = 630 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 631 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 632 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 633 634 /* 635 * If "default_sense" bit is set, we move the port to "AUTO" mode 636 * and perform sense_port FW command to try and set the correct 637 * port type from beginning 638 */ 639 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 640 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 641 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 642 mlx4_SENSE_PORT(dev, i, &sensed_port); 643 if (sensed_port != MLX4_PORT_TYPE_NONE) 644 dev->caps.port_type[i] = sensed_port; 645 } else { 646 dev->caps.possible_type[i] = dev->caps.port_type[i]; 647 } 648 649 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 650 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 651 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 652 i, 1 << dev->caps.log_num_macs); 653 } 654 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 655 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 656 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 657 i, 1 << dev->caps.log_num_vlans); 658 } 659 } 660 661 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 662 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 663 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 664 mlx4_warn(dev, 665 "Granular QoS per VF not supported with IB/Eth configuration\n"); 666 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 667 } 668 669 dev->caps.max_counters = dev_cap->max_counters; 670 671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 672 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 673 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 674 (1 << dev->caps.log_num_macs) * 675 (1 << dev->caps.log_num_vlans) * 676 dev->caps.num_ports; 677 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 678 679 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 680 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 681 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 682 else 683 dev->caps.dmfs_high_rate_qpn_base = 684 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 685 686 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 687 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 688 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 689 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 690 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 691 } else { 692 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 693 dev->caps.dmfs_high_rate_qpn_base = 694 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 695 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 696 } 697 698 dev->caps.rl_caps = dev_cap->rl_caps; 699 700 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 701 dev->caps.dmfs_high_rate_qpn_range; 702 703 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 704 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 705 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 706 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 707 708 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 709 710 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 711 if (dev_cap->flags & 712 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 713 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 714 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 715 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 716 } 717 718 if (dev_cap->flags2 & 719 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 720 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 721 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 722 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 723 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 724 } 725 } 726 727 if ((dev->caps.flags & 728 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 729 mlx4_is_master(dev)) 730 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 731 732 if (!mlx4_is_slave(dev)) { 733 mlx4_enable_cqe_eqe_stride(dev); 734 dev->caps.alloc_res_qp_mask = 735 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 736 MLX4_RESERVE_A0_QP; 737 738 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 739 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 740 mlx4_warn(dev, "Old device ETS support detected\n"); 741 mlx4_warn(dev, "Consider upgrading device FW.\n"); 742 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 743 } 744 745 } else { 746 dev->caps.alloc_res_qp_mask = 0; 747 } 748 749 mlx4_enable_ignore_fcs(dev); 750 751 return 0; 752 } 753 754 /*The function checks if there are live vf, return the num of them*/ 755 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 756 { 757 struct mlx4_priv *priv = mlx4_priv(dev); 758 struct mlx4_slave_state *s_state; 759 int i; 760 int ret = 0; 761 762 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 763 s_state = &priv->mfunc.master.slave_state[i]; 764 if (s_state->active && s_state->last_cmd != 765 MLX4_COMM_CMD_RESET) { 766 mlx4_warn(dev, "%s: slave: %d is still active\n", 767 __func__, i); 768 ret++; 769 } 770 } 771 return ret; 772 } 773 774 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 775 { 776 u32 qk = MLX4_RESERVED_QKEY_BASE; 777 778 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 779 qpn < dev->phys_caps.base_proxy_sqpn) 780 return -EINVAL; 781 782 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 783 /* tunnel qp */ 784 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 785 else 786 qk += qpn - dev->phys_caps.base_proxy_sqpn; 787 *qkey = qk; 788 return 0; 789 } 790 EXPORT_SYMBOL(mlx4_get_parav_qkey); 791 792 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 793 { 794 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 795 796 if (!mlx4_is_master(dev)) 797 return; 798 799 priv->virt2phys_pkey[slave][port - 1][i] = val; 800 } 801 EXPORT_SYMBOL(mlx4_sync_pkey_table); 802 803 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 804 { 805 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 806 807 if (!mlx4_is_master(dev)) 808 return; 809 810 priv->slave_node_guids[slave] = guid; 811 } 812 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 813 814 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 815 { 816 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 817 818 if (!mlx4_is_master(dev)) 819 return 0; 820 821 return priv->slave_node_guids[slave]; 822 } 823 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 824 825 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 826 { 827 struct mlx4_priv *priv = mlx4_priv(dev); 828 struct mlx4_slave_state *s_slave; 829 830 if (!mlx4_is_master(dev)) 831 return 0; 832 833 s_slave = &priv->mfunc.master.slave_state[slave]; 834 return !!s_slave->active; 835 } 836 EXPORT_SYMBOL(mlx4_is_slave_active); 837 838 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 839 struct _rule_hw *eth_header) 840 { 841 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 842 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 843 struct mlx4_net_trans_rule_hw_eth *eth = 844 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 845 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 846 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 847 next_rule->rsvd == 0; 848 849 if (last_rule) 850 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 851 } 852 } 853 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 854 855 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 856 struct mlx4_dev_cap *dev_cap, 857 struct mlx4_init_hca_param *hca_param) 858 { 859 dev->caps.steering_mode = hca_param->steering_mode; 860 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 861 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 862 dev->caps.fs_log_max_ucast_qp_range_size = 863 dev_cap->fs_log_max_ucast_qp_range_size; 864 } else 865 dev->caps.num_qp_per_mgm = 866 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 867 868 mlx4_dbg(dev, "Steering mode is: %s\n", 869 mlx4_steering_mode_str(dev->caps.steering_mode)); 870 } 871 872 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 873 { 874 kfree(dev->caps.spec_qps); 875 dev->caps.spec_qps = NULL; 876 } 877 878 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 879 { 880 struct mlx4_func_cap *func_cap = NULL; 881 struct mlx4_caps *caps = &dev->caps; 882 int i, err = 0; 883 884 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 885 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 886 887 if (!func_cap || !caps->spec_qps) { 888 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 889 err = -ENOMEM; 890 goto err_mem; 891 } 892 893 for (i = 1; i <= caps->num_ports; ++i) { 894 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 895 if (err) { 896 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 897 i, err); 898 goto err_mem; 899 } 900 caps->spec_qps[i - 1] = func_cap->spec_qps; 901 caps->port_mask[i] = caps->port_type[i]; 902 caps->phys_port_id[i] = func_cap->phys_port_id; 903 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 904 &caps->gid_table_len[i], 905 &caps->pkey_table_len[i]); 906 if (err) { 907 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 908 i, err); 909 goto err_mem; 910 } 911 } 912 913 err_mem: 914 if (err) 915 mlx4_slave_destroy_special_qp_cap(dev); 916 kfree(func_cap); 917 return err; 918 } 919 920 static int mlx4_slave_cap(struct mlx4_dev *dev) 921 { 922 int err; 923 u32 page_size; 924 struct mlx4_dev_cap *dev_cap = NULL; 925 struct mlx4_func_cap *func_cap = NULL; 926 struct mlx4_init_hca_param *hca_param = NULL; 927 928 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 929 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 930 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 931 if (!hca_param || !func_cap || !dev_cap) { 932 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 933 err = -ENOMEM; 934 goto free_mem; 935 } 936 937 err = mlx4_QUERY_HCA(dev, hca_param); 938 if (err) { 939 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 940 goto free_mem; 941 } 942 943 /* fail if the hca has an unknown global capability 944 * at this time global_caps should be always zeroed 945 */ 946 if (hca_param->global_caps) { 947 mlx4_err(dev, "Unknown hca global capabilities\n"); 948 err = -EINVAL; 949 goto free_mem; 950 } 951 952 dev->caps.hca_core_clock = hca_param->hca_core_clock; 953 954 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 955 err = mlx4_dev_cap(dev, dev_cap); 956 if (err) { 957 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 958 goto free_mem; 959 } 960 961 err = mlx4_QUERY_FW(dev); 962 if (err) 963 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 964 965 page_size = ~dev->caps.page_size_cap + 1; 966 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 967 if (page_size > PAGE_SIZE) { 968 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 969 page_size, PAGE_SIZE); 970 err = -ENODEV; 971 goto free_mem; 972 } 973 974 /* Set uar_page_shift for VF */ 975 dev->uar_page_shift = hca_param->uar_page_sz + 12; 976 977 /* Make sure the master uar page size is valid */ 978 if (dev->uar_page_shift > PAGE_SHIFT) { 979 mlx4_err(dev, 980 "Invalid configuration: uar page size is larger than system page size\n"); 981 err = -ENODEV; 982 goto free_mem; 983 } 984 985 /* Set reserved_uars based on the uar_page_shift */ 986 mlx4_set_num_reserved_uars(dev, dev_cap); 987 988 /* Although uar page size in FW differs from system page size, 989 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 990 * still works with assumption that uar page size == system page size 991 */ 992 dev->caps.uar_page_size = PAGE_SIZE; 993 994 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 995 if (err) { 996 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 997 err); 998 goto free_mem; 999 } 1000 1001 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 1002 PF_CONTEXT_BEHAVIOUR_MASK) { 1003 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 1004 func_cap->pf_context_behaviour, 1005 PF_CONTEXT_BEHAVIOUR_MASK); 1006 err = -EINVAL; 1007 goto free_mem; 1008 } 1009 1010 dev->caps.num_ports = func_cap->num_ports; 1011 dev->quotas.qp = func_cap->qp_quota; 1012 dev->quotas.srq = func_cap->srq_quota; 1013 dev->quotas.cq = func_cap->cq_quota; 1014 dev->quotas.mpt = func_cap->mpt_quota; 1015 dev->quotas.mtt = func_cap->mtt_quota; 1016 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1017 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1018 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1019 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1020 dev->caps.num_eqs = func_cap->max_eq; 1021 dev->caps.reserved_eqs = func_cap->reserved_eq; 1022 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1023 dev->caps.num_pds = MLX4_NUM_PDS; 1024 dev->caps.num_mgms = 0; 1025 dev->caps.num_amgms = 0; 1026 1027 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1028 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1029 dev->caps.num_ports, MLX4_MAX_PORTS); 1030 err = -ENODEV; 1031 goto free_mem; 1032 } 1033 1034 mlx4_replace_zero_macs(dev); 1035 1036 err = mlx4_slave_special_qp_cap(dev); 1037 if (err) { 1038 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1039 goto free_mem; 1040 } 1041 1042 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1043 dev->caps.reserved_uars) > 1044 pci_resource_len(dev->persist->pdev, 1045 2)) { 1046 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1047 dev->caps.uar_page_size * dev->caps.num_uars, 1048 (unsigned long long) 1049 pci_resource_len(dev->persist->pdev, 2)); 1050 err = -ENOMEM; 1051 goto err_mem; 1052 } 1053 1054 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1055 dev->caps.eqe_size = 64; 1056 dev->caps.eqe_factor = 1; 1057 } else { 1058 dev->caps.eqe_size = 32; 1059 dev->caps.eqe_factor = 0; 1060 } 1061 1062 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1063 dev->caps.cqe_size = 64; 1064 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1065 } else { 1066 dev->caps.cqe_size = 32; 1067 } 1068 1069 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1070 dev->caps.eqe_size = hca_param->eqe_size; 1071 dev->caps.eqe_factor = 0; 1072 } 1073 1074 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1075 dev->caps.cqe_size = hca_param->cqe_size; 1076 /* User still need to know when CQE > 32B */ 1077 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1078 } 1079 1080 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1081 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1082 1083 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1084 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1085 1086 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1087 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1088 hca_param->rss_ip_frags ? "on" : "off"); 1089 1090 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1091 dev->caps.bf_reg_size) 1092 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1093 1094 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1095 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1096 1097 err_mem: 1098 if (err) 1099 mlx4_slave_destroy_special_qp_cap(dev); 1100 free_mem: 1101 kfree(hca_param); 1102 kfree(func_cap); 1103 kfree(dev_cap); 1104 return err; 1105 } 1106 1107 static void mlx4_request_modules(struct mlx4_dev *dev) 1108 { 1109 int port; 1110 int has_ib_port = false; 1111 int has_eth_port = false; 1112 #define EN_DRV_NAME "mlx4_en" 1113 #define IB_DRV_NAME "mlx4_ib" 1114 1115 for (port = 1; port <= dev->caps.num_ports; port++) { 1116 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1117 has_ib_port = true; 1118 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1119 has_eth_port = true; 1120 } 1121 1122 if (has_eth_port) 1123 request_module_nowait(EN_DRV_NAME); 1124 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1125 request_module_nowait(IB_DRV_NAME); 1126 } 1127 1128 /* 1129 * Change the port configuration of the device. 1130 * Every user of this function must hold the port mutex. 1131 */ 1132 int mlx4_change_port_types(struct mlx4_dev *dev, 1133 enum mlx4_port_type *port_types) 1134 { 1135 int err = 0; 1136 int change = 0; 1137 int port; 1138 1139 for (port = 0; port < dev->caps.num_ports; port++) { 1140 /* Change the port type only if the new type is different 1141 * from the current, and not set to Auto */ 1142 if (port_types[port] != dev->caps.port_type[port + 1]) 1143 change = 1; 1144 } 1145 if (change) { 1146 mlx4_unregister_device(dev); 1147 for (port = 1; port <= dev->caps.num_ports; port++) { 1148 mlx4_CLOSE_PORT(dev, port); 1149 dev->caps.port_type[port] = port_types[port - 1]; 1150 err = mlx4_SET_PORT(dev, port, -1); 1151 if (err) { 1152 mlx4_err(dev, "Failed to set port %d, aborting\n", 1153 port); 1154 goto out; 1155 } 1156 } 1157 mlx4_set_port_mask(dev); 1158 err = mlx4_register_device(dev); 1159 if (err) { 1160 mlx4_err(dev, "Failed to register device\n"); 1161 goto out; 1162 } 1163 mlx4_request_modules(dev); 1164 } 1165 1166 out: 1167 return err; 1168 } 1169 1170 static ssize_t show_port_type(struct device *dev, 1171 struct device_attribute *attr, 1172 char *buf) 1173 { 1174 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1175 port_attr); 1176 struct mlx4_dev *mdev = info->dev; 1177 char type[8]; 1178 1179 sprintf(type, "%s", 1180 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1181 "ib" : "eth"); 1182 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1183 sprintf(buf, "auto (%s)\n", type); 1184 else 1185 sprintf(buf, "%s\n", type); 1186 1187 return strlen(buf); 1188 } 1189 1190 static int __set_port_type(struct mlx4_port_info *info, 1191 enum mlx4_port_type port_type) 1192 { 1193 struct mlx4_dev *mdev = info->dev; 1194 struct mlx4_priv *priv = mlx4_priv(mdev); 1195 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1196 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1197 int i; 1198 int err = 0; 1199 1200 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1201 mlx4_err(mdev, 1202 "Requested port type for port %d is not supported on this HCA\n", 1203 info->port); 1204 err = -EINVAL; 1205 goto err_sup; 1206 } 1207 1208 mlx4_stop_sense(mdev); 1209 mutex_lock(&priv->port_mutex); 1210 info->tmp_type = port_type; 1211 1212 /* Possible type is always the one that was delivered */ 1213 mdev->caps.possible_type[info->port] = info->tmp_type; 1214 1215 for (i = 0; i < mdev->caps.num_ports; i++) { 1216 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1217 mdev->caps.possible_type[i+1]; 1218 if (types[i] == MLX4_PORT_TYPE_AUTO) 1219 types[i] = mdev->caps.port_type[i+1]; 1220 } 1221 1222 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1223 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1224 for (i = 1; i <= mdev->caps.num_ports; i++) { 1225 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1226 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1227 err = -EINVAL; 1228 } 1229 } 1230 } 1231 if (err) { 1232 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1233 goto out; 1234 } 1235 1236 mlx4_do_sense_ports(mdev, new_types, types); 1237 1238 err = mlx4_check_port_params(mdev, new_types); 1239 if (err) 1240 goto out; 1241 1242 /* We are about to apply the changes after the configuration 1243 * was verified, no need to remember the temporary types 1244 * any more */ 1245 for (i = 0; i < mdev->caps.num_ports; i++) 1246 priv->port[i + 1].tmp_type = 0; 1247 1248 err = mlx4_change_port_types(mdev, new_types); 1249 1250 out: 1251 mlx4_start_sense(mdev); 1252 mutex_unlock(&priv->port_mutex); 1253 err_sup: 1254 return err; 1255 } 1256 1257 static ssize_t set_port_type(struct device *dev, 1258 struct device_attribute *attr, 1259 const char *buf, size_t count) 1260 { 1261 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1262 port_attr); 1263 struct mlx4_dev *mdev = info->dev; 1264 enum mlx4_port_type port_type; 1265 static DEFINE_MUTEX(set_port_type_mutex); 1266 int err; 1267 1268 mutex_lock(&set_port_type_mutex); 1269 1270 if (!strcmp(buf, "ib\n")) { 1271 port_type = MLX4_PORT_TYPE_IB; 1272 } else if (!strcmp(buf, "eth\n")) { 1273 port_type = MLX4_PORT_TYPE_ETH; 1274 } else if (!strcmp(buf, "auto\n")) { 1275 port_type = MLX4_PORT_TYPE_AUTO; 1276 } else { 1277 mlx4_err(mdev, "%s is not supported port type\n", buf); 1278 err = -EINVAL; 1279 goto err_out; 1280 } 1281 1282 err = __set_port_type(info, port_type); 1283 1284 err_out: 1285 mutex_unlock(&set_port_type_mutex); 1286 1287 return err ? err : count; 1288 } 1289 1290 enum ibta_mtu { 1291 IB_MTU_256 = 1, 1292 IB_MTU_512 = 2, 1293 IB_MTU_1024 = 3, 1294 IB_MTU_2048 = 4, 1295 IB_MTU_4096 = 5 1296 }; 1297 1298 static inline int int_to_ibta_mtu(int mtu) 1299 { 1300 switch (mtu) { 1301 case 256: return IB_MTU_256; 1302 case 512: return IB_MTU_512; 1303 case 1024: return IB_MTU_1024; 1304 case 2048: return IB_MTU_2048; 1305 case 4096: return IB_MTU_4096; 1306 default: return -1; 1307 } 1308 } 1309 1310 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1311 { 1312 switch (mtu) { 1313 case IB_MTU_256: return 256; 1314 case IB_MTU_512: return 512; 1315 case IB_MTU_1024: return 1024; 1316 case IB_MTU_2048: return 2048; 1317 case IB_MTU_4096: return 4096; 1318 default: return -1; 1319 } 1320 } 1321 1322 static ssize_t show_port_ib_mtu(struct device *dev, 1323 struct device_attribute *attr, 1324 char *buf) 1325 { 1326 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1327 port_mtu_attr); 1328 struct mlx4_dev *mdev = info->dev; 1329 1330 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1331 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1332 1333 sprintf(buf, "%d\n", 1334 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1335 return strlen(buf); 1336 } 1337 1338 static ssize_t set_port_ib_mtu(struct device *dev, 1339 struct device_attribute *attr, 1340 const char *buf, size_t count) 1341 { 1342 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1343 port_mtu_attr); 1344 struct mlx4_dev *mdev = info->dev; 1345 struct mlx4_priv *priv = mlx4_priv(mdev); 1346 int err, port, mtu, ibta_mtu = -1; 1347 1348 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1349 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1350 return -EINVAL; 1351 } 1352 1353 err = kstrtoint(buf, 0, &mtu); 1354 if (!err) 1355 ibta_mtu = int_to_ibta_mtu(mtu); 1356 1357 if (err || ibta_mtu < 0) { 1358 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1359 return -EINVAL; 1360 } 1361 1362 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1363 1364 mlx4_stop_sense(mdev); 1365 mutex_lock(&priv->port_mutex); 1366 mlx4_unregister_device(mdev); 1367 for (port = 1; port <= mdev->caps.num_ports; port++) { 1368 mlx4_CLOSE_PORT(mdev, port); 1369 err = mlx4_SET_PORT(mdev, port, -1); 1370 if (err) { 1371 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1372 port); 1373 goto err_set_port; 1374 } 1375 } 1376 err = mlx4_register_device(mdev); 1377 err_set_port: 1378 mutex_unlock(&priv->port_mutex); 1379 mlx4_start_sense(mdev); 1380 return err ? err : count; 1381 } 1382 1383 /* bond for multi-function device */ 1384 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1385 static int mlx4_mf_bond(struct mlx4_dev *dev) 1386 { 1387 int err = 0; 1388 int nvfs; 1389 struct mlx4_slaves_pport slaves_port1; 1390 struct mlx4_slaves_pport slaves_port2; 1391 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1392 1393 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1394 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1395 bitmap_and(slaves_port_1_2, 1396 slaves_port1.slaves, slaves_port2.slaves, 1397 dev->persist->num_vfs + 1); 1398 1399 /* only single port vfs are allowed */ 1400 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1401 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1402 return -EINVAL; 1403 } 1404 1405 /* number of virtual functions is number of total functions minus one 1406 * physical function for each port. 1407 */ 1408 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1409 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1410 1411 /* limit on maximum allowed VFs */ 1412 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1413 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1414 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1415 return -EINVAL; 1416 } 1417 1418 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1419 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1420 return -EINVAL; 1421 } 1422 1423 err = mlx4_bond_mac_table(dev); 1424 if (err) 1425 return err; 1426 err = mlx4_bond_vlan_table(dev); 1427 if (err) 1428 goto err1; 1429 err = mlx4_bond_fs_rules(dev); 1430 if (err) 1431 goto err2; 1432 1433 return 0; 1434 err2: 1435 (void)mlx4_unbond_vlan_table(dev); 1436 err1: 1437 (void)mlx4_unbond_mac_table(dev); 1438 return err; 1439 } 1440 1441 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1442 { 1443 int ret, ret1; 1444 1445 ret = mlx4_unbond_fs_rules(dev); 1446 if (ret) 1447 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1448 ret1 = mlx4_unbond_mac_table(dev); 1449 if (ret1) { 1450 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1451 ret = ret1; 1452 } 1453 ret1 = mlx4_unbond_vlan_table(dev); 1454 if (ret1) { 1455 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1456 ret = ret1; 1457 } 1458 return ret; 1459 } 1460 1461 int mlx4_bond(struct mlx4_dev *dev) 1462 { 1463 int ret = 0; 1464 struct mlx4_priv *priv = mlx4_priv(dev); 1465 1466 mutex_lock(&priv->bond_mutex); 1467 1468 if (!mlx4_is_bonded(dev)) { 1469 ret = mlx4_do_bond(dev, true); 1470 if (ret) 1471 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1472 if (!ret && mlx4_is_master(dev)) { 1473 ret = mlx4_mf_bond(dev); 1474 if (ret) { 1475 mlx4_err(dev, "bond for multifunction failed\n"); 1476 mlx4_do_bond(dev, false); 1477 } 1478 } 1479 } 1480 1481 mutex_unlock(&priv->bond_mutex); 1482 if (!ret) 1483 mlx4_dbg(dev, "Device is bonded\n"); 1484 1485 return ret; 1486 } 1487 EXPORT_SYMBOL_GPL(mlx4_bond); 1488 1489 int mlx4_unbond(struct mlx4_dev *dev) 1490 { 1491 int ret = 0; 1492 struct mlx4_priv *priv = mlx4_priv(dev); 1493 1494 mutex_lock(&priv->bond_mutex); 1495 1496 if (mlx4_is_bonded(dev)) { 1497 int ret2 = 0; 1498 1499 ret = mlx4_do_bond(dev, false); 1500 if (ret) 1501 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1502 if (mlx4_is_master(dev)) 1503 ret2 = mlx4_mf_unbond(dev); 1504 if (ret2) { 1505 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1506 ret = ret2; 1507 } 1508 } 1509 1510 mutex_unlock(&priv->bond_mutex); 1511 if (!ret) 1512 mlx4_dbg(dev, "Device is unbonded\n"); 1513 1514 return ret; 1515 } 1516 EXPORT_SYMBOL_GPL(mlx4_unbond); 1517 1518 1519 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1520 { 1521 u8 port1 = v2p->port1; 1522 u8 port2 = v2p->port2; 1523 struct mlx4_priv *priv = mlx4_priv(dev); 1524 int err; 1525 1526 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1527 return -EOPNOTSUPP; 1528 1529 mutex_lock(&priv->bond_mutex); 1530 1531 /* zero means keep current mapping for this port */ 1532 if (port1 == 0) 1533 port1 = priv->v2p.port1; 1534 if (port2 == 0) 1535 port2 = priv->v2p.port2; 1536 1537 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1538 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1539 (port1 == 2 && port2 == 1)) { 1540 /* besides boundary checks cross mapping makes 1541 * no sense and therefore not allowed */ 1542 err = -EINVAL; 1543 } else if ((port1 == priv->v2p.port1) && 1544 (port2 == priv->v2p.port2)) { 1545 err = 0; 1546 } else { 1547 err = mlx4_virt2phy_port_map(dev, port1, port2); 1548 if (!err) { 1549 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1550 port1, port2); 1551 priv->v2p.port1 = port1; 1552 priv->v2p.port2 = port2; 1553 } else { 1554 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1555 } 1556 } 1557 1558 mutex_unlock(&priv->bond_mutex); 1559 return err; 1560 } 1561 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1562 1563 static int mlx4_load_fw(struct mlx4_dev *dev) 1564 { 1565 struct mlx4_priv *priv = mlx4_priv(dev); 1566 int err; 1567 1568 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1569 GFP_HIGHUSER | __GFP_NOWARN, 0); 1570 if (!priv->fw.fw_icm) { 1571 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1572 return -ENOMEM; 1573 } 1574 1575 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1576 if (err) { 1577 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1578 goto err_free; 1579 } 1580 1581 err = mlx4_RUN_FW(dev); 1582 if (err) { 1583 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1584 goto err_unmap_fa; 1585 } 1586 1587 return 0; 1588 1589 err_unmap_fa: 1590 mlx4_UNMAP_FA(dev); 1591 1592 err_free: 1593 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1594 return err; 1595 } 1596 1597 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1598 int cmpt_entry_sz) 1599 { 1600 struct mlx4_priv *priv = mlx4_priv(dev); 1601 int err; 1602 int num_eqs; 1603 1604 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1605 cmpt_base + 1606 ((u64) (MLX4_CMPT_TYPE_QP * 1607 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1608 cmpt_entry_sz, dev->caps.num_qps, 1609 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1610 0, 0); 1611 if (err) 1612 goto err; 1613 1614 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1615 cmpt_base + 1616 ((u64) (MLX4_CMPT_TYPE_SRQ * 1617 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1618 cmpt_entry_sz, dev->caps.num_srqs, 1619 dev->caps.reserved_srqs, 0, 0); 1620 if (err) 1621 goto err_qp; 1622 1623 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1624 cmpt_base + 1625 ((u64) (MLX4_CMPT_TYPE_CQ * 1626 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1627 cmpt_entry_sz, dev->caps.num_cqs, 1628 dev->caps.reserved_cqs, 0, 0); 1629 if (err) 1630 goto err_srq; 1631 1632 num_eqs = dev->phys_caps.num_phys_eqs; 1633 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1634 cmpt_base + 1635 ((u64) (MLX4_CMPT_TYPE_EQ * 1636 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1637 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1638 if (err) 1639 goto err_cq; 1640 1641 return 0; 1642 1643 err_cq: 1644 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1645 1646 err_srq: 1647 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1648 1649 err_qp: 1650 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1651 1652 err: 1653 return err; 1654 } 1655 1656 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1657 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1658 { 1659 struct mlx4_priv *priv = mlx4_priv(dev); 1660 u64 aux_pages; 1661 int num_eqs; 1662 int err; 1663 1664 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1665 if (err) { 1666 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1667 return err; 1668 } 1669 1670 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1671 (unsigned long long) icm_size >> 10, 1672 (unsigned long long) aux_pages << 2); 1673 1674 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1675 GFP_HIGHUSER | __GFP_NOWARN, 0); 1676 if (!priv->fw.aux_icm) { 1677 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1678 return -ENOMEM; 1679 } 1680 1681 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1682 if (err) { 1683 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1684 goto err_free_aux; 1685 } 1686 1687 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1688 if (err) { 1689 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1690 goto err_unmap_aux; 1691 } 1692 1693 1694 num_eqs = dev->phys_caps.num_phys_eqs; 1695 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1696 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1697 num_eqs, num_eqs, 0, 0); 1698 if (err) { 1699 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1700 goto err_unmap_cmpt; 1701 } 1702 1703 /* 1704 * Reserved MTT entries must be aligned up to a cacheline 1705 * boundary, since the FW will write to them, while the driver 1706 * writes to all other MTT entries. (The variable 1707 * dev->caps.mtt_entry_sz below is really the MTT segment 1708 * size, not the raw entry size) 1709 */ 1710 dev->caps.reserved_mtts = 1711 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1712 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1713 1714 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1715 init_hca->mtt_base, 1716 dev->caps.mtt_entry_sz, 1717 dev->caps.num_mtts, 1718 dev->caps.reserved_mtts, 1, 0); 1719 if (err) { 1720 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1721 goto err_unmap_eq; 1722 } 1723 1724 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1725 init_hca->dmpt_base, 1726 dev_cap->dmpt_entry_sz, 1727 dev->caps.num_mpts, 1728 dev->caps.reserved_mrws, 1, 1); 1729 if (err) { 1730 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1731 goto err_unmap_mtt; 1732 } 1733 1734 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1735 init_hca->qpc_base, 1736 dev_cap->qpc_entry_sz, 1737 dev->caps.num_qps, 1738 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1739 0, 0); 1740 if (err) { 1741 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1742 goto err_unmap_dmpt; 1743 } 1744 1745 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1746 init_hca->auxc_base, 1747 dev_cap->aux_entry_sz, 1748 dev->caps.num_qps, 1749 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1750 0, 0); 1751 if (err) { 1752 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1753 goto err_unmap_qp; 1754 } 1755 1756 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1757 init_hca->altc_base, 1758 dev_cap->altc_entry_sz, 1759 dev->caps.num_qps, 1760 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1761 0, 0); 1762 if (err) { 1763 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1764 goto err_unmap_auxc; 1765 } 1766 1767 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1768 init_hca->rdmarc_base, 1769 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1770 dev->caps.num_qps, 1771 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1772 0, 0); 1773 if (err) { 1774 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1775 goto err_unmap_altc; 1776 } 1777 1778 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1779 init_hca->cqc_base, 1780 dev_cap->cqc_entry_sz, 1781 dev->caps.num_cqs, 1782 dev->caps.reserved_cqs, 0, 0); 1783 if (err) { 1784 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1785 goto err_unmap_rdmarc; 1786 } 1787 1788 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1789 init_hca->srqc_base, 1790 dev_cap->srq_entry_sz, 1791 dev->caps.num_srqs, 1792 dev->caps.reserved_srqs, 0, 0); 1793 if (err) { 1794 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1795 goto err_unmap_cq; 1796 } 1797 1798 /* 1799 * For flow steering device managed mode it is required to use 1800 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1801 * required, but for simplicity just map the whole multicast 1802 * group table now. The table isn't very big and it's a lot 1803 * easier than trying to track ref counts. 1804 */ 1805 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1806 init_hca->mc_base, 1807 mlx4_get_mgm_entry_size(dev), 1808 dev->caps.num_mgms + dev->caps.num_amgms, 1809 dev->caps.num_mgms + dev->caps.num_amgms, 1810 0, 0); 1811 if (err) { 1812 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1813 goto err_unmap_srq; 1814 } 1815 1816 return 0; 1817 1818 err_unmap_srq: 1819 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1820 1821 err_unmap_cq: 1822 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1823 1824 err_unmap_rdmarc: 1825 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1826 1827 err_unmap_altc: 1828 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1829 1830 err_unmap_auxc: 1831 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1832 1833 err_unmap_qp: 1834 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1835 1836 err_unmap_dmpt: 1837 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1838 1839 err_unmap_mtt: 1840 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1841 1842 err_unmap_eq: 1843 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1844 1845 err_unmap_cmpt: 1846 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1847 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1848 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1849 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1850 1851 err_unmap_aux: 1852 mlx4_UNMAP_ICM_AUX(dev); 1853 1854 err_free_aux: 1855 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1856 1857 return err; 1858 } 1859 1860 static void mlx4_free_icms(struct mlx4_dev *dev) 1861 { 1862 struct mlx4_priv *priv = mlx4_priv(dev); 1863 1864 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1865 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1866 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1867 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1868 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1869 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1870 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1871 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1872 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1873 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1874 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1875 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1876 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1877 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1878 1879 mlx4_UNMAP_ICM_AUX(dev); 1880 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1881 } 1882 1883 static void mlx4_slave_exit(struct mlx4_dev *dev) 1884 { 1885 struct mlx4_priv *priv = mlx4_priv(dev); 1886 1887 mutex_lock(&priv->cmd.slave_cmd_mutex); 1888 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1889 MLX4_COMM_TIME)) 1890 mlx4_warn(dev, "Failed to close slave function\n"); 1891 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1892 } 1893 1894 static int map_bf_area(struct mlx4_dev *dev) 1895 { 1896 struct mlx4_priv *priv = mlx4_priv(dev); 1897 resource_size_t bf_start; 1898 resource_size_t bf_len; 1899 int err = 0; 1900 1901 if (!dev->caps.bf_reg_size) 1902 return -ENXIO; 1903 1904 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1905 (dev->caps.num_uars << PAGE_SHIFT); 1906 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1907 (dev->caps.num_uars << PAGE_SHIFT); 1908 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1909 if (!priv->bf_mapping) 1910 err = -ENOMEM; 1911 1912 return err; 1913 } 1914 1915 static void unmap_bf_area(struct mlx4_dev *dev) 1916 { 1917 if (mlx4_priv(dev)->bf_mapping) 1918 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1919 } 1920 1921 u64 mlx4_read_clock(struct mlx4_dev *dev) 1922 { 1923 u32 clockhi, clocklo, clockhi1; 1924 u64 cycles; 1925 int i; 1926 struct mlx4_priv *priv = mlx4_priv(dev); 1927 1928 for (i = 0; i < 10; i++) { 1929 clockhi = swab32(readl(priv->clock_mapping)); 1930 clocklo = swab32(readl(priv->clock_mapping + 4)); 1931 clockhi1 = swab32(readl(priv->clock_mapping)); 1932 if (clockhi == clockhi1) 1933 break; 1934 } 1935 1936 cycles = (u64) clockhi << 32 | (u64) clocklo; 1937 1938 return cycles; 1939 } 1940 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1941 1942 1943 static int map_internal_clock(struct mlx4_dev *dev) 1944 { 1945 struct mlx4_priv *priv = mlx4_priv(dev); 1946 1947 priv->clock_mapping = 1948 ioremap(pci_resource_start(dev->persist->pdev, 1949 priv->fw.clock_bar) + 1950 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1951 1952 if (!priv->clock_mapping) 1953 return -ENOMEM; 1954 1955 return 0; 1956 } 1957 1958 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1959 struct mlx4_clock_params *params) 1960 { 1961 struct mlx4_priv *priv = mlx4_priv(dev); 1962 1963 if (mlx4_is_slave(dev)) 1964 return -EOPNOTSUPP; 1965 1966 if (!params) 1967 return -EINVAL; 1968 1969 params->bar = priv->fw.clock_bar; 1970 params->offset = priv->fw.clock_offset; 1971 params->size = MLX4_CLOCK_SIZE; 1972 1973 return 0; 1974 } 1975 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1976 1977 static void unmap_internal_clock(struct mlx4_dev *dev) 1978 { 1979 struct mlx4_priv *priv = mlx4_priv(dev); 1980 1981 if (priv->clock_mapping) 1982 iounmap(priv->clock_mapping); 1983 } 1984 1985 static void mlx4_close_hca(struct mlx4_dev *dev) 1986 { 1987 unmap_internal_clock(dev); 1988 unmap_bf_area(dev); 1989 if (mlx4_is_slave(dev)) 1990 mlx4_slave_exit(dev); 1991 else { 1992 mlx4_CLOSE_HCA(dev, 0); 1993 mlx4_free_icms(dev); 1994 } 1995 } 1996 1997 static void mlx4_close_fw(struct mlx4_dev *dev) 1998 { 1999 if (!mlx4_is_slave(dev)) { 2000 mlx4_UNMAP_FA(dev); 2001 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 2002 } 2003 } 2004 2005 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 2006 { 2007 #define COMM_CHAN_OFFLINE_OFFSET 0x09 2008 2009 u32 comm_flags; 2010 u32 offline_bit; 2011 unsigned long end; 2012 struct mlx4_priv *priv = mlx4_priv(dev); 2013 2014 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2015 while (time_before(jiffies, end)) { 2016 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2017 MLX4_COMM_CHAN_FLAGS)); 2018 offline_bit = (comm_flags & 2019 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2020 if (!offline_bit) 2021 return 0; 2022 2023 /* If device removal has been requested, 2024 * do not continue retrying. 2025 */ 2026 if (dev->persist->interface_state & 2027 MLX4_INTERFACE_STATE_NOWAIT) 2028 break; 2029 2030 /* There are cases as part of AER/Reset flow that PF needs 2031 * around 100 msec to load. We therefore sleep for 100 msec 2032 * to allow other tasks to make use of that CPU during this 2033 * time interval. 2034 */ 2035 msleep(100); 2036 } 2037 mlx4_err(dev, "Communication channel is offline.\n"); 2038 return -EIO; 2039 } 2040 2041 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2042 { 2043 #define COMM_CHAN_RST_OFFSET 0x1e 2044 2045 struct mlx4_priv *priv = mlx4_priv(dev); 2046 u32 comm_rst; 2047 u32 comm_caps; 2048 2049 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2050 MLX4_COMM_CHAN_CAPS)); 2051 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2052 2053 if (comm_rst) 2054 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2055 } 2056 2057 static int mlx4_init_slave(struct mlx4_dev *dev) 2058 { 2059 struct mlx4_priv *priv = mlx4_priv(dev); 2060 u64 dma = (u64) priv->mfunc.vhcr_dma; 2061 int ret_from_reset = 0; 2062 u32 slave_read; 2063 u32 cmd_channel_ver; 2064 2065 if (atomic_read(&pf_loading)) { 2066 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2067 return -EPROBE_DEFER; 2068 } 2069 2070 mutex_lock(&priv->cmd.slave_cmd_mutex); 2071 priv->cmd.max_cmds = 1; 2072 if (mlx4_comm_check_offline(dev)) { 2073 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2074 goto err_offline; 2075 } 2076 2077 mlx4_reset_vf_support(dev); 2078 mlx4_warn(dev, "Sending reset\n"); 2079 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2080 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2081 /* if we are in the middle of flr the slave will try 2082 * NUM_OF_RESET_RETRIES times before leaving.*/ 2083 if (ret_from_reset) { 2084 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2085 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2086 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2087 return -EPROBE_DEFER; 2088 } else 2089 goto err; 2090 } 2091 2092 /* check the driver version - the slave I/F revision 2093 * must match the master's */ 2094 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2095 cmd_channel_ver = mlx4_comm_get_version(); 2096 2097 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2098 MLX4_COMM_GET_IF_REV(slave_read)) { 2099 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2100 goto err; 2101 } 2102 2103 mlx4_warn(dev, "Sending vhcr0\n"); 2104 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2105 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2106 goto err; 2107 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2108 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2109 goto err; 2110 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2111 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2112 goto err; 2113 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2114 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2115 goto err; 2116 2117 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2118 return 0; 2119 2120 err: 2121 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2122 err_offline: 2123 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2124 return -EIO; 2125 } 2126 2127 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2128 { 2129 int i; 2130 2131 for (i = 1; i <= dev->caps.num_ports; i++) { 2132 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2133 dev->caps.gid_table_len[i] = 2134 mlx4_get_slave_num_gids(dev, 0, i); 2135 else 2136 dev->caps.gid_table_len[i] = 1; 2137 dev->caps.pkey_table_len[i] = 2138 dev->phys_caps.pkey_phys_table_len[i] - 1; 2139 } 2140 } 2141 2142 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2143 { 2144 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2145 2146 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2147 i++) { 2148 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2149 break; 2150 } 2151 2152 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2153 } 2154 2155 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2156 { 2157 switch (dmfs_high_steer_mode) { 2158 case MLX4_STEERING_DMFS_A0_DEFAULT: 2159 return "default performance"; 2160 2161 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2162 return "dynamic hybrid mode"; 2163 2164 case MLX4_STEERING_DMFS_A0_STATIC: 2165 return "performance optimized for limited rule configuration (static)"; 2166 2167 case MLX4_STEERING_DMFS_A0_DISABLE: 2168 return "disabled performance optimized steering"; 2169 2170 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2171 return "performance optimized steering not supported"; 2172 2173 default: 2174 return "Unrecognized mode"; 2175 } 2176 } 2177 2178 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2179 2180 static void choose_steering_mode(struct mlx4_dev *dev, 2181 struct mlx4_dev_cap *dev_cap) 2182 { 2183 if (mlx4_log_num_mgm_entry_size <= 0) { 2184 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2185 if (dev->caps.dmfs_high_steer_mode == 2186 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2187 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2188 else 2189 dev->caps.dmfs_high_steer_mode = 2190 MLX4_STEERING_DMFS_A0_STATIC; 2191 } 2192 } 2193 2194 if (mlx4_log_num_mgm_entry_size <= 0 && 2195 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2196 (!mlx4_is_mfunc(dev) || 2197 (dev_cap->fs_max_num_qp_per_entry >= 2198 (dev->persist->num_vfs + 1))) && 2199 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2200 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2201 dev->oper_log_mgm_entry_size = 2202 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2203 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2204 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2205 dev->caps.fs_log_max_ucast_qp_range_size = 2206 dev_cap->fs_log_max_ucast_qp_range_size; 2207 } else { 2208 if (dev->caps.dmfs_high_steer_mode != 2209 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2210 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2211 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2212 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2213 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2214 else { 2215 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2216 2217 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2218 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2219 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2220 } 2221 dev->oper_log_mgm_entry_size = 2222 mlx4_log_num_mgm_entry_size > 0 ? 2223 mlx4_log_num_mgm_entry_size : 2224 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2225 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2226 } 2227 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2228 mlx4_steering_mode_str(dev->caps.steering_mode), 2229 dev->oper_log_mgm_entry_size, 2230 mlx4_log_num_mgm_entry_size); 2231 } 2232 2233 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2234 struct mlx4_dev_cap *dev_cap) 2235 { 2236 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2237 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2238 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2239 else 2240 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2241 2242 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2243 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2244 } 2245 2246 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2247 { 2248 int i; 2249 struct mlx4_port_cap port_cap; 2250 2251 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2252 return -EINVAL; 2253 2254 for (i = 1; i <= dev->caps.num_ports; i++) { 2255 if (mlx4_dev_port(dev, i, &port_cap)) { 2256 mlx4_err(dev, 2257 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 2258 } else if ((dev->caps.dmfs_high_steer_mode != 2259 MLX4_STEERING_DMFS_A0_DEFAULT) && 2260 (port_cap.dmfs_optimized_state == 2261 !!(dev->caps.dmfs_high_steer_mode == 2262 MLX4_STEERING_DMFS_A0_DISABLE))) { 2263 mlx4_err(dev, 2264 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2265 dmfs_high_rate_steering_mode_str( 2266 dev->caps.dmfs_high_steer_mode), 2267 (port_cap.dmfs_optimized_state ? 2268 "enabled" : "disabled")); 2269 } 2270 } 2271 2272 return 0; 2273 } 2274 2275 static int mlx4_init_fw(struct mlx4_dev *dev) 2276 { 2277 struct mlx4_mod_stat_cfg mlx4_cfg; 2278 int err = 0; 2279 2280 if (!mlx4_is_slave(dev)) { 2281 err = mlx4_QUERY_FW(dev); 2282 if (err) { 2283 if (err == -EACCES) 2284 mlx4_info(dev, "non-primary physical function, skipping\n"); 2285 else 2286 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2287 return err; 2288 } 2289 2290 err = mlx4_load_fw(dev); 2291 if (err) { 2292 mlx4_err(dev, "Failed to start FW, aborting\n"); 2293 return err; 2294 } 2295 2296 mlx4_cfg.log_pg_sz_m = 1; 2297 mlx4_cfg.log_pg_sz = 0; 2298 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2299 if (err) 2300 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2301 } 2302 2303 return err; 2304 } 2305 2306 static int mlx4_init_hca(struct mlx4_dev *dev) 2307 { 2308 struct mlx4_priv *priv = mlx4_priv(dev); 2309 struct mlx4_adapter adapter; 2310 struct mlx4_dev_cap dev_cap; 2311 struct mlx4_profile profile; 2312 struct mlx4_init_hca_param init_hca; 2313 u64 icm_size; 2314 struct mlx4_config_dev_params params; 2315 int err; 2316 2317 if (!mlx4_is_slave(dev)) { 2318 err = mlx4_dev_cap(dev, &dev_cap); 2319 if (err) { 2320 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2321 return err; 2322 } 2323 2324 choose_steering_mode(dev, &dev_cap); 2325 choose_tunnel_offload_mode(dev, &dev_cap); 2326 2327 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2328 mlx4_is_master(dev)) 2329 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2330 2331 err = mlx4_get_phys_port_id(dev); 2332 if (err) 2333 mlx4_err(dev, "Fail to get physical port id\n"); 2334 2335 if (mlx4_is_master(dev)) 2336 mlx4_parav_master_pf_caps(dev); 2337 2338 if (mlx4_low_memory_profile()) { 2339 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2340 profile = low_mem_profile; 2341 } else { 2342 profile = default_profile; 2343 } 2344 if (dev->caps.steering_mode == 2345 MLX4_STEERING_MODE_DEVICE_MANAGED) 2346 profile.num_mcg = MLX4_FS_NUM_MCG; 2347 2348 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2349 &init_hca); 2350 if ((long long) icm_size < 0) { 2351 err = icm_size; 2352 return err; 2353 } 2354 2355 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2356 2357 if (enable_4k_uar || !dev->persist->num_vfs) { 2358 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) + 2359 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2360 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2361 } else { 2362 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2363 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2364 } 2365 2366 init_hca.mw_enabled = 0; 2367 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2368 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2369 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2370 2371 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2372 if (err) 2373 return err; 2374 2375 err = mlx4_INIT_HCA(dev, &init_hca); 2376 if (err) { 2377 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2378 goto err_free_icm; 2379 } 2380 2381 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2382 err = mlx4_query_func(dev, &dev_cap); 2383 if (err < 0) { 2384 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2385 goto err_close; 2386 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2387 dev->caps.num_eqs = dev_cap.max_eqs; 2388 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2389 dev->caps.reserved_uars = dev_cap.reserved_uars; 2390 } 2391 } 2392 2393 /* 2394 * If TS is supported by FW 2395 * read HCA frequency by QUERY_HCA command 2396 */ 2397 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2398 memset(&init_hca, 0, sizeof(init_hca)); 2399 err = mlx4_QUERY_HCA(dev, &init_hca); 2400 if (err) { 2401 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2402 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2403 } else { 2404 dev->caps.hca_core_clock = 2405 init_hca.hca_core_clock; 2406 } 2407 2408 /* In case we got HCA frequency 0 - disable timestamping 2409 * to avoid dividing by zero 2410 */ 2411 if (!dev->caps.hca_core_clock) { 2412 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2413 mlx4_err(dev, 2414 "HCA frequency is 0 - timestamping is not supported\n"); 2415 } else if (map_internal_clock(dev)) { 2416 /* 2417 * Map internal clock, 2418 * in case of failure disable timestamping 2419 */ 2420 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2421 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2422 } 2423 } 2424 2425 if (dev->caps.dmfs_high_steer_mode != 2426 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2427 if (mlx4_validate_optimized_steering(dev)) 2428 mlx4_warn(dev, "Optimized steering validation failed\n"); 2429 2430 if (dev->caps.dmfs_high_steer_mode == 2431 MLX4_STEERING_DMFS_A0_DISABLE) { 2432 dev->caps.dmfs_high_rate_qpn_base = 2433 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2434 dev->caps.dmfs_high_rate_qpn_range = 2435 MLX4_A0_STEERING_TABLE_SIZE; 2436 } 2437 2438 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2439 dmfs_high_rate_steering_mode_str( 2440 dev->caps.dmfs_high_steer_mode)); 2441 } 2442 } else { 2443 err = mlx4_init_slave(dev); 2444 if (err) { 2445 if (err != -EPROBE_DEFER) 2446 mlx4_err(dev, "Failed to initialize slave\n"); 2447 return err; 2448 } 2449 2450 err = mlx4_slave_cap(dev); 2451 if (err) { 2452 mlx4_err(dev, "Failed to obtain slave caps\n"); 2453 goto err_close; 2454 } 2455 } 2456 2457 if (map_bf_area(dev)) 2458 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2459 2460 /*Only the master set the ports, all the rest got it from it.*/ 2461 if (!mlx4_is_slave(dev)) 2462 mlx4_set_port_mask(dev); 2463 2464 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2465 if (err) { 2466 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2467 goto unmap_bf; 2468 } 2469 2470 /* Query CONFIG_DEV parameters */ 2471 err = mlx4_config_dev_retrieval(dev, ¶ms); 2472 if (err && err != -EOPNOTSUPP) { 2473 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2474 } else if (!err) { 2475 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2476 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2477 } 2478 priv->eq_table.inta_pin = adapter.inta_pin; 2479 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2480 2481 return 0; 2482 2483 unmap_bf: 2484 unmap_internal_clock(dev); 2485 unmap_bf_area(dev); 2486 2487 if (mlx4_is_slave(dev)) 2488 mlx4_slave_destroy_special_qp_cap(dev); 2489 2490 err_close: 2491 if (mlx4_is_slave(dev)) 2492 mlx4_slave_exit(dev); 2493 else 2494 mlx4_CLOSE_HCA(dev, 0); 2495 2496 err_free_icm: 2497 if (!mlx4_is_slave(dev)) 2498 mlx4_free_icms(dev); 2499 2500 return err; 2501 } 2502 2503 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2504 { 2505 struct mlx4_priv *priv = mlx4_priv(dev); 2506 int nent_pow2; 2507 2508 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2509 return -ENOENT; 2510 2511 if (!dev->caps.max_counters) 2512 return -ENOSPC; 2513 2514 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2515 /* reserve last counter index for sink counter */ 2516 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2517 nent_pow2 - 1, 0, 2518 nent_pow2 - dev->caps.max_counters + 1); 2519 } 2520 2521 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2522 { 2523 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2524 return; 2525 2526 if (!dev->caps.max_counters) 2527 return; 2528 2529 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2530 } 2531 2532 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2533 { 2534 struct mlx4_priv *priv = mlx4_priv(dev); 2535 int port; 2536 2537 for (port = 0; port < dev->caps.num_ports; port++) 2538 if (priv->def_counter[port] != -1) 2539 mlx4_counter_free(dev, priv->def_counter[port]); 2540 } 2541 2542 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2543 { 2544 struct mlx4_priv *priv = mlx4_priv(dev); 2545 int port, err = 0; 2546 u32 idx; 2547 2548 for (port = 0; port < dev->caps.num_ports; port++) 2549 priv->def_counter[port] = -1; 2550 2551 for (port = 0; port < dev->caps.num_ports; port++) { 2552 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2553 2554 if (!err || err == -ENOSPC) { 2555 priv->def_counter[port] = idx; 2556 } else if (err == -ENOENT) { 2557 err = 0; 2558 continue; 2559 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2560 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2561 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2562 MLX4_SINK_COUNTER_INDEX(dev)); 2563 err = 0; 2564 } else { 2565 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2566 __func__, port + 1, err); 2567 mlx4_cleanup_default_counters(dev); 2568 return err; 2569 } 2570 2571 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2572 __func__, priv->def_counter[port], port + 1); 2573 } 2574 2575 return err; 2576 } 2577 2578 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2579 { 2580 struct mlx4_priv *priv = mlx4_priv(dev); 2581 2582 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2583 return -ENOENT; 2584 2585 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2586 if (*idx == -1) { 2587 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2588 return -ENOSPC; 2589 } 2590 2591 return 0; 2592 } 2593 2594 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2595 { 2596 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2597 u64 out_param; 2598 int err; 2599 2600 if (mlx4_is_mfunc(dev)) { 2601 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2602 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2603 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2604 if (!err) 2605 *idx = get_param_l(&out_param); 2606 2607 return err; 2608 } 2609 return __mlx4_counter_alloc(dev, idx); 2610 } 2611 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2612 2613 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2614 u8 counter_index) 2615 { 2616 struct mlx4_cmd_mailbox *if_stat_mailbox; 2617 int err; 2618 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2619 2620 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2621 if (IS_ERR(if_stat_mailbox)) 2622 return PTR_ERR(if_stat_mailbox); 2623 2624 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2625 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2626 MLX4_CMD_NATIVE); 2627 2628 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2629 return err; 2630 } 2631 2632 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2633 { 2634 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2635 return; 2636 2637 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2638 return; 2639 2640 __mlx4_clear_if_stat(dev, idx); 2641 2642 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2643 return; 2644 } 2645 2646 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2647 { 2648 u64 in_param = 0; 2649 2650 if (mlx4_is_mfunc(dev)) { 2651 set_param_l(&in_param, idx); 2652 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2653 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2654 MLX4_CMD_WRAPPED); 2655 return; 2656 } 2657 __mlx4_counter_free(dev, idx); 2658 } 2659 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2660 2661 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2662 { 2663 struct mlx4_priv *priv = mlx4_priv(dev); 2664 2665 return priv->def_counter[port - 1]; 2666 } 2667 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2668 2669 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2670 { 2671 struct mlx4_priv *priv = mlx4_priv(dev); 2672 2673 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2674 } 2675 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2676 2677 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2678 { 2679 struct mlx4_priv *priv = mlx4_priv(dev); 2680 2681 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2682 } 2683 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2684 2685 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2686 { 2687 struct mlx4_priv *priv = mlx4_priv(dev); 2688 __be64 guid; 2689 2690 /* hw GUID */ 2691 if (entry == 0) 2692 return; 2693 2694 get_random_bytes((char *)&guid, sizeof(guid)); 2695 guid &= ~(cpu_to_be64(1ULL << 56)); 2696 guid |= cpu_to_be64(1ULL << 57); 2697 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2698 } 2699 2700 static int mlx4_setup_hca(struct mlx4_dev *dev) 2701 { 2702 struct mlx4_priv *priv = mlx4_priv(dev); 2703 int err; 2704 int port; 2705 __be32 ib_port_default_caps; 2706 2707 err = mlx4_init_uar_table(dev); 2708 if (err) { 2709 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2710 return err; 2711 } 2712 2713 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2714 if (err) { 2715 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2716 goto err_uar_table_free; 2717 } 2718 2719 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2720 if (!priv->kar) { 2721 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2722 err = -ENOMEM; 2723 goto err_uar_free; 2724 } 2725 2726 err = mlx4_init_pd_table(dev); 2727 if (err) { 2728 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2729 goto err_kar_unmap; 2730 } 2731 2732 err = mlx4_init_xrcd_table(dev); 2733 if (err) { 2734 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2735 goto err_pd_table_free; 2736 } 2737 2738 err = mlx4_init_mr_table(dev); 2739 if (err) { 2740 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2741 goto err_xrcd_table_free; 2742 } 2743 2744 if (!mlx4_is_slave(dev)) { 2745 err = mlx4_init_mcg_table(dev); 2746 if (err) { 2747 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2748 goto err_mr_table_free; 2749 } 2750 err = mlx4_config_mad_demux(dev); 2751 if (err) { 2752 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2753 goto err_mcg_table_free; 2754 } 2755 } 2756 2757 err = mlx4_init_eq_table(dev); 2758 if (err) { 2759 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2760 goto err_mcg_table_free; 2761 } 2762 2763 err = mlx4_cmd_use_events(dev); 2764 if (err) { 2765 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2766 goto err_eq_table_free; 2767 } 2768 2769 err = mlx4_NOP(dev); 2770 if (err) { 2771 if (dev->flags & MLX4_FLAG_MSI_X) { 2772 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2773 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2774 mlx4_warn(dev, "Trying again without MSI-X\n"); 2775 } else { 2776 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2777 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2778 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2779 } 2780 2781 goto err_cmd_poll; 2782 } 2783 2784 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2785 2786 err = mlx4_init_cq_table(dev); 2787 if (err) { 2788 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2789 goto err_cmd_poll; 2790 } 2791 2792 err = mlx4_init_srq_table(dev); 2793 if (err) { 2794 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2795 goto err_cq_table_free; 2796 } 2797 2798 err = mlx4_init_qp_table(dev); 2799 if (err) { 2800 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2801 goto err_srq_table_free; 2802 } 2803 2804 if (!mlx4_is_slave(dev)) { 2805 err = mlx4_init_counters_table(dev); 2806 if (err && err != -ENOENT) { 2807 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2808 goto err_qp_table_free; 2809 } 2810 } 2811 2812 err = mlx4_allocate_default_counters(dev); 2813 if (err) { 2814 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2815 goto err_counters_table_free; 2816 } 2817 2818 if (!mlx4_is_slave(dev)) { 2819 for (port = 1; port <= dev->caps.num_ports; port++) { 2820 ib_port_default_caps = 0; 2821 err = mlx4_get_port_ib_caps(dev, port, 2822 &ib_port_default_caps); 2823 if (err) 2824 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2825 port, err); 2826 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2827 2828 /* initialize per-slave default ib port capabilities */ 2829 if (mlx4_is_master(dev)) { 2830 int i; 2831 for (i = 0; i < dev->num_slaves; i++) { 2832 if (i == mlx4_master_func_num(dev)) 2833 continue; 2834 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2835 ib_port_default_caps; 2836 } 2837 } 2838 2839 if (mlx4_is_mfunc(dev)) 2840 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2841 else 2842 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2843 2844 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2845 dev->caps.pkey_table_len[port] : -1); 2846 if (err) { 2847 mlx4_err(dev, "Failed to set port %d, aborting\n", 2848 port); 2849 goto err_default_countes_free; 2850 } 2851 } 2852 } 2853 2854 return 0; 2855 2856 err_default_countes_free: 2857 mlx4_cleanup_default_counters(dev); 2858 2859 err_counters_table_free: 2860 if (!mlx4_is_slave(dev)) 2861 mlx4_cleanup_counters_table(dev); 2862 2863 err_qp_table_free: 2864 mlx4_cleanup_qp_table(dev); 2865 2866 err_srq_table_free: 2867 mlx4_cleanup_srq_table(dev); 2868 2869 err_cq_table_free: 2870 mlx4_cleanup_cq_table(dev); 2871 2872 err_cmd_poll: 2873 mlx4_cmd_use_polling(dev); 2874 2875 err_eq_table_free: 2876 mlx4_cleanup_eq_table(dev); 2877 2878 err_mcg_table_free: 2879 if (!mlx4_is_slave(dev)) 2880 mlx4_cleanup_mcg_table(dev); 2881 2882 err_mr_table_free: 2883 mlx4_cleanup_mr_table(dev); 2884 2885 err_xrcd_table_free: 2886 mlx4_cleanup_xrcd_table(dev); 2887 2888 err_pd_table_free: 2889 mlx4_cleanup_pd_table(dev); 2890 2891 err_kar_unmap: 2892 iounmap(priv->kar); 2893 2894 err_uar_free: 2895 mlx4_uar_free(dev, &priv->driver_uar); 2896 2897 err_uar_table_free: 2898 mlx4_cleanup_uar_table(dev); 2899 return err; 2900 } 2901 2902 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2903 { 2904 int requested_cpu = 0; 2905 struct mlx4_priv *priv = mlx4_priv(dev); 2906 struct mlx4_eq *eq; 2907 int off = 0; 2908 int i; 2909 2910 if (eqn > dev->caps.num_comp_vectors) 2911 return -EINVAL; 2912 2913 for (i = 1; i < port; i++) 2914 off += mlx4_get_eqs_per_port(dev, i); 2915 2916 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2917 2918 /* Meaning EQs are shared, and this call comes from the second port */ 2919 if (requested_cpu < 0) 2920 return 0; 2921 2922 eq = &priv->eq_table.eq[eqn]; 2923 2924 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2925 return -ENOMEM; 2926 2927 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2928 2929 return 0; 2930 } 2931 2932 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2933 { 2934 struct mlx4_priv *priv = mlx4_priv(dev); 2935 struct msix_entry *entries; 2936 int i; 2937 int port = 0; 2938 2939 if (msi_x) { 2940 int nreq = min3(dev->caps.num_ports * 2941 (int)num_online_cpus() + 1, 2942 dev->caps.num_eqs - dev->caps.reserved_eqs, 2943 MAX_MSIX); 2944 2945 if (msi_x > 1) 2946 nreq = min_t(int, nreq, msi_x); 2947 2948 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2949 if (!entries) 2950 goto no_msi; 2951 2952 for (i = 0; i < nreq; ++i) 2953 entries[i].entry = i; 2954 2955 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2956 nreq); 2957 2958 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2959 kfree(entries); 2960 goto no_msi; 2961 } 2962 /* 1 is reserved for events (asyncrounous EQ) */ 2963 dev->caps.num_comp_vectors = nreq - 1; 2964 2965 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2966 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2967 dev->caps.num_ports); 2968 2969 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2970 if (i == MLX4_EQ_ASYNC) 2971 continue; 2972 2973 priv->eq_table.eq[i].irq = 2974 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2975 2976 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2977 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2978 dev->caps.num_ports); 2979 /* We don't set affinity hint when there 2980 * aren't enough EQs 2981 */ 2982 } else { 2983 set_bit(port, 2984 priv->eq_table.eq[i].actv_ports.ports); 2985 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2986 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2987 i); 2988 } 2989 /* We divide the Eqs evenly between the two ports. 2990 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2991 * refers to the number of Eqs per port 2992 * (i.e eqs_per_port). Theoretically, we would like to 2993 * write something like (i + 1) % eqs_per_port == 0. 2994 * However, since there's an asynchronous Eq, we have 2995 * to skip over it by comparing this condition to 2996 * !!((i + 1) > MLX4_EQ_ASYNC). 2997 */ 2998 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2999 ((i + 1) % 3000 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 3001 !!((i + 1) > MLX4_EQ_ASYNC)) 3002 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 3003 * everything is shared anyway. 3004 */ 3005 port++; 3006 } 3007 3008 dev->flags |= MLX4_FLAG_MSI_X; 3009 3010 kfree(entries); 3011 return; 3012 } 3013 3014 no_msi: 3015 dev->caps.num_comp_vectors = 1; 3016 3017 BUG_ON(MLX4_EQ_ASYNC >= 2); 3018 for (i = 0; i < 2; ++i) { 3019 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3020 if (i != MLX4_EQ_ASYNC) { 3021 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3022 dev->caps.num_ports); 3023 } 3024 } 3025 } 3026 3027 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3028 { 3029 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3030 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3031 int err; 3032 3033 err = devlink_port_register(devlink, &info->devlink_port, port); 3034 if (err) 3035 return err; 3036 3037 info->dev = dev; 3038 info->port = port; 3039 if (!mlx4_is_slave(dev)) { 3040 mlx4_init_mac_table(dev, &info->mac_table); 3041 mlx4_init_vlan_table(dev, &info->vlan_table); 3042 mlx4_init_roce_gid_table(dev, &info->gid_table); 3043 info->base_qpn = mlx4_get_base_qpn(dev, port); 3044 } 3045 3046 sprintf(info->dev_name, "mlx4_port%d", port); 3047 info->port_attr.attr.name = info->dev_name; 3048 if (mlx4_is_mfunc(dev)) { 3049 info->port_attr.attr.mode = 0444; 3050 } else { 3051 info->port_attr.attr.mode = 0644; 3052 info->port_attr.store = set_port_type; 3053 } 3054 info->port_attr.show = show_port_type; 3055 sysfs_attr_init(&info->port_attr.attr); 3056 3057 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3058 if (err) { 3059 mlx4_err(dev, "Failed to create file for port %d\n", port); 3060 devlink_port_unregister(&info->devlink_port); 3061 info->port = -1; 3062 return err; 3063 } 3064 3065 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3066 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3067 if (mlx4_is_mfunc(dev)) { 3068 info->port_mtu_attr.attr.mode = 0444; 3069 } else { 3070 info->port_mtu_attr.attr.mode = 0644; 3071 info->port_mtu_attr.store = set_port_ib_mtu; 3072 } 3073 info->port_mtu_attr.show = show_port_ib_mtu; 3074 sysfs_attr_init(&info->port_mtu_attr.attr); 3075 3076 err = device_create_file(&dev->persist->pdev->dev, 3077 &info->port_mtu_attr); 3078 if (err) { 3079 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3080 device_remove_file(&info->dev->persist->pdev->dev, 3081 &info->port_attr); 3082 devlink_port_unregister(&info->devlink_port); 3083 info->port = -1; 3084 return err; 3085 } 3086 3087 return 0; 3088 } 3089 3090 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3091 { 3092 if (info->port < 0) 3093 return; 3094 3095 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3096 device_remove_file(&info->dev->persist->pdev->dev, 3097 &info->port_mtu_attr); 3098 devlink_port_unregister(&info->devlink_port); 3099 3100 #ifdef CONFIG_RFS_ACCEL 3101 free_irq_cpu_rmap(info->rmap); 3102 info->rmap = NULL; 3103 #endif 3104 } 3105 3106 static int mlx4_init_steering(struct mlx4_dev *dev) 3107 { 3108 struct mlx4_priv *priv = mlx4_priv(dev); 3109 int num_entries = dev->caps.num_ports; 3110 int i, j; 3111 3112 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3113 GFP_KERNEL); 3114 if (!priv->steer) 3115 return -ENOMEM; 3116 3117 for (i = 0; i < num_entries; i++) 3118 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3119 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3120 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3121 } 3122 return 0; 3123 } 3124 3125 static void mlx4_clear_steering(struct mlx4_dev *dev) 3126 { 3127 struct mlx4_priv *priv = mlx4_priv(dev); 3128 struct mlx4_steer_index *entry, *tmp_entry; 3129 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3130 int num_entries = dev->caps.num_ports; 3131 int i, j; 3132 3133 for (i = 0; i < num_entries; i++) { 3134 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3135 list_for_each_entry_safe(pqp, tmp_pqp, 3136 &priv->steer[i].promisc_qps[j], 3137 list) { 3138 list_del(&pqp->list); 3139 kfree(pqp); 3140 } 3141 list_for_each_entry_safe(entry, tmp_entry, 3142 &priv->steer[i].steer_entries[j], 3143 list) { 3144 list_del(&entry->list); 3145 list_for_each_entry_safe(pqp, tmp_pqp, 3146 &entry->duplicates, 3147 list) { 3148 list_del(&pqp->list); 3149 kfree(pqp); 3150 } 3151 kfree(entry); 3152 } 3153 } 3154 } 3155 kfree(priv->steer); 3156 } 3157 3158 static int extended_func_num(struct pci_dev *pdev) 3159 { 3160 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3161 } 3162 3163 #define MLX4_OWNER_BASE 0x8069c 3164 #define MLX4_OWNER_SIZE 4 3165 3166 static int mlx4_get_ownership(struct mlx4_dev *dev) 3167 { 3168 void __iomem *owner; 3169 u32 ret; 3170 3171 if (pci_channel_offline(dev->persist->pdev)) 3172 return -EIO; 3173 3174 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3175 MLX4_OWNER_BASE, 3176 MLX4_OWNER_SIZE); 3177 if (!owner) { 3178 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3179 return -ENOMEM; 3180 } 3181 3182 ret = readl(owner); 3183 iounmap(owner); 3184 return (int) !!ret; 3185 } 3186 3187 static void mlx4_free_ownership(struct mlx4_dev *dev) 3188 { 3189 void __iomem *owner; 3190 3191 if (pci_channel_offline(dev->persist->pdev)) 3192 return; 3193 3194 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3195 MLX4_OWNER_BASE, 3196 MLX4_OWNER_SIZE); 3197 if (!owner) { 3198 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3199 return; 3200 } 3201 writel(0, owner); 3202 msleep(1000); 3203 iounmap(owner); 3204 } 3205 3206 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3207 !!((flags) & MLX4_FLAG_MASTER)) 3208 3209 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3210 u8 total_vfs, int existing_vfs, int reset_flow) 3211 { 3212 u64 dev_flags = dev->flags; 3213 int err = 0; 3214 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3215 MLX4_MAX_NUM_VF); 3216 3217 if (reset_flow) { 3218 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3219 GFP_KERNEL); 3220 if (!dev->dev_vfs) 3221 goto free_mem; 3222 return dev_flags; 3223 } 3224 3225 atomic_inc(&pf_loading); 3226 if (dev->flags & MLX4_FLAG_SRIOV) { 3227 if (existing_vfs != total_vfs) { 3228 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3229 existing_vfs, total_vfs); 3230 total_vfs = existing_vfs; 3231 } 3232 } 3233 3234 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3235 if (NULL == dev->dev_vfs) { 3236 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3237 goto disable_sriov; 3238 } 3239 3240 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3241 if (total_vfs > fw_enabled_sriov_vfs) { 3242 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3243 total_vfs, fw_enabled_sriov_vfs); 3244 err = -ENOMEM; 3245 goto disable_sriov; 3246 } 3247 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3248 err = pci_enable_sriov(pdev, total_vfs); 3249 } 3250 if (err) { 3251 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3252 err); 3253 goto disable_sriov; 3254 } else { 3255 mlx4_warn(dev, "Running in master mode\n"); 3256 dev_flags |= MLX4_FLAG_SRIOV | 3257 MLX4_FLAG_MASTER; 3258 dev_flags &= ~MLX4_FLAG_SLAVE; 3259 dev->persist->num_vfs = total_vfs; 3260 } 3261 return dev_flags; 3262 3263 disable_sriov: 3264 atomic_dec(&pf_loading); 3265 free_mem: 3266 dev->persist->num_vfs = 0; 3267 kfree(dev->dev_vfs); 3268 dev->dev_vfs = NULL; 3269 return dev_flags & ~MLX4_FLAG_MASTER; 3270 } 3271 3272 enum { 3273 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3274 }; 3275 3276 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3277 int *nvfs) 3278 { 3279 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3280 /* Checking for 64 VFs as a limitation of CX2 */ 3281 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3282 requested_vfs >= 64) { 3283 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3284 requested_vfs); 3285 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3286 } 3287 return 0; 3288 } 3289 3290 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3291 { 3292 struct pci_dev *pdev = dev->persist->pdev; 3293 int err = 0; 3294 3295 mutex_lock(&dev->persist->pci_status_mutex); 3296 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3297 err = pci_enable_device(pdev); 3298 if (!err) 3299 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3300 } 3301 mutex_unlock(&dev->persist->pci_status_mutex); 3302 3303 return err; 3304 } 3305 3306 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3307 { 3308 struct pci_dev *pdev = dev->persist->pdev; 3309 3310 mutex_lock(&dev->persist->pci_status_mutex); 3311 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3312 pci_disable_device(pdev); 3313 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3314 } 3315 mutex_unlock(&dev->persist->pci_status_mutex); 3316 } 3317 3318 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3319 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3320 int reset_flow) 3321 { 3322 struct mlx4_dev *dev; 3323 unsigned sum = 0; 3324 int err; 3325 int port; 3326 int i; 3327 struct mlx4_dev_cap *dev_cap = NULL; 3328 int existing_vfs = 0; 3329 3330 dev = &priv->dev; 3331 3332 INIT_LIST_HEAD(&priv->ctx_list); 3333 spin_lock_init(&priv->ctx_lock); 3334 3335 mutex_init(&priv->port_mutex); 3336 mutex_init(&priv->bond_mutex); 3337 3338 INIT_LIST_HEAD(&priv->pgdir_list); 3339 mutex_init(&priv->pgdir_mutex); 3340 spin_lock_init(&priv->cmd.context_lock); 3341 3342 INIT_LIST_HEAD(&priv->bf_list); 3343 mutex_init(&priv->bf_mutex); 3344 3345 dev->rev_id = pdev->revision; 3346 dev->numa_node = dev_to_node(&pdev->dev); 3347 3348 /* Detect if this device is a virtual function */ 3349 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3350 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3351 dev->flags |= MLX4_FLAG_SLAVE; 3352 } else { 3353 /* We reset the device and enable SRIOV only for physical 3354 * devices. Try to claim ownership on the device; 3355 * if already taken, skip -- do not allow multiple PFs */ 3356 err = mlx4_get_ownership(dev); 3357 if (err) { 3358 if (err < 0) 3359 return err; 3360 else { 3361 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3362 return -EINVAL; 3363 } 3364 } 3365 3366 atomic_set(&priv->opreq_count, 0); 3367 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3368 3369 /* 3370 * Now reset the HCA before we touch the PCI capabilities or 3371 * attempt a firmware command, since a boot ROM may have left 3372 * the HCA in an undefined state. 3373 */ 3374 err = mlx4_reset(dev); 3375 if (err) { 3376 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3377 goto err_sriov; 3378 } 3379 3380 if (total_vfs) { 3381 dev->flags = MLX4_FLAG_MASTER; 3382 existing_vfs = pci_num_vf(pdev); 3383 if (existing_vfs) 3384 dev->flags |= MLX4_FLAG_SRIOV; 3385 dev->persist->num_vfs = total_vfs; 3386 } 3387 } 3388 3389 /* on load remove any previous indication of internal error, 3390 * device is up. 3391 */ 3392 dev->persist->state = MLX4_DEVICE_STATE_UP; 3393 3394 slave_start: 3395 err = mlx4_cmd_init(dev); 3396 if (err) { 3397 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3398 goto err_sriov; 3399 } 3400 3401 /* In slave functions, the communication channel must be initialized 3402 * before posting commands. Also, init num_slaves before calling 3403 * mlx4_init_hca */ 3404 if (mlx4_is_mfunc(dev)) { 3405 if (mlx4_is_master(dev)) { 3406 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3407 3408 } else { 3409 dev->num_slaves = 0; 3410 err = mlx4_multi_func_init(dev); 3411 if (err) { 3412 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3413 goto err_cmd; 3414 } 3415 } 3416 } 3417 3418 err = mlx4_init_fw(dev); 3419 if (err) { 3420 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3421 goto err_mfunc; 3422 } 3423 3424 if (mlx4_is_master(dev)) { 3425 /* when we hit the goto slave_start below, dev_cap already initialized */ 3426 if (!dev_cap) { 3427 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3428 3429 if (!dev_cap) { 3430 err = -ENOMEM; 3431 goto err_fw; 3432 } 3433 3434 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3435 if (err) { 3436 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3437 goto err_fw; 3438 } 3439 3440 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3441 goto err_fw; 3442 3443 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3444 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3445 total_vfs, 3446 existing_vfs, 3447 reset_flow); 3448 3449 mlx4_close_fw(dev); 3450 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3451 dev->flags = dev_flags; 3452 if (!SRIOV_VALID_STATE(dev->flags)) { 3453 mlx4_err(dev, "Invalid SRIOV state\n"); 3454 goto err_sriov; 3455 } 3456 err = mlx4_reset(dev); 3457 if (err) { 3458 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3459 goto err_sriov; 3460 } 3461 goto slave_start; 3462 } 3463 } else { 3464 /* Legacy mode FW requires SRIOV to be enabled before 3465 * doing QUERY_DEV_CAP, since max_eq's value is different if 3466 * SRIOV is enabled. 3467 */ 3468 memset(dev_cap, 0, sizeof(*dev_cap)); 3469 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3470 if (err) { 3471 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3472 goto err_fw; 3473 } 3474 3475 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3476 goto err_fw; 3477 } 3478 } 3479 3480 err = mlx4_init_hca(dev); 3481 if (err) { 3482 if (err == -EACCES) { 3483 /* Not primary Physical function 3484 * Running in slave mode */ 3485 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3486 /* We're not a PF */ 3487 if (dev->flags & MLX4_FLAG_SRIOV) { 3488 if (!existing_vfs) 3489 pci_disable_sriov(pdev); 3490 if (mlx4_is_master(dev) && !reset_flow) 3491 atomic_dec(&pf_loading); 3492 dev->flags &= ~MLX4_FLAG_SRIOV; 3493 } 3494 if (!mlx4_is_slave(dev)) 3495 mlx4_free_ownership(dev); 3496 dev->flags |= MLX4_FLAG_SLAVE; 3497 dev->flags &= ~MLX4_FLAG_MASTER; 3498 goto slave_start; 3499 } else 3500 goto err_fw; 3501 } 3502 3503 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3504 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3505 existing_vfs, reset_flow); 3506 3507 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3508 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3509 dev->flags = dev_flags; 3510 err = mlx4_cmd_init(dev); 3511 if (err) { 3512 /* Only VHCR is cleaned up, so could still 3513 * send FW commands 3514 */ 3515 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3516 goto err_close; 3517 } 3518 } else { 3519 dev->flags = dev_flags; 3520 } 3521 3522 if (!SRIOV_VALID_STATE(dev->flags)) { 3523 mlx4_err(dev, "Invalid SRIOV state\n"); 3524 goto err_close; 3525 } 3526 } 3527 3528 /* check if the device is functioning at its maximum possible speed. 3529 * No return code for this call, just warn the user in case of PCI 3530 * express device capabilities are under-satisfied by the bus. 3531 */ 3532 if (!mlx4_is_slave(dev)) 3533 pcie_print_link_status(dev->persist->pdev); 3534 3535 /* In master functions, the communication channel must be initialized 3536 * after obtaining its address from fw */ 3537 if (mlx4_is_master(dev)) { 3538 if (dev->caps.num_ports < 2 && 3539 num_vfs_argc > 1) { 3540 err = -EINVAL; 3541 mlx4_err(dev, 3542 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3543 dev->caps.num_ports); 3544 goto err_close; 3545 } 3546 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3547 3548 for (i = 0; 3549 i < sizeof(dev->persist->nvfs)/ 3550 sizeof(dev->persist->nvfs[0]); i++) { 3551 unsigned j; 3552 3553 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3554 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3555 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3556 dev->caps.num_ports; 3557 } 3558 } 3559 3560 /* In master functions, the communication channel 3561 * must be initialized after obtaining its address from fw 3562 */ 3563 err = mlx4_multi_func_init(dev); 3564 if (err) { 3565 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3566 goto err_close; 3567 } 3568 } 3569 3570 err = mlx4_alloc_eq_table(dev); 3571 if (err) 3572 goto err_master_mfunc; 3573 3574 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3575 mutex_init(&priv->msix_ctl.pool_lock); 3576 3577 mlx4_enable_msi_x(dev); 3578 if ((mlx4_is_mfunc(dev)) && 3579 !(dev->flags & MLX4_FLAG_MSI_X)) { 3580 err = -EOPNOTSUPP; 3581 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3582 goto err_free_eq; 3583 } 3584 3585 if (!mlx4_is_slave(dev)) { 3586 err = mlx4_init_steering(dev); 3587 if (err) 3588 goto err_disable_msix; 3589 } 3590 3591 mlx4_init_quotas(dev); 3592 3593 err = mlx4_setup_hca(dev); 3594 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3595 !mlx4_is_mfunc(dev)) { 3596 dev->flags &= ~MLX4_FLAG_MSI_X; 3597 dev->caps.num_comp_vectors = 1; 3598 pci_disable_msix(pdev); 3599 err = mlx4_setup_hca(dev); 3600 } 3601 3602 if (err) 3603 goto err_steer; 3604 3605 /* When PF resources are ready arm its comm channel to enable 3606 * getting commands 3607 */ 3608 if (mlx4_is_master(dev)) { 3609 err = mlx4_ARM_COMM_CHANNEL(dev); 3610 if (err) { 3611 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3612 err); 3613 goto err_steer; 3614 } 3615 } 3616 3617 for (port = 1; port <= dev->caps.num_ports; port++) { 3618 err = mlx4_init_port_info(dev, port); 3619 if (err) 3620 goto err_port; 3621 } 3622 3623 priv->v2p.port1 = 1; 3624 priv->v2p.port2 = 2; 3625 3626 err = mlx4_register_device(dev); 3627 if (err) 3628 goto err_port; 3629 3630 mlx4_request_modules(dev); 3631 3632 mlx4_sense_init(dev); 3633 mlx4_start_sense(dev); 3634 3635 priv->removed = 0; 3636 3637 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3638 atomic_dec(&pf_loading); 3639 3640 kfree(dev_cap); 3641 return 0; 3642 3643 err_port: 3644 for (--port; port >= 1; --port) 3645 mlx4_cleanup_port_info(&priv->port[port]); 3646 3647 mlx4_cleanup_default_counters(dev); 3648 if (!mlx4_is_slave(dev)) 3649 mlx4_cleanup_counters_table(dev); 3650 mlx4_cleanup_qp_table(dev); 3651 mlx4_cleanup_srq_table(dev); 3652 mlx4_cleanup_cq_table(dev); 3653 mlx4_cmd_use_polling(dev); 3654 mlx4_cleanup_eq_table(dev); 3655 mlx4_cleanup_mcg_table(dev); 3656 mlx4_cleanup_mr_table(dev); 3657 mlx4_cleanup_xrcd_table(dev); 3658 mlx4_cleanup_pd_table(dev); 3659 mlx4_cleanup_uar_table(dev); 3660 3661 err_steer: 3662 if (!mlx4_is_slave(dev)) 3663 mlx4_clear_steering(dev); 3664 3665 err_disable_msix: 3666 if (dev->flags & MLX4_FLAG_MSI_X) 3667 pci_disable_msix(pdev); 3668 3669 err_free_eq: 3670 mlx4_free_eq_table(dev); 3671 3672 err_master_mfunc: 3673 if (mlx4_is_master(dev)) { 3674 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3675 mlx4_multi_func_cleanup(dev); 3676 } 3677 3678 if (mlx4_is_slave(dev)) 3679 mlx4_slave_destroy_special_qp_cap(dev); 3680 3681 err_close: 3682 mlx4_close_hca(dev); 3683 3684 err_fw: 3685 mlx4_close_fw(dev); 3686 3687 err_mfunc: 3688 if (mlx4_is_slave(dev)) 3689 mlx4_multi_func_cleanup(dev); 3690 3691 err_cmd: 3692 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3693 3694 err_sriov: 3695 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3696 pci_disable_sriov(pdev); 3697 dev->flags &= ~MLX4_FLAG_SRIOV; 3698 } 3699 3700 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3701 atomic_dec(&pf_loading); 3702 3703 kfree(priv->dev.dev_vfs); 3704 3705 if (!mlx4_is_slave(dev)) 3706 mlx4_free_ownership(dev); 3707 3708 kfree(dev_cap); 3709 return err; 3710 } 3711 3712 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3713 struct mlx4_priv *priv) 3714 { 3715 int err; 3716 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3717 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3718 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3719 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3720 unsigned total_vfs = 0; 3721 unsigned int i; 3722 3723 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3724 3725 err = mlx4_pci_enable_device(&priv->dev); 3726 if (err) { 3727 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3728 return err; 3729 } 3730 3731 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3732 * per port, we must limit the number of VFs to 63 (since their are 3733 * 128 MACs) 3734 */ 3735 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3736 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3737 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3738 if (nvfs[i] < 0) { 3739 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3740 err = -EINVAL; 3741 goto err_disable_pdev; 3742 } 3743 } 3744 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3745 i++) { 3746 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3747 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3748 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3749 err = -EINVAL; 3750 goto err_disable_pdev; 3751 } 3752 } 3753 if (total_vfs > MLX4_MAX_NUM_VF) { 3754 dev_err(&pdev->dev, 3755 "Requested more VF's (%d) than allowed by hw (%d)\n", 3756 total_vfs, MLX4_MAX_NUM_VF); 3757 err = -EINVAL; 3758 goto err_disable_pdev; 3759 } 3760 3761 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3762 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3763 dev_err(&pdev->dev, 3764 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3765 nvfs[i] + nvfs[2], i + 1, 3766 MLX4_MAX_NUM_VF_P_PORT); 3767 err = -EINVAL; 3768 goto err_disable_pdev; 3769 } 3770 } 3771 3772 /* Check for BARs. */ 3773 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3774 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3775 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3776 pci_dev_data, pci_resource_flags(pdev, 0)); 3777 err = -ENODEV; 3778 goto err_disable_pdev; 3779 } 3780 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3781 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3782 err = -ENODEV; 3783 goto err_disable_pdev; 3784 } 3785 3786 err = pci_request_regions(pdev, DRV_NAME); 3787 if (err) { 3788 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3789 goto err_disable_pdev; 3790 } 3791 3792 pci_set_master(pdev); 3793 3794 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3795 if (err) { 3796 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3797 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3798 if (err) { 3799 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3800 goto err_release_regions; 3801 } 3802 } 3803 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3804 if (err) { 3805 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3806 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3807 if (err) { 3808 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3809 goto err_release_regions; 3810 } 3811 } 3812 3813 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3814 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3815 /* Detect if this device is a virtual function */ 3816 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3817 /* When acting as pf, we normally skip vfs unless explicitly 3818 * requested to probe them. 3819 */ 3820 if (total_vfs) { 3821 unsigned vfs_offset = 0; 3822 3823 for (i = 0; i < ARRAY_SIZE(nvfs) && 3824 vfs_offset + nvfs[i] < extended_func_num(pdev); 3825 vfs_offset += nvfs[i], i++) 3826 ; 3827 if (i == ARRAY_SIZE(nvfs)) { 3828 err = -ENODEV; 3829 goto err_release_regions; 3830 } 3831 if ((extended_func_num(pdev) - vfs_offset) 3832 > prb_vf[i]) { 3833 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3834 extended_func_num(pdev)); 3835 err = -ENODEV; 3836 goto err_release_regions; 3837 } 3838 } 3839 } 3840 3841 err = mlx4_crdump_init(&priv->dev); 3842 if (err) 3843 goto err_release_regions; 3844 3845 err = mlx4_catas_init(&priv->dev); 3846 if (err) 3847 goto err_crdump; 3848 3849 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3850 if (err) 3851 goto err_catas; 3852 3853 return 0; 3854 3855 err_catas: 3856 mlx4_catas_end(&priv->dev); 3857 3858 err_crdump: 3859 mlx4_crdump_end(&priv->dev); 3860 3861 err_release_regions: 3862 pci_release_regions(pdev); 3863 3864 err_disable_pdev: 3865 mlx4_pci_disable_device(&priv->dev); 3866 return err; 3867 } 3868 3869 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3870 enum devlink_port_type port_type) 3871 { 3872 struct mlx4_port_info *info = container_of(devlink_port, 3873 struct mlx4_port_info, 3874 devlink_port); 3875 enum mlx4_port_type mlx4_port_type; 3876 3877 switch (port_type) { 3878 case DEVLINK_PORT_TYPE_AUTO: 3879 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3880 break; 3881 case DEVLINK_PORT_TYPE_ETH: 3882 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3883 break; 3884 case DEVLINK_PORT_TYPE_IB: 3885 mlx4_port_type = MLX4_PORT_TYPE_IB; 3886 break; 3887 default: 3888 return -EOPNOTSUPP; 3889 } 3890 3891 return __set_port_type(info, mlx4_port_type); 3892 } 3893 3894 static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3895 { 3896 struct mlx4_priv *priv = devlink_priv(devlink); 3897 struct mlx4_dev *dev = &priv->dev; 3898 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3899 union devlink_param_value saved_value; 3900 int err; 3901 3902 err = devlink_param_driverinit_value_get(devlink, 3903 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3904 &saved_value); 3905 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3906 mlx4_internal_err_reset = saved_value.vbool; 3907 /* Notify on value changed on runtime configuration mode */ 3908 devlink_param_value_changed(devlink, 3909 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3910 } 3911 err = devlink_param_driverinit_value_get(devlink, 3912 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3913 &saved_value); 3914 if (!err) 3915 log_num_mac = order_base_2(saved_value.vu32); 3916 err = devlink_param_driverinit_value_get(devlink, 3917 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3918 &saved_value); 3919 if (!err) 3920 enable_64b_cqe_eqe = saved_value.vbool; 3921 err = devlink_param_driverinit_value_get(devlink, 3922 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3923 &saved_value); 3924 if (!err) 3925 enable_4k_uar = saved_value.vbool; 3926 err = devlink_param_driverinit_value_get(devlink, 3927 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3928 &saved_value); 3929 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3930 crdump->snapshot_enable = saved_value.vbool; 3931 devlink_param_value_changed(devlink, 3932 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3933 } 3934 } 3935 3936 static int mlx4_devlink_reload(struct devlink *devlink, 3937 struct netlink_ext_ack *extack) 3938 { 3939 struct mlx4_priv *priv = devlink_priv(devlink); 3940 struct mlx4_dev *dev = &priv->dev; 3941 struct mlx4_dev_persistent *persist = dev->persist; 3942 int err; 3943 3944 if (persist->num_vfs) 3945 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 3946 err = mlx4_restart_one(persist->pdev, true, devlink); 3947 if (err) 3948 mlx4_err(persist->dev, "mlx4_restart_one failed, ret=%d\n", err); 3949 3950 return err; 3951 } 3952 3953 static const struct devlink_ops mlx4_devlink_ops = { 3954 .port_type_set = mlx4_devlink_port_type_set, 3955 .reload = mlx4_devlink_reload, 3956 }; 3957 3958 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3959 { 3960 struct devlink *devlink; 3961 struct mlx4_priv *priv; 3962 struct mlx4_dev *dev; 3963 int ret; 3964 3965 printk_once(KERN_INFO "%s", mlx4_version); 3966 3967 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3968 if (!devlink) 3969 return -ENOMEM; 3970 priv = devlink_priv(devlink); 3971 3972 dev = &priv->dev; 3973 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3974 if (!dev->persist) { 3975 ret = -ENOMEM; 3976 goto err_devlink_free; 3977 } 3978 dev->persist->pdev = pdev; 3979 dev->persist->dev = dev; 3980 pci_set_drvdata(pdev, dev->persist); 3981 priv->pci_dev_data = id->driver_data; 3982 mutex_init(&dev->persist->device_state_mutex); 3983 mutex_init(&dev->persist->interface_state_mutex); 3984 mutex_init(&dev->persist->pci_status_mutex); 3985 3986 ret = devlink_register(devlink, &pdev->dev); 3987 if (ret) 3988 goto err_persist_free; 3989 ret = devlink_params_register(devlink, mlx4_devlink_params, 3990 ARRAY_SIZE(mlx4_devlink_params)); 3991 if (ret) 3992 goto err_devlink_unregister; 3993 mlx4_devlink_set_params_init_values(devlink); 3994 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3995 if (ret) 3996 goto err_params_unregister; 3997 3998 pci_save_state(pdev); 3999 return 0; 4000 4001 err_params_unregister: 4002 devlink_params_unregister(devlink, mlx4_devlink_params, 4003 ARRAY_SIZE(mlx4_devlink_params)); 4004 err_devlink_unregister: 4005 devlink_unregister(devlink); 4006 err_persist_free: 4007 kfree(dev->persist); 4008 err_devlink_free: 4009 devlink_free(devlink); 4010 return ret; 4011 } 4012 4013 static void mlx4_clean_dev(struct mlx4_dev *dev) 4014 { 4015 struct mlx4_dev_persistent *persist = dev->persist; 4016 struct mlx4_priv *priv = mlx4_priv(dev); 4017 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4018 4019 memset(priv, 0, sizeof(*priv)); 4020 priv->dev.persist = persist; 4021 priv->dev.flags = flags; 4022 } 4023 4024 static void mlx4_unload_one(struct pci_dev *pdev) 4025 { 4026 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4027 struct mlx4_dev *dev = persist->dev; 4028 struct mlx4_priv *priv = mlx4_priv(dev); 4029 int pci_dev_data; 4030 int p, i; 4031 4032 if (priv->removed) 4033 return; 4034 4035 /* saving current ports type for further use */ 4036 for (i = 0; i < dev->caps.num_ports; i++) { 4037 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4038 dev->persist->curr_port_poss_type[i] = dev->caps. 4039 possible_type[i + 1]; 4040 } 4041 4042 pci_dev_data = priv->pci_dev_data; 4043 4044 mlx4_stop_sense(dev); 4045 mlx4_unregister_device(dev); 4046 4047 for (p = 1; p <= dev->caps.num_ports; p++) { 4048 mlx4_cleanup_port_info(&priv->port[p]); 4049 mlx4_CLOSE_PORT(dev, p); 4050 } 4051 4052 if (mlx4_is_master(dev)) 4053 mlx4_free_resource_tracker(dev, 4054 RES_TR_FREE_SLAVES_ONLY); 4055 4056 mlx4_cleanup_default_counters(dev); 4057 if (!mlx4_is_slave(dev)) 4058 mlx4_cleanup_counters_table(dev); 4059 mlx4_cleanup_qp_table(dev); 4060 mlx4_cleanup_srq_table(dev); 4061 mlx4_cleanup_cq_table(dev); 4062 mlx4_cmd_use_polling(dev); 4063 mlx4_cleanup_eq_table(dev); 4064 mlx4_cleanup_mcg_table(dev); 4065 mlx4_cleanup_mr_table(dev); 4066 mlx4_cleanup_xrcd_table(dev); 4067 mlx4_cleanup_pd_table(dev); 4068 4069 if (mlx4_is_master(dev)) 4070 mlx4_free_resource_tracker(dev, 4071 RES_TR_FREE_STRUCTS_ONLY); 4072 4073 iounmap(priv->kar); 4074 mlx4_uar_free(dev, &priv->driver_uar); 4075 mlx4_cleanup_uar_table(dev); 4076 if (!mlx4_is_slave(dev)) 4077 mlx4_clear_steering(dev); 4078 mlx4_free_eq_table(dev); 4079 if (mlx4_is_master(dev)) 4080 mlx4_multi_func_cleanup(dev); 4081 mlx4_close_hca(dev); 4082 mlx4_close_fw(dev); 4083 if (mlx4_is_slave(dev)) 4084 mlx4_multi_func_cleanup(dev); 4085 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4086 4087 if (dev->flags & MLX4_FLAG_MSI_X) 4088 pci_disable_msix(pdev); 4089 4090 if (!mlx4_is_slave(dev)) 4091 mlx4_free_ownership(dev); 4092 4093 mlx4_slave_destroy_special_qp_cap(dev); 4094 kfree(dev->dev_vfs); 4095 4096 mlx4_clean_dev(dev); 4097 priv->pci_dev_data = pci_dev_data; 4098 priv->removed = 1; 4099 } 4100 4101 static void mlx4_remove_one(struct pci_dev *pdev) 4102 { 4103 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4104 struct mlx4_dev *dev = persist->dev; 4105 struct mlx4_priv *priv = mlx4_priv(dev); 4106 struct devlink *devlink = priv_to_devlink(priv); 4107 int active_vfs = 0; 4108 4109 if (mlx4_is_slave(dev)) 4110 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4111 4112 mutex_lock(&persist->interface_state_mutex); 4113 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4114 mutex_unlock(&persist->interface_state_mutex); 4115 4116 /* Disabling SR-IOV is not allowed while there are active vf's */ 4117 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4118 active_vfs = mlx4_how_many_lives_vf(dev); 4119 if (active_vfs) { 4120 pr_warn("Removing PF when there are active VF's !!\n"); 4121 pr_warn("Will not disable SR-IOV.\n"); 4122 } 4123 } 4124 4125 /* device marked to be under deletion running now without the lock 4126 * letting other tasks to be terminated 4127 */ 4128 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4129 mlx4_unload_one(pdev); 4130 else 4131 mlx4_info(dev, "%s: interface is down\n", __func__); 4132 mlx4_catas_end(dev); 4133 mlx4_crdump_end(dev); 4134 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4135 mlx4_warn(dev, "Disabling SR-IOV\n"); 4136 pci_disable_sriov(pdev); 4137 } 4138 4139 pci_release_regions(pdev); 4140 mlx4_pci_disable_device(dev); 4141 devlink_params_unregister(devlink, mlx4_devlink_params, 4142 ARRAY_SIZE(mlx4_devlink_params)); 4143 devlink_unregister(devlink); 4144 kfree(dev->persist); 4145 devlink_free(devlink); 4146 } 4147 4148 static int restore_current_port_types(struct mlx4_dev *dev, 4149 enum mlx4_port_type *types, 4150 enum mlx4_port_type *poss_types) 4151 { 4152 struct mlx4_priv *priv = mlx4_priv(dev); 4153 int err, i; 4154 4155 mlx4_stop_sense(dev); 4156 4157 mutex_lock(&priv->port_mutex); 4158 for (i = 0; i < dev->caps.num_ports; i++) 4159 dev->caps.possible_type[i + 1] = poss_types[i]; 4160 err = mlx4_change_port_types(dev, types); 4161 mlx4_start_sense(dev); 4162 mutex_unlock(&priv->port_mutex); 4163 4164 return err; 4165 } 4166 4167 int mlx4_restart_one(struct pci_dev *pdev, bool reload, struct devlink *devlink) 4168 { 4169 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4170 struct mlx4_dev *dev = persist->dev; 4171 struct mlx4_priv *priv = mlx4_priv(dev); 4172 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4173 int pci_dev_data, err, total_vfs; 4174 4175 pci_dev_data = priv->pci_dev_data; 4176 total_vfs = dev->persist->num_vfs; 4177 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4178 4179 mlx4_unload_one(pdev); 4180 if (reload) 4181 mlx4_devlink_param_load_driverinit_values(devlink); 4182 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4183 if (err) { 4184 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4185 __func__, pci_name(pdev), err); 4186 return err; 4187 } 4188 4189 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4190 dev->persist->curr_port_poss_type); 4191 if (err) 4192 mlx4_err(dev, "could not restore original port types (%d)\n", 4193 err); 4194 4195 return err; 4196 } 4197 4198 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4199 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4200 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4201 4202 static const struct pci_device_id mlx4_pci_table[] = { 4203 #ifdef CONFIG_MLX4_CORE_GEN2 4204 /* MT25408 "Hermon" */ 4205 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4206 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4207 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4208 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4209 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4210 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4211 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4212 /* MT25458 ConnectX EN 10GBASE-T */ 4213 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4214 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4215 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4216 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4217 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4218 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4219 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4220 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4221 /* MT25400 Family [ConnectX-2] */ 4222 MLX_VF(0x1002), /* Virtual Function */ 4223 #endif /* CONFIG_MLX4_CORE_GEN2 */ 4224 /* MT27500 Family [ConnectX-3] */ 4225 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4226 MLX_VF(0x1004), /* Virtual Function */ 4227 MLX_GN(0x1005), /* MT27510 Family */ 4228 MLX_GN(0x1006), /* MT27511 Family */ 4229 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4230 MLX_GN(0x1008), /* MT27521 Family */ 4231 MLX_GN(0x1009), /* MT27530 Family */ 4232 MLX_GN(0x100a), /* MT27531 Family */ 4233 MLX_GN(0x100b), /* MT27540 Family */ 4234 MLX_GN(0x100c), /* MT27541 Family */ 4235 MLX_GN(0x100d), /* MT27550 Family */ 4236 MLX_GN(0x100e), /* MT27551 Family */ 4237 MLX_GN(0x100f), /* MT27560 Family */ 4238 MLX_GN(0x1010), /* MT27561 Family */ 4239 4240 /* 4241 * See the mellanox_check_broken_intx_masking() quirk when 4242 * adding devices 4243 */ 4244 4245 { 0, } 4246 }; 4247 4248 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4249 4250 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4251 pci_channel_state_t state) 4252 { 4253 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4254 4255 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4256 mlx4_enter_error_state(persist); 4257 4258 mutex_lock(&persist->interface_state_mutex); 4259 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4260 mlx4_unload_one(pdev); 4261 4262 mutex_unlock(&persist->interface_state_mutex); 4263 if (state == pci_channel_io_perm_failure) 4264 return PCI_ERS_RESULT_DISCONNECT; 4265 4266 mlx4_pci_disable_device(persist->dev); 4267 return PCI_ERS_RESULT_NEED_RESET; 4268 } 4269 4270 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4271 { 4272 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4273 struct mlx4_dev *dev = persist->dev; 4274 int err; 4275 4276 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4277 err = mlx4_pci_enable_device(dev); 4278 if (err) { 4279 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4280 return PCI_ERS_RESULT_DISCONNECT; 4281 } 4282 4283 pci_set_master(pdev); 4284 pci_restore_state(pdev); 4285 pci_save_state(pdev); 4286 return PCI_ERS_RESULT_RECOVERED; 4287 } 4288 4289 static void mlx4_pci_resume(struct pci_dev *pdev) 4290 { 4291 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4292 struct mlx4_dev *dev = persist->dev; 4293 struct mlx4_priv *priv = mlx4_priv(dev); 4294 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4295 int total_vfs; 4296 int err; 4297 4298 mlx4_err(dev, "%s was called\n", __func__); 4299 total_vfs = dev->persist->num_vfs; 4300 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4301 4302 mutex_lock(&persist->interface_state_mutex); 4303 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4304 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4305 priv, 1); 4306 if (err) { 4307 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4308 __func__, err); 4309 goto end; 4310 } 4311 4312 err = restore_current_port_types(dev, dev->persist-> 4313 curr_port_type, dev->persist-> 4314 curr_port_poss_type); 4315 if (err) 4316 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4317 } 4318 end: 4319 mutex_unlock(&persist->interface_state_mutex); 4320 4321 } 4322 4323 static void mlx4_shutdown(struct pci_dev *pdev) 4324 { 4325 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4326 4327 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4328 mutex_lock(&persist->interface_state_mutex); 4329 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4330 mlx4_unload_one(pdev); 4331 mutex_unlock(&persist->interface_state_mutex); 4332 } 4333 4334 static const struct pci_error_handlers mlx4_err_handler = { 4335 .error_detected = mlx4_pci_err_detected, 4336 .slot_reset = mlx4_pci_slot_reset, 4337 .resume = mlx4_pci_resume, 4338 }; 4339 4340 static int mlx4_suspend(struct pci_dev *pdev, pm_message_t state) 4341 { 4342 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4343 struct mlx4_dev *dev = persist->dev; 4344 4345 mlx4_err(dev, "suspend was called\n"); 4346 mutex_lock(&persist->interface_state_mutex); 4347 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4348 mlx4_unload_one(pdev); 4349 mutex_unlock(&persist->interface_state_mutex); 4350 4351 return 0; 4352 } 4353 4354 static int mlx4_resume(struct pci_dev *pdev) 4355 { 4356 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4357 struct mlx4_dev *dev = persist->dev; 4358 struct mlx4_priv *priv = mlx4_priv(dev); 4359 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4360 int total_vfs; 4361 int ret = 0; 4362 4363 mlx4_err(dev, "resume was called\n"); 4364 total_vfs = dev->persist->num_vfs; 4365 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4366 4367 mutex_lock(&persist->interface_state_mutex); 4368 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4369 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4370 nvfs, priv, 1); 4371 if (!ret) { 4372 ret = restore_current_port_types(dev, 4373 dev->persist->curr_port_type, 4374 dev->persist->curr_port_poss_type); 4375 if (ret) 4376 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4377 } 4378 } 4379 mutex_unlock(&persist->interface_state_mutex); 4380 4381 return ret; 4382 } 4383 4384 static struct pci_driver mlx4_driver = { 4385 .name = DRV_NAME, 4386 .id_table = mlx4_pci_table, 4387 .probe = mlx4_init_one, 4388 .shutdown = mlx4_shutdown, 4389 .remove = mlx4_remove_one, 4390 .suspend = mlx4_suspend, 4391 .resume = mlx4_resume, 4392 .err_handler = &mlx4_err_handler, 4393 }; 4394 4395 static int __init mlx4_verify_params(void) 4396 { 4397 if (msi_x < 0) { 4398 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4399 return -1; 4400 } 4401 4402 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4403 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4404 return -1; 4405 } 4406 4407 if (log_num_vlan != 0) 4408 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4409 MLX4_LOG_NUM_VLANS); 4410 4411 if (use_prio != 0) 4412 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4413 4414 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 4415 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4416 log_mtts_per_seg); 4417 return -1; 4418 } 4419 4420 /* Check if module param for ports type has legal combination */ 4421 if (port_type_array[0] == false && port_type_array[1] == true) { 4422 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4423 port_type_array[0] = true; 4424 } 4425 4426 if (mlx4_log_num_mgm_entry_size < -7 || 4427 (mlx4_log_num_mgm_entry_size > 0 && 4428 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4429 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4430 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4431 mlx4_log_num_mgm_entry_size, 4432 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4433 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4434 return -1; 4435 } 4436 4437 return 0; 4438 } 4439 4440 static int __init mlx4_init(void) 4441 { 4442 int ret; 4443 4444 if (mlx4_verify_params()) 4445 return -EINVAL; 4446 4447 4448 mlx4_wq = create_singlethread_workqueue("mlx4"); 4449 if (!mlx4_wq) 4450 return -ENOMEM; 4451 4452 ret = pci_register_driver(&mlx4_driver); 4453 if (ret < 0) 4454 destroy_workqueue(mlx4_wq); 4455 return ret < 0 ? ret : 0; 4456 } 4457 4458 static void __exit mlx4_cleanup(void) 4459 { 4460 pci_unregister_driver(&mlx4_driver); 4461 destroy_workqueue(mlx4_wq); 4462 } 4463 4464 module_init(mlx4_init); 4465 module_exit(mlx4_cleanup); 4466