1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 #include <linux/etherdevice.h> 46 #include <net/devlink.h> 47 48 #include <linux/mlx4/device.h> 49 #include <linux/mlx4/doorbell.h> 50 51 #include "mlx4.h" 52 #include "fw.h" 53 #include "icm.h" 54 55 MODULE_AUTHOR("Roland Dreier"); 56 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 57 MODULE_LICENSE("Dual BSD/GPL"); 58 MODULE_VERSION(DRV_VERSION); 59 60 struct workqueue_struct *mlx4_wq; 61 62 #ifdef CONFIG_MLX4_DEBUG 63 64 int mlx4_debug_level = 0; 65 module_param_named(debug_level, mlx4_debug_level, int, 0644); 66 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 67 68 #endif /* CONFIG_MLX4_DEBUG */ 69 70 #ifdef CONFIG_PCI_MSI 71 72 static int msi_x = 1; 73 module_param(msi_x, int, 0444); 74 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 75 76 #else /* CONFIG_PCI_MSI */ 77 78 #define msi_x (0) 79 80 #endif /* CONFIG_PCI_MSI */ 81 82 static uint8_t num_vfs[3] = {0, 0, 0}; 83 static int num_vfs_argc; 84 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 85 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 86 "num_vfs=port1,port2,port1+2"); 87 88 static uint8_t probe_vf[3] = {0, 0, 0}; 89 static int probe_vfs_argc; 90 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 91 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 92 "probe_vf=port1,port2,port1+2"); 93 94 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 95 module_param_named(log_num_mgm_entry_size, 96 mlx4_log_num_mgm_entry_size, int, 0444); 97 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 98 " of qp per mcg, for example:" 99 " 10 gives 248.range: 7 <=" 100 " log_num_mgm_entry_size <= 12." 101 " To activate device managed" 102 " flow steering when available, set to -1"); 103 104 static bool enable_64b_cqe_eqe = true; 105 module_param(enable_64b_cqe_eqe, bool, 0444); 106 MODULE_PARM_DESC(enable_64b_cqe_eqe, 107 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 108 109 static bool enable_4k_uar; 110 module_param(enable_4k_uar, bool, 0444); 111 MODULE_PARM_DESC(enable_4k_uar, 112 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 113 114 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 115 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 116 MLX4_FUNC_CAP_DMFS_A0_STATIC) 117 118 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 119 120 static char mlx4_version[] = 121 DRV_NAME ": Mellanox ConnectX core driver v" 122 DRV_VERSION "\n"; 123 124 static const struct mlx4_profile default_profile = { 125 .num_qp = 1 << 18, 126 .num_srq = 1 << 16, 127 .rdmarc_per_qp = 1 << 4, 128 .num_cq = 1 << 16, 129 .num_mcg = 1 << 13, 130 .num_mpt = 1 << 19, 131 .num_mtt = 1 << 20, /* It is really num mtt segements */ 132 }; 133 134 static const struct mlx4_profile low_mem_profile = { 135 .num_qp = 1 << 17, 136 .num_srq = 1 << 6, 137 .rdmarc_per_qp = 1 << 4, 138 .num_cq = 1 << 8, 139 .num_mcg = 1 << 8, 140 .num_mpt = 1 << 9, 141 .num_mtt = 1 << 7, 142 }; 143 144 static int log_num_mac = 7; 145 module_param_named(log_num_mac, log_num_mac, int, 0444); 146 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 147 148 static int log_num_vlan; 149 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 150 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 151 /* Log2 max number of VLANs per ETH port (0-7) */ 152 #define MLX4_LOG_NUM_VLANS 7 153 #define MLX4_MIN_LOG_NUM_VLANS 0 154 #define MLX4_MIN_LOG_NUM_MAC 1 155 156 static bool use_prio; 157 module_param_named(use_prio, use_prio, bool, 0444); 158 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 159 160 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 161 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 162 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 163 164 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 165 static int arr_argc = 2; 166 module_param_array(port_type_array, int, &arr_argc, 0444); 167 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 168 "1 for IB, 2 for Ethernet"); 169 170 struct mlx4_port_config { 171 struct list_head list; 172 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 173 struct pci_dev *pdev; 174 }; 175 176 static atomic_t pf_loading = ATOMIC_INIT(0); 177 178 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 179 struct mlx4_dev_cap *dev_cap) 180 { 181 /* The reserved_uars is calculated by system page size unit. 182 * Therefore, adjustment is added when the uar page size is less 183 * than the system page size 184 */ 185 dev->caps.reserved_uars = 186 max_t(int, 187 mlx4_get_num_reserved_uar(dev), 188 dev_cap->reserved_uars / 189 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 190 } 191 192 int mlx4_check_port_params(struct mlx4_dev *dev, 193 enum mlx4_port_type *port_type) 194 { 195 int i; 196 197 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 198 for (i = 0; i < dev->caps.num_ports - 1; i++) { 199 if (port_type[i] != port_type[i + 1]) { 200 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 201 return -EINVAL; 202 } 203 } 204 } 205 206 for (i = 0; i < dev->caps.num_ports; i++) { 207 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 208 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 209 i + 1); 210 return -EINVAL; 211 } 212 } 213 return 0; 214 } 215 216 static void mlx4_set_port_mask(struct mlx4_dev *dev) 217 { 218 int i; 219 220 for (i = 1; i <= dev->caps.num_ports; ++i) 221 dev->caps.port_mask[i] = dev->caps.port_type[i]; 222 } 223 224 enum { 225 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 226 }; 227 228 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 229 { 230 int err = 0; 231 struct mlx4_func func; 232 233 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 234 err = mlx4_QUERY_FUNC(dev, &func, 0); 235 if (err) { 236 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 237 return err; 238 } 239 dev_cap->max_eqs = func.max_eq; 240 dev_cap->reserved_eqs = func.rsvd_eqs; 241 dev_cap->reserved_uars = func.rsvd_uars; 242 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 243 } 244 return err; 245 } 246 247 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 248 { 249 struct mlx4_caps *dev_cap = &dev->caps; 250 251 /* FW not supporting or cancelled by user */ 252 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 253 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 254 return; 255 256 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 257 * When FW has NCSI it may decide not to report 64B CQE/EQEs 258 */ 259 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 260 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 261 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 262 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 263 return; 264 } 265 266 if (cache_line_size() == 128 || cache_line_size() == 256) { 267 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 268 /* Changing the real data inside CQE size to 32B */ 269 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 270 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 271 272 if (mlx4_is_master(dev)) 273 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 274 } else { 275 if (cache_line_size() != 32 && cache_line_size() != 64) 276 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 277 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 278 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 279 } 280 } 281 282 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 283 struct mlx4_port_cap *port_cap) 284 { 285 dev->caps.vl_cap[port] = port_cap->max_vl; 286 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 287 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 288 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 289 /* set gid and pkey table operating lengths by default 290 * to non-sriov values 291 */ 292 dev->caps.gid_table_len[port] = port_cap->max_gids; 293 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 294 dev->caps.port_width_cap[port] = port_cap->max_port_width; 295 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 296 dev->caps.max_tc_eth = port_cap->max_tc_eth; 297 dev->caps.def_mac[port] = port_cap->def_mac; 298 dev->caps.supported_type[port] = port_cap->supported_port_types; 299 dev->caps.suggested_type[port] = port_cap->suggested_type; 300 dev->caps.default_sense[port] = port_cap->default_sense; 301 dev->caps.trans_type[port] = port_cap->trans_type; 302 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 303 dev->caps.wavelength[port] = port_cap->wavelength; 304 dev->caps.trans_code[port] = port_cap->trans_code; 305 306 return 0; 307 } 308 309 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 310 struct mlx4_port_cap *port_cap) 311 { 312 int err = 0; 313 314 err = mlx4_QUERY_PORT(dev, port, port_cap); 315 316 if (err) 317 mlx4_err(dev, "QUERY_PORT command failed.\n"); 318 319 return err; 320 } 321 322 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 323 { 324 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 325 return; 326 327 if (mlx4_is_mfunc(dev)) { 328 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 329 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 330 return; 331 } 332 333 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 334 mlx4_dbg(dev, 335 "Keep FCS is not supported - Disabling Ignore FCS"); 336 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 337 return; 338 } 339 } 340 341 #define MLX4_A0_STEERING_TABLE_SIZE 256 342 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 343 { 344 int err; 345 int i; 346 347 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 348 if (err) { 349 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 350 return err; 351 } 352 mlx4_dev_cap_dump(dev, dev_cap); 353 354 if (dev_cap->min_page_sz > PAGE_SIZE) { 355 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 356 dev_cap->min_page_sz, PAGE_SIZE); 357 return -ENODEV; 358 } 359 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 360 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 361 dev_cap->num_ports, MLX4_MAX_PORTS); 362 return -ENODEV; 363 } 364 365 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 366 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 367 dev_cap->uar_size, 368 (unsigned long long) 369 pci_resource_len(dev->persist->pdev, 2)); 370 return -ENODEV; 371 } 372 373 dev->caps.num_ports = dev_cap->num_ports; 374 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 375 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 376 dev->caps.num_sys_eqs : 377 MLX4_MAX_EQ_NUM; 378 for (i = 1; i <= dev->caps.num_ports; ++i) { 379 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 380 if (err) { 381 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 382 return err; 383 } 384 } 385 386 dev->caps.uar_page_size = PAGE_SIZE; 387 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 388 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 389 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 390 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 391 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 392 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 393 dev->caps.max_wqes = dev_cap->max_qp_sz; 394 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 395 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 396 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 397 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 398 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 399 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 400 /* 401 * Subtract 1 from the limit because we need to allocate a 402 * spare CQE so the HCA HW can tell the difference between an 403 * empty CQ and a full CQ. 404 */ 405 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 406 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 407 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 408 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 409 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 410 411 dev->caps.reserved_pds = dev_cap->reserved_pds; 412 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 413 dev_cap->reserved_xrcds : 0; 414 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 415 dev_cap->max_xrcds : 0; 416 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 417 418 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 419 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 420 dev->caps.flags = dev_cap->flags; 421 dev->caps.flags2 = dev_cap->flags2; 422 dev->caps.bmme_flags = dev_cap->bmme_flags; 423 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 424 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 425 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 426 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 427 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 428 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 429 430 /* Save uar page shift */ 431 if (!mlx4_is_slave(dev)) { 432 /* Virtual PCI function needs to determine UAR page size from 433 * firmware. Only master PCI function can set the uar page size 434 */ 435 if (enable_4k_uar || !dev->persist->num_vfs) 436 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 437 else 438 dev->uar_page_shift = PAGE_SHIFT; 439 440 mlx4_set_num_reserved_uars(dev, dev_cap); 441 } 442 443 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 444 struct mlx4_init_hca_param hca_param; 445 446 memset(&hca_param, 0, sizeof(hca_param)); 447 err = mlx4_QUERY_HCA(dev, &hca_param); 448 /* Turn off PHV_EN flag in case phv_check_en is set. 449 * phv_check_en is a HW check that parse the packet and verify 450 * phv bit was reported correctly in the wqe. To allow QinQ 451 * PHV_EN flag should be set and phv_check_en must be cleared 452 * otherwise QinQ packets will be drop by the HW. 453 */ 454 if (err || hca_param.phv_check_en) 455 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 456 } 457 458 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 459 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 460 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 461 /* Don't do sense port on multifunction devices (for now at least) */ 462 if (mlx4_is_mfunc(dev)) 463 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 464 465 if (mlx4_low_memory_profile()) { 466 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 467 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 468 } else { 469 dev->caps.log_num_macs = log_num_mac; 470 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 471 } 472 473 for (i = 1; i <= dev->caps.num_ports; ++i) { 474 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 475 if (dev->caps.supported_type[i]) { 476 /* if only ETH is supported - assign ETH */ 477 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 478 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 479 /* if only IB is supported, assign IB */ 480 else if (dev->caps.supported_type[i] == 481 MLX4_PORT_TYPE_IB) 482 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 483 else { 484 /* if IB and ETH are supported, we set the port 485 * type according to user selection of port type; 486 * if user selected none, take the FW hint */ 487 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 488 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 489 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 490 else 491 dev->caps.port_type[i] = port_type_array[i - 1]; 492 } 493 } 494 /* 495 * Link sensing is allowed on the port if 3 conditions are true: 496 * 1. Both protocols are supported on the port. 497 * 2. Different types are supported on the port 498 * 3. FW declared that it supports link sensing 499 */ 500 mlx4_priv(dev)->sense.sense_allowed[i] = 501 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 502 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 503 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 504 505 /* 506 * If "default_sense" bit is set, we move the port to "AUTO" mode 507 * and perform sense_port FW command to try and set the correct 508 * port type from beginning 509 */ 510 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 511 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 512 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 513 mlx4_SENSE_PORT(dev, i, &sensed_port); 514 if (sensed_port != MLX4_PORT_TYPE_NONE) 515 dev->caps.port_type[i] = sensed_port; 516 } else { 517 dev->caps.possible_type[i] = dev->caps.port_type[i]; 518 } 519 520 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 521 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 522 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 523 i, 1 << dev->caps.log_num_macs); 524 } 525 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 526 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 527 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 528 i, 1 << dev->caps.log_num_vlans); 529 } 530 } 531 532 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 533 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 534 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 535 mlx4_warn(dev, 536 "Granular QoS per VF not supported with IB/Eth configuration\n"); 537 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 538 } 539 540 dev->caps.max_counters = dev_cap->max_counters; 541 542 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 543 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 545 (1 << dev->caps.log_num_macs) * 546 (1 << dev->caps.log_num_vlans) * 547 dev->caps.num_ports; 548 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 549 550 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 551 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 552 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 553 else 554 dev->caps.dmfs_high_rate_qpn_base = 555 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 556 557 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 558 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 559 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 560 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 561 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 562 } else { 563 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 564 dev->caps.dmfs_high_rate_qpn_base = 565 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 566 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 567 } 568 569 dev->caps.rl_caps = dev_cap->rl_caps; 570 571 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 572 dev->caps.dmfs_high_rate_qpn_range; 573 574 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 575 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 576 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 577 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 578 579 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 580 581 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 582 if (dev_cap->flags & 583 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 584 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 585 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 586 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 587 } 588 589 if (dev_cap->flags2 & 590 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 591 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 592 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 593 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 594 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 595 } 596 } 597 598 if ((dev->caps.flags & 599 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 600 mlx4_is_master(dev)) 601 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 602 603 if (!mlx4_is_slave(dev)) { 604 mlx4_enable_cqe_eqe_stride(dev); 605 dev->caps.alloc_res_qp_mask = 606 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 607 MLX4_RESERVE_A0_QP; 608 609 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 610 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 611 mlx4_warn(dev, "Old device ETS support detected\n"); 612 mlx4_warn(dev, "Consider upgrading device FW.\n"); 613 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 614 } 615 616 } else { 617 dev->caps.alloc_res_qp_mask = 0; 618 } 619 620 mlx4_enable_ignore_fcs(dev); 621 622 return 0; 623 } 624 625 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 626 enum pci_bus_speed *speed, 627 enum pcie_link_width *width) 628 { 629 u32 lnkcap1, lnkcap2; 630 int err1, err2; 631 632 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 633 634 *speed = PCI_SPEED_UNKNOWN; 635 *width = PCIE_LNK_WIDTH_UNKNOWN; 636 637 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP, 638 &lnkcap1); 639 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2, 640 &lnkcap2); 641 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 642 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 643 *speed = PCIE_SPEED_8_0GT; 644 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 645 *speed = PCIE_SPEED_5_0GT; 646 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 647 *speed = PCIE_SPEED_2_5GT; 648 } 649 if (!err1) { 650 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 651 if (!lnkcap2) { /* pre-r3.0 */ 652 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 653 *speed = PCIE_SPEED_5_0GT; 654 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 655 *speed = PCIE_SPEED_2_5GT; 656 } 657 } 658 659 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 660 return err1 ? err1 : 661 err2 ? err2 : -EINVAL; 662 } 663 return 0; 664 } 665 666 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 667 { 668 enum pcie_link_width width, width_cap; 669 enum pci_bus_speed speed, speed_cap; 670 int err; 671 672 #define PCIE_SPEED_STR(speed) \ 673 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 674 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 675 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 676 "Unknown") 677 678 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 679 if (err) { 680 mlx4_warn(dev, 681 "Unable to determine PCIe device BW capabilities\n"); 682 return; 683 } 684 685 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width); 686 if (err || speed == PCI_SPEED_UNKNOWN || 687 width == PCIE_LNK_WIDTH_UNKNOWN) { 688 mlx4_warn(dev, 689 "Unable to determine PCI device chain minimum BW\n"); 690 return; 691 } 692 693 if (width != width_cap || speed != speed_cap) 694 mlx4_warn(dev, 695 "PCIe BW is different than device's capability\n"); 696 697 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 698 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 699 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 700 width, width_cap); 701 return; 702 } 703 704 /*The function checks if there are live vf, return the num of them*/ 705 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 706 { 707 struct mlx4_priv *priv = mlx4_priv(dev); 708 struct mlx4_slave_state *s_state; 709 int i; 710 int ret = 0; 711 712 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 713 s_state = &priv->mfunc.master.slave_state[i]; 714 if (s_state->active && s_state->last_cmd != 715 MLX4_COMM_CMD_RESET) { 716 mlx4_warn(dev, "%s: slave: %d is still active\n", 717 __func__, i); 718 ret++; 719 } 720 } 721 return ret; 722 } 723 724 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 725 { 726 u32 qk = MLX4_RESERVED_QKEY_BASE; 727 728 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 729 qpn < dev->phys_caps.base_proxy_sqpn) 730 return -EINVAL; 731 732 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 733 /* tunnel qp */ 734 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 735 else 736 qk += qpn - dev->phys_caps.base_proxy_sqpn; 737 *qkey = qk; 738 return 0; 739 } 740 EXPORT_SYMBOL(mlx4_get_parav_qkey); 741 742 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 743 { 744 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 745 746 if (!mlx4_is_master(dev)) 747 return; 748 749 priv->virt2phys_pkey[slave][port - 1][i] = val; 750 } 751 EXPORT_SYMBOL(mlx4_sync_pkey_table); 752 753 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 754 { 755 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 756 757 if (!mlx4_is_master(dev)) 758 return; 759 760 priv->slave_node_guids[slave] = guid; 761 } 762 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 763 764 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 765 { 766 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 767 768 if (!mlx4_is_master(dev)) 769 return 0; 770 771 return priv->slave_node_guids[slave]; 772 } 773 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 774 775 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 776 { 777 struct mlx4_priv *priv = mlx4_priv(dev); 778 struct mlx4_slave_state *s_slave; 779 780 if (!mlx4_is_master(dev)) 781 return 0; 782 783 s_slave = &priv->mfunc.master.slave_state[slave]; 784 return !!s_slave->active; 785 } 786 EXPORT_SYMBOL(mlx4_is_slave_active); 787 788 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 789 struct _rule_hw *eth_header) 790 { 791 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 792 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 793 struct mlx4_net_trans_rule_hw_eth *eth = 794 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 795 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 796 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 797 next_rule->rsvd == 0; 798 799 if (last_rule) 800 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 801 } 802 } 803 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 804 805 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 806 struct mlx4_dev_cap *dev_cap, 807 struct mlx4_init_hca_param *hca_param) 808 { 809 dev->caps.steering_mode = hca_param->steering_mode; 810 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 811 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 812 dev->caps.fs_log_max_ucast_qp_range_size = 813 dev_cap->fs_log_max_ucast_qp_range_size; 814 } else 815 dev->caps.num_qp_per_mgm = 816 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 817 818 mlx4_dbg(dev, "Steering mode is: %s\n", 819 mlx4_steering_mode_str(dev->caps.steering_mode)); 820 } 821 822 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 823 { 824 kfree(dev->caps.spec_qps); 825 dev->caps.spec_qps = NULL; 826 } 827 828 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 829 { 830 struct mlx4_func_cap *func_cap = NULL; 831 struct mlx4_caps *caps = &dev->caps; 832 int i, err = 0; 833 834 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 835 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 836 837 if (!func_cap || !caps->spec_qps) { 838 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 839 err = -ENOMEM; 840 goto err_mem; 841 } 842 843 for (i = 1; i <= caps->num_ports; ++i) { 844 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 845 if (err) { 846 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 847 i, err); 848 goto err_mem; 849 } 850 caps->spec_qps[i - 1] = func_cap->spec_qps; 851 caps->port_mask[i] = caps->port_type[i]; 852 caps->phys_port_id[i] = func_cap->phys_port_id; 853 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 854 &caps->gid_table_len[i], 855 &caps->pkey_table_len[i]); 856 if (err) { 857 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 858 i, err); 859 goto err_mem; 860 } 861 } 862 863 err_mem: 864 if (err) 865 mlx4_slave_destroy_special_qp_cap(dev); 866 kfree(func_cap); 867 return err; 868 } 869 870 static int mlx4_slave_cap(struct mlx4_dev *dev) 871 { 872 int err; 873 u32 page_size; 874 struct mlx4_dev_cap *dev_cap = NULL; 875 struct mlx4_func_cap *func_cap = NULL; 876 struct mlx4_init_hca_param *hca_param = NULL; 877 878 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 879 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 880 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 881 if (!hca_param || !func_cap || !dev_cap) { 882 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 883 err = -ENOMEM; 884 goto free_mem; 885 } 886 887 err = mlx4_QUERY_HCA(dev, hca_param); 888 if (err) { 889 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 890 goto free_mem; 891 } 892 893 /* fail if the hca has an unknown global capability 894 * at this time global_caps should be always zeroed 895 */ 896 if (hca_param->global_caps) { 897 mlx4_err(dev, "Unknown hca global capabilities\n"); 898 err = -EINVAL; 899 goto free_mem; 900 } 901 902 dev->caps.hca_core_clock = hca_param->hca_core_clock; 903 904 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 905 err = mlx4_dev_cap(dev, dev_cap); 906 if (err) { 907 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 908 goto free_mem; 909 } 910 911 err = mlx4_QUERY_FW(dev); 912 if (err) 913 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 914 915 page_size = ~dev->caps.page_size_cap + 1; 916 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 917 if (page_size > PAGE_SIZE) { 918 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 919 page_size, PAGE_SIZE); 920 err = -ENODEV; 921 goto free_mem; 922 } 923 924 /* Set uar_page_shift for VF */ 925 dev->uar_page_shift = hca_param->uar_page_sz + 12; 926 927 /* Make sure the master uar page size is valid */ 928 if (dev->uar_page_shift > PAGE_SHIFT) { 929 mlx4_err(dev, 930 "Invalid configuration: uar page size is larger than system page size\n"); 931 err = -ENODEV; 932 goto free_mem; 933 } 934 935 /* Set reserved_uars based on the uar_page_shift */ 936 mlx4_set_num_reserved_uars(dev, dev_cap); 937 938 /* Although uar page size in FW differs from system page size, 939 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 940 * still works with assumption that uar page size == system page size 941 */ 942 dev->caps.uar_page_size = PAGE_SIZE; 943 944 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 945 if (err) { 946 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 947 err); 948 goto free_mem; 949 } 950 951 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 952 PF_CONTEXT_BEHAVIOUR_MASK) { 953 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 954 func_cap->pf_context_behaviour, 955 PF_CONTEXT_BEHAVIOUR_MASK); 956 err = -EINVAL; 957 goto free_mem; 958 } 959 960 dev->caps.num_ports = func_cap->num_ports; 961 dev->quotas.qp = func_cap->qp_quota; 962 dev->quotas.srq = func_cap->srq_quota; 963 dev->quotas.cq = func_cap->cq_quota; 964 dev->quotas.mpt = func_cap->mpt_quota; 965 dev->quotas.mtt = func_cap->mtt_quota; 966 dev->caps.num_qps = 1 << hca_param->log_num_qps; 967 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 968 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 969 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 970 dev->caps.num_eqs = func_cap->max_eq; 971 dev->caps.reserved_eqs = func_cap->reserved_eq; 972 dev->caps.reserved_lkey = func_cap->reserved_lkey; 973 dev->caps.num_pds = MLX4_NUM_PDS; 974 dev->caps.num_mgms = 0; 975 dev->caps.num_amgms = 0; 976 977 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 978 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 979 dev->caps.num_ports, MLX4_MAX_PORTS); 980 return -ENODEV; 981 } 982 983 mlx4_replace_zero_macs(dev); 984 985 err = mlx4_slave_special_qp_cap(dev); 986 if (err) { 987 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 988 goto free_mem; 989 } 990 991 if (dev->caps.uar_page_size * (dev->caps.num_uars - 992 dev->caps.reserved_uars) > 993 pci_resource_len(dev->persist->pdev, 994 2)) { 995 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 996 dev->caps.uar_page_size * dev->caps.num_uars, 997 (unsigned long long) 998 pci_resource_len(dev->persist->pdev, 2)); 999 err = -ENOMEM; 1000 goto err_mem; 1001 } 1002 1003 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1004 dev->caps.eqe_size = 64; 1005 dev->caps.eqe_factor = 1; 1006 } else { 1007 dev->caps.eqe_size = 32; 1008 dev->caps.eqe_factor = 0; 1009 } 1010 1011 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1012 dev->caps.cqe_size = 64; 1013 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1014 } else { 1015 dev->caps.cqe_size = 32; 1016 } 1017 1018 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1019 dev->caps.eqe_size = hca_param->eqe_size; 1020 dev->caps.eqe_factor = 0; 1021 } 1022 1023 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1024 dev->caps.cqe_size = hca_param->cqe_size; 1025 /* User still need to know when CQE > 32B */ 1026 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1027 } 1028 1029 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1030 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1031 1032 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1033 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1034 hca_param->rss_ip_frags ? "on" : "off"); 1035 1036 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1037 dev->caps.bf_reg_size) 1038 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1039 1040 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1041 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1042 1043 err_mem: 1044 if (err) 1045 mlx4_slave_destroy_special_qp_cap(dev); 1046 free_mem: 1047 kfree(hca_param); 1048 kfree(func_cap); 1049 kfree(dev_cap); 1050 return err; 1051 } 1052 1053 static void mlx4_request_modules(struct mlx4_dev *dev) 1054 { 1055 int port; 1056 int has_ib_port = false; 1057 int has_eth_port = false; 1058 #define EN_DRV_NAME "mlx4_en" 1059 #define IB_DRV_NAME "mlx4_ib" 1060 1061 for (port = 1; port <= dev->caps.num_ports; port++) { 1062 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1063 has_ib_port = true; 1064 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1065 has_eth_port = true; 1066 } 1067 1068 if (has_eth_port) 1069 request_module_nowait(EN_DRV_NAME); 1070 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1071 request_module_nowait(IB_DRV_NAME); 1072 } 1073 1074 /* 1075 * Change the port configuration of the device. 1076 * Every user of this function must hold the port mutex. 1077 */ 1078 int mlx4_change_port_types(struct mlx4_dev *dev, 1079 enum mlx4_port_type *port_types) 1080 { 1081 int err = 0; 1082 int change = 0; 1083 int port; 1084 1085 for (port = 0; port < dev->caps.num_ports; port++) { 1086 /* Change the port type only if the new type is different 1087 * from the current, and not set to Auto */ 1088 if (port_types[port] != dev->caps.port_type[port + 1]) 1089 change = 1; 1090 } 1091 if (change) { 1092 mlx4_unregister_device(dev); 1093 for (port = 1; port <= dev->caps.num_ports; port++) { 1094 mlx4_CLOSE_PORT(dev, port); 1095 dev->caps.port_type[port] = port_types[port - 1]; 1096 err = mlx4_SET_PORT(dev, port, -1); 1097 if (err) { 1098 mlx4_err(dev, "Failed to set port %d, aborting\n", 1099 port); 1100 goto out; 1101 } 1102 } 1103 mlx4_set_port_mask(dev); 1104 err = mlx4_register_device(dev); 1105 if (err) { 1106 mlx4_err(dev, "Failed to register device\n"); 1107 goto out; 1108 } 1109 mlx4_request_modules(dev); 1110 } 1111 1112 out: 1113 return err; 1114 } 1115 1116 static ssize_t show_port_type(struct device *dev, 1117 struct device_attribute *attr, 1118 char *buf) 1119 { 1120 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1121 port_attr); 1122 struct mlx4_dev *mdev = info->dev; 1123 char type[8]; 1124 1125 sprintf(type, "%s", 1126 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1127 "ib" : "eth"); 1128 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1129 sprintf(buf, "auto (%s)\n", type); 1130 else 1131 sprintf(buf, "%s\n", type); 1132 1133 return strlen(buf); 1134 } 1135 1136 static int __set_port_type(struct mlx4_port_info *info, 1137 enum mlx4_port_type port_type) 1138 { 1139 struct mlx4_dev *mdev = info->dev; 1140 struct mlx4_priv *priv = mlx4_priv(mdev); 1141 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1142 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1143 int i; 1144 int err = 0; 1145 1146 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1147 mlx4_err(mdev, 1148 "Requested port type for port %d is not supported on this HCA\n", 1149 info->port); 1150 err = -EINVAL; 1151 goto err_sup; 1152 } 1153 1154 mlx4_stop_sense(mdev); 1155 mutex_lock(&priv->port_mutex); 1156 info->tmp_type = port_type; 1157 1158 /* Possible type is always the one that was delivered */ 1159 mdev->caps.possible_type[info->port] = info->tmp_type; 1160 1161 for (i = 0; i < mdev->caps.num_ports; i++) { 1162 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1163 mdev->caps.possible_type[i+1]; 1164 if (types[i] == MLX4_PORT_TYPE_AUTO) 1165 types[i] = mdev->caps.port_type[i+1]; 1166 } 1167 1168 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1169 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1170 for (i = 1; i <= mdev->caps.num_ports; i++) { 1171 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1172 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1173 err = -EINVAL; 1174 } 1175 } 1176 } 1177 if (err) { 1178 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1179 goto out; 1180 } 1181 1182 mlx4_do_sense_ports(mdev, new_types, types); 1183 1184 err = mlx4_check_port_params(mdev, new_types); 1185 if (err) 1186 goto out; 1187 1188 /* We are about to apply the changes after the configuration 1189 * was verified, no need to remember the temporary types 1190 * any more */ 1191 for (i = 0; i < mdev->caps.num_ports; i++) 1192 priv->port[i + 1].tmp_type = 0; 1193 1194 err = mlx4_change_port_types(mdev, new_types); 1195 1196 out: 1197 mlx4_start_sense(mdev); 1198 mutex_unlock(&priv->port_mutex); 1199 err_sup: 1200 return err; 1201 } 1202 1203 static ssize_t set_port_type(struct device *dev, 1204 struct device_attribute *attr, 1205 const char *buf, size_t count) 1206 { 1207 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1208 port_attr); 1209 struct mlx4_dev *mdev = info->dev; 1210 enum mlx4_port_type port_type; 1211 static DEFINE_MUTEX(set_port_type_mutex); 1212 int err; 1213 1214 mutex_lock(&set_port_type_mutex); 1215 1216 if (!strcmp(buf, "ib\n")) { 1217 port_type = MLX4_PORT_TYPE_IB; 1218 } else if (!strcmp(buf, "eth\n")) { 1219 port_type = MLX4_PORT_TYPE_ETH; 1220 } else if (!strcmp(buf, "auto\n")) { 1221 port_type = MLX4_PORT_TYPE_AUTO; 1222 } else { 1223 mlx4_err(mdev, "%s is not supported port type\n", buf); 1224 err = -EINVAL; 1225 goto err_out; 1226 } 1227 1228 err = __set_port_type(info, port_type); 1229 1230 err_out: 1231 mutex_unlock(&set_port_type_mutex); 1232 1233 return err ? err : count; 1234 } 1235 1236 enum ibta_mtu { 1237 IB_MTU_256 = 1, 1238 IB_MTU_512 = 2, 1239 IB_MTU_1024 = 3, 1240 IB_MTU_2048 = 4, 1241 IB_MTU_4096 = 5 1242 }; 1243 1244 static inline int int_to_ibta_mtu(int mtu) 1245 { 1246 switch (mtu) { 1247 case 256: return IB_MTU_256; 1248 case 512: return IB_MTU_512; 1249 case 1024: return IB_MTU_1024; 1250 case 2048: return IB_MTU_2048; 1251 case 4096: return IB_MTU_4096; 1252 default: return -1; 1253 } 1254 } 1255 1256 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1257 { 1258 switch (mtu) { 1259 case IB_MTU_256: return 256; 1260 case IB_MTU_512: return 512; 1261 case IB_MTU_1024: return 1024; 1262 case IB_MTU_2048: return 2048; 1263 case IB_MTU_4096: return 4096; 1264 default: return -1; 1265 } 1266 } 1267 1268 static ssize_t show_port_ib_mtu(struct device *dev, 1269 struct device_attribute *attr, 1270 char *buf) 1271 { 1272 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1273 port_mtu_attr); 1274 struct mlx4_dev *mdev = info->dev; 1275 1276 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1277 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1278 1279 sprintf(buf, "%d\n", 1280 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1281 return strlen(buf); 1282 } 1283 1284 static ssize_t set_port_ib_mtu(struct device *dev, 1285 struct device_attribute *attr, 1286 const char *buf, size_t count) 1287 { 1288 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1289 port_mtu_attr); 1290 struct mlx4_dev *mdev = info->dev; 1291 struct mlx4_priv *priv = mlx4_priv(mdev); 1292 int err, port, mtu, ibta_mtu = -1; 1293 1294 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1295 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1296 return -EINVAL; 1297 } 1298 1299 err = kstrtoint(buf, 0, &mtu); 1300 if (!err) 1301 ibta_mtu = int_to_ibta_mtu(mtu); 1302 1303 if (err || ibta_mtu < 0) { 1304 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1305 return -EINVAL; 1306 } 1307 1308 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1309 1310 mlx4_stop_sense(mdev); 1311 mutex_lock(&priv->port_mutex); 1312 mlx4_unregister_device(mdev); 1313 for (port = 1; port <= mdev->caps.num_ports; port++) { 1314 mlx4_CLOSE_PORT(mdev, port); 1315 err = mlx4_SET_PORT(mdev, port, -1); 1316 if (err) { 1317 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1318 port); 1319 goto err_set_port; 1320 } 1321 } 1322 err = mlx4_register_device(mdev); 1323 err_set_port: 1324 mutex_unlock(&priv->port_mutex); 1325 mlx4_start_sense(mdev); 1326 return err ? err : count; 1327 } 1328 1329 /* bond for multi-function device */ 1330 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1331 static int mlx4_mf_bond(struct mlx4_dev *dev) 1332 { 1333 int err = 0; 1334 int nvfs; 1335 struct mlx4_slaves_pport slaves_port1; 1336 struct mlx4_slaves_pport slaves_port2; 1337 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1338 1339 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1340 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1341 bitmap_and(slaves_port_1_2, 1342 slaves_port1.slaves, slaves_port2.slaves, 1343 dev->persist->num_vfs + 1); 1344 1345 /* only single port vfs are allowed */ 1346 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1347 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1348 return -EINVAL; 1349 } 1350 1351 /* number of virtual functions is number of total functions minus one 1352 * physical function for each port. 1353 */ 1354 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1355 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1356 1357 /* limit on maximum allowed VFs */ 1358 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1359 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1360 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1361 return -EINVAL; 1362 } 1363 1364 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1365 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1366 return -EINVAL; 1367 } 1368 1369 err = mlx4_bond_mac_table(dev); 1370 if (err) 1371 return err; 1372 err = mlx4_bond_vlan_table(dev); 1373 if (err) 1374 goto err1; 1375 err = mlx4_bond_fs_rules(dev); 1376 if (err) 1377 goto err2; 1378 1379 return 0; 1380 err2: 1381 (void)mlx4_unbond_vlan_table(dev); 1382 err1: 1383 (void)mlx4_unbond_mac_table(dev); 1384 return err; 1385 } 1386 1387 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1388 { 1389 int ret, ret1; 1390 1391 ret = mlx4_unbond_fs_rules(dev); 1392 if (ret) 1393 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret); 1394 ret1 = mlx4_unbond_mac_table(dev); 1395 if (ret1) { 1396 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1397 ret = ret1; 1398 } 1399 ret1 = mlx4_unbond_vlan_table(dev); 1400 if (ret1) { 1401 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1402 ret = ret1; 1403 } 1404 return ret; 1405 } 1406 1407 int mlx4_bond(struct mlx4_dev *dev) 1408 { 1409 int ret = 0; 1410 struct mlx4_priv *priv = mlx4_priv(dev); 1411 1412 mutex_lock(&priv->bond_mutex); 1413 1414 if (!mlx4_is_bonded(dev)) { 1415 ret = mlx4_do_bond(dev, true); 1416 if (ret) 1417 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1418 if (!ret && mlx4_is_master(dev)) { 1419 ret = mlx4_mf_bond(dev); 1420 if (ret) { 1421 mlx4_err(dev, "bond for multifunction failed\n"); 1422 mlx4_do_bond(dev, false); 1423 } 1424 } 1425 } 1426 1427 mutex_unlock(&priv->bond_mutex); 1428 if (!ret) 1429 mlx4_dbg(dev, "Device is bonded\n"); 1430 1431 return ret; 1432 } 1433 EXPORT_SYMBOL_GPL(mlx4_bond); 1434 1435 int mlx4_unbond(struct mlx4_dev *dev) 1436 { 1437 int ret = 0; 1438 struct mlx4_priv *priv = mlx4_priv(dev); 1439 1440 mutex_lock(&priv->bond_mutex); 1441 1442 if (mlx4_is_bonded(dev)) { 1443 int ret2 = 0; 1444 1445 ret = mlx4_do_bond(dev, false); 1446 if (ret) 1447 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1448 if (mlx4_is_master(dev)) 1449 ret2 = mlx4_mf_unbond(dev); 1450 if (ret2) { 1451 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1452 ret = ret2; 1453 } 1454 } 1455 1456 mutex_unlock(&priv->bond_mutex); 1457 if (!ret) 1458 mlx4_dbg(dev, "Device is unbonded\n"); 1459 1460 return ret; 1461 } 1462 EXPORT_SYMBOL_GPL(mlx4_unbond); 1463 1464 1465 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1466 { 1467 u8 port1 = v2p->port1; 1468 u8 port2 = v2p->port2; 1469 struct mlx4_priv *priv = mlx4_priv(dev); 1470 int err; 1471 1472 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1473 return -EOPNOTSUPP; 1474 1475 mutex_lock(&priv->bond_mutex); 1476 1477 /* zero means keep current mapping for this port */ 1478 if (port1 == 0) 1479 port1 = priv->v2p.port1; 1480 if (port2 == 0) 1481 port2 = priv->v2p.port2; 1482 1483 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1484 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1485 (port1 == 2 && port2 == 1)) { 1486 /* besides boundary checks cross mapping makes 1487 * no sense and therefore not allowed */ 1488 err = -EINVAL; 1489 } else if ((port1 == priv->v2p.port1) && 1490 (port2 == priv->v2p.port2)) { 1491 err = 0; 1492 } else { 1493 err = mlx4_virt2phy_port_map(dev, port1, port2); 1494 if (!err) { 1495 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1496 port1, port2); 1497 priv->v2p.port1 = port1; 1498 priv->v2p.port2 = port2; 1499 } else { 1500 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1501 } 1502 } 1503 1504 mutex_unlock(&priv->bond_mutex); 1505 return err; 1506 } 1507 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1508 1509 static int mlx4_load_fw(struct mlx4_dev *dev) 1510 { 1511 struct mlx4_priv *priv = mlx4_priv(dev); 1512 int err; 1513 1514 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1515 GFP_HIGHUSER | __GFP_NOWARN, 0); 1516 if (!priv->fw.fw_icm) { 1517 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1518 return -ENOMEM; 1519 } 1520 1521 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1522 if (err) { 1523 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1524 goto err_free; 1525 } 1526 1527 err = mlx4_RUN_FW(dev); 1528 if (err) { 1529 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1530 goto err_unmap_fa; 1531 } 1532 1533 return 0; 1534 1535 err_unmap_fa: 1536 mlx4_UNMAP_FA(dev); 1537 1538 err_free: 1539 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1540 return err; 1541 } 1542 1543 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1544 int cmpt_entry_sz) 1545 { 1546 struct mlx4_priv *priv = mlx4_priv(dev); 1547 int err; 1548 int num_eqs; 1549 1550 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1551 cmpt_base + 1552 ((u64) (MLX4_CMPT_TYPE_QP * 1553 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1554 cmpt_entry_sz, dev->caps.num_qps, 1555 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1556 0, 0); 1557 if (err) 1558 goto err; 1559 1560 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1561 cmpt_base + 1562 ((u64) (MLX4_CMPT_TYPE_SRQ * 1563 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1564 cmpt_entry_sz, dev->caps.num_srqs, 1565 dev->caps.reserved_srqs, 0, 0); 1566 if (err) 1567 goto err_qp; 1568 1569 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1570 cmpt_base + 1571 ((u64) (MLX4_CMPT_TYPE_CQ * 1572 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1573 cmpt_entry_sz, dev->caps.num_cqs, 1574 dev->caps.reserved_cqs, 0, 0); 1575 if (err) 1576 goto err_srq; 1577 1578 num_eqs = dev->phys_caps.num_phys_eqs; 1579 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1580 cmpt_base + 1581 ((u64) (MLX4_CMPT_TYPE_EQ * 1582 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1583 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1584 if (err) 1585 goto err_cq; 1586 1587 return 0; 1588 1589 err_cq: 1590 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1591 1592 err_srq: 1593 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1594 1595 err_qp: 1596 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1597 1598 err: 1599 return err; 1600 } 1601 1602 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1603 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1604 { 1605 struct mlx4_priv *priv = mlx4_priv(dev); 1606 u64 aux_pages; 1607 int num_eqs; 1608 int err; 1609 1610 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1611 if (err) { 1612 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1613 return err; 1614 } 1615 1616 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1617 (unsigned long long) icm_size >> 10, 1618 (unsigned long long) aux_pages << 2); 1619 1620 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1621 GFP_HIGHUSER | __GFP_NOWARN, 0); 1622 if (!priv->fw.aux_icm) { 1623 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1624 return -ENOMEM; 1625 } 1626 1627 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1628 if (err) { 1629 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1630 goto err_free_aux; 1631 } 1632 1633 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1634 if (err) { 1635 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1636 goto err_unmap_aux; 1637 } 1638 1639 1640 num_eqs = dev->phys_caps.num_phys_eqs; 1641 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1642 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1643 num_eqs, num_eqs, 0, 0); 1644 if (err) { 1645 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1646 goto err_unmap_cmpt; 1647 } 1648 1649 /* 1650 * Reserved MTT entries must be aligned up to a cacheline 1651 * boundary, since the FW will write to them, while the driver 1652 * writes to all other MTT entries. (The variable 1653 * dev->caps.mtt_entry_sz below is really the MTT segment 1654 * size, not the raw entry size) 1655 */ 1656 dev->caps.reserved_mtts = 1657 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1658 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1659 1660 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1661 init_hca->mtt_base, 1662 dev->caps.mtt_entry_sz, 1663 dev->caps.num_mtts, 1664 dev->caps.reserved_mtts, 1, 0); 1665 if (err) { 1666 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1667 goto err_unmap_eq; 1668 } 1669 1670 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1671 init_hca->dmpt_base, 1672 dev_cap->dmpt_entry_sz, 1673 dev->caps.num_mpts, 1674 dev->caps.reserved_mrws, 1, 1); 1675 if (err) { 1676 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1677 goto err_unmap_mtt; 1678 } 1679 1680 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1681 init_hca->qpc_base, 1682 dev_cap->qpc_entry_sz, 1683 dev->caps.num_qps, 1684 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1685 0, 0); 1686 if (err) { 1687 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1688 goto err_unmap_dmpt; 1689 } 1690 1691 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1692 init_hca->auxc_base, 1693 dev_cap->aux_entry_sz, 1694 dev->caps.num_qps, 1695 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1696 0, 0); 1697 if (err) { 1698 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1699 goto err_unmap_qp; 1700 } 1701 1702 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1703 init_hca->altc_base, 1704 dev_cap->altc_entry_sz, 1705 dev->caps.num_qps, 1706 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1707 0, 0); 1708 if (err) { 1709 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1710 goto err_unmap_auxc; 1711 } 1712 1713 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1714 init_hca->rdmarc_base, 1715 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1716 dev->caps.num_qps, 1717 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1718 0, 0); 1719 if (err) { 1720 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1721 goto err_unmap_altc; 1722 } 1723 1724 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1725 init_hca->cqc_base, 1726 dev_cap->cqc_entry_sz, 1727 dev->caps.num_cqs, 1728 dev->caps.reserved_cqs, 0, 0); 1729 if (err) { 1730 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1731 goto err_unmap_rdmarc; 1732 } 1733 1734 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1735 init_hca->srqc_base, 1736 dev_cap->srq_entry_sz, 1737 dev->caps.num_srqs, 1738 dev->caps.reserved_srqs, 0, 0); 1739 if (err) { 1740 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1741 goto err_unmap_cq; 1742 } 1743 1744 /* 1745 * For flow steering device managed mode it is required to use 1746 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1747 * required, but for simplicity just map the whole multicast 1748 * group table now. The table isn't very big and it's a lot 1749 * easier than trying to track ref counts. 1750 */ 1751 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1752 init_hca->mc_base, 1753 mlx4_get_mgm_entry_size(dev), 1754 dev->caps.num_mgms + dev->caps.num_amgms, 1755 dev->caps.num_mgms + dev->caps.num_amgms, 1756 0, 0); 1757 if (err) { 1758 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1759 goto err_unmap_srq; 1760 } 1761 1762 return 0; 1763 1764 err_unmap_srq: 1765 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1766 1767 err_unmap_cq: 1768 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1769 1770 err_unmap_rdmarc: 1771 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1772 1773 err_unmap_altc: 1774 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1775 1776 err_unmap_auxc: 1777 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1778 1779 err_unmap_qp: 1780 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1781 1782 err_unmap_dmpt: 1783 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1784 1785 err_unmap_mtt: 1786 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1787 1788 err_unmap_eq: 1789 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1790 1791 err_unmap_cmpt: 1792 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1793 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1794 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1795 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1796 1797 err_unmap_aux: 1798 mlx4_UNMAP_ICM_AUX(dev); 1799 1800 err_free_aux: 1801 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1802 1803 return err; 1804 } 1805 1806 static void mlx4_free_icms(struct mlx4_dev *dev) 1807 { 1808 struct mlx4_priv *priv = mlx4_priv(dev); 1809 1810 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1811 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1812 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1813 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1814 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1815 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1816 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1817 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1818 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1819 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1820 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1821 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1822 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1823 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1824 1825 mlx4_UNMAP_ICM_AUX(dev); 1826 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1827 } 1828 1829 static void mlx4_slave_exit(struct mlx4_dev *dev) 1830 { 1831 struct mlx4_priv *priv = mlx4_priv(dev); 1832 1833 mutex_lock(&priv->cmd.slave_cmd_mutex); 1834 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1835 MLX4_COMM_TIME)) 1836 mlx4_warn(dev, "Failed to close slave function\n"); 1837 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1838 } 1839 1840 static int map_bf_area(struct mlx4_dev *dev) 1841 { 1842 struct mlx4_priv *priv = mlx4_priv(dev); 1843 resource_size_t bf_start; 1844 resource_size_t bf_len; 1845 int err = 0; 1846 1847 if (!dev->caps.bf_reg_size) 1848 return -ENXIO; 1849 1850 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1851 (dev->caps.num_uars << PAGE_SHIFT); 1852 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1853 (dev->caps.num_uars << PAGE_SHIFT); 1854 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1855 if (!priv->bf_mapping) 1856 err = -ENOMEM; 1857 1858 return err; 1859 } 1860 1861 static void unmap_bf_area(struct mlx4_dev *dev) 1862 { 1863 if (mlx4_priv(dev)->bf_mapping) 1864 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1865 } 1866 1867 u64 mlx4_read_clock(struct mlx4_dev *dev) 1868 { 1869 u32 clockhi, clocklo, clockhi1; 1870 u64 cycles; 1871 int i; 1872 struct mlx4_priv *priv = mlx4_priv(dev); 1873 1874 for (i = 0; i < 10; i++) { 1875 clockhi = swab32(readl(priv->clock_mapping)); 1876 clocklo = swab32(readl(priv->clock_mapping + 4)); 1877 clockhi1 = swab32(readl(priv->clock_mapping)); 1878 if (clockhi == clockhi1) 1879 break; 1880 } 1881 1882 cycles = (u64) clockhi << 32 | (u64) clocklo; 1883 1884 return cycles; 1885 } 1886 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1887 1888 1889 static int map_internal_clock(struct mlx4_dev *dev) 1890 { 1891 struct mlx4_priv *priv = mlx4_priv(dev); 1892 1893 priv->clock_mapping = 1894 ioremap(pci_resource_start(dev->persist->pdev, 1895 priv->fw.clock_bar) + 1896 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1897 1898 if (!priv->clock_mapping) 1899 return -ENOMEM; 1900 1901 return 0; 1902 } 1903 1904 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1905 struct mlx4_clock_params *params) 1906 { 1907 struct mlx4_priv *priv = mlx4_priv(dev); 1908 1909 if (mlx4_is_slave(dev)) 1910 return -EOPNOTSUPP; 1911 1912 if (!params) 1913 return -EINVAL; 1914 1915 params->bar = priv->fw.clock_bar; 1916 params->offset = priv->fw.clock_offset; 1917 params->size = MLX4_CLOCK_SIZE; 1918 1919 return 0; 1920 } 1921 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1922 1923 static void unmap_internal_clock(struct mlx4_dev *dev) 1924 { 1925 struct mlx4_priv *priv = mlx4_priv(dev); 1926 1927 if (priv->clock_mapping) 1928 iounmap(priv->clock_mapping); 1929 } 1930 1931 static void mlx4_close_hca(struct mlx4_dev *dev) 1932 { 1933 unmap_internal_clock(dev); 1934 unmap_bf_area(dev); 1935 if (mlx4_is_slave(dev)) 1936 mlx4_slave_exit(dev); 1937 else { 1938 mlx4_CLOSE_HCA(dev, 0); 1939 mlx4_free_icms(dev); 1940 } 1941 } 1942 1943 static void mlx4_close_fw(struct mlx4_dev *dev) 1944 { 1945 if (!mlx4_is_slave(dev)) { 1946 mlx4_UNMAP_FA(dev); 1947 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1948 } 1949 } 1950 1951 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1952 { 1953 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1954 1955 u32 comm_flags; 1956 u32 offline_bit; 1957 unsigned long end; 1958 struct mlx4_priv *priv = mlx4_priv(dev); 1959 1960 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 1961 while (time_before(jiffies, end)) { 1962 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 1963 MLX4_COMM_CHAN_FLAGS)); 1964 offline_bit = (comm_flags & 1965 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 1966 if (!offline_bit) 1967 return 0; 1968 1969 /* If device removal has been requested, 1970 * do not continue retrying. 1971 */ 1972 if (dev->persist->interface_state & 1973 MLX4_INTERFACE_STATE_NOWAIT) 1974 break; 1975 1976 /* There are cases as part of AER/Reset flow that PF needs 1977 * around 100 msec to load. We therefore sleep for 100 msec 1978 * to allow other tasks to make use of that CPU during this 1979 * time interval. 1980 */ 1981 msleep(100); 1982 } 1983 mlx4_err(dev, "Communication channel is offline.\n"); 1984 return -EIO; 1985 } 1986 1987 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 1988 { 1989 #define COMM_CHAN_RST_OFFSET 0x1e 1990 1991 struct mlx4_priv *priv = mlx4_priv(dev); 1992 u32 comm_rst; 1993 u32 comm_caps; 1994 1995 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 1996 MLX4_COMM_CHAN_CAPS)); 1997 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 1998 1999 if (comm_rst) 2000 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2001 } 2002 2003 static int mlx4_init_slave(struct mlx4_dev *dev) 2004 { 2005 struct mlx4_priv *priv = mlx4_priv(dev); 2006 u64 dma = (u64) priv->mfunc.vhcr_dma; 2007 int ret_from_reset = 0; 2008 u32 slave_read; 2009 u32 cmd_channel_ver; 2010 2011 if (atomic_read(&pf_loading)) { 2012 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2013 return -EPROBE_DEFER; 2014 } 2015 2016 mutex_lock(&priv->cmd.slave_cmd_mutex); 2017 priv->cmd.max_cmds = 1; 2018 if (mlx4_comm_check_offline(dev)) { 2019 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2020 goto err_offline; 2021 } 2022 2023 mlx4_reset_vf_support(dev); 2024 mlx4_warn(dev, "Sending reset\n"); 2025 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2026 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2027 /* if we are in the middle of flr the slave will try 2028 * NUM_OF_RESET_RETRIES times before leaving.*/ 2029 if (ret_from_reset) { 2030 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2031 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2032 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2033 return -EPROBE_DEFER; 2034 } else 2035 goto err; 2036 } 2037 2038 /* check the driver version - the slave I/F revision 2039 * must match the master's */ 2040 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2041 cmd_channel_ver = mlx4_comm_get_version(); 2042 2043 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2044 MLX4_COMM_GET_IF_REV(slave_read)) { 2045 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2046 goto err; 2047 } 2048 2049 mlx4_warn(dev, "Sending vhcr0\n"); 2050 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2051 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2052 goto err; 2053 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2054 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2055 goto err; 2056 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2057 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2058 goto err; 2059 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2060 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2061 goto err; 2062 2063 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2064 return 0; 2065 2066 err: 2067 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2068 err_offline: 2069 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2070 return -EIO; 2071 } 2072 2073 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2074 { 2075 int i; 2076 2077 for (i = 1; i <= dev->caps.num_ports; i++) { 2078 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2079 dev->caps.gid_table_len[i] = 2080 mlx4_get_slave_num_gids(dev, 0, i); 2081 else 2082 dev->caps.gid_table_len[i] = 1; 2083 dev->caps.pkey_table_len[i] = 2084 dev->phys_caps.pkey_phys_table_len[i] - 1; 2085 } 2086 } 2087 2088 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2089 { 2090 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2091 2092 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2093 i++) { 2094 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2095 break; 2096 } 2097 2098 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2099 } 2100 2101 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2102 { 2103 switch (dmfs_high_steer_mode) { 2104 case MLX4_STEERING_DMFS_A0_DEFAULT: 2105 return "default performance"; 2106 2107 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2108 return "dynamic hybrid mode"; 2109 2110 case MLX4_STEERING_DMFS_A0_STATIC: 2111 return "performance optimized for limited rule configuration (static)"; 2112 2113 case MLX4_STEERING_DMFS_A0_DISABLE: 2114 return "disabled performance optimized steering"; 2115 2116 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2117 return "performance optimized steering not supported"; 2118 2119 default: 2120 return "Unrecognized mode"; 2121 } 2122 } 2123 2124 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2125 2126 static void choose_steering_mode(struct mlx4_dev *dev, 2127 struct mlx4_dev_cap *dev_cap) 2128 { 2129 if (mlx4_log_num_mgm_entry_size <= 0) { 2130 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2131 if (dev->caps.dmfs_high_steer_mode == 2132 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2133 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2134 else 2135 dev->caps.dmfs_high_steer_mode = 2136 MLX4_STEERING_DMFS_A0_STATIC; 2137 } 2138 } 2139 2140 if (mlx4_log_num_mgm_entry_size <= 0 && 2141 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2142 (!mlx4_is_mfunc(dev) || 2143 (dev_cap->fs_max_num_qp_per_entry >= 2144 (dev->persist->num_vfs + 1))) && 2145 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2146 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2147 dev->oper_log_mgm_entry_size = 2148 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2149 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2150 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2151 dev->caps.fs_log_max_ucast_qp_range_size = 2152 dev_cap->fs_log_max_ucast_qp_range_size; 2153 } else { 2154 if (dev->caps.dmfs_high_steer_mode != 2155 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2156 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2157 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2158 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2159 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2160 else { 2161 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2162 2163 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2164 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2165 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2166 } 2167 dev->oper_log_mgm_entry_size = 2168 mlx4_log_num_mgm_entry_size > 0 ? 2169 mlx4_log_num_mgm_entry_size : 2170 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2171 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2172 } 2173 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2174 mlx4_steering_mode_str(dev->caps.steering_mode), 2175 dev->oper_log_mgm_entry_size, 2176 mlx4_log_num_mgm_entry_size); 2177 } 2178 2179 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2180 struct mlx4_dev_cap *dev_cap) 2181 { 2182 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2183 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2184 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2185 else 2186 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2187 2188 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2189 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2190 } 2191 2192 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2193 { 2194 int i; 2195 struct mlx4_port_cap port_cap; 2196 2197 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2198 return -EINVAL; 2199 2200 for (i = 1; i <= dev->caps.num_ports; i++) { 2201 if (mlx4_dev_port(dev, i, &port_cap)) { 2202 mlx4_err(dev, 2203 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 2204 } else if ((dev->caps.dmfs_high_steer_mode != 2205 MLX4_STEERING_DMFS_A0_DEFAULT) && 2206 (port_cap.dmfs_optimized_state == 2207 !!(dev->caps.dmfs_high_steer_mode == 2208 MLX4_STEERING_DMFS_A0_DISABLE))) { 2209 mlx4_err(dev, 2210 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2211 dmfs_high_rate_steering_mode_str( 2212 dev->caps.dmfs_high_steer_mode), 2213 (port_cap.dmfs_optimized_state ? 2214 "enabled" : "disabled")); 2215 } 2216 } 2217 2218 return 0; 2219 } 2220 2221 static int mlx4_init_fw(struct mlx4_dev *dev) 2222 { 2223 struct mlx4_mod_stat_cfg mlx4_cfg; 2224 int err = 0; 2225 2226 if (!mlx4_is_slave(dev)) { 2227 err = mlx4_QUERY_FW(dev); 2228 if (err) { 2229 if (err == -EACCES) 2230 mlx4_info(dev, "non-primary physical function, skipping\n"); 2231 else 2232 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2233 return err; 2234 } 2235 2236 err = mlx4_load_fw(dev); 2237 if (err) { 2238 mlx4_err(dev, "Failed to start FW, aborting\n"); 2239 return err; 2240 } 2241 2242 mlx4_cfg.log_pg_sz_m = 1; 2243 mlx4_cfg.log_pg_sz = 0; 2244 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2245 if (err) 2246 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2247 } 2248 2249 return err; 2250 } 2251 2252 static int mlx4_init_hca(struct mlx4_dev *dev) 2253 { 2254 struct mlx4_priv *priv = mlx4_priv(dev); 2255 struct mlx4_adapter adapter; 2256 struct mlx4_dev_cap dev_cap; 2257 struct mlx4_profile profile; 2258 struct mlx4_init_hca_param init_hca; 2259 u64 icm_size; 2260 struct mlx4_config_dev_params params; 2261 int err; 2262 2263 if (!mlx4_is_slave(dev)) { 2264 err = mlx4_dev_cap(dev, &dev_cap); 2265 if (err) { 2266 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2267 return err; 2268 } 2269 2270 choose_steering_mode(dev, &dev_cap); 2271 choose_tunnel_offload_mode(dev, &dev_cap); 2272 2273 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2274 mlx4_is_master(dev)) 2275 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2276 2277 err = mlx4_get_phys_port_id(dev); 2278 if (err) 2279 mlx4_err(dev, "Fail to get physical port id\n"); 2280 2281 if (mlx4_is_master(dev)) 2282 mlx4_parav_master_pf_caps(dev); 2283 2284 if (mlx4_low_memory_profile()) { 2285 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2286 profile = low_mem_profile; 2287 } else { 2288 profile = default_profile; 2289 } 2290 if (dev->caps.steering_mode == 2291 MLX4_STEERING_MODE_DEVICE_MANAGED) 2292 profile.num_mcg = MLX4_FS_NUM_MCG; 2293 2294 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2295 &init_hca); 2296 if ((long long) icm_size < 0) { 2297 err = icm_size; 2298 return err; 2299 } 2300 2301 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2302 2303 if (enable_4k_uar || !dev->persist->num_vfs) { 2304 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) + 2305 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2306 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2307 } else { 2308 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2309 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2310 } 2311 2312 init_hca.mw_enabled = 0; 2313 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2314 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2315 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2316 2317 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2318 if (err) 2319 return err; 2320 2321 err = mlx4_INIT_HCA(dev, &init_hca); 2322 if (err) { 2323 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2324 goto err_free_icm; 2325 } 2326 2327 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2328 err = mlx4_query_func(dev, &dev_cap); 2329 if (err < 0) { 2330 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2331 goto err_close; 2332 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2333 dev->caps.num_eqs = dev_cap.max_eqs; 2334 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2335 dev->caps.reserved_uars = dev_cap.reserved_uars; 2336 } 2337 } 2338 2339 /* 2340 * If TS is supported by FW 2341 * read HCA frequency by QUERY_HCA command 2342 */ 2343 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2344 memset(&init_hca, 0, sizeof(init_hca)); 2345 err = mlx4_QUERY_HCA(dev, &init_hca); 2346 if (err) { 2347 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2348 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2349 } else { 2350 dev->caps.hca_core_clock = 2351 init_hca.hca_core_clock; 2352 } 2353 2354 /* In case we got HCA frequency 0 - disable timestamping 2355 * to avoid dividing by zero 2356 */ 2357 if (!dev->caps.hca_core_clock) { 2358 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2359 mlx4_err(dev, 2360 "HCA frequency is 0 - timestamping is not supported\n"); 2361 } else if (map_internal_clock(dev)) { 2362 /* 2363 * Map internal clock, 2364 * in case of failure disable timestamping 2365 */ 2366 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2367 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2368 } 2369 } 2370 2371 if (dev->caps.dmfs_high_steer_mode != 2372 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2373 if (mlx4_validate_optimized_steering(dev)) 2374 mlx4_warn(dev, "Optimized steering validation failed\n"); 2375 2376 if (dev->caps.dmfs_high_steer_mode == 2377 MLX4_STEERING_DMFS_A0_DISABLE) { 2378 dev->caps.dmfs_high_rate_qpn_base = 2379 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2380 dev->caps.dmfs_high_rate_qpn_range = 2381 MLX4_A0_STEERING_TABLE_SIZE; 2382 } 2383 2384 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2385 dmfs_high_rate_steering_mode_str( 2386 dev->caps.dmfs_high_steer_mode)); 2387 } 2388 } else { 2389 err = mlx4_init_slave(dev); 2390 if (err) { 2391 if (err != -EPROBE_DEFER) 2392 mlx4_err(dev, "Failed to initialize slave\n"); 2393 return err; 2394 } 2395 2396 err = mlx4_slave_cap(dev); 2397 if (err) { 2398 mlx4_err(dev, "Failed to obtain slave caps\n"); 2399 goto err_close; 2400 } 2401 } 2402 2403 if (map_bf_area(dev)) 2404 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2405 2406 /*Only the master set the ports, all the rest got it from it.*/ 2407 if (!mlx4_is_slave(dev)) 2408 mlx4_set_port_mask(dev); 2409 2410 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2411 if (err) { 2412 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2413 goto unmap_bf; 2414 } 2415 2416 /* Query CONFIG_DEV parameters */ 2417 err = mlx4_config_dev_retrieval(dev, ¶ms); 2418 if (err && err != -EOPNOTSUPP) { 2419 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2420 } else if (!err) { 2421 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2422 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2423 } 2424 priv->eq_table.inta_pin = adapter.inta_pin; 2425 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2426 2427 return 0; 2428 2429 unmap_bf: 2430 unmap_internal_clock(dev); 2431 unmap_bf_area(dev); 2432 2433 if (mlx4_is_slave(dev)) 2434 mlx4_slave_destroy_special_qp_cap(dev); 2435 2436 err_close: 2437 if (mlx4_is_slave(dev)) 2438 mlx4_slave_exit(dev); 2439 else 2440 mlx4_CLOSE_HCA(dev, 0); 2441 2442 err_free_icm: 2443 if (!mlx4_is_slave(dev)) 2444 mlx4_free_icms(dev); 2445 2446 return err; 2447 } 2448 2449 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2450 { 2451 struct mlx4_priv *priv = mlx4_priv(dev); 2452 int nent_pow2; 2453 2454 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2455 return -ENOENT; 2456 2457 if (!dev->caps.max_counters) 2458 return -ENOSPC; 2459 2460 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2461 /* reserve last counter index for sink counter */ 2462 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2463 nent_pow2 - 1, 0, 2464 nent_pow2 - dev->caps.max_counters + 1); 2465 } 2466 2467 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2468 { 2469 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2470 return; 2471 2472 if (!dev->caps.max_counters) 2473 return; 2474 2475 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2476 } 2477 2478 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2479 { 2480 struct mlx4_priv *priv = mlx4_priv(dev); 2481 int port; 2482 2483 for (port = 0; port < dev->caps.num_ports; port++) 2484 if (priv->def_counter[port] != -1) 2485 mlx4_counter_free(dev, priv->def_counter[port]); 2486 } 2487 2488 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2489 { 2490 struct mlx4_priv *priv = mlx4_priv(dev); 2491 int port, err = 0; 2492 u32 idx; 2493 2494 for (port = 0; port < dev->caps.num_ports; port++) 2495 priv->def_counter[port] = -1; 2496 2497 for (port = 0; port < dev->caps.num_ports; port++) { 2498 err = mlx4_counter_alloc(dev, &idx); 2499 2500 if (!err || err == -ENOSPC) { 2501 priv->def_counter[port] = idx; 2502 } else if (err == -ENOENT) { 2503 err = 0; 2504 continue; 2505 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2506 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2507 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2508 MLX4_SINK_COUNTER_INDEX(dev)); 2509 err = 0; 2510 } else { 2511 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2512 __func__, port + 1, err); 2513 mlx4_cleanup_default_counters(dev); 2514 return err; 2515 } 2516 2517 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2518 __func__, priv->def_counter[port], port + 1); 2519 } 2520 2521 return err; 2522 } 2523 2524 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2525 { 2526 struct mlx4_priv *priv = mlx4_priv(dev); 2527 2528 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2529 return -ENOENT; 2530 2531 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2532 if (*idx == -1) { 2533 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2534 return -ENOSPC; 2535 } 2536 2537 return 0; 2538 } 2539 2540 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2541 { 2542 u64 out_param; 2543 int err; 2544 2545 if (mlx4_is_mfunc(dev)) { 2546 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 2547 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2548 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2549 if (!err) 2550 *idx = get_param_l(&out_param); 2551 2552 return err; 2553 } 2554 return __mlx4_counter_alloc(dev, idx); 2555 } 2556 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2557 2558 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2559 u8 counter_index) 2560 { 2561 struct mlx4_cmd_mailbox *if_stat_mailbox; 2562 int err; 2563 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2564 2565 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2566 if (IS_ERR(if_stat_mailbox)) 2567 return PTR_ERR(if_stat_mailbox); 2568 2569 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2570 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2571 MLX4_CMD_NATIVE); 2572 2573 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2574 return err; 2575 } 2576 2577 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2578 { 2579 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2580 return; 2581 2582 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2583 return; 2584 2585 __mlx4_clear_if_stat(dev, idx); 2586 2587 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2588 return; 2589 } 2590 2591 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2592 { 2593 u64 in_param = 0; 2594 2595 if (mlx4_is_mfunc(dev)) { 2596 set_param_l(&in_param, idx); 2597 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2598 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2599 MLX4_CMD_WRAPPED); 2600 return; 2601 } 2602 __mlx4_counter_free(dev, idx); 2603 } 2604 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2605 2606 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2607 { 2608 struct mlx4_priv *priv = mlx4_priv(dev); 2609 2610 return priv->def_counter[port - 1]; 2611 } 2612 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2613 2614 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2615 { 2616 struct mlx4_priv *priv = mlx4_priv(dev); 2617 2618 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2619 } 2620 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2621 2622 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2623 { 2624 struct mlx4_priv *priv = mlx4_priv(dev); 2625 2626 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2627 } 2628 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2629 2630 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2631 { 2632 struct mlx4_priv *priv = mlx4_priv(dev); 2633 __be64 guid; 2634 2635 /* hw GUID */ 2636 if (entry == 0) 2637 return; 2638 2639 get_random_bytes((char *)&guid, sizeof(guid)); 2640 guid &= ~(cpu_to_be64(1ULL << 56)); 2641 guid |= cpu_to_be64(1ULL << 57); 2642 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2643 } 2644 2645 static int mlx4_setup_hca(struct mlx4_dev *dev) 2646 { 2647 struct mlx4_priv *priv = mlx4_priv(dev); 2648 int err; 2649 int port; 2650 __be32 ib_port_default_caps; 2651 2652 err = mlx4_init_uar_table(dev); 2653 if (err) { 2654 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2655 return err; 2656 } 2657 2658 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2659 if (err) { 2660 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2661 goto err_uar_table_free; 2662 } 2663 2664 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2665 if (!priv->kar) { 2666 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2667 err = -ENOMEM; 2668 goto err_uar_free; 2669 } 2670 2671 err = mlx4_init_pd_table(dev); 2672 if (err) { 2673 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2674 goto err_kar_unmap; 2675 } 2676 2677 err = mlx4_init_xrcd_table(dev); 2678 if (err) { 2679 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2680 goto err_pd_table_free; 2681 } 2682 2683 err = mlx4_init_mr_table(dev); 2684 if (err) { 2685 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2686 goto err_xrcd_table_free; 2687 } 2688 2689 if (!mlx4_is_slave(dev)) { 2690 err = mlx4_init_mcg_table(dev); 2691 if (err) { 2692 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2693 goto err_mr_table_free; 2694 } 2695 err = mlx4_config_mad_demux(dev); 2696 if (err) { 2697 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2698 goto err_mcg_table_free; 2699 } 2700 } 2701 2702 err = mlx4_init_eq_table(dev); 2703 if (err) { 2704 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2705 goto err_mcg_table_free; 2706 } 2707 2708 err = mlx4_cmd_use_events(dev); 2709 if (err) { 2710 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2711 goto err_eq_table_free; 2712 } 2713 2714 err = mlx4_NOP(dev); 2715 if (err) { 2716 if (dev->flags & MLX4_FLAG_MSI_X) { 2717 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2718 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2719 mlx4_warn(dev, "Trying again without MSI-X\n"); 2720 } else { 2721 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2722 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2723 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2724 } 2725 2726 goto err_cmd_poll; 2727 } 2728 2729 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2730 2731 err = mlx4_init_cq_table(dev); 2732 if (err) { 2733 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2734 goto err_cmd_poll; 2735 } 2736 2737 err = mlx4_init_srq_table(dev); 2738 if (err) { 2739 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2740 goto err_cq_table_free; 2741 } 2742 2743 err = mlx4_init_qp_table(dev); 2744 if (err) { 2745 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2746 goto err_srq_table_free; 2747 } 2748 2749 if (!mlx4_is_slave(dev)) { 2750 err = mlx4_init_counters_table(dev); 2751 if (err && err != -ENOENT) { 2752 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2753 goto err_qp_table_free; 2754 } 2755 } 2756 2757 err = mlx4_allocate_default_counters(dev); 2758 if (err) { 2759 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2760 goto err_counters_table_free; 2761 } 2762 2763 if (!mlx4_is_slave(dev)) { 2764 for (port = 1; port <= dev->caps.num_ports; port++) { 2765 ib_port_default_caps = 0; 2766 err = mlx4_get_port_ib_caps(dev, port, 2767 &ib_port_default_caps); 2768 if (err) 2769 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2770 port, err); 2771 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2772 2773 /* initialize per-slave default ib port capabilities */ 2774 if (mlx4_is_master(dev)) { 2775 int i; 2776 for (i = 0; i < dev->num_slaves; i++) { 2777 if (i == mlx4_master_func_num(dev)) 2778 continue; 2779 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2780 ib_port_default_caps; 2781 } 2782 } 2783 2784 if (mlx4_is_mfunc(dev)) 2785 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2786 else 2787 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2788 2789 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2790 dev->caps.pkey_table_len[port] : -1); 2791 if (err) { 2792 mlx4_err(dev, "Failed to set port %d, aborting\n", 2793 port); 2794 goto err_default_countes_free; 2795 } 2796 } 2797 } 2798 2799 return 0; 2800 2801 err_default_countes_free: 2802 mlx4_cleanup_default_counters(dev); 2803 2804 err_counters_table_free: 2805 if (!mlx4_is_slave(dev)) 2806 mlx4_cleanup_counters_table(dev); 2807 2808 err_qp_table_free: 2809 mlx4_cleanup_qp_table(dev); 2810 2811 err_srq_table_free: 2812 mlx4_cleanup_srq_table(dev); 2813 2814 err_cq_table_free: 2815 mlx4_cleanup_cq_table(dev); 2816 2817 err_cmd_poll: 2818 mlx4_cmd_use_polling(dev); 2819 2820 err_eq_table_free: 2821 mlx4_cleanup_eq_table(dev); 2822 2823 err_mcg_table_free: 2824 if (!mlx4_is_slave(dev)) 2825 mlx4_cleanup_mcg_table(dev); 2826 2827 err_mr_table_free: 2828 mlx4_cleanup_mr_table(dev); 2829 2830 err_xrcd_table_free: 2831 mlx4_cleanup_xrcd_table(dev); 2832 2833 err_pd_table_free: 2834 mlx4_cleanup_pd_table(dev); 2835 2836 err_kar_unmap: 2837 iounmap(priv->kar); 2838 2839 err_uar_free: 2840 mlx4_uar_free(dev, &priv->driver_uar); 2841 2842 err_uar_table_free: 2843 mlx4_cleanup_uar_table(dev); 2844 return err; 2845 } 2846 2847 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2848 { 2849 int requested_cpu = 0; 2850 struct mlx4_priv *priv = mlx4_priv(dev); 2851 struct mlx4_eq *eq; 2852 int off = 0; 2853 int i; 2854 2855 if (eqn > dev->caps.num_comp_vectors) 2856 return -EINVAL; 2857 2858 for (i = 1; i < port; i++) 2859 off += mlx4_get_eqs_per_port(dev, i); 2860 2861 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2862 2863 /* Meaning EQs are shared, and this call comes from the second port */ 2864 if (requested_cpu < 0) 2865 return 0; 2866 2867 eq = &priv->eq_table.eq[eqn]; 2868 2869 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2870 return -ENOMEM; 2871 2872 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2873 2874 return 0; 2875 } 2876 2877 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2878 { 2879 struct mlx4_priv *priv = mlx4_priv(dev); 2880 struct msix_entry *entries; 2881 int i; 2882 int port = 0; 2883 2884 if (msi_x) { 2885 int nreq = min3(dev->caps.num_ports * 2886 (int)num_online_cpus() + 1, 2887 dev->caps.num_eqs - dev->caps.reserved_eqs, 2888 MAX_MSIX); 2889 2890 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2891 if (!entries) 2892 goto no_msi; 2893 2894 for (i = 0; i < nreq; ++i) 2895 entries[i].entry = i; 2896 2897 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2898 nreq); 2899 2900 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2901 kfree(entries); 2902 goto no_msi; 2903 } 2904 /* 1 is reserved for events (asyncrounous EQ) */ 2905 dev->caps.num_comp_vectors = nreq - 1; 2906 2907 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2908 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2909 dev->caps.num_ports); 2910 2911 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2912 if (i == MLX4_EQ_ASYNC) 2913 continue; 2914 2915 priv->eq_table.eq[i].irq = 2916 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2917 2918 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2919 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2920 dev->caps.num_ports); 2921 /* We don't set affinity hint when there 2922 * aren't enough EQs 2923 */ 2924 } else { 2925 set_bit(port, 2926 priv->eq_table.eq[i].actv_ports.ports); 2927 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2928 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2929 i); 2930 } 2931 /* We divide the Eqs evenly between the two ports. 2932 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2933 * refers to the number of Eqs per port 2934 * (i.e eqs_per_port). Theoretically, we would like to 2935 * write something like (i + 1) % eqs_per_port == 0. 2936 * However, since there's an asynchronous Eq, we have 2937 * to skip over it by comparing this condition to 2938 * !!((i + 1) > MLX4_EQ_ASYNC). 2939 */ 2940 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2941 ((i + 1) % 2942 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 2943 !!((i + 1) > MLX4_EQ_ASYNC)) 2944 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 2945 * everything is shared anyway. 2946 */ 2947 port++; 2948 } 2949 2950 dev->flags |= MLX4_FLAG_MSI_X; 2951 2952 kfree(entries); 2953 return; 2954 } 2955 2956 no_msi: 2957 dev->caps.num_comp_vectors = 1; 2958 2959 BUG_ON(MLX4_EQ_ASYNC >= 2); 2960 for (i = 0; i < 2; ++i) { 2961 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 2962 if (i != MLX4_EQ_ASYNC) { 2963 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2964 dev->caps.num_ports); 2965 } 2966 } 2967 } 2968 2969 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2970 { 2971 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 2972 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2973 int err; 2974 2975 err = devlink_port_register(devlink, &info->devlink_port, port); 2976 if (err) 2977 return err; 2978 2979 info->dev = dev; 2980 info->port = port; 2981 if (!mlx4_is_slave(dev)) { 2982 mlx4_init_mac_table(dev, &info->mac_table); 2983 mlx4_init_vlan_table(dev, &info->vlan_table); 2984 mlx4_init_roce_gid_table(dev, &info->gid_table); 2985 info->base_qpn = mlx4_get_base_qpn(dev, port); 2986 } 2987 2988 sprintf(info->dev_name, "mlx4_port%d", port); 2989 info->port_attr.attr.name = info->dev_name; 2990 if (mlx4_is_mfunc(dev)) 2991 info->port_attr.attr.mode = S_IRUGO; 2992 else { 2993 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2994 info->port_attr.store = set_port_type; 2995 } 2996 info->port_attr.show = show_port_type; 2997 sysfs_attr_init(&info->port_attr.attr); 2998 2999 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3000 if (err) { 3001 mlx4_err(dev, "Failed to create file for port %d\n", port); 3002 devlink_port_unregister(&info->devlink_port); 3003 info->port = -1; 3004 } 3005 3006 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3007 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3008 if (mlx4_is_mfunc(dev)) 3009 info->port_mtu_attr.attr.mode = S_IRUGO; 3010 else { 3011 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 3012 info->port_mtu_attr.store = set_port_ib_mtu; 3013 } 3014 info->port_mtu_attr.show = show_port_ib_mtu; 3015 sysfs_attr_init(&info->port_mtu_attr.attr); 3016 3017 err = device_create_file(&dev->persist->pdev->dev, 3018 &info->port_mtu_attr); 3019 if (err) { 3020 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3021 device_remove_file(&info->dev->persist->pdev->dev, 3022 &info->port_attr); 3023 devlink_port_unregister(&info->devlink_port); 3024 info->port = -1; 3025 } 3026 3027 return err; 3028 } 3029 3030 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3031 { 3032 if (info->port < 0) 3033 return; 3034 3035 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3036 device_remove_file(&info->dev->persist->pdev->dev, 3037 &info->port_mtu_attr); 3038 devlink_port_unregister(&info->devlink_port); 3039 3040 #ifdef CONFIG_RFS_ACCEL 3041 free_irq_cpu_rmap(info->rmap); 3042 info->rmap = NULL; 3043 #endif 3044 } 3045 3046 static int mlx4_init_steering(struct mlx4_dev *dev) 3047 { 3048 struct mlx4_priv *priv = mlx4_priv(dev); 3049 int num_entries = dev->caps.num_ports; 3050 int i, j; 3051 3052 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 3053 if (!priv->steer) 3054 return -ENOMEM; 3055 3056 for (i = 0; i < num_entries; i++) 3057 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3058 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3059 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3060 } 3061 return 0; 3062 } 3063 3064 static void mlx4_clear_steering(struct mlx4_dev *dev) 3065 { 3066 struct mlx4_priv *priv = mlx4_priv(dev); 3067 struct mlx4_steer_index *entry, *tmp_entry; 3068 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3069 int num_entries = dev->caps.num_ports; 3070 int i, j; 3071 3072 for (i = 0; i < num_entries; i++) { 3073 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3074 list_for_each_entry_safe(pqp, tmp_pqp, 3075 &priv->steer[i].promisc_qps[j], 3076 list) { 3077 list_del(&pqp->list); 3078 kfree(pqp); 3079 } 3080 list_for_each_entry_safe(entry, tmp_entry, 3081 &priv->steer[i].steer_entries[j], 3082 list) { 3083 list_del(&entry->list); 3084 list_for_each_entry_safe(pqp, tmp_pqp, 3085 &entry->duplicates, 3086 list) { 3087 list_del(&pqp->list); 3088 kfree(pqp); 3089 } 3090 kfree(entry); 3091 } 3092 } 3093 } 3094 kfree(priv->steer); 3095 } 3096 3097 static int extended_func_num(struct pci_dev *pdev) 3098 { 3099 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3100 } 3101 3102 #define MLX4_OWNER_BASE 0x8069c 3103 #define MLX4_OWNER_SIZE 4 3104 3105 static int mlx4_get_ownership(struct mlx4_dev *dev) 3106 { 3107 void __iomem *owner; 3108 u32 ret; 3109 3110 if (pci_channel_offline(dev->persist->pdev)) 3111 return -EIO; 3112 3113 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3114 MLX4_OWNER_BASE, 3115 MLX4_OWNER_SIZE); 3116 if (!owner) { 3117 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3118 return -ENOMEM; 3119 } 3120 3121 ret = readl(owner); 3122 iounmap(owner); 3123 return (int) !!ret; 3124 } 3125 3126 static void mlx4_free_ownership(struct mlx4_dev *dev) 3127 { 3128 void __iomem *owner; 3129 3130 if (pci_channel_offline(dev->persist->pdev)) 3131 return; 3132 3133 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3134 MLX4_OWNER_BASE, 3135 MLX4_OWNER_SIZE); 3136 if (!owner) { 3137 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3138 return; 3139 } 3140 writel(0, owner); 3141 msleep(1000); 3142 iounmap(owner); 3143 } 3144 3145 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3146 !!((flags) & MLX4_FLAG_MASTER)) 3147 3148 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3149 u8 total_vfs, int existing_vfs, int reset_flow) 3150 { 3151 u64 dev_flags = dev->flags; 3152 int err = 0; 3153 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3154 MLX4_MAX_NUM_VF); 3155 3156 if (reset_flow) { 3157 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3158 GFP_KERNEL); 3159 if (!dev->dev_vfs) 3160 goto free_mem; 3161 return dev_flags; 3162 } 3163 3164 atomic_inc(&pf_loading); 3165 if (dev->flags & MLX4_FLAG_SRIOV) { 3166 if (existing_vfs != total_vfs) { 3167 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3168 existing_vfs, total_vfs); 3169 total_vfs = existing_vfs; 3170 } 3171 } 3172 3173 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL); 3174 if (NULL == dev->dev_vfs) { 3175 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3176 goto disable_sriov; 3177 } 3178 3179 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3180 if (total_vfs > fw_enabled_sriov_vfs) { 3181 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3182 total_vfs, fw_enabled_sriov_vfs); 3183 err = -ENOMEM; 3184 goto disable_sriov; 3185 } 3186 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3187 err = pci_enable_sriov(pdev, total_vfs); 3188 } 3189 if (err) { 3190 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3191 err); 3192 goto disable_sriov; 3193 } else { 3194 mlx4_warn(dev, "Running in master mode\n"); 3195 dev_flags |= MLX4_FLAG_SRIOV | 3196 MLX4_FLAG_MASTER; 3197 dev_flags &= ~MLX4_FLAG_SLAVE; 3198 dev->persist->num_vfs = total_vfs; 3199 } 3200 return dev_flags; 3201 3202 disable_sriov: 3203 atomic_dec(&pf_loading); 3204 free_mem: 3205 dev->persist->num_vfs = 0; 3206 kfree(dev->dev_vfs); 3207 dev->dev_vfs = NULL; 3208 return dev_flags & ~MLX4_FLAG_MASTER; 3209 } 3210 3211 enum { 3212 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3213 }; 3214 3215 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3216 int *nvfs) 3217 { 3218 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3219 /* Checking for 64 VFs as a limitation of CX2 */ 3220 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3221 requested_vfs >= 64) { 3222 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3223 requested_vfs); 3224 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3225 } 3226 return 0; 3227 } 3228 3229 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3230 { 3231 struct pci_dev *pdev = dev->persist->pdev; 3232 int err = 0; 3233 3234 mutex_lock(&dev->persist->pci_status_mutex); 3235 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3236 err = pci_enable_device(pdev); 3237 if (!err) 3238 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3239 } 3240 mutex_unlock(&dev->persist->pci_status_mutex); 3241 3242 return err; 3243 } 3244 3245 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3246 { 3247 struct pci_dev *pdev = dev->persist->pdev; 3248 3249 mutex_lock(&dev->persist->pci_status_mutex); 3250 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3251 pci_disable_device(pdev); 3252 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3253 } 3254 mutex_unlock(&dev->persist->pci_status_mutex); 3255 } 3256 3257 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3258 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3259 int reset_flow) 3260 { 3261 struct mlx4_dev *dev; 3262 unsigned sum = 0; 3263 int err; 3264 int port; 3265 int i; 3266 struct mlx4_dev_cap *dev_cap = NULL; 3267 int existing_vfs = 0; 3268 3269 dev = &priv->dev; 3270 3271 INIT_LIST_HEAD(&priv->ctx_list); 3272 spin_lock_init(&priv->ctx_lock); 3273 3274 mutex_init(&priv->port_mutex); 3275 mutex_init(&priv->bond_mutex); 3276 3277 INIT_LIST_HEAD(&priv->pgdir_list); 3278 mutex_init(&priv->pgdir_mutex); 3279 spin_lock_init(&priv->cmd.context_lock); 3280 3281 INIT_LIST_HEAD(&priv->bf_list); 3282 mutex_init(&priv->bf_mutex); 3283 3284 dev->rev_id = pdev->revision; 3285 dev->numa_node = dev_to_node(&pdev->dev); 3286 3287 /* Detect if this device is a virtual function */ 3288 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3289 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3290 dev->flags |= MLX4_FLAG_SLAVE; 3291 } else { 3292 /* We reset the device and enable SRIOV only for physical 3293 * devices. Try to claim ownership on the device; 3294 * if already taken, skip -- do not allow multiple PFs */ 3295 err = mlx4_get_ownership(dev); 3296 if (err) { 3297 if (err < 0) 3298 return err; 3299 else { 3300 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3301 return -EINVAL; 3302 } 3303 } 3304 3305 atomic_set(&priv->opreq_count, 0); 3306 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3307 3308 /* 3309 * Now reset the HCA before we touch the PCI capabilities or 3310 * attempt a firmware command, since a boot ROM may have left 3311 * the HCA in an undefined state. 3312 */ 3313 err = mlx4_reset(dev); 3314 if (err) { 3315 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3316 goto err_sriov; 3317 } 3318 3319 if (total_vfs) { 3320 dev->flags = MLX4_FLAG_MASTER; 3321 existing_vfs = pci_num_vf(pdev); 3322 if (existing_vfs) 3323 dev->flags |= MLX4_FLAG_SRIOV; 3324 dev->persist->num_vfs = total_vfs; 3325 } 3326 } 3327 3328 /* on load remove any previous indication of internal error, 3329 * device is up. 3330 */ 3331 dev->persist->state = MLX4_DEVICE_STATE_UP; 3332 3333 slave_start: 3334 err = mlx4_cmd_init(dev); 3335 if (err) { 3336 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3337 goto err_sriov; 3338 } 3339 3340 /* In slave functions, the communication channel must be initialized 3341 * before posting commands. Also, init num_slaves before calling 3342 * mlx4_init_hca */ 3343 if (mlx4_is_mfunc(dev)) { 3344 if (mlx4_is_master(dev)) { 3345 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3346 3347 } else { 3348 dev->num_slaves = 0; 3349 err = mlx4_multi_func_init(dev); 3350 if (err) { 3351 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3352 goto err_cmd; 3353 } 3354 } 3355 } 3356 3357 err = mlx4_init_fw(dev); 3358 if (err) { 3359 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3360 goto err_mfunc; 3361 } 3362 3363 if (mlx4_is_master(dev)) { 3364 /* when we hit the goto slave_start below, dev_cap already initialized */ 3365 if (!dev_cap) { 3366 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3367 3368 if (!dev_cap) { 3369 err = -ENOMEM; 3370 goto err_fw; 3371 } 3372 3373 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3374 if (err) { 3375 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3376 goto err_fw; 3377 } 3378 3379 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3380 goto err_fw; 3381 3382 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3383 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3384 total_vfs, 3385 existing_vfs, 3386 reset_flow); 3387 3388 mlx4_close_fw(dev); 3389 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3390 dev->flags = dev_flags; 3391 if (!SRIOV_VALID_STATE(dev->flags)) { 3392 mlx4_err(dev, "Invalid SRIOV state\n"); 3393 goto err_sriov; 3394 } 3395 err = mlx4_reset(dev); 3396 if (err) { 3397 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3398 goto err_sriov; 3399 } 3400 goto slave_start; 3401 } 3402 } else { 3403 /* Legacy mode FW requires SRIOV to be enabled before 3404 * doing QUERY_DEV_CAP, since max_eq's value is different if 3405 * SRIOV is enabled. 3406 */ 3407 memset(dev_cap, 0, sizeof(*dev_cap)); 3408 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3409 if (err) { 3410 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3411 goto err_fw; 3412 } 3413 3414 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3415 goto err_fw; 3416 } 3417 } 3418 3419 err = mlx4_init_hca(dev); 3420 if (err) { 3421 if (err == -EACCES) { 3422 /* Not primary Physical function 3423 * Running in slave mode */ 3424 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3425 /* We're not a PF */ 3426 if (dev->flags & MLX4_FLAG_SRIOV) { 3427 if (!existing_vfs) 3428 pci_disable_sriov(pdev); 3429 if (mlx4_is_master(dev) && !reset_flow) 3430 atomic_dec(&pf_loading); 3431 dev->flags &= ~MLX4_FLAG_SRIOV; 3432 } 3433 if (!mlx4_is_slave(dev)) 3434 mlx4_free_ownership(dev); 3435 dev->flags |= MLX4_FLAG_SLAVE; 3436 dev->flags &= ~MLX4_FLAG_MASTER; 3437 goto slave_start; 3438 } else 3439 goto err_fw; 3440 } 3441 3442 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3443 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3444 existing_vfs, reset_flow); 3445 3446 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3447 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3448 dev->flags = dev_flags; 3449 err = mlx4_cmd_init(dev); 3450 if (err) { 3451 /* Only VHCR is cleaned up, so could still 3452 * send FW commands 3453 */ 3454 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3455 goto err_close; 3456 } 3457 } else { 3458 dev->flags = dev_flags; 3459 } 3460 3461 if (!SRIOV_VALID_STATE(dev->flags)) { 3462 mlx4_err(dev, "Invalid SRIOV state\n"); 3463 goto err_close; 3464 } 3465 } 3466 3467 /* check if the device is functioning at its maximum possible speed. 3468 * No return code for this call, just warn the user in case of PCI 3469 * express device capabilities are under-satisfied by the bus. 3470 */ 3471 if (!mlx4_is_slave(dev)) 3472 mlx4_check_pcie_caps(dev); 3473 3474 /* In master functions, the communication channel must be initialized 3475 * after obtaining its address from fw */ 3476 if (mlx4_is_master(dev)) { 3477 if (dev->caps.num_ports < 2 && 3478 num_vfs_argc > 1) { 3479 err = -EINVAL; 3480 mlx4_err(dev, 3481 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3482 dev->caps.num_ports); 3483 goto err_close; 3484 } 3485 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3486 3487 for (i = 0; 3488 i < sizeof(dev->persist->nvfs)/ 3489 sizeof(dev->persist->nvfs[0]); i++) { 3490 unsigned j; 3491 3492 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3493 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3494 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3495 dev->caps.num_ports; 3496 } 3497 } 3498 3499 /* In master functions, the communication channel 3500 * must be initialized after obtaining its address from fw 3501 */ 3502 err = mlx4_multi_func_init(dev); 3503 if (err) { 3504 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3505 goto err_close; 3506 } 3507 } 3508 3509 err = mlx4_alloc_eq_table(dev); 3510 if (err) 3511 goto err_master_mfunc; 3512 3513 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3514 mutex_init(&priv->msix_ctl.pool_lock); 3515 3516 mlx4_enable_msi_x(dev); 3517 if ((mlx4_is_mfunc(dev)) && 3518 !(dev->flags & MLX4_FLAG_MSI_X)) { 3519 err = -EOPNOTSUPP; 3520 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3521 goto err_free_eq; 3522 } 3523 3524 if (!mlx4_is_slave(dev)) { 3525 err = mlx4_init_steering(dev); 3526 if (err) 3527 goto err_disable_msix; 3528 } 3529 3530 mlx4_init_quotas(dev); 3531 3532 err = mlx4_setup_hca(dev); 3533 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3534 !mlx4_is_mfunc(dev)) { 3535 dev->flags &= ~MLX4_FLAG_MSI_X; 3536 dev->caps.num_comp_vectors = 1; 3537 pci_disable_msix(pdev); 3538 err = mlx4_setup_hca(dev); 3539 } 3540 3541 if (err) 3542 goto err_steer; 3543 3544 /* When PF resources are ready arm its comm channel to enable 3545 * getting commands 3546 */ 3547 if (mlx4_is_master(dev)) { 3548 err = mlx4_ARM_COMM_CHANNEL(dev); 3549 if (err) { 3550 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3551 err); 3552 goto err_steer; 3553 } 3554 } 3555 3556 for (port = 1; port <= dev->caps.num_ports; port++) { 3557 err = mlx4_init_port_info(dev, port); 3558 if (err) 3559 goto err_port; 3560 } 3561 3562 priv->v2p.port1 = 1; 3563 priv->v2p.port2 = 2; 3564 3565 err = mlx4_register_device(dev); 3566 if (err) 3567 goto err_port; 3568 3569 mlx4_request_modules(dev); 3570 3571 mlx4_sense_init(dev); 3572 mlx4_start_sense(dev); 3573 3574 priv->removed = 0; 3575 3576 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3577 atomic_dec(&pf_loading); 3578 3579 kfree(dev_cap); 3580 return 0; 3581 3582 err_port: 3583 for (--port; port >= 1; --port) 3584 mlx4_cleanup_port_info(&priv->port[port]); 3585 3586 mlx4_cleanup_default_counters(dev); 3587 if (!mlx4_is_slave(dev)) 3588 mlx4_cleanup_counters_table(dev); 3589 mlx4_cleanup_qp_table(dev); 3590 mlx4_cleanup_srq_table(dev); 3591 mlx4_cleanup_cq_table(dev); 3592 mlx4_cmd_use_polling(dev); 3593 mlx4_cleanup_eq_table(dev); 3594 mlx4_cleanup_mcg_table(dev); 3595 mlx4_cleanup_mr_table(dev); 3596 mlx4_cleanup_xrcd_table(dev); 3597 mlx4_cleanup_pd_table(dev); 3598 mlx4_cleanup_uar_table(dev); 3599 3600 err_steer: 3601 if (!mlx4_is_slave(dev)) 3602 mlx4_clear_steering(dev); 3603 3604 err_disable_msix: 3605 if (dev->flags & MLX4_FLAG_MSI_X) 3606 pci_disable_msix(pdev); 3607 3608 err_free_eq: 3609 mlx4_free_eq_table(dev); 3610 3611 err_master_mfunc: 3612 if (mlx4_is_master(dev)) { 3613 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3614 mlx4_multi_func_cleanup(dev); 3615 } 3616 3617 if (mlx4_is_slave(dev)) 3618 mlx4_slave_destroy_special_qp_cap(dev); 3619 3620 err_close: 3621 mlx4_close_hca(dev); 3622 3623 err_fw: 3624 mlx4_close_fw(dev); 3625 3626 err_mfunc: 3627 if (mlx4_is_slave(dev)) 3628 mlx4_multi_func_cleanup(dev); 3629 3630 err_cmd: 3631 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3632 3633 err_sriov: 3634 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3635 pci_disable_sriov(pdev); 3636 dev->flags &= ~MLX4_FLAG_SRIOV; 3637 } 3638 3639 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3640 atomic_dec(&pf_loading); 3641 3642 kfree(priv->dev.dev_vfs); 3643 3644 if (!mlx4_is_slave(dev)) 3645 mlx4_free_ownership(dev); 3646 3647 kfree(dev_cap); 3648 return err; 3649 } 3650 3651 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3652 struct mlx4_priv *priv) 3653 { 3654 int err; 3655 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3656 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3657 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3658 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3659 unsigned total_vfs = 0; 3660 unsigned int i; 3661 3662 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3663 3664 err = mlx4_pci_enable_device(&priv->dev); 3665 if (err) { 3666 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3667 return err; 3668 } 3669 3670 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3671 * per port, we must limit the number of VFs to 63 (since their are 3672 * 128 MACs) 3673 */ 3674 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 3675 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3676 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3677 if (nvfs[i] < 0) { 3678 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3679 err = -EINVAL; 3680 goto err_disable_pdev; 3681 } 3682 } 3683 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 3684 i++) { 3685 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3686 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3687 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3688 err = -EINVAL; 3689 goto err_disable_pdev; 3690 } 3691 } 3692 if (total_vfs > MLX4_MAX_NUM_VF) { 3693 dev_err(&pdev->dev, 3694 "Requested more VF's (%d) than allowed by hw (%d)\n", 3695 total_vfs, MLX4_MAX_NUM_VF); 3696 err = -EINVAL; 3697 goto err_disable_pdev; 3698 } 3699 3700 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3701 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3702 dev_err(&pdev->dev, 3703 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3704 nvfs[i] + nvfs[2], i + 1, 3705 MLX4_MAX_NUM_VF_P_PORT); 3706 err = -EINVAL; 3707 goto err_disable_pdev; 3708 } 3709 } 3710 3711 /* Check for BARs. */ 3712 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3713 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3714 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3715 pci_dev_data, pci_resource_flags(pdev, 0)); 3716 err = -ENODEV; 3717 goto err_disable_pdev; 3718 } 3719 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3720 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3721 err = -ENODEV; 3722 goto err_disable_pdev; 3723 } 3724 3725 err = pci_request_regions(pdev, DRV_NAME); 3726 if (err) { 3727 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3728 goto err_disable_pdev; 3729 } 3730 3731 pci_set_master(pdev); 3732 3733 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3734 if (err) { 3735 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3736 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3737 if (err) { 3738 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3739 goto err_release_regions; 3740 } 3741 } 3742 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3743 if (err) { 3744 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3745 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3746 if (err) { 3747 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3748 goto err_release_regions; 3749 } 3750 } 3751 3752 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3753 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3754 /* Detect if this device is a virtual function */ 3755 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3756 /* When acting as pf, we normally skip vfs unless explicitly 3757 * requested to probe them. 3758 */ 3759 if (total_vfs) { 3760 unsigned vfs_offset = 0; 3761 3762 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 3763 vfs_offset + nvfs[i] < extended_func_num(pdev); 3764 vfs_offset += nvfs[i], i++) 3765 ; 3766 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 3767 err = -ENODEV; 3768 goto err_release_regions; 3769 } 3770 if ((extended_func_num(pdev) - vfs_offset) 3771 > prb_vf[i]) { 3772 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3773 extended_func_num(pdev)); 3774 err = -ENODEV; 3775 goto err_release_regions; 3776 } 3777 } 3778 } 3779 3780 err = mlx4_catas_init(&priv->dev); 3781 if (err) 3782 goto err_release_regions; 3783 3784 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3785 if (err) 3786 goto err_catas; 3787 3788 return 0; 3789 3790 err_catas: 3791 mlx4_catas_end(&priv->dev); 3792 3793 err_release_regions: 3794 pci_release_regions(pdev); 3795 3796 err_disable_pdev: 3797 mlx4_pci_disable_device(&priv->dev); 3798 return err; 3799 } 3800 3801 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3802 enum devlink_port_type port_type) 3803 { 3804 struct mlx4_port_info *info = container_of(devlink_port, 3805 struct mlx4_port_info, 3806 devlink_port); 3807 enum mlx4_port_type mlx4_port_type; 3808 3809 switch (port_type) { 3810 case DEVLINK_PORT_TYPE_AUTO: 3811 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3812 break; 3813 case DEVLINK_PORT_TYPE_ETH: 3814 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3815 break; 3816 case DEVLINK_PORT_TYPE_IB: 3817 mlx4_port_type = MLX4_PORT_TYPE_IB; 3818 break; 3819 default: 3820 return -EOPNOTSUPP; 3821 } 3822 3823 return __set_port_type(info, mlx4_port_type); 3824 } 3825 3826 static const struct devlink_ops mlx4_devlink_ops = { 3827 .port_type_set = mlx4_devlink_port_type_set, 3828 }; 3829 3830 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3831 { 3832 struct devlink *devlink; 3833 struct mlx4_priv *priv; 3834 struct mlx4_dev *dev; 3835 int ret; 3836 3837 printk_once(KERN_INFO "%s", mlx4_version); 3838 3839 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3840 if (!devlink) 3841 return -ENOMEM; 3842 priv = devlink_priv(devlink); 3843 3844 dev = &priv->dev; 3845 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3846 if (!dev->persist) { 3847 ret = -ENOMEM; 3848 goto err_devlink_free; 3849 } 3850 dev->persist->pdev = pdev; 3851 dev->persist->dev = dev; 3852 pci_set_drvdata(pdev, dev->persist); 3853 priv->pci_dev_data = id->driver_data; 3854 mutex_init(&dev->persist->device_state_mutex); 3855 mutex_init(&dev->persist->interface_state_mutex); 3856 mutex_init(&dev->persist->pci_status_mutex); 3857 3858 ret = devlink_register(devlink, &pdev->dev); 3859 if (ret) 3860 goto err_persist_free; 3861 3862 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3863 if (ret) 3864 goto err_devlink_unregister; 3865 3866 pci_save_state(pdev); 3867 return 0; 3868 3869 err_devlink_unregister: 3870 devlink_unregister(devlink); 3871 err_persist_free: 3872 kfree(dev->persist); 3873 err_devlink_free: 3874 devlink_free(devlink); 3875 return ret; 3876 } 3877 3878 static void mlx4_clean_dev(struct mlx4_dev *dev) 3879 { 3880 struct mlx4_dev_persistent *persist = dev->persist; 3881 struct mlx4_priv *priv = mlx4_priv(dev); 3882 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 3883 3884 memset(priv, 0, sizeof(*priv)); 3885 priv->dev.persist = persist; 3886 priv->dev.flags = flags; 3887 } 3888 3889 static void mlx4_unload_one(struct pci_dev *pdev) 3890 { 3891 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3892 struct mlx4_dev *dev = persist->dev; 3893 struct mlx4_priv *priv = mlx4_priv(dev); 3894 int pci_dev_data; 3895 int p, i; 3896 3897 if (priv->removed) 3898 return; 3899 3900 /* saving current ports type for further use */ 3901 for (i = 0; i < dev->caps.num_ports; i++) { 3902 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 3903 dev->persist->curr_port_poss_type[i] = dev->caps. 3904 possible_type[i + 1]; 3905 } 3906 3907 pci_dev_data = priv->pci_dev_data; 3908 3909 mlx4_stop_sense(dev); 3910 mlx4_unregister_device(dev); 3911 3912 for (p = 1; p <= dev->caps.num_ports; p++) { 3913 mlx4_cleanup_port_info(&priv->port[p]); 3914 mlx4_CLOSE_PORT(dev, p); 3915 } 3916 3917 if (mlx4_is_master(dev)) 3918 mlx4_free_resource_tracker(dev, 3919 RES_TR_FREE_SLAVES_ONLY); 3920 3921 mlx4_cleanup_default_counters(dev); 3922 if (!mlx4_is_slave(dev)) 3923 mlx4_cleanup_counters_table(dev); 3924 mlx4_cleanup_qp_table(dev); 3925 mlx4_cleanup_srq_table(dev); 3926 mlx4_cleanup_cq_table(dev); 3927 mlx4_cmd_use_polling(dev); 3928 mlx4_cleanup_eq_table(dev); 3929 mlx4_cleanup_mcg_table(dev); 3930 mlx4_cleanup_mr_table(dev); 3931 mlx4_cleanup_xrcd_table(dev); 3932 mlx4_cleanup_pd_table(dev); 3933 3934 if (mlx4_is_master(dev)) 3935 mlx4_free_resource_tracker(dev, 3936 RES_TR_FREE_STRUCTS_ONLY); 3937 3938 iounmap(priv->kar); 3939 mlx4_uar_free(dev, &priv->driver_uar); 3940 mlx4_cleanup_uar_table(dev); 3941 if (!mlx4_is_slave(dev)) 3942 mlx4_clear_steering(dev); 3943 mlx4_free_eq_table(dev); 3944 if (mlx4_is_master(dev)) 3945 mlx4_multi_func_cleanup(dev); 3946 mlx4_close_hca(dev); 3947 mlx4_close_fw(dev); 3948 if (mlx4_is_slave(dev)) 3949 mlx4_multi_func_cleanup(dev); 3950 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3951 3952 if (dev->flags & MLX4_FLAG_MSI_X) 3953 pci_disable_msix(pdev); 3954 3955 if (!mlx4_is_slave(dev)) 3956 mlx4_free_ownership(dev); 3957 3958 mlx4_slave_destroy_special_qp_cap(dev); 3959 kfree(dev->dev_vfs); 3960 3961 mlx4_clean_dev(dev); 3962 priv->pci_dev_data = pci_dev_data; 3963 priv->removed = 1; 3964 } 3965 3966 static void mlx4_remove_one(struct pci_dev *pdev) 3967 { 3968 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3969 struct mlx4_dev *dev = persist->dev; 3970 struct mlx4_priv *priv = mlx4_priv(dev); 3971 struct devlink *devlink = priv_to_devlink(priv); 3972 int active_vfs = 0; 3973 3974 if (mlx4_is_slave(dev)) 3975 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 3976 3977 mutex_lock(&persist->interface_state_mutex); 3978 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 3979 mutex_unlock(&persist->interface_state_mutex); 3980 3981 /* Disabling SR-IOV is not allowed while there are active vf's */ 3982 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 3983 active_vfs = mlx4_how_many_lives_vf(dev); 3984 if (active_vfs) { 3985 pr_warn("Removing PF when there are active VF's !!\n"); 3986 pr_warn("Will not disable SR-IOV.\n"); 3987 } 3988 } 3989 3990 /* device marked to be under deletion running now without the lock 3991 * letting other tasks to be terminated 3992 */ 3993 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3994 mlx4_unload_one(pdev); 3995 else 3996 mlx4_info(dev, "%s: interface is down\n", __func__); 3997 mlx4_catas_end(dev); 3998 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 3999 mlx4_warn(dev, "Disabling SR-IOV\n"); 4000 pci_disable_sriov(pdev); 4001 } 4002 4003 pci_release_regions(pdev); 4004 mlx4_pci_disable_device(dev); 4005 devlink_unregister(devlink); 4006 kfree(dev->persist); 4007 devlink_free(devlink); 4008 } 4009 4010 static int restore_current_port_types(struct mlx4_dev *dev, 4011 enum mlx4_port_type *types, 4012 enum mlx4_port_type *poss_types) 4013 { 4014 struct mlx4_priv *priv = mlx4_priv(dev); 4015 int err, i; 4016 4017 mlx4_stop_sense(dev); 4018 4019 mutex_lock(&priv->port_mutex); 4020 for (i = 0; i < dev->caps.num_ports; i++) 4021 dev->caps.possible_type[i + 1] = poss_types[i]; 4022 err = mlx4_change_port_types(dev, types); 4023 mlx4_start_sense(dev); 4024 mutex_unlock(&priv->port_mutex); 4025 4026 return err; 4027 } 4028 4029 int mlx4_restart_one(struct pci_dev *pdev) 4030 { 4031 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4032 struct mlx4_dev *dev = persist->dev; 4033 struct mlx4_priv *priv = mlx4_priv(dev); 4034 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4035 int pci_dev_data, err, total_vfs; 4036 4037 pci_dev_data = priv->pci_dev_data; 4038 total_vfs = dev->persist->num_vfs; 4039 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4040 4041 mlx4_unload_one(pdev); 4042 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4043 if (err) { 4044 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4045 __func__, pci_name(pdev), err); 4046 return err; 4047 } 4048 4049 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4050 dev->persist->curr_port_poss_type); 4051 if (err) 4052 mlx4_err(dev, "could not restore original port types (%d)\n", 4053 err); 4054 4055 return err; 4056 } 4057 4058 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4059 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4060 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4061 4062 static const struct pci_device_id mlx4_pci_table[] = { 4063 /* MT25408 "Hermon" */ 4064 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4065 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4066 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4067 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4068 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4069 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4070 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4071 /* MT25458 ConnectX EN 10GBASE-T */ 4072 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4073 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4074 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4075 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4076 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4077 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4078 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4079 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4080 /* MT25400 Family [ConnectX-2] */ 4081 MLX_VF(0x1002), /* Virtual Function */ 4082 /* MT27500 Family [ConnectX-3] */ 4083 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4084 MLX_VF(0x1004), /* Virtual Function */ 4085 MLX_GN(0x1005), /* MT27510 Family */ 4086 MLX_GN(0x1006), /* MT27511 Family */ 4087 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4088 MLX_GN(0x1008), /* MT27521 Family */ 4089 MLX_GN(0x1009), /* MT27530 Family */ 4090 MLX_GN(0x100a), /* MT27531 Family */ 4091 MLX_GN(0x100b), /* MT27540 Family */ 4092 MLX_GN(0x100c), /* MT27541 Family */ 4093 MLX_GN(0x100d), /* MT27550 Family */ 4094 MLX_GN(0x100e), /* MT27551 Family */ 4095 MLX_GN(0x100f), /* MT27560 Family */ 4096 MLX_GN(0x1010), /* MT27561 Family */ 4097 4098 /* 4099 * See the mellanox_check_broken_intx_masking() quirk when 4100 * adding devices 4101 */ 4102 4103 { 0, } 4104 }; 4105 4106 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4107 4108 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4109 pci_channel_state_t state) 4110 { 4111 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4112 4113 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4114 mlx4_enter_error_state(persist); 4115 4116 mutex_lock(&persist->interface_state_mutex); 4117 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4118 mlx4_unload_one(pdev); 4119 4120 mutex_unlock(&persist->interface_state_mutex); 4121 if (state == pci_channel_io_perm_failure) 4122 return PCI_ERS_RESULT_DISCONNECT; 4123 4124 mlx4_pci_disable_device(persist->dev); 4125 return PCI_ERS_RESULT_NEED_RESET; 4126 } 4127 4128 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4129 { 4130 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4131 struct mlx4_dev *dev = persist->dev; 4132 int err; 4133 4134 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4135 err = mlx4_pci_enable_device(dev); 4136 if (err) { 4137 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4138 return PCI_ERS_RESULT_DISCONNECT; 4139 } 4140 4141 pci_set_master(pdev); 4142 pci_restore_state(pdev); 4143 pci_save_state(pdev); 4144 return PCI_ERS_RESULT_RECOVERED; 4145 } 4146 4147 static void mlx4_pci_resume(struct pci_dev *pdev) 4148 { 4149 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4150 struct mlx4_dev *dev = persist->dev; 4151 struct mlx4_priv *priv = mlx4_priv(dev); 4152 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4153 int total_vfs; 4154 int err; 4155 4156 mlx4_err(dev, "%s was called\n", __func__); 4157 total_vfs = dev->persist->num_vfs; 4158 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4159 4160 mutex_lock(&persist->interface_state_mutex); 4161 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4162 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4163 priv, 1); 4164 if (err) { 4165 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4166 __func__, err); 4167 goto end; 4168 } 4169 4170 err = restore_current_port_types(dev, dev->persist-> 4171 curr_port_type, dev->persist-> 4172 curr_port_poss_type); 4173 if (err) 4174 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4175 } 4176 end: 4177 mutex_unlock(&persist->interface_state_mutex); 4178 4179 } 4180 4181 static void mlx4_shutdown(struct pci_dev *pdev) 4182 { 4183 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4184 4185 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4186 mutex_lock(&persist->interface_state_mutex); 4187 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4188 mlx4_unload_one(pdev); 4189 mutex_unlock(&persist->interface_state_mutex); 4190 } 4191 4192 static const struct pci_error_handlers mlx4_err_handler = { 4193 .error_detected = mlx4_pci_err_detected, 4194 .slot_reset = mlx4_pci_slot_reset, 4195 .resume = mlx4_pci_resume, 4196 }; 4197 4198 static struct pci_driver mlx4_driver = { 4199 .name = DRV_NAME, 4200 .id_table = mlx4_pci_table, 4201 .probe = mlx4_init_one, 4202 .shutdown = mlx4_shutdown, 4203 .remove = mlx4_remove_one, 4204 .err_handler = &mlx4_err_handler, 4205 }; 4206 4207 static int __init mlx4_verify_params(void) 4208 { 4209 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4210 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4211 return -1; 4212 } 4213 4214 if (log_num_vlan != 0) 4215 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4216 MLX4_LOG_NUM_VLANS); 4217 4218 if (use_prio != 0) 4219 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4220 4221 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 4222 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4223 log_mtts_per_seg); 4224 return -1; 4225 } 4226 4227 /* Check if module param for ports type has legal combination */ 4228 if (port_type_array[0] == false && port_type_array[1] == true) { 4229 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4230 port_type_array[0] = true; 4231 } 4232 4233 if (mlx4_log_num_mgm_entry_size < -7 || 4234 (mlx4_log_num_mgm_entry_size > 0 && 4235 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4236 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4237 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4238 mlx4_log_num_mgm_entry_size, 4239 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4240 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4241 return -1; 4242 } 4243 4244 return 0; 4245 } 4246 4247 static int __init mlx4_init(void) 4248 { 4249 int ret; 4250 4251 if (mlx4_verify_params()) 4252 return -EINVAL; 4253 4254 4255 mlx4_wq = create_singlethread_workqueue("mlx4"); 4256 if (!mlx4_wq) 4257 return -ENOMEM; 4258 4259 ret = pci_register_driver(&mlx4_driver); 4260 if (ret < 0) 4261 destroy_workqueue(mlx4_wq); 4262 return ret < 0 ? ret : 0; 4263 } 4264 4265 static void __exit mlx4_cleanup(void) 4266 { 4267 pci_unregister_driver(&mlx4_driver); 4268 destroy_workqueue(mlx4_wq); 4269 } 4270 4271 module_init(mlx4_init); 4272 module_exit(mlx4_cleanup); 4273