1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 45 #include <linux/mlx4/device.h> 46 #include <linux/mlx4/doorbell.h> 47 48 #include "mlx4.h" 49 #include "fw.h" 50 #include "icm.h" 51 52 MODULE_AUTHOR("Roland Dreier"); 53 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 54 MODULE_LICENSE("Dual BSD/GPL"); 55 MODULE_VERSION(DRV_VERSION); 56 57 struct workqueue_struct *mlx4_wq; 58 59 #ifdef CONFIG_MLX4_DEBUG 60 61 int mlx4_debug_level = 0; 62 module_param_named(debug_level, mlx4_debug_level, int, 0644); 63 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 64 65 #endif /* CONFIG_MLX4_DEBUG */ 66 67 #ifdef CONFIG_PCI_MSI 68 69 static int msi_x = 1; 70 module_param(msi_x, int, 0444); 71 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 72 73 #else /* CONFIG_PCI_MSI */ 74 75 #define msi_x (0) 76 77 #endif /* CONFIG_PCI_MSI */ 78 79 static int num_vfs; 80 module_param(num_vfs, int, 0444); 81 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0"); 82 83 static int probe_vf; 84 module_param(probe_vf, int, 0644); 85 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); 86 87 int mlx4_log_num_mgm_entry_size = 10; 88 module_param_named(log_num_mgm_entry_size, 89 mlx4_log_num_mgm_entry_size, int, 0444); 90 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 91 " of qp per mcg, for example:" 92 " 10 gives 248.range: 9<=" 93 " log_num_mgm_entry_size <= 12"); 94 95 #define MLX4_VF (1 << 0) 96 97 #define HCA_GLOBAL_CAP_MASK 0 98 #define PF_CONTEXT_BEHAVIOUR_MASK 0 99 100 static char mlx4_version[] __devinitdata = 101 DRV_NAME ": Mellanox ConnectX core driver v" 102 DRV_VERSION " (" DRV_RELDATE ")\n"; 103 104 static struct mlx4_profile default_profile = { 105 .num_qp = 1 << 18, 106 .num_srq = 1 << 16, 107 .rdmarc_per_qp = 1 << 4, 108 .num_cq = 1 << 16, 109 .num_mcg = 1 << 13, 110 .num_mpt = 1 << 19, 111 .num_mtt = 1 << 20, /* It is really num mtt segements */ 112 }; 113 114 static int log_num_mac = 7; 115 module_param_named(log_num_mac, log_num_mac, int, 0444); 116 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 117 118 static int log_num_vlan; 119 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 120 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 121 /* Log2 max number of VLANs per ETH port (0-7) */ 122 #define MLX4_LOG_NUM_VLANS 7 123 124 static bool use_prio; 125 module_param_named(use_prio, use_prio, bool, 0444); 126 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " 127 "(0/1, default 0)"); 128 129 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 130 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 131 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 132 133 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 134 static int arr_argc = 2; 135 module_param_array(port_type_array, int, &arr_argc, 0444); 136 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 137 "1 for IB, 2 for Ethernet"); 138 139 struct mlx4_port_config { 140 struct list_head list; 141 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 142 struct pci_dev *pdev; 143 }; 144 145 static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev) 146 { 147 return dev->caps.reserved_eqs + 148 MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1); 149 } 150 151 int mlx4_check_port_params(struct mlx4_dev *dev, 152 enum mlx4_port_type *port_type) 153 { 154 int i; 155 156 for (i = 0; i < dev->caps.num_ports - 1; i++) { 157 if (port_type[i] != port_type[i + 1]) { 158 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 159 mlx4_err(dev, "Only same port types supported " 160 "on this HCA, aborting.\n"); 161 return -EINVAL; 162 } 163 if (port_type[i] == MLX4_PORT_TYPE_ETH && 164 port_type[i + 1] == MLX4_PORT_TYPE_IB) 165 return -EINVAL; 166 } 167 } 168 169 for (i = 0; i < dev->caps.num_ports; i++) { 170 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 171 mlx4_err(dev, "Requested port type for port %d is not " 172 "supported on this HCA\n", i + 1); 173 return -EINVAL; 174 } 175 } 176 return 0; 177 } 178 179 static void mlx4_set_port_mask(struct mlx4_dev *dev) 180 { 181 int i; 182 183 for (i = 1; i <= dev->caps.num_ports; ++i) 184 dev->caps.port_mask[i] = dev->caps.port_type[i]; 185 } 186 187 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 188 { 189 int err; 190 int i; 191 192 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 193 if (err) { 194 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 195 return err; 196 } 197 198 if (dev_cap->min_page_sz > PAGE_SIZE) { 199 mlx4_err(dev, "HCA minimum page size of %d bigger than " 200 "kernel PAGE_SIZE of %ld, aborting.\n", 201 dev_cap->min_page_sz, PAGE_SIZE); 202 return -ENODEV; 203 } 204 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 205 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 206 "aborting.\n", 207 dev_cap->num_ports, MLX4_MAX_PORTS); 208 return -ENODEV; 209 } 210 211 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 212 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " 213 "PCI resource 2 size of 0x%llx, aborting.\n", 214 dev_cap->uar_size, 215 (unsigned long long) pci_resource_len(dev->pdev, 2)); 216 return -ENODEV; 217 } 218 219 dev->caps.num_ports = dev_cap->num_ports; 220 for (i = 1; i <= dev->caps.num_ports; ++i) { 221 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 222 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 223 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 224 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 225 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 226 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 227 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 228 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 229 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 230 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 231 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 232 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 233 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 234 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 235 } 236 237 dev->caps.uar_page_size = PAGE_SIZE; 238 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 239 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 240 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 241 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 242 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 243 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 244 dev->caps.max_wqes = dev_cap->max_qp_sz; 245 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 246 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 247 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 248 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 249 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 250 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 251 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 252 /* 253 * Subtract 1 from the limit because we need to allocate a 254 * spare CQE so the HCA HW can tell the difference between an 255 * empty CQ and a full CQ. 256 */ 257 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 258 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 259 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 260 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 261 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 262 263 /* The first 128 UARs are used for EQ doorbells */ 264 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 265 dev->caps.reserved_pds = dev_cap->reserved_pds; 266 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 267 dev_cap->reserved_xrcds : 0; 268 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 269 dev_cap->max_xrcds : 0; 270 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 271 272 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 273 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 274 dev->caps.flags = dev_cap->flags; 275 dev->caps.flags2 = dev_cap->flags2; 276 dev->caps.bmme_flags = dev_cap->bmme_flags; 277 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 278 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 279 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 280 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 281 282 /* Sense port always allowed on supported devices for ConnectX1 and 2 */ 283 if (dev->pdev->device != 0x1003) 284 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 285 286 dev->caps.log_num_macs = log_num_mac; 287 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 288 dev->caps.log_num_prios = use_prio ? 3 : 0; 289 290 for (i = 1; i <= dev->caps.num_ports; ++i) { 291 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 292 if (dev->caps.supported_type[i]) { 293 /* if only ETH is supported - assign ETH */ 294 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 295 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 296 /* if only IB is supported, 297 * assign IB only if SRIOV is off*/ 298 else if (dev->caps.supported_type[i] == 299 MLX4_PORT_TYPE_IB) { 300 if (dev->flags & MLX4_FLAG_SRIOV) 301 dev->caps.port_type[i] = 302 MLX4_PORT_TYPE_NONE; 303 else 304 dev->caps.port_type[i] = 305 MLX4_PORT_TYPE_IB; 306 /* if IB and ETH are supported, 307 * first of all check if SRIOV is on */ 308 } else if (dev->flags & MLX4_FLAG_SRIOV) 309 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 310 else { 311 /* In non-SRIOV mode, we set the port type 312 * according to user selection of port type, 313 * if usere selected none, take the FW hint */ 314 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE) 315 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 316 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 317 else 318 dev->caps.port_type[i] = port_type_array[i-1]; 319 } 320 } 321 /* 322 * Link sensing is allowed on the port if 3 conditions are true: 323 * 1. Both protocols are supported on the port. 324 * 2. Different types are supported on the port 325 * 3. FW declared that it supports link sensing 326 */ 327 mlx4_priv(dev)->sense.sense_allowed[i] = 328 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 329 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 330 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 331 332 /* 333 * If "default_sense" bit is set, we move the port to "AUTO" mode 334 * and perform sense_port FW command to try and set the correct 335 * port type from beginning 336 */ 337 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 338 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 339 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 340 mlx4_SENSE_PORT(dev, i, &sensed_port); 341 if (sensed_port != MLX4_PORT_TYPE_NONE) 342 dev->caps.port_type[i] = sensed_port; 343 } else { 344 dev->caps.possible_type[i] = dev->caps.port_type[i]; 345 } 346 347 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 348 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 349 mlx4_warn(dev, "Requested number of MACs is too much " 350 "for port %d, reducing to %d.\n", 351 i, 1 << dev->caps.log_num_macs); 352 } 353 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 354 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 355 mlx4_warn(dev, "Requested number of VLANs is too much " 356 "for port %d, reducing to %d.\n", 357 i, 1 << dev->caps.log_num_vlans); 358 } 359 } 360 361 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 362 363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 364 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 366 (1 << dev->caps.log_num_macs) * 367 (1 << dev->caps.log_num_vlans) * 368 (1 << dev->caps.log_num_prios) * 369 dev->caps.num_ports; 370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 371 372 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 376 377 return 0; 378 } 379 /*The function checks if there are live vf, return the num of them*/ 380 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 381 { 382 struct mlx4_priv *priv = mlx4_priv(dev); 383 struct mlx4_slave_state *s_state; 384 int i; 385 int ret = 0; 386 387 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 388 s_state = &priv->mfunc.master.slave_state[i]; 389 if (s_state->active && s_state->last_cmd != 390 MLX4_COMM_CMD_RESET) { 391 mlx4_warn(dev, "%s: slave: %d is still active\n", 392 __func__, i); 393 ret++; 394 } 395 } 396 return ret; 397 } 398 399 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 400 { 401 struct mlx4_priv *priv = mlx4_priv(dev); 402 struct mlx4_slave_state *s_slave; 403 404 if (!mlx4_is_master(dev)) 405 return 0; 406 407 s_slave = &priv->mfunc.master.slave_state[slave]; 408 return !!s_slave->active; 409 } 410 EXPORT_SYMBOL(mlx4_is_slave_active); 411 412 static int mlx4_slave_cap(struct mlx4_dev *dev) 413 { 414 int err; 415 u32 page_size; 416 struct mlx4_dev_cap dev_cap; 417 struct mlx4_func_cap func_cap; 418 struct mlx4_init_hca_param hca_param; 419 int i; 420 421 memset(&hca_param, 0, sizeof(hca_param)); 422 err = mlx4_QUERY_HCA(dev, &hca_param); 423 if (err) { 424 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); 425 return err; 426 } 427 428 /*fail if the hca has an unknown capability */ 429 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != 430 HCA_GLOBAL_CAP_MASK) { 431 mlx4_err(dev, "Unknown hca global capabilities\n"); 432 return -ENOSYS; 433 } 434 435 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 436 437 memset(&dev_cap, 0, sizeof(dev_cap)); 438 err = mlx4_dev_cap(dev, &dev_cap); 439 if (err) { 440 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 441 return err; 442 } 443 444 page_size = ~dev->caps.page_size_cap + 1; 445 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 446 if (page_size > PAGE_SIZE) { 447 mlx4_err(dev, "HCA minimum page size of %d bigger than " 448 "kernel PAGE_SIZE of %ld, aborting.\n", 449 page_size, PAGE_SIZE); 450 return -ENODEV; 451 } 452 453 /* slave gets uar page size from QUERY_HCA fw command */ 454 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 455 456 /* TODO: relax this assumption */ 457 if (dev->caps.uar_page_size != PAGE_SIZE) { 458 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 459 dev->caps.uar_page_size, PAGE_SIZE); 460 return -ENODEV; 461 } 462 463 memset(&func_cap, 0, sizeof(func_cap)); 464 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap); 465 if (err) { 466 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n"); 467 return err; 468 } 469 470 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 471 PF_CONTEXT_BEHAVIOUR_MASK) { 472 mlx4_err(dev, "Unknown pf context behaviour\n"); 473 return -ENOSYS; 474 } 475 476 dev->caps.num_ports = func_cap.num_ports; 477 dev->caps.num_qps = func_cap.qp_quota; 478 dev->caps.num_srqs = func_cap.srq_quota; 479 dev->caps.num_cqs = func_cap.cq_quota; 480 dev->caps.num_eqs = func_cap.max_eq; 481 dev->caps.reserved_eqs = func_cap.reserved_eq; 482 dev->caps.num_mpts = func_cap.mpt_quota; 483 dev->caps.num_mtts = func_cap.mtt_quota; 484 dev->caps.num_pds = MLX4_NUM_PDS; 485 dev->caps.num_mgms = 0; 486 dev->caps.num_amgms = 0; 487 488 for (i = 1; i <= dev->caps.num_ports; ++i) 489 dev->caps.port_mask[i] = dev->caps.port_type[i]; 490 491 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 492 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 493 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); 494 return -ENODEV; 495 } 496 497 if (dev->caps.uar_page_size * (dev->caps.num_uars - 498 dev->caps.reserved_uars) > 499 pci_resource_len(dev->pdev, 2)) { 500 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " 501 "PCI resource 2 size of 0x%llx, aborting.\n", 502 dev->caps.uar_page_size * dev->caps.num_uars, 503 (unsigned long long) pci_resource_len(dev->pdev, 2)); 504 return -ENODEV; 505 } 506 507 #if 0 508 mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux); 509 mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n", 510 dev->caps.num_uars, dev->caps.reserved_uars, 511 dev->caps.uar_page_size * dev->caps.num_uars, 512 pci_resource_len(dev->pdev, 2)); 513 mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs, 514 dev->caps.reserved_eqs); 515 mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n", 516 dev->caps.num_pds, dev->caps.reserved_pds, 517 dev->caps.slave_pd_shift, dev->caps.pd_base); 518 #endif 519 return 0; 520 } 521 522 /* 523 * Change the port configuration of the device. 524 * Every user of this function must hold the port mutex. 525 */ 526 int mlx4_change_port_types(struct mlx4_dev *dev, 527 enum mlx4_port_type *port_types) 528 { 529 int err = 0; 530 int change = 0; 531 int port; 532 533 for (port = 0; port < dev->caps.num_ports; port++) { 534 /* Change the port type only if the new type is different 535 * from the current, and not set to Auto */ 536 if (port_types[port] != dev->caps.port_type[port + 1]) 537 change = 1; 538 } 539 if (change) { 540 mlx4_unregister_device(dev); 541 for (port = 1; port <= dev->caps.num_ports; port++) { 542 mlx4_CLOSE_PORT(dev, port); 543 dev->caps.port_type[port] = port_types[port - 1]; 544 err = mlx4_SET_PORT(dev, port); 545 if (err) { 546 mlx4_err(dev, "Failed to set port %d, " 547 "aborting\n", port); 548 goto out; 549 } 550 } 551 mlx4_set_port_mask(dev); 552 err = mlx4_register_device(dev); 553 } 554 555 out: 556 return err; 557 } 558 559 static ssize_t show_port_type(struct device *dev, 560 struct device_attribute *attr, 561 char *buf) 562 { 563 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 564 port_attr); 565 struct mlx4_dev *mdev = info->dev; 566 char type[8]; 567 568 sprintf(type, "%s", 569 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 570 "ib" : "eth"); 571 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 572 sprintf(buf, "auto (%s)\n", type); 573 else 574 sprintf(buf, "%s\n", type); 575 576 return strlen(buf); 577 } 578 579 static ssize_t set_port_type(struct device *dev, 580 struct device_attribute *attr, 581 const char *buf, size_t count) 582 { 583 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 584 port_attr); 585 struct mlx4_dev *mdev = info->dev; 586 struct mlx4_priv *priv = mlx4_priv(mdev); 587 enum mlx4_port_type types[MLX4_MAX_PORTS]; 588 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 589 int i; 590 int err = 0; 591 592 if (!strcmp(buf, "ib\n")) 593 info->tmp_type = MLX4_PORT_TYPE_IB; 594 else if (!strcmp(buf, "eth\n")) 595 info->tmp_type = MLX4_PORT_TYPE_ETH; 596 else if (!strcmp(buf, "auto\n")) 597 info->tmp_type = MLX4_PORT_TYPE_AUTO; 598 else { 599 mlx4_err(mdev, "%s is not supported port type\n", buf); 600 return -EINVAL; 601 } 602 603 mlx4_stop_sense(mdev); 604 mutex_lock(&priv->port_mutex); 605 /* Possible type is always the one that was delivered */ 606 mdev->caps.possible_type[info->port] = info->tmp_type; 607 608 for (i = 0; i < mdev->caps.num_ports; i++) { 609 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 610 mdev->caps.possible_type[i+1]; 611 if (types[i] == MLX4_PORT_TYPE_AUTO) 612 types[i] = mdev->caps.port_type[i+1]; 613 } 614 615 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 616 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 617 for (i = 1; i <= mdev->caps.num_ports; i++) { 618 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 619 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 620 err = -EINVAL; 621 } 622 } 623 } 624 if (err) { 625 mlx4_err(mdev, "Auto sensing is not supported on this HCA. " 626 "Set only 'eth' or 'ib' for both ports " 627 "(should be the same)\n"); 628 goto out; 629 } 630 631 mlx4_do_sense_ports(mdev, new_types, types); 632 633 err = mlx4_check_port_params(mdev, new_types); 634 if (err) 635 goto out; 636 637 /* We are about to apply the changes after the configuration 638 * was verified, no need to remember the temporary types 639 * any more */ 640 for (i = 0; i < mdev->caps.num_ports; i++) 641 priv->port[i + 1].tmp_type = 0; 642 643 err = mlx4_change_port_types(mdev, new_types); 644 645 out: 646 mlx4_start_sense(mdev); 647 mutex_unlock(&priv->port_mutex); 648 return err ? err : count; 649 } 650 651 enum ibta_mtu { 652 IB_MTU_256 = 1, 653 IB_MTU_512 = 2, 654 IB_MTU_1024 = 3, 655 IB_MTU_2048 = 4, 656 IB_MTU_4096 = 5 657 }; 658 659 static inline int int_to_ibta_mtu(int mtu) 660 { 661 switch (mtu) { 662 case 256: return IB_MTU_256; 663 case 512: return IB_MTU_512; 664 case 1024: return IB_MTU_1024; 665 case 2048: return IB_MTU_2048; 666 case 4096: return IB_MTU_4096; 667 default: return -1; 668 } 669 } 670 671 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 672 { 673 switch (mtu) { 674 case IB_MTU_256: return 256; 675 case IB_MTU_512: return 512; 676 case IB_MTU_1024: return 1024; 677 case IB_MTU_2048: return 2048; 678 case IB_MTU_4096: return 4096; 679 default: return -1; 680 } 681 } 682 683 static ssize_t show_port_ib_mtu(struct device *dev, 684 struct device_attribute *attr, 685 char *buf) 686 { 687 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 688 port_mtu_attr); 689 struct mlx4_dev *mdev = info->dev; 690 691 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 692 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 693 694 sprintf(buf, "%d\n", 695 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 696 return strlen(buf); 697 } 698 699 static ssize_t set_port_ib_mtu(struct device *dev, 700 struct device_attribute *attr, 701 const char *buf, size_t count) 702 { 703 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 704 port_mtu_attr); 705 struct mlx4_dev *mdev = info->dev; 706 struct mlx4_priv *priv = mlx4_priv(mdev); 707 int err, port, mtu, ibta_mtu = -1; 708 709 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 710 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 711 return -EINVAL; 712 } 713 714 err = sscanf(buf, "%d", &mtu); 715 if (err > 0) 716 ibta_mtu = int_to_ibta_mtu(mtu); 717 718 if (err <= 0 || ibta_mtu < 0) { 719 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 720 return -EINVAL; 721 } 722 723 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 724 725 mlx4_stop_sense(mdev); 726 mutex_lock(&priv->port_mutex); 727 mlx4_unregister_device(mdev); 728 for (port = 1; port <= mdev->caps.num_ports; port++) { 729 mlx4_CLOSE_PORT(mdev, port); 730 err = mlx4_SET_PORT(mdev, port); 731 if (err) { 732 mlx4_err(mdev, "Failed to set port %d, " 733 "aborting\n", port); 734 goto err_set_port; 735 } 736 } 737 err = mlx4_register_device(mdev); 738 err_set_port: 739 mutex_unlock(&priv->port_mutex); 740 mlx4_start_sense(mdev); 741 return err ? err : count; 742 } 743 744 static int mlx4_load_fw(struct mlx4_dev *dev) 745 { 746 struct mlx4_priv *priv = mlx4_priv(dev); 747 int err; 748 749 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 750 GFP_HIGHUSER | __GFP_NOWARN, 0); 751 if (!priv->fw.fw_icm) { 752 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); 753 return -ENOMEM; 754 } 755 756 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 757 if (err) { 758 mlx4_err(dev, "MAP_FA command failed, aborting.\n"); 759 goto err_free; 760 } 761 762 err = mlx4_RUN_FW(dev); 763 if (err) { 764 mlx4_err(dev, "RUN_FW command failed, aborting.\n"); 765 goto err_unmap_fa; 766 } 767 768 return 0; 769 770 err_unmap_fa: 771 mlx4_UNMAP_FA(dev); 772 773 err_free: 774 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 775 return err; 776 } 777 778 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 779 int cmpt_entry_sz) 780 { 781 struct mlx4_priv *priv = mlx4_priv(dev); 782 int err; 783 int num_eqs; 784 785 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 786 cmpt_base + 787 ((u64) (MLX4_CMPT_TYPE_QP * 788 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 789 cmpt_entry_sz, dev->caps.num_qps, 790 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 791 0, 0); 792 if (err) 793 goto err; 794 795 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 796 cmpt_base + 797 ((u64) (MLX4_CMPT_TYPE_SRQ * 798 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 799 cmpt_entry_sz, dev->caps.num_srqs, 800 dev->caps.reserved_srqs, 0, 0); 801 if (err) 802 goto err_qp; 803 804 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 805 cmpt_base + 806 ((u64) (MLX4_CMPT_TYPE_CQ * 807 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 808 cmpt_entry_sz, dev->caps.num_cqs, 809 dev->caps.reserved_cqs, 0, 0); 810 if (err) 811 goto err_srq; 812 813 num_eqs = (mlx4_is_master(dev)) ? 814 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) : 815 dev->caps.num_eqs; 816 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 817 cmpt_base + 818 ((u64) (MLX4_CMPT_TYPE_EQ * 819 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 820 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 821 if (err) 822 goto err_cq; 823 824 return 0; 825 826 err_cq: 827 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 828 829 err_srq: 830 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 831 832 err_qp: 833 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 834 835 err: 836 return err; 837 } 838 839 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 840 struct mlx4_init_hca_param *init_hca, u64 icm_size) 841 { 842 struct mlx4_priv *priv = mlx4_priv(dev); 843 u64 aux_pages; 844 int num_eqs; 845 int err; 846 847 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 848 if (err) { 849 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); 850 return err; 851 } 852 853 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", 854 (unsigned long long) icm_size >> 10, 855 (unsigned long long) aux_pages << 2); 856 857 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 858 GFP_HIGHUSER | __GFP_NOWARN, 0); 859 if (!priv->fw.aux_icm) { 860 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); 861 return -ENOMEM; 862 } 863 864 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 865 if (err) { 866 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); 867 goto err_free_aux; 868 } 869 870 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 871 if (err) { 872 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); 873 goto err_unmap_aux; 874 } 875 876 877 num_eqs = (mlx4_is_master(dev)) ? 878 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) : 879 dev->caps.num_eqs; 880 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 881 init_hca->eqc_base, dev_cap->eqc_entry_sz, 882 num_eqs, num_eqs, 0, 0); 883 if (err) { 884 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); 885 goto err_unmap_cmpt; 886 } 887 888 /* 889 * Reserved MTT entries must be aligned up to a cacheline 890 * boundary, since the FW will write to them, while the driver 891 * writes to all other MTT entries. (The variable 892 * dev->caps.mtt_entry_sz below is really the MTT segment 893 * size, not the raw entry size) 894 */ 895 dev->caps.reserved_mtts = 896 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 897 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 898 899 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 900 init_hca->mtt_base, 901 dev->caps.mtt_entry_sz, 902 dev->caps.num_mtts, 903 dev->caps.reserved_mtts, 1, 0); 904 if (err) { 905 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); 906 goto err_unmap_eq; 907 } 908 909 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 910 init_hca->dmpt_base, 911 dev_cap->dmpt_entry_sz, 912 dev->caps.num_mpts, 913 dev->caps.reserved_mrws, 1, 1); 914 if (err) { 915 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); 916 goto err_unmap_mtt; 917 } 918 919 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 920 init_hca->qpc_base, 921 dev_cap->qpc_entry_sz, 922 dev->caps.num_qps, 923 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 924 0, 0); 925 if (err) { 926 mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); 927 goto err_unmap_dmpt; 928 } 929 930 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 931 init_hca->auxc_base, 932 dev_cap->aux_entry_sz, 933 dev->caps.num_qps, 934 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 935 0, 0); 936 if (err) { 937 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); 938 goto err_unmap_qp; 939 } 940 941 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 942 init_hca->altc_base, 943 dev_cap->altc_entry_sz, 944 dev->caps.num_qps, 945 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 946 0, 0); 947 if (err) { 948 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); 949 goto err_unmap_auxc; 950 } 951 952 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 953 init_hca->rdmarc_base, 954 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 955 dev->caps.num_qps, 956 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 957 0, 0); 958 if (err) { 959 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 960 goto err_unmap_altc; 961 } 962 963 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 964 init_hca->cqc_base, 965 dev_cap->cqc_entry_sz, 966 dev->caps.num_cqs, 967 dev->caps.reserved_cqs, 0, 0); 968 if (err) { 969 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); 970 goto err_unmap_rdmarc; 971 } 972 973 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 974 init_hca->srqc_base, 975 dev_cap->srq_entry_sz, 976 dev->caps.num_srqs, 977 dev->caps.reserved_srqs, 0, 0); 978 if (err) { 979 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); 980 goto err_unmap_cq; 981 } 982 983 /* 984 * It's not strictly required, but for simplicity just map the 985 * whole multicast group table now. The table isn't very big 986 * and it's a lot easier than trying to track ref counts. 987 */ 988 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 989 init_hca->mc_base, 990 mlx4_get_mgm_entry_size(dev), 991 dev->caps.num_mgms + dev->caps.num_amgms, 992 dev->caps.num_mgms + dev->caps.num_amgms, 993 0, 0); 994 if (err) { 995 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); 996 goto err_unmap_srq; 997 } 998 999 return 0; 1000 1001 err_unmap_srq: 1002 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1003 1004 err_unmap_cq: 1005 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1006 1007 err_unmap_rdmarc: 1008 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1009 1010 err_unmap_altc: 1011 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1012 1013 err_unmap_auxc: 1014 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1015 1016 err_unmap_qp: 1017 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1018 1019 err_unmap_dmpt: 1020 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1021 1022 err_unmap_mtt: 1023 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1024 1025 err_unmap_eq: 1026 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1027 1028 err_unmap_cmpt: 1029 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1030 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1031 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1032 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1033 1034 err_unmap_aux: 1035 mlx4_UNMAP_ICM_AUX(dev); 1036 1037 err_free_aux: 1038 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1039 1040 return err; 1041 } 1042 1043 static void mlx4_free_icms(struct mlx4_dev *dev) 1044 { 1045 struct mlx4_priv *priv = mlx4_priv(dev); 1046 1047 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1048 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1049 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1050 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1051 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1052 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1053 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1054 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1055 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1056 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1057 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1058 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1059 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1060 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1061 1062 mlx4_UNMAP_ICM_AUX(dev); 1063 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1064 } 1065 1066 static void mlx4_slave_exit(struct mlx4_dev *dev) 1067 { 1068 struct mlx4_priv *priv = mlx4_priv(dev); 1069 1070 down(&priv->cmd.slave_sem); 1071 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1072 mlx4_warn(dev, "Failed to close slave function.\n"); 1073 up(&priv->cmd.slave_sem); 1074 } 1075 1076 static int map_bf_area(struct mlx4_dev *dev) 1077 { 1078 struct mlx4_priv *priv = mlx4_priv(dev); 1079 resource_size_t bf_start; 1080 resource_size_t bf_len; 1081 int err = 0; 1082 1083 if (!dev->caps.bf_reg_size) 1084 return -ENXIO; 1085 1086 bf_start = pci_resource_start(dev->pdev, 2) + 1087 (dev->caps.num_uars << PAGE_SHIFT); 1088 bf_len = pci_resource_len(dev->pdev, 2) - 1089 (dev->caps.num_uars << PAGE_SHIFT); 1090 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1091 if (!priv->bf_mapping) 1092 err = -ENOMEM; 1093 1094 return err; 1095 } 1096 1097 static void unmap_bf_area(struct mlx4_dev *dev) 1098 { 1099 if (mlx4_priv(dev)->bf_mapping) 1100 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1101 } 1102 1103 static void mlx4_close_hca(struct mlx4_dev *dev) 1104 { 1105 unmap_bf_area(dev); 1106 if (mlx4_is_slave(dev)) 1107 mlx4_slave_exit(dev); 1108 else { 1109 mlx4_CLOSE_HCA(dev, 0); 1110 mlx4_free_icms(dev); 1111 mlx4_UNMAP_FA(dev); 1112 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1113 } 1114 } 1115 1116 static int mlx4_init_slave(struct mlx4_dev *dev) 1117 { 1118 struct mlx4_priv *priv = mlx4_priv(dev); 1119 u64 dma = (u64) priv->mfunc.vhcr_dma; 1120 int num_of_reset_retries = NUM_OF_RESET_RETRIES; 1121 int ret_from_reset = 0; 1122 u32 slave_read; 1123 u32 cmd_channel_ver; 1124 1125 down(&priv->cmd.slave_sem); 1126 priv->cmd.max_cmds = 1; 1127 mlx4_warn(dev, "Sending reset\n"); 1128 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1129 MLX4_COMM_TIME); 1130 /* if we are in the middle of flr the slave will try 1131 * NUM_OF_RESET_RETRIES times before leaving.*/ 1132 if (ret_from_reset) { 1133 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1134 msleep(SLEEP_TIME_IN_RESET); 1135 while (ret_from_reset && num_of_reset_retries) { 1136 mlx4_warn(dev, "slave is currently in the" 1137 "middle of FLR. retrying..." 1138 "(try num:%d)\n", 1139 (NUM_OF_RESET_RETRIES - 1140 num_of_reset_retries + 1)); 1141 ret_from_reset = 1142 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 1143 0, MLX4_COMM_TIME); 1144 num_of_reset_retries = num_of_reset_retries - 1; 1145 } 1146 } else 1147 goto err; 1148 } 1149 1150 /* check the driver version - the slave I/F revision 1151 * must match the master's */ 1152 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1153 cmd_channel_ver = mlx4_comm_get_version(); 1154 1155 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1156 MLX4_COMM_GET_IF_REV(slave_read)) { 1157 mlx4_err(dev, "slave driver version is not supported" 1158 " by the master\n"); 1159 goto err; 1160 } 1161 1162 mlx4_warn(dev, "Sending vhcr0\n"); 1163 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1164 MLX4_COMM_TIME)) 1165 goto err; 1166 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1167 MLX4_COMM_TIME)) 1168 goto err; 1169 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1170 MLX4_COMM_TIME)) 1171 goto err; 1172 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1173 goto err; 1174 up(&priv->cmd.slave_sem); 1175 return 0; 1176 1177 err: 1178 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1179 up(&priv->cmd.slave_sem); 1180 return -EIO; 1181 } 1182 1183 static int mlx4_init_hca(struct mlx4_dev *dev) 1184 { 1185 struct mlx4_priv *priv = mlx4_priv(dev); 1186 struct mlx4_adapter adapter; 1187 struct mlx4_dev_cap dev_cap; 1188 struct mlx4_mod_stat_cfg mlx4_cfg; 1189 struct mlx4_profile profile; 1190 struct mlx4_init_hca_param init_hca; 1191 u64 icm_size; 1192 int err; 1193 1194 if (!mlx4_is_slave(dev)) { 1195 err = mlx4_QUERY_FW(dev); 1196 if (err) { 1197 if (err == -EACCES) 1198 mlx4_info(dev, "non-primary physical function, skipping.\n"); 1199 else 1200 mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); 1201 goto unmap_bf; 1202 } 1203 1204 err = mlx4_load_fw(dev); 1205 if (err) { 1206 mlx4_err(dev, "Failed to start FW, aborting.\n"); 1207 goto unmap_bf; 1208 } 1209 1210 mlx4_cfg.log_pg_sz_m = 1; 1211 mlx4_cfg.log_pg_sz = 0; 1212 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1213 if (err) 1214 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1215 1216 err = mlx4_dev_cap(dev, &dev_cap); 1217 if (err) { 1218 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 1219 goto err_stop_fw; 1220 } 1221 1222 profile = default_profile; 1223 1224 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 1225 &init_hca); 1226 if ((long long) icm_size < 0) { 1227 err = icm_size; 1228 goto err_stop_fw; 1229 } 1230 1231 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 1232 1233 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 1234 init_hca.uar_page_sz = PAGE_SHIFT - 12; 1235 1236 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 1237 if (err) 1238 goto err_stop_fw; 1239 1240 err = mlx4_INIT_HCA(dev, &init_hca); 1241 if (err) { 1242 mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); 1243 goto err_free_icm; 1244 } 1245 } else { 1246 err = mlx4_init_slave(dev); 1247 if (err) { 1248 mlx4_err(dev, "Failed to initialize slave\n"); 1249 goto unmap_bf; 1250 } 1251 1252 err = mlx4_slave_cap(dev); 1253 if (err) { 1254 mlx4_err(dev, "Failed to obtain slave caps\n"); 1255 goto err_close; 1256 } 1257 } 1258 1259 if (map_bf_area(dev)) 1260 mlx4_dbg(dev, "Failed to map blue flame area\n"); 1261 1262 /*Only the master set the ports, all the rest got it from it.*/ 1263 if (!mlx4_is_slave(dev)) 1264 mlx4_set_port_mask(dev); 1265 1266 err = mlx4_QUERY_ADAPTER(dev, &adapter); 1267 if (err) { 1268 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); 1269 goto err_close; 1270 } 1271 1272 priv->eq_table.inta_pin = adapter.inta_pin; 1273 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 1274 1275 return 0; 1276 1277 err_close: 1278 mlx4_close_hca(dev); 1279 1280 err_free_icm: 1281 if (!mlx4_is_slave(dev)) 1282 mlx4_free_icms(dev); 1283 1284 err_stop_fw: 1285 if (!mlx4_is_slave(dev)) { 1286 mlx4_UNMAP_FA(dev); 1287 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1288 } 1289 unmap_bf: 1290 unmap_bf_area(dev); 1291 return err; 1292 } 1293 1294 static int mlx4_init_counters_table(struct mlx4_dev *dev) 1295 { 1296 struct mlx4_priv *priv = mlx4_priv(dev); 1297 int nent; 1298 1299 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1300 return -ENOENT; 1301 1302 nent = dev->caps.max_counters; 1303 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 1304 } 1305 1306 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 1307 { 1308 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 1309 } 1310 1311 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1312 { 1313 struct mlx4_priv *priv = mlx4_priv(dev); 1314 1315 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1316 return -ENOENT; 1317 1318 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 1319 if (*idx == -1) 1320 return -ENOMEM; 1321 1322 return 0; 1323 } 1324 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 1325 1326 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1327 { 1328 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx); 1329 return; 1330 } 1331 EXPORT_SYMBOL_GPL(mlx4_counter_free); 1332 1333 static int mlx4_setup_hca(struct mlx4_dev *dev) 1334 { 1335 struct mlx4_priv *priv = mlx4_priv(dev); 1336 int err; 1337 int port; 1338 __be32 ib_port_default_caps; 1339 1340 err = mlx4_init_uar_table(dev); 1341 if (err) { 1342 mlx4_err(dev, "Failed to initialize " 1343 "user access region table, aborting.\n"); 1344 return err; 1345 } 1346 1347 err = mlx4_uar_alloc(dev, &priv->driver_uar); 1348 if (err) { 1349 mlx4_err(dev, "Failed to allocate driver access region, " 1350 "aborting.\n"); 1351 goto err_uar_table_free; 1352 } 1353 1354 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 1355 if (!priv->kar) { 1356 mlx4_err(dev, "Couldn't map kernel access region, " 1357 "aborting.\n"); 1358 err = -ENOMEM; 1359 goto err_uar_free; 1360 } 1361 1362 err = mlx4_init_pd_table(dev); 1363 if (err) { 1364 mlx4_err(dev, "Failed to initialize " 1365 "protection domain table, aborting.\n"); 1366 goto err_kar_unmap; 1367 } 1368 1369 err = mlx4_init_xrcd_table(dev); 1370 if (err) { 1371 mlx4_err(dev, "Failed to initialize " 1372 "reliable connection domain table, aborting.\n"); 1373 goto err_pd_table_free; 1374 } 1375 1376 err = mlx4_init_mr_table(dev); 1377 if (err) { 1378 mlx4_err(dev, "Failed to initialize " 1379 "memory region table, aborting.\n"); 1380 goto err_xrcd_table_free; 1381 } 1382 1383 err = mlx4_init_eq_table(dev); 1384 if (err) { 1385 mlx4_err(dev, "Failed to initialize " 1386 "event queue table, aborting.\n"); 1387 goto err_mr_table_free; 1388 } 1389 1390 err = mlx4_cmd_use_events(dev); 1391 if (err) { 1392 mlx4_err(dev, "Failed to switch to event-driven " 1393 "firmware commands, aborting.\n"); 1394 goto err_eq_table_free; 1395 } 1396 1397 err = mlx4_NOP(dev); 1398 if (err) { 1399 if (dev->flags & MLX4_FLAG_MSI_X) { 1400 mlx4_warn(dev, "NOP command failed to generate MSI-X " 1401 "interrupt IRQ %d).\n", 1402 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1403 mlx4_warn(dev, "Trying again without MSI-X.\n"); 1404 } else { 1405 mlx4_err(dev, "NOP command failed to generate interrupt " 1406 "(IRQ %d), aborting.\n", 1407 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1408 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 1409 } 1410 1411 goto err_cmd_poll; 1412 } 1413 1414 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 1415 1416 err = mlx4_init_cq_table(dev); 1417 if (err) { 1418 mlx4_err(dev, "Failed to initialize " 1419 "completion queue table, aborting.\n"); 1420 goto err_cmd_poll; 1421 } 1422 1423 err = mlx4_init_srq_table(dev); 1424 if (err) { 1425 mlx4_err(dev, "Failed to initialize " 1426 "shared receive queue table, aborting.\n"); 1427 goto err_cq_table_free; 1428 } 1429 1430 err = mlx4_init_qp_table(dev); 1431 if (err) { 1432 mlx4_err(dev, "Failed to initialize " 1433 "queue pair table, aborting.\n"); 1434 goto err_srq_table_free; 1435 } 1436 1437 if (!mlx4_is_slave(dev)) { 1438 err = mlx4_init_mcg_table(dev); 1439 if (err) { 1440 mlx4_err(dev, "Failed to initialize " 1441 "multicast group table, aborting.\n"); 1442 goto err_qp_table_free; 1443 } 1444 } 1445 1446 err = mlx4_init_counters_table(dev); 1447 if (err && err != -ENOENT) { 1448 mlx4_err(dev, "Failed to initialize counters table, aborting.\n"); 1449 goto err_mcg_table_free; 1450 } 1451 1452 if (!mlx4_is_slave(dev)) { 1453 for (port = 1; port <= dev->caps.num_ports; port++) { 1454 ib_port_default_caps = 0; 1455 err = mlx4_get_port_ib_caps(dev, port, 1456 &ib_port_default_caps); 1457 if (err) 1458 mlx4_warn(dev, "failed to get port %d default " 1459 "ib capabilities (%d). Continuing " 1460 "with caps = 0\n", port, err); 1461 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 1462 1463 if (mlx4_is_mfunc(dev)) 1464 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 1465 else 1466 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 1467 1468 err = mlx4_SET_PORT(dev, port); 1469 if (err) { 1470 mlx4_err(dev, "Failed to set port %d, aborting\n", 1471 port); 1472 goto err_counters_table_free; 1473 } 1474 } 1475 } 1476 1477 return 0; 1478 1479 err_counters_table_free: 1480 mlx4_cleanup_counters_table(dev); 1481 1482 err_mcg_table_free: 1483 mlx4_cleanup_mcg_table(dev); 1484 1485 err_qp_table_free: 1486 mlx4_cleanup_qp_table(dev); 1487 1488 err_srq_table_free: 1489 mlx4_cleanup_srq_table(dev); 1490 1491 err_cq_table_free: 1492 mlx4_cleanup_cq_table(dev); 1493 1494 err_cmd_poll: 1495 mlx4_cmd_use_polling(dev); 1496 1497 err_eq_table_free: 1498 mlx4_cleanup_eq_table(dev); 1499 1500 err_mr_table_free: 1501 mlx4_cleanup_mr_table(dev); 1502 1503 err_xrcd_table_free: 1504 mlx4_cleanup_xrcd_table(dev); 1505 1506 err_pd_table_free: 1507 mlx4_cleanup_pd_table(dev); 1508 1509 err_kar_unmap: 1510 iounmap(priv->kar); 1511 1512 err_uar_free: 1513 mlx4_uar_free(dev, &priv->driver_uar); 1514 1515 err_uar_table_free: 1516 mlx4_cleanup_uar_table(dev); 1517 return err; 1518 } 1519 1520 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 1521 { 1522 struct mlx4_priv *priv = mlx4_priv(dev); 1523 struct msix_entry *entries; 1524 int nreq = min_t(int, dev->caps.num_ports * 1525 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT) 1526 + MSIX_LEGACY_SZ, MAX_MSIX); 1527 int err; 1528 int i; 1529 1530 if (msi_x) { 1531 /* In multifunction mode each function gets 2 msi-X vectors 1532 * one for data path completions anf the other for asynch events 1533 * or command completions */ 1534 if (mlx4_is_mfunc(dev)) { 1535 nreq = 2; 1536 } else { 1537 nreq = min_t(int, dev->caps.num_eqs - 1538 dev->caps.reserved_eqs, nreq); 1539 } 1540 1541 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 1542 if (!entries) 1543 goto no_msi; 1544 1545 for (i = 0; i < nreq; ++i) 1546 entries[i].entry = i; 1547 1548 retry: 1549 err = pci_enable_msix(dev->pdev, entries, nreq); 1550 if (err) { 1551 /* Try again if at least 2 vectors are available */ 1552 if (err > 1) { 1553 mlx4_info(dev, "Requested %d vectors, " 1554 "but only %d MSI-X vectors available, " 1555 "trying again\n", nreq, err); 1556 nreq = err; 1557 goto retry; 1558 } 1559 kfree(entries); 1560 goto no_msi; 1561 } 1562 1563 if (nreq < 1564 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { 1565 /*Working in legacy mode , all EQ's shared*/ 1566 dev->caps.comp_pool = 0; 1567 dev->caps.num_comp_vectors = nreq - 1; 1568 } else { 1569 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 1570 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 1571 } 1572 for (i = 0; i < nreq; ++i) 1573 priv->eq_table.eq[i].irq = entries[i].vector; 1574 1575 dev->flags |= MLX4_FLAG_MSI_X; 1576 1577 kfree(entries); 1578 return; 1579 } 1580 1581 no_msi: 1582 dev->caps.num_comp_vectors = 1; 1583 dev->caps.comp_pool = 0; 1584 1585 for (i = 0; i < 2; ++i) 1586 priv->eq_table.eq[i].irq = dev->pdev->irq; 1587 } 1588 1589 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 1590 { 1591 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 1592 int err = 0; 1593 1594 info->dev = dev; 1595 info->port = port; 1596 if (!mlx4_is_slave(dev)) { 1597 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL); 1598 mlx4_init_mac_table(dev, &info->mac_table); 1599 mlx4_init_vlan_table(dev, &info->vlan_table); 1600 info->base_qpn = 1601 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + 1602 (port - 1) * (1 << log_num_mac); 1603 } 1604 1605 sprintf(info->dev_name, "mlx4_port%d", port); 1606 info->port_attr.attr.name = info->dev_name; 1607 if (mlx4_is_mfunc(dev)) 1608 info->port_attr.attr.mode = S_IRUGO; 1609 else { 1610 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 1611 info->port_attr.store = set_port_type; 1612 } 1613 info->port_attr.show = show_port_type; 1614 sysfs_attr_init(&info->port_attr.attr); 1615 1616 err = device_create_file(&dev->pdev->dev, &info->port_attr); 1617 if (err) { 1618 mlx4_err(dev, "Failed to create file for port %d\n", port); 1619 info->port = -1; 1620 } 1621 1622 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 1623 info->port_mtu_attr.attr.name = info->dev_mtu_name; 1624 if (mlx4_is_mfunc(dev)) 1625 info->port_mtu_attr.attr.mode = S_IRUGO; 1626 else { 1627 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 1628 info->port_mtu_attr.store = set_port_ib_mtu; 1629 } 1630 info->port_mtu_attr.show = show_port_ib_mtu; 1631 sysfs_attr_init(&info->port_mtu_attr.attr); 1632 1633 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 1634 if (err) { 1635 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 1636 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1637 info->port = -1; 1638 } 1639 1640 return err; 1641 } 1642 1643 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 1644 { 1645 if (info->port < 0) 1646 return; 1647 1648 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1649 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 1650 } 1651 1652 static int mlx4_init_steering(struct mlx4_dev *dev) 1653 { 1654 struct mlx4_priv *priv = mlx4_priv(dev); 1655 int num_entries = dev->caps.num_ports; 1656 int i, j; 1657 1658 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 1659 if (!priv->steer) 1660 return -ENOMEM; 1661 1662 for (i = 0; i < num_entries; i++) 1663 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1664 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 1665 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 1666 } 1667 return 0; 1668 } 1669 1670 static void mlx4_clear_steering(struct mlx4_dev *dev) 1671 { 1672 struct mlx4_priv *priv = mlx4_priv(dev); 1673 struct mlx4_steer_index *entry, *tmp_entry; 1674 struct mlx4_promisc_qp *pqp, *tmp_pqp; 1675 int num_entries = dev->caps.num_ports; 1676 int i, j; 1677 1678 for (i = 0; i < num_entries; i++) { 1679 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1680 list_for_each_entry_safe(pqp, tmp_pqp, 1681 &priv->steer[i].promisc_qps[j], 1682 list) { 1683 list_del(&pqp->list); 1684 kfree(pqp); 1685 } 1686 list_for_each_entry_safe(entry, tmp_entry, 1687 &priv->steer[i].steer_entries[j], 1688 list) { 1689 list_del(&entry->list); 1690 list_for_each_entry_safe(pqp, tmp_pqp, 1691 &entry->duplicates, 1692 list) { 1693 list_del(&pqp->list); 1694 kfree(pqp); 1695 } 1696 kfree(entry); 1697 } 1698 } 1699 } 1700 kfree(priv->steer); 1701 } 1702 1703 static int extended_func_num(struct pci_dev *pdev) 1704 { 1705 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 1706 } 1707 1708 #define MLX4_OWNER_BASE 0x8069c 1709 #define MLX4_OWNER_SIZE 4 1710 1711 static int mlx4_get_ownership(struct mlx4_dev *dev) 1712 { 1713 void __iomem *owner; 1714 u32 ret; 1715 1716 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 1717 MLX4_OWNER_SIZE); 1718 if (!owner) { 1719 mlx4_err(dev, "Failed to obtain ownership bit\n"); 1720 return -ENOMEM; 1721 } 1722 1723 ret = readl(owner); 1724 iounmap(owner); 1725 return (int) !!ret; 1726 } 1727 1728 static void mlx4_free_ownership(struct mlx4_dev *dev) 1729 { 1730 void __iomem *owner; 1731 1732 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 1733 MLX4_OWNER_SIZE); 1734 if (!owner) { 1735 mlx4_err(dev, "Failed to obtain ownership bit\n"); 1736 return; 1737 } 1738 writel(0, owner); 1739 msleep(1000); 1740 iounmap(owner); 1741 } 1742 1743 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1744 { 1745 struct mlx4_priv *priv; 1746 struct mlx4_dev *dev; 1747 int err; 1748 int port; 1749 1750 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 1751 1752 err = pci_enable_device(pdev); 1753 if (err) { 1754 dev_err(&pdev->dev, "Cannot enable PCI device, " 1755 "aborting.\n"); 1756 return err; 1757 } 1758 if (num_vfs > MLX4_MAX_NUM_VF) { 1759 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n", 1760 num_vfs, MLX4_MAX_NUM_VF); 1761 return -EINVAL; 1762 } 1763 /* 1764 * Check for BARs. 1765 */ 1766 if (((id == NULL) || !(id->driver_data & MLX4_VF)) && 1767 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 1768 dev_err(&pdev->dev, "Missing DCS, aborting." 1769 "(id == 0X%p, id->driver_data: 0x%lx," 1770 " pci_resource_flags(pdev, 0):0x%lx)\n", id, 1771 id ? id->driver_data : 0, pci_resource_flags(pdev, 0)); 1772 err = -ENODEV; 1773 goto err_disable_pdev; 1774 } 1775 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 1776 dev_err(&pdev->dev, "Missing UAR, aborting.\n"); 1777 err = -ENODEV; 1778 goto err_disable_pdev; 1779 } 1780 1781 err = pci_request_regions(pdev, DRV_NAME); 1782 if (err) { 1783 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 1784 goto err_disable_pdev; 1785 } 1786 1787 pci_set_master(pdev); 1788 1789 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1790 if (err) { 1791 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); 1792 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1793 if (err) { 1794 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); 1795 goto err_release_regions; 1796 } 1797 } 1798 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1799 if (err) { 1800 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " 1801 "consistent PCI DMA mask.\n"); 1802 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1803 if (err) { 1804 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " 1805 "aborting.\n"); 1806 goto err_release_regions; 1807 } 1808 } 1809 1810 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 1811 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 1812 1813 priv = kzalloc(sizeof *priv, GFP_KERNEL); 1814 if (!priv) { 1815 dev_err(&pdev->dev, "Device struct alloc failed, " 1816 "aborting.\n"); 1817 err = -ENOMEM; 1818 goto err_release_regions; 1819 } 1820 1821 dev = &priv->dev; 1822 dev->pdev = pdev; 1823 INIT_LIST_HEAD(&priv->ctx_list); 1824 spin_lock_init(&priv->ctx_lock); 1825 1826 mutex_init(&priv->port_mutex); 1827 1828 INIT_LIST_HEAD(&priv->pgdir_list); 1829 mutex_init(&priv->pgdir_mutex); 1830 1831 INIT_LIST_HEAD(&priv->bf_list); 1832 mutex_init(&priv->bf_mutex); 1833 1834 dev->rev_id = pdev->revision; 1835 /* Detect if this device is a virtual function */ 1836 if (id && id->driver_data & MLX4_VF) { 1837 /* When acting as pf, we normally skip vfs unless explicitly 1838 * requested to probe them. */ 1839 if (num_vfs && extended_func_num(pdev) > probe_vf) { 1840 mlx4_warn(dev, "Skipping virtual function:%d\n", 1841 extended_func_num(pdev)); 1842 err = -ENODEV; 1843 goto err_free_dev; 1844 } 1845 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 1846 dev->flags |= MLX4_FLAG_SLAVE; 1847 } else { 1848 /* We reset the device and enable SRIOV only for physical 1849 * devices. Try to claim ownership on the device; 1850 * if already taken, skip -- do not allow multiple PFs */ 1851 err = mlx4_get_ownership(dev); 1852 if (err) { 1853 if (err < 0) 1854 goto err_free_dev; 1855 else { 1856 mlx4_warn(dev, "Multiple PFs not yet supported." 1857 " Skipping PF.\n"); 1858 err = -EINVAL; 1859 goto err_free_dev; 1860 } 1861 } 1862 1863 if (num_vfs) { 1864 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs); 1865 err = pci_enable_sriov(pdev, num_vfs); 1866 if (err) { 1867 mlx4_err(dev, "Failed to enable sriov," 1868 "continuing without sriov enabled" 1869 " (err = %d).\n", err); 1870 num_vfs = 0; 1871 err = 0; 1872 } else { 1873 mlx4_warn(dev, "Running in master mode\n"); 1874 dev->flags |= MLX4_FLAG_SRIOV | 1875 MLX4_FLAG_MASTER; 1876 dev->num_vfs = num_vfs; 1877 } 1878 } 1879 1880 /* 1881 * Now reset the HCA before we touch the PCI capabilities or 1882 * attempt a firmware command, since a boot ROM may have left 1883 * the HCA in an undefined state. 1884 */ 1885 err = mlx4_reset(dev); 1886 if (err) { 1887 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 1888 goto err_rel_own; 1889 } 1890 } 1891 1892 slave_start: 1893 if (mlx4_cmd_init(dev)) { 1894 mlx4_err(dev, "Failed to init command interface, aborting.\n"); 1895 goto err_sriov; 1896 } 1897 1898 /* In slave functions, the communication channel must be initialized 1899 * before posting commands. Also, init num_slaves before calling 1900 * mlx4_init_hca */ 1901 if (mlx4_is_mfunc(dev)) { 1902 if (mlx4_is_master(dev)) 1903 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 1904 else { 1905 dev->num_slaves = 0; 1906 if (mlx4_multi_func_init(dev)) { 1907 mlx4_err(dev, "Failed to init slave mfunc" 1908 " interface, aborting.\n"); 1909 goto err_cmd; 1910 } 1911 } 1912 } 1913 1914 err = mlx4_init_hca(dev); 1915 if (err) { 1916 if (err == -EACCES) { 1917 /* Not primary Physical function 1918 * Running in slave mode */ 1919 mlx4_cmd_cleanup(dev); 1920 dev->flags |= MLX4_FLAG_SLAVE; 1921 dev->flags &= ~MLX4_FLAG_MASTER; 1922 goto slave_start; 1923 } else 1924 goto err_mfunc; 1925 } 1926 1927 /* In master functions, the communication channel must be initialized 1928 * after obtaining its address from fw */ 1929 if (mlx4_is_master(dev)) { 1930 if (mlx4_multi_func_init(dev)) { 1931 mlx4_err(dev, "Failed to init master mfunc" 1932 "interface, aborting.\n"); 1933 goto err_close; 1934 } 1935 } 1936 1937 err = mlx4_alloc_eq_table(dev); 1938 if (err) 1939 goto err_master_mfunc; 1940 1941 priv->msix_ctl.pool_bm = 0; 1942 mutex_init(&priv->msix_ctl.pool_lock); 1943 1944 mlx4_enable_msi_x(dev); 1945 if ((mlx4_is_mfunc(dev)) && 1946 !(dev->flags & MLX4_FLAG_MSI_X)) { 1947 mlx4_err(dev, "INTx is not supported in multi-function mode." 1948 " aborting.\n"); 1949 goto err_free_eq; 1950 } 1951 1952 if (!mlx4_is_slave(dev)) { 1953 err = mlx4_init_steering(dev); 1954 if (err) 1955 goto err_free_eq; 1956 } 1957 1958 err = mlx4_setup_hca(dev); 1959 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 1960 !mlx4_is_mfunc(dev)) { 1961 dev->flags &= ~MLX4_FLAG_MSI_X; 1962 pci_disable_msix(pdev); 1963 err = mlx4_setup_hca(dev); 1964 } 1965 1966 if (err) 1967 goto err_steer; 1968 1969 for (port = 1; port <= dev->caps.num_ports; port++) { 1970 err = mlx4_init_port_info(dev, port); 1971 if (err) 1972 goto err_port; 1973 } 1974 1975 err = mlx4_register_device(dev); 1976 if (err) 1977 goto err_port; 1978 1979 mlx4_sense_init(dev); 1980 mlx4_start_sense(dev); 1981 1982 pci_set_drvdata(pdev, dev); 1983 1984 return 0; 1985 1986 err_port: 1987 for (--port; port >= 1; --port) 1988 mlx4_cleanup_port_info(&priv->port[port]); 1989 1990 mlx4_cleanup_counters_table(dev); 1991 mlx4_cleanup_mcg_table(dev); 1992 mlx4_cleanup_qp_table(dev); 1993 mlx4_cleanup_srq_table(dev); 1994 mlx4_cleanup_cq_table(dev); 1995 mlx4_cmd_use_polling(dev); 1996 mlx4_cleanup_eq_table(dev); 1997 mlx4_cleanup_mr_table(dev); 1998 mlx4_cleanup_xrcd_table(dev); 1999 mlx4_cleanup_pd_table(dev); 2000 mlx4_cleanup_uar_table(dev); 2001 2002 err_steer: 2003 if (!mlx4_is_slave(dev)) 2004 mlx4_clear_steering(dev); 2005 2006 err_free_eq: 2007 mlx4_free_eq_table(dev); 2008 2009 err_master_mfunc: 2010 if (mlx4_is_master(dev)) 2011 mlx4_multi_func_cleanup(dev); 2012 2013 err_close: 2014 if (dev->flags & MLX4_FLAG_MSI_X) 2015 pci_disable_msix(pdev); 2016 2017 mlx4_close_hca(dev); 2018 2019 err_mfunc: 2020 if (mlx4_is_slave(dev)) 2021 mlx4_multi_func_cleanup(dev); 2022 2023 err_cmd: 2024 mlx4_cmd_cleanup(dev); 2025 2026 err_sriov: 2027 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) 2028 pci_disable_sriov(pdev); 2029 2030 err_rel_own: 2031 if (!mlx4_is_slave(dev)) 2032 mlx4_free_ownership(dev); 2033 2034 err_free_dev: 2035 kfree(priv); 2036 2037 err_release_regions: 2038 pci_release_regions(pdev); 2039 2040 err_disable_pdev: 2041 pci_disable_device(pdev); 2042 pci_set_drvdata(pdev, NULL); 2043 return err; 2044 } 2045 2046 static int __devinit mlx4_init_one(struct pci_dev *pdev, 2047 const struct pci_device_id *id) 2048 { 2049 printk_once(KERN_INFO "%s", mlx4_version); 2050 2051 return __mlx4_init_one(pdev, id); 2052 } 2053 2054 static void mlx4_remove_one(struct pci_dev *pdev) 2055 { 2056 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2057 struct mlx4_priv *priv = mlx4_priv(dev); 2058 int p; 2059 2060 if (dev) { 2061 /* in SRIOV it is not allowed to unload the pf's 2062 * driver while there are alive vf's */ 2063 if (mlx4_is_master(dev)) { 2064 if (mlx4_how_many_lives_vf(dev)) 2065 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); 2066 } 2067 mlx4_stop_sense(dev); 2068 mlx4_unregister_device(dev); 2069 2070 for (p = 1; p <= dev->caps.num_ports; p++) { 2071 mlx4_cleanup_port_info(&priv->port[p]); 2072 mlx4_CLOSE_PORT(dev, p); 2073 } 2074 2075 mlx4_cleanup_counters_table(dev); 2076 mlx4_cleanup_mcg_table(dev); 2077 mlx4_cleanup_qp_table(dev); 2078 mlx4_cleanup_srq_table(dev); 2079 mlx4_cleanup_cq_table(dev); 2080 mlx4_cmd_use_polling(dev); 2081 mlx4_cleanup_eq_table(dev); 2082 mlx4_cleanup_mr_table(dev); 2083 mlx4_cleanup_xrcd_table(dev); 2084 mlx4_cleanup_pd_table(dev); 2085 2086 if (mlx4_is_master(dev)) 2087 mlx4_free_resource_tracker(dev); 2088 2089 iounmap(priv->kar); 2090 mlx4_uar_free(dev, &priv->driver_uar); 2091 mlx4_cleanup_uar_table(dev); 2092 if (!mlx4_is_slave(dev)) 2093 mlx4_clear_steering(dev); 2094 mlx4_free_eq_table(dev); 2095 if (mlx4_is_master(dev)) 2096 mlx4_multi_func_cleanup(dev); 2097 mlx4_close_hca(dev); 2098 if (mlx4_is_slave(dev)) 2099 mlx4_multi_func_cleanup(dev); 2100 mlx4_cmd_cleanup(dev); 2101 2102 if (dev->flags & MLX4_FLAG_MSI_X) 2103 pci_disable_msix(pdev); 2104 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) { 2105 mlx4_warn(dev, "Disabling sriov\n"); 2106 pci_disable_sriov(pdev); 2107 } 2108 2109 if (!mlx4_is_slave(dev)) 2110 mlx4_free_ownership(dev); 2111 kfree(priv); 2112 pci_release_regions(pdev); 2113 pci_disable_device(pdev); 2114 pci_set_drvdata(pdev, NULL); 2115 } 2116 } 2117 2118 int mlx4_restart_one(struct pci_dev *pdev) 2119 { 2120 mlx4_remove_one(pdev); 2121 return __mlx4_init_one(pdev, NULL); 2122 } 2123 2124 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { 2125 /* MT25408 "Hermon" SDR */ 2126 { PCI_VDEVICE(MELLANOX, 0x6340), 0 }, 2127 /* MT25408 "Hermon" DDR */ 2128 { PCI_VDEVICE(MELLANOX, 0x634a), 0 }, 2129 /* MT25408 "Hermon" QDR */ 2130 { PCI_VDEVICE(MELLANOX, 0x6354), 0 }, 2131 /* MT25408 "Hermon" DDR PCIe gen2 */ 2132 { PCI_VDEVICE(MELLANOX, 0x6732), 0 }, 2133 /* MT25408 "Hermon" QDR PCIe gen2 */ 2134 { PCI_VDEVICE(MELLANOX, 0x673c), 0 }, 2135 /* MT25408 "Hermon" EN 10GigE */ 2136 { PCI_VDEVICE(MELLANOX, 0x6368), 0 }, 2137 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 2138 { PCI_VDEVICE(MELLANOX, 0x6750), 0 }, 2139 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 2140 { PCI_VDEVICE(MELLANOX, 0x6372), 0 }, 2141 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 2142 { PCI_VDEVICE(MELLANOX, 0x675a), 0 }, 2143 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 2144 { PCI_VDEVICE(MELLANOX, 0x6764), 0 }, 2145 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 2146 { PCI_VDEVICE(MELLANOX, 0x6746), 0 }, 2147 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 2148 { PCI_VDEVICE(MELLANOX, 0x676e), 0 }, 2149 /* MT25400 Family [ConnectX-2 Virtual Function] */ 2150 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF }, 2151 /* MT27500 Family [ConnectX-3] */ 2152 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 2153 /* MT27500 Family [ConnectX-3 Virtual Function] */ 2154 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF }, 2155 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 2156 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 2157 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 2158 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 2159 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 2160 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 2161 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 2162 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 2163 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 2164 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 2165 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 2166 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 2167 { 0, } 2168 }; 2169 2170 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 2171 2172 static struct pci_driver mlx4_driver = { 2173 .name = DRV_NAME, 2174 .id_table = mlx4_pci_table, 2175 .probe = mlx4_init_one, 2176 .remove = __devexit_p(mlx4_remove_one) 2177 }; 2178 2179 static int __init mlx4_verify_params(void) 2180 { 2181 if ((log_num_mac < 0) || (log_num_mac > 7)) { 2182 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); 2183 return -1; 2184 } 2185 2186 if (log_num_vlan != 0) 2187 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 2188 MLX4_LOG_NUM_VLANS); 2189 2190 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 2191 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); 2192 return -1; 2193 } 2194 2195 /* Check if module param for ports type has legal combination */ 2196 if (port_type_array[0] == false && port_type_array[1] == true) { 2197 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 2198 port_type_array[0] = true; 2199 } 2200 2201 return 0; 2202 } 2203 2204 static int __init mlx4_init(void) 2205 { 2206 int ret; 2207 2208 if (mlx4_verify_params()) 2209 return -EINVAL; 2210 2211 mlx4_catas_init(); 2212 2213 mlx4_wq = create_singlethread_workqueue("mlx4"); 2214 if (!mlx4_wq) 2215 return -ENOMEM; 2216 2217 ret = pci_register_driver(&mlx4_driver); 2218 return ret < 0 ? ret : 0; 2219 } 2220 2221 static void __exit mlx4_cleanup(void) 2222 { 2223 pci_unregister_driver(&mlx4_driver); 2224 destroy_workqueue(mlx4_wq); 2225 } 2226 2227 module_init(mlx4_init); 2228 module_exit(mlx4_cleanup); 2229