1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/netdevice.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static int num_vfs; 81 module_param(num_vfs, int, 0444); 82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0"); 83 84 static int probe_vf; 85 module_param(probe_vf, int, 0644); 86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); 87 88 int mlx4_log_num_mgm_entry_size = 10; 89 module_param_named(log_num_mgm_entry_size, 90 mlx4_log_num_mgm_entry_size, int, 0444); 91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 92 " of qp per mcg, for example:" 93 " 10 gives 248.range: 9<=" 94 " log_num_mgm_entry_size <= 12." 95 " Not in use with device managed" 96 " flow steering"); 97 98 #define MLX4_VF (1 << 0) 99 100 #define HCA_GLOBAL_CAP_MASK 0 101 #define PF_CONTEXT_BEHAVIOUR_MASK 0 102 103 static char mlx4_version[] __devinitdata = 104 DRV_NAME ": Mellanox ConnectX core driver v" 105 DRV_VERSION " (" DRV_RELDATE ")\n"; 106 107 static struct mlx4_profile default_profile = { 108 .num_qp = 1 << 18, 109 .num_srq = 1 << 16, 110 .rdmarc_per_qp = 1 << 4, 111 .num_cq = 1 << 16, 112 .num_mcg = 1 << 13, 113 .num_mpt = 1 << 19, 114 .num_mtt = 1 << 20, /* It is really num mtt segements */ 115 }; 116 117 static int log_num_mac = 7; 118 module_param_named(log_num_mac, log_num_mac, int, 0444); 119 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 120 121 static int log_num_vlan; 122 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 123 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 124 /* Log2 max number of VLANs per ETH port (0-7) */ 125 #define MLX4_LOG_NUM_VLANS 7 126 127 static bool use_prio; 128 module_param_named(use_prio, use_prio, bool, 0444); 129 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " 130 "(0/1, default 0)"); 131 132 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 133 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 134 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 135 136 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 137 static int arr_argc = 2; 138 module_param_array(port_type_array, int, &arr_argc, 0444); 139 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 140 "1 for IB, 2 for Ethernet"); 141 142 struct mlx4_port_config { 143 struct list_head list; 144 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 145 struct pci_dev *pdev; 146 }; 147 148 int mlx4_check_port_params(struct mlx4_dev *dev, 149 enum mlx4_port_type *port_type) 150 { 151 int i; 152 153 for (i = 0; i < dev->caps.num_ports - 1; i++) { 154 if (port_type[i] != port_type[i + 1]) { 155 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 156 mlx4_err(dev, "Only same port types supported " 157 "on this HCA, aborting.\n"); 158 return -EINVAL; 159 } 160 } 161 } 162 163 for (i = 0; i < dev->caps.num_ports; i++) { 164 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 165 mlx4_err(dev, "Requested port type for port %d is not " 166 "supported on this HCA\n", i + 1); 167 return -EINVAL; 168 } 169 } 170 return 0; 171 } 172 173 static void mlx4_set_port_mask(struct mlx4_dev *dev) 174 { 175 int i; 176 177 for (i = 1; i <= dev->caps.num_ports; ++i) 178 dev->caps.port_mask[i] = dev->caps.port_type[i]; 179 } 180 181 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 182 { 183 int err; 184 int i; 185 186 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 187 if (err) { 188 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 189 return err; 190 } 191 192 if (dev_cap->min_page_sz > PAGE_SIZE) { 193 mlx4_err(dev, "HCA minimum page size of %d bigger than " 194 "kernel PAGE_SIZE of %ld, aborting.\n", 195 dev_cap->min_page_sz, PAGE_SIZE); 196 return -ENODEV; 197 } 198 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 199 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 200 "aborting.\n", 201 dev_cap->num_ports, MLX4_MAX_PORTS); 202 return -ENODEV; 203 } 204 205 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 206 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " 207 "PCI resource 2 size of 0x%llx, aborting.\n", 208 dev_cap->uar_size, 209 (unsigned long long) pci_resource_len(dev->pdev, 2)); 210 return -ENODEV; 211 } 212 213 dev->caps.num_ports = dev_cap->num_ports; 214 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; 215 for (i = 1; i <= dev->caps.num_ports; ++i) { 216 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 217 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 218 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 219 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 220 /* set gid and pkey table operating lengths by default 221 * to non-sriov values */ 222 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 223 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 224 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 225 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 226 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 227 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 228 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 229 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 230 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 231 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 232 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 233 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 234 } 235 236 dev->caps.uar_page_size = PAGE_SIZE; 237 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 238 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 239 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 240 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 241 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 242 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 243 dev->caps.max_wqes = dev_cap->max_qp_sz; 244 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 245 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 246 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 247 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 248 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 249 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 250 /* 251 * Subtract 1 from the limit because we need to allocate a 252 * spare CQE so the HCA HW can tell the difference between an 253 * empty CQ and a full CQ. 254 */ 255 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 256 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 257 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 258 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 259 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 260 261 /* The first 128 UARs are used for EQ doorbells */ 262 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 263 dev->caps.reserved_pds = dev_cap->reserved_pds; 264 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 265 dev_cap->reserved_xrcds : 0; 266 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 267 dev_cap->max_xrcds : 0; 268 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 269 270 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 271 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 272 dev->caps.flags = dev_cap->flags; 273 dev->caps.flags2 = dev_cap->flags2; 274 dev->caps.bmme_flags = dev_cap->bmme_flags; 275 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 276 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 277 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 278 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 279 280 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 281 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 282 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 283 dev->caps.fs_log_max_ucast_qp_range_size = 284 dev_cap->fs_log_max_ucast_qp_range_size; 285 } else { 286 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 287 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) { 288 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 289 } else { 290 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 291 292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 293 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 294 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags " 295 "set to use B0 steering. Falling back to A0 steering mode.\n"); 296 } 297 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 298 } 299 mlx4_dbg(dev, "Steering mode is: %s\n", 300 mlx4_steering_mode_str(dev->caps.steering_mode)); 301 302 /* Sense port always allowed on supported devices for ConnectX1 and 2 */ 303 if (dev->pdev->device != 0x1003) 304 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 305 306 dev->caps.log_num_macs = log_num_mac; 307 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 308 dev->caps.log_num_prios = use_prio ? 3 : 0; 309 310 for (i = 1; i <= dev->caps.num_ports; ++i) { 311 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 312 if (dev->caps.supported_type[i]) { 313 /* if only ETH is supported - assign ETH */ 314 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 315 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 316 /* if only IB is supported, assign IB */ 317 else if (dev->caps.supported_type[i] == 318 MLX4_PORT_TYPE_IB) 319 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 320 else { 321 /* if IB and ETH are supported, we set the port 322 * type according to user selection of port type; 323 * if user selected none, take the FW hint */ 324 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 325 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 326 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 327 else 328 dev->caps.port_type[i] = port_type_array[i - 1]; 329 } 330 } 331 /* 332 * Link sensing is allowed on the port if 3 conditions are true: 333 * 1. Both protocols are supported on the port. 334 * 2. Different types are supported on the port 335 * 3. FW declared that it supports link sensing 336 */ 337 mlx4_priv(dev)->sense.sense_allowed[i] = 338 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 339 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 340 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 341 342 /* 343 * If "default_sense" bit is set, we move the port to "AUTO" mode 344 * and perform sense_port FW command to try and set the correct 345 * port type from beginning 346 */ 347 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 348 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 349 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 350 mlx4_SENSE_PORT(dev, i, &sensed_port); 351 if (sensed_port != MLX4_PORT_TYPE_NONE) 352 dev->caps.port_type[i] = sensed_port; 353 } else { 354 dev->caps.possible_type[i] = dev->caps.port_type[i]; 355 } 356 357 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 358 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 359 mlx4_warn(dev, "Requested number of MACs is too much " 360 "for port %d, reducing to %d.\n", 361 i, 1 << dev->caps.log_num_macs); 362 } 363 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 364 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 365 mlx4_warn(dev, "Requested number of VLANs is too much " 366 "for port %d, reducing to %d.\n", 367 i, 1 << dev->caps.log_num_vlans); 368 } 369 } 370 371 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 372 373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 376 (1 << dev->caps.log_num_macs) * 377 (1 << dev->caps.log_num_vlans) * 378 (1 << dev->caps.log_num_prios) * 379 dev->caps.num_ports; 380 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 381 382 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 383 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 385 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 386 387 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 388 return 0; 389 } 390 /*The function checks if there are live vf, return the num of them*/ 391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 392 { 393 struct mlx4_priv *priv = mlx4_priv(dev); 394 struct mlx4_slave_state *s_state; 395 int i; 396 int ret = 0; 397 398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 399 s_state = &priv->mfunc.master.slave_state[i]; 400 if (s_state->active && s_state->last_cmd != 401 MLX4_COMM_CMD_RESET) { 402 mlx4_warn(dev, "%s: slave: %d is still active\n", 403 __func__, i); 404 ret++; 405 } 406 } 407 return ret; 408 } 409 410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 411 { 412 u32 qk = MLX4_RESERVED_QKEY_BASE; 413 if (qpn >= dev->caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 414 qpn < dev->caps.sqp_start) 415 return -EINVAL; 416 417 if (qpn >= dev->caps.base_tunnel_sqpn) 418 /* tunnel qp */ 419 qk += qpn - dev->caps.base_tunnel_sqpn; 420 else 421 qk += qpn - dev->caps.sqp_start; 422 *qkey = qk; 423 return 0; 424 } 425 EXPORT_SYMBOL(mlx4_get_parav_qkey); 426 427 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 428 { 429 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 430 431 if (!mlx4_is_master(dev)) 432 return; 433 434 priv->virt2phys_pkey[slave][port - 1][i] = val; 435 } 436 EXPORT_SYMBOL(mlx4_sync_pkey_table); 437 438 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 439 { 440 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 441 442 if (!mlx4_is_master(dev)) 443 return; 444 445 priv->slave_node_guids[slave] = guid; 446 } 447 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 448 449 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 450 { 451 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 452 453 if (!mlx4_is_master(dev)) 454 return 0; 455 456 return priv->slave_node_guids[slave]; 457 } 458 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 459 460 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 461 { 462 struct mlx4_priv *priv = mlx4_priv(dev); 463 struct mlx4_slave_state *s_slave; 464 465 if (!mlx4_is_master(dev)) 466 return 0; 467 468 s_slave = &priv->mfunc.master.slave_state[slave]; 469 return !!s_slave->active; 470 } 471 EXPORT_SYMBOL(mlx4_is_slave_active); 472 473 static int mlx4_slave_cap(struct mlx4_dev *dev) 474 { 475 int err; 476 u32 page_size; 477 struct mlx4_dev_cap dev_cap; 478 struct mlx4_func_cap func_cap; 479 struct mlx4_init_hca_param hca_param; 480 int i; 481 482 memset(&hca_param, 0, sizeof(hca_param)); 483 err = mlx4_QUERY_HCA(dev, &hca_param); 484 if (err) { 485 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); 486 return err; 487 } 488 489 /*fail if the hca has an unknown capability */ 490 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != 491 HCA_GLOBAL_CAP_MASK) { 492 mlx4_err(dev, "Unknown hca global capabilities\n"); 493 return -ENOSYS; 494 } 495 496 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 497 498 memset(&dev_cap, 0, sizeof(dev_cap)); 499 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 500 err = mlx4_dev_cap(dev, &dev_cap); 501 if (err) { 502 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 503 return err; 504 } 505 506 err = mlx4_QUERY_FW(dev); 507 if (err) 508 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n"); 509 510 page_size = ~dev->caps.page_size_cap + 1; 511 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 512 if (page_size > PAGE_SIZE) { 513 mlx4_err(dev, "HCA minimum page size of %d bigger than " 514 "kernel PAGE_SIZE of %ld, aborting.\n", 515 page_size, PAGE_SIZE); 516 return -ENODEV; 517 } 518 519 /* slave gets uar page size from QUERY_HCA fw command */ 520 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 521 522 /* TODO: relax this assumption */ 523 if (dev->caps.uar_page_size != PAGE_SIZE) { 524 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 525 dev->caps.uar_page_size, PAGE_SIZE); 526 return -ENODEV; 527 } 528 529 memset(&func_cap, 0, sizeof(func_cap)); 530 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap); 531 if (err) { 532 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n"); 533 return err; 534 } 535 536 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 537 PF_CONTEXT_BEHAVIOUR_MASK) { 538 mlx4_err(dev, "Unknown pf context behaviour\n"); 539 return -ENOSYS; 540 } 541 542 dev->caps.num_ports = func_cap.num_ports; 543 dev->caps.num_qps = func_cap.qp_quota; 544 dev->caps.num_srqs = func_cap.srq_quota; 545 dev->caps.num_cqs = func_cap.cq_quota; 546 dev->caps.num_eqs = func_cap.max_eq; 547 dev->caps.reserved_eqs = func_cap.reserved_eq; 548 dev->caps.num_mpts = func_cap.mpt_quota; 549 dev->caps.num_mtts = func_cap.mtt_quota; 550 dev->caps.num_pds = MLX4_NUM_PDS; 551 dev->caps.num_mgms = 0; 552 dev->caps.num_amgms = 0; 553 554 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 555 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 556 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); 557 return -ENODEV; 558 } 559 560 for (i = 1; i <= dev->caps.num_ports; ++i) { 561 dev->caps.port_mask[i] = dev->caps.port_type[i]; 562 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 563 &dev->caps.gid_table_len[i], 564 &dev->caps.pkey_table_len[i])) 565 return -ENODEV; 566 } 567 568 if (dev->caps.uar_page_size * (dev->caps.num_uars - 569 dev->caps.reserved_uars) > 570 pci_resource_len(dev->pdev, 2)) { 571 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " 572 "PCI resource 2 size of 0x%llx, aborting.\n", 573 dev->caps.uar_page_size * dev->caps.num_uars, 574 (unsigned long long) pci_resource_len(dev->pdev, 2)); 575 return -ENODEV; 576 } 577 578 /* Calculate our sqp_start */ 579 dev->caps.sqp_start = func_cap.base_proxy_qpn; 580 dev->caps.base_tunnel_sqpn = func_cap.base_tunnel_qpn; 581 582 return 0; 583 } 584 585 /* 586 * Change the port configuration of the device. 587 * Every user of this function must hold the port mutex. 588 */ 589 int mlx4_change_port_types(struct mlx4_dev *dev, 590 enum mlx4_port_type *port_types) 591 { 592 int err = 0; 593 int change = 0; 594 int port; 595 596 for (port = 0; port < dev->caps.num_ports; port++) { 597 /* Change the port type only if the new type is different 598 * from the current, and not set to Auto */ 599 if (port_types[port] != dev->caps.port_type[port + 1]) 600 change = 1; 601 } 602 if (change) { 603 mlx4_unregister_device(dev); 604 for (port = 1; port <= dev->caps.num_ports; port++) { 605 mlx4_CLOSE_PORT(dev, port); 606 dev->caps.port_type[port] = port_types[port - 1]; 607 err = mlx4_SET_PORT(dev, port, -1); 608 if (err) { 609 mlx4_err(dev, "Failed to set port %d, " 610 "aborting\n", port); 611 goto out; 612 } 613 } 614 mlx4_set_port_mask(dev); 615 err = mlx4_register_device(dev); 616 } 617 618 out: 619 return err; 620 } 621 622 static ssize_t show_port_type(struct device *dev, 623 struct device_attribute *attr, 624 char *buf) 625 { 626 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 627 port_attr); 628 struct mlx4_dev *mdev = info->dev; 629 char type[8]; 630 631 sprintf(type, "%s", 632 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 633 "ib" : "eth"); 634 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 635 sprintf(buf, "auto (%s)\n", type); 636 else 637 sprintf(buf, "%s\n", type); 638 639 return strlen(buf); 640 } 641 642 static ssize_t set_port_type(struct device *dev, 643 struct device_attribute *attr, 644 const char *buf, size_t count) 645 { 646 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 647 port_attr); 648 struct mlx4_dev *mdev = info->dev; 649 struct mlx4_priv *priv = mlx4_priv(mdev); 650 enum mlx4_port_type types[MLX4_MAX_PORTS]; 651 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 652 int i; 653 int err = 0; 654 655 if (!strcmp(buf, "ib\n")) 656 info->tmp_type = MLX4_PORT_TYPE_IB; 657 else if (!strcmp(buf, "eth\n")) 658 info->tmp_type = MLX4_PORT_TYPE_ETH; 659 else if (!strcmp(buf, "auto\n")) 660 info->tmp_type = MLX4_PORT_TYPE_AUTO; 661 else { 662 mlx4_err(mdev, "%s is not supported port type\n", buf); 663 return -EINVAL; 664 } 665 666 mlx4_stop_sense(mdev); 667 mutex_lock(&priv->port_mutex); 668 /* Possible type is always the one that was delivered */ 669 mdev->caps.possible_type[info->port] = info->tmp_type; 670 671 for (i = 0; i < mdev->caps.num_ports; i++) { 672 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 673 mdev->caps.possible_type[i+1]; 674 if (types[i] == MLX4_PORT_TYPE_AUTO) 675 types[i] = mdev->caps.port_type[i+1]; 676 } 677 678 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 679 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 680 for (i = 1; i <= mdev->caps.num_ports; i++) { 681 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 682 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 683 err = -EINVAL; 684 } 685 } 686 } 687 if (err) { 688 mlx4_err(mdev, "Auto sensing is not supported on this HCA. " 689 "Set only 'eth' or 'ib' for both ports " 690 "(should be the same)\n"); 691 goto out; 692 } 693 694 mlx4_do_sense_ports(mdev, new_types, types); 695 696 err = mlx4_check_port_params(mdev, new_types); 697 if (err) 698 goto out; 699 700 /* We are about to apply the changes after the configuration 701 * was verified, no need to remember the temporary types 702 * any more */ 703 for (i = 0; i < mdev->caps.num_ports; i++) 704 priv->port[i + 1].tmp_type = 0; 705 706 err = mlx4_change_port_types(mdev, new_types); 707 708 out: 709 mlx4_start_sense(mdev); 710 mutex_unlock(&priv->port_mutex); 711 return err ? err : count; 712 } 713 714 enum ibta_mtu { 715 IB_MTU_256 = 1, 716 IB_MTU_512 = 2, 717 IB_MTU_1024 = 3, 718 IB_MTU_2048 = 4, 719 IB_MTU_4096 = 5 720 }; 721 722 static inline int int_to_ibta_mtu(int mtu) 723 { 724 switch (mtu) { 725 case 256: return IB_MTU_256; 726 case 512: return IB_MTU_512; 727 case 1024: return IB_MTU_1024; 728 case 2048: return IB_MTU_2048; 729 case 4096: return IB_MTU_4096; 730 default: return -1; 731 } 732 } 733 734 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 735 { 736 switch (mtu) { 737 case IB_MTU_256: return 256; 738 case IB_MTU_512: return 512; 739 case IB_MTU_1024: return 1024; 740 case IB_MTU_2048: return 2048; 741 case IB_MTU_4096: return 4096; 742 default: return -1; 743 } 744 } 745 746 static ssize_t show_port_ib_mtu(struct device *dev, 747 struct device_attribute *attr, 748 char *buf) 749 { 750 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 751 port_mtu_attr); 752 struct mlx4_dev *mdev = info->dev; 753 754 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 755 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 756 757 sprintf(buf, "%d\n", 758 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 759 return strlen(buf); 760 } 761 762 static ssize_t set_port_ib_mtu(struct device *dev, 763 struct device_attribute *attr, 764 const char *buf, size_t count) 765 { 766 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 767 port_mtu_attr); 768 struct mlx4_dev *mdev = info->dev; 769 struct mlx4_priv *priv = mlx4_priv(mdev); 770 int err, port, mtu, ibta_mtu = -1; 771 772 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 773 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 774 return -EINVAL; 775 } 776 777 err = sscanf(buf, "%d", &mtu); 778 if (err > 0) 779 ibta_mtu = int_to_ibta_mtu(mtu); 780 781 if (err <= 0 || ibta_mtu < 0) { 782 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 783 return -EINVAL; 784 } 785 786 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 787 788 mlx4_stop_sense(mdev); 789 mutex_lock(&priv->port_mutex); 790 mlx4_unregister_device(mdev); 791 for (port = 1; port <= mdev->caps.num_ports; port++) { 792 mlx4_CLOSE_PORT(mdev, port); 793 err = mlx4_SET_PORT(mdev, port, -1); 794 if (err) { 795 mlx4_err(mdev, "Failed to set port %d, " 796 "aborting\n", port); 797 goto err_set_port; 798 } 799 } 800 err = mlx4_register_device(mdev); 801 err_set_port: 802 mutex_unlock(&priv->port_mutex); 803 mlx4_start_sense(mdev); 804 return err ? err : count; 805 } 806 807 static int mlx4_load_fw(struct mlx4_dev *dev) 808 { 809 struct mlx4_priv *priv = mlx4_priv(dev); 810 int err; 811 812 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 813 GFP_HIGHUSER | __GFP_NOWARN, 0); 814 if (!priv->fw.fw_icm) { 815 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); 816 return -ENOMEM; 817 } 818 819 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 820 if (err) { 821 mlx4_err(dev, "MAP_FA command failed, aborting.\n"); 822 goto err_free; 823 } 824 825 err = mlx4_RUN_FW(dev); 826 if (err) { 827 mlx4_err(dev, "RUN_FW command failed, aborting.\n"); 828 goto err_unmap_fa; 829 } 830 831 return 0; 832 833 err_unmap_fa: 834 mlx4_UNMAP_FA(dev); 835 836 err_free: 837 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 838 return err; 839 } 840 841 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 842 int cmpt_entry_sz) 843 { 844 struct mlx4_priv *priv = mlx4_priv(dev); 845 int err; 846 int num_eqs; 847 848 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 849 cmpt_base + 850 ((u64) (MLX4_CMPT_TYPE_QP * 851 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 852 cmpt_entry_sz, dev->caps.num_qps, 853 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 854 0, 0); 855 if (err) 856 goto err; 857 858 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 859 cmpt_base + 860 ((u64) (MLX4_CMPT_TYPE_SRQ * 861 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 862 cmpt_entry_sz, dev->caps.num_srqs, 863 dev->caps.reserved_srqs, 0, 0); 864 if (err) 865 goto err_qp; 866 867 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 868 cmpt_base + 869 ((u64) (MLX4_CMPT_TYPE_CQ * 870 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 871 cmpt_entry_sz, dev->caps.num_cqs, 872 dev->caps.reserved_cqs, 0, 0); 873 if (err) 874 goto err_srq; 875 876 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 877 dev->caps.num_eqs; 878 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 879 cmpt_base + 880 ((u64) (MLX4_CMPT_TYPE_EQ * 881 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 882 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 883 if (err) 884 goto err_cq; 885 886 return 0; 887 888 err_cq: 889 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 890 891 err_srq: 892 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 893 894 err_qp: 895 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 896 897 err: 898 return err; 899 } 900 901 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 902 struct mlx4_init_hca_param *init_hca, u64 icm_size) 903 { 904 struct mlx4_priv *priv = mlx4_priv(dev); 905 u64 aux_pages; 906 int num_eqs; 907 int err; 908 909 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 910 if (err) { 911 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); 912 return err; 913 } 914 915 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", 916 (unsigned long long) icm_size >> 10, 917 (unsigned long long) aux_pages << 2); 918 919 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 920 GFP_HIGHUSER | __GFP_NOWARN, 0); 921 if (!priv->fw.aux_icm) { 922 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); 923 return -ENOMEM; 924 } 925 926 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 927 if (err) { 928 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); 929 goto err_free_aux; 930 } 931 932 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 933 if (err) { 934 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); 935 goto err_unmap_aux; 936 } 937 938 939 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 940 dev->caps.num_eqs; 941 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 942 init_hca->eqc_base, dev_cap->eqc_entry_sz, 943 num_eqs, num_eqs, 0, 0); 944 if (err) { 945 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); 946 goto err_unmap_cmpt; 947 } 948 949 /* 950 * Reserved MTT entries must be aligned up to a cacheline 951 * boundary, since the FW will write to them, while the driver 952 * writes to all other MTT entries. (The variable 953 * dev->caps.mtt_entry_sz below is really the MTT segment 954 * size, not the raw entry size) 955 */ 956 dev->caps.reserved_mtts = 957 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 958 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 959 960 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 961 init_hca->mtt_base, 962 dev->caps.mtt_entry_sz, 963 dev->caps.num_mtts, 964 dev->caps.reserved_mtts, 1, 0); 965 if (err) { 966 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); 967 goto err_unmap_eq; 968 } 969 970 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 971 init_hca->dmpt_base, 972 dev_cap->dmpt_entry_sz, 973 dev->caps.num_mpts, 974 dev->caps.reserved_mrws, 1, 1); 975 if (err) { 976 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); 977 goto err_unmap_mtt; 978 } 979 980 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 981 init_hca->qpc_base, 982 dev_cap->qpc_entry_sz, 983 dev->caps.num_qps, 984 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 985 0, 0); 986 if (err) { 987 mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); 988 goto err_unmap_dmpt; 989 } 990 991 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 992 init_hca->auxc_base, 993 dev_cap->aux_entry_sz, 994 dev->caps.num_qps, 995 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 996 0, 0); 997 if (err) { 998 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); 999 goto err_unmap_qp; 1000 } 1001 1002 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1003 init_hca->altc_base, 1004 dev_cap->altc_entry_sz, 1005 dev->caps.num_qps, 1006 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1007 0, 0); 1008 if (err) { 1009 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); 1010 goto err_unmap_auxc; 1011 } 1012 1013 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1014 init_hca->rdmarc_base, 1015 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1016 dev->caps.num_qps, 1017 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1018 0, 0); 1019 if (err) { 1020 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1021 goto err_unmap_altc; 1022 } 1023 1024 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1025 init_hca->cqc_base, 1026 dev_cap->cqc_entry_sz, 1027 dev->caps.num_cqs, 1028 dev->caps.reserved_cqs, 0, 0); 1029 if (err) { 1030 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); 1031 goto err_unmap_rdmarc; 1032 } 1033 1034 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1035 init_hca->srqc_base, 1036 dev_cap->srq_entry_sz, 1037 dev->caps.num_srqs, 1038 dev->caps.reserved_srqs, 0, 0); 1039 if (err) { 1040 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); 1041 goto err_unmap_cq; 1042 } 1043 1044 /* 1045 * For flow steering device managed mode it is required to use 1046 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1047 * required, but for simplicity just map the whole multicast 1048 * group table now. The table isn't very big and it's a lot 1049 * easier than trying to track ref counts. 1050 */ 1051 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1052 init_hca->mc_base, 1053 mlx4_get_mgm_entry_size(dev), 1054 dev->caps.num_mgms + dev->caps.num_amgms, 1055 dev->caps.num_mgms + dev->caps.num_amgms, 1056 0, 0); 1057 if (err) { 1058 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); 1059 goto err_unmap_srq; 1060 } 1061 1062 return 0; 1063 1064 err_unmap_srq: 1065 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1066 1067 err_unmap_cq: 1068 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1069 1070 err_unmap_rdmarc: 1071 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1072 1073 err_unmap_altc: 1074 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1075 1076 err_unmap_auxc: 1077 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1078 1079 err_unmap_qp: 1080 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1081 1082 err_unmap_dmpt: 1083 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1084 1085 err_unmap_mtt: 1086 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1087 1088 err_unmap_eq: 1089 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1090 1091 err_unmap_cmpt: 1092 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1093 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1094 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1095 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1096 1097 err_unmap_aux: 1098 mlx4_UNMAP_ICM_AUX(dev); 1099 1100 err_free_aux: 1101 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1102 1103 return err; 1104 } 1105 1106 static void mlx4_free_icms(struct mlx4_dev *dev) 1107 { 1108 struct mlx4_priv *priv = mlx4_priv(dev); 1109 1110 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1111 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1112 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1113 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1114 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1115 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1116 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1117 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1118 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1119 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1120 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1121 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1122 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1123 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1124 1125 mlx4_UNMAP_ICM_AUX(dev); 1126 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1127 } 1128 1129 static void mlx4_slave_exit(struct mlx4_dev *dev) 1130 { 1131 struct mlx4_priv *priv = mlx4_priv(dev); 1132 1133 down(&priv->cmd.slave_sem); 1134 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1135 mlx4_warn(dev, "Failed to close slave function.\n"); 1136 up(&priv->cmd.slave_sem); 1137 } 1138 1139 static int map_bf_area(struct mlx4_dev *dev) 1140 { 1141 struct mlx4_priv *priv = mlx4_priv(dev); 1142 resource_size_t bf_start; 1143 resource_size_t bf_len; 1144 int err = 0; 1145 1146 if (!dev->caps.bf_reg_size) 1147 return -ENXIO; 1148 1149 bf_start = pci_resource_start(dev->pdev, 2) + 1150 (dev->caps.num_uars << PAGE_SHIFT); 1151 bf_len = pci_resource_len(dev->pdev, 2) - 1152 (dev->caps.num_uars << PAGE_SHIFT); 1153 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1154 if (!priv->bf_mapping) 1155 err = -ENOMEM; 1156 1157 return err; 1158 } 1159 1160 static void unmap_bf_area(struct mlx4_dev *dev) 1161 { 1162 if (mlx4_priv(dev)->bf_mapping) 1163 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1164 } 1165 1166 static void mlx4_close_hca(struct mlx4_dev *dev) 1167 { 1168 unmap_bf_area(dev); 1169 if (mlx4_is_slave(dev)) 1170 mlx4_slave_exit(dev); 1171 else { 1172 mlx4_CLOSE_HCA(dev, 0); 1173 mlx4_free_icms(dev); 1174 mlx4_UNMAP_FA(dev); 1175 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1176 } 1177 } 1178 1179 static int mlx4_init_slave(struct mlx4_dev *dev) 1180 { 1181 struct mlx4_priv *priv = mlx4_priv(dev); 1182 u64 dma = (u64) priv->mfunc.vhcr_dma; 1183 int num_of_reset_retries = NUM_OF_RESET_RETRIES; 1184 int ret_from_reset = 0; 1185 u32 slave_read; 1186 u32 cmd_channel_ver; 1187 1188 down(&priv->cmd.slave_sem); 1189 priv->cmd.max_cmds = 1; 1190 mlx4_warn(dev, "Sending reset\n"); 1191 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1192 MLX4_COMM_TIME); 1193 /* if we are in the middle of flr the slave will try 1194 * NUM_OF_RESET_RETRIES times before leaving.*/ 1195 if (ret_from_reset) { 1196 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1197 msleep(SLEEP_TIME_IN_RESET); 1198 while (ret_from_reset && num_of_reset_retries) { 1199 mlx4_warn(dev, "slave is currently in the" 1200 "middle of FLR. retrying..." 1201 "(try num:%d)\n", 1202 (NUM_OF_RESET_RETRIES - 1203 num_of_reset_retries + 1)); 1204 ret_from_reset = 1205 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 1206 0, MLX4_COMM_TIME); 1207 num_of_reset_retries = num_of_reset_retries - 1; 1208 } 1209 } else 1210 goto err; 1211 } 1212 1213 /* check the driver version - the slave I/F revision 1214 * must match the master's */ 1215 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1216 cmd_channel_ver = mlx4_comm_get_version(); 1217 1218 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1219 MLX4_COMM_GET_IF_REV(slave_read)) { 1220 mlx4_err(dev, "slave driver version is not supported" 1221 " by the master\n"); 1222 goto err; 1223 } 1224 1225 mlx4_warn(dev, "Sending vhcr0\n"); 1226 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1227 MLX4_COMM_TIME)) 1228 goto err; 1229 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1230 MLX4_COMM_TIME)) 1231 goto err; 1232 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1233 MLX4_COMM_TIME)) 1234 goto err; 1235 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1236 goto err; 1237 up(&priv->cmd.slave_sem); 1238 return 0; 1239 1240 err: 1241 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1242 up(&priv->cmd.slave_sem); 1243 return -EIO; 1244 } 1245 1246 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1247 { 1248 int i; 1249 1250 for (i = 1; i <= dev->caps.num_ports; i++) { 1251 dev->caps.gid_table_len[i] = 1; 1252 dev->caps.pkey_table_len[i] = 1253 dev->phys_caps.pkey_phys_table_len[i] - 1; 1254 } 1255 } 1256 1257 static int mlx4_init_hca(struct mlx4_dev *dev) 1258 { 1259 struct mlx4_priv *priv = mlx4_priv(dev); 1260 struct mlx4_adapter adapter; 1261 struct mlx4_dev_cap dev_cap; 1262 struct mlx4_mod_stat_cfg mlx4_cfg; 1263 struct mlx4_profile profile; 1264 struct mlx4_init_hca_param init_hca; 1265 u64 icm_size; 1266 int err; 1267 1268 if (!mlx4_is_slave(dev)) { 1269 err = mlx4_QUERY_FW(dev); 1270 if (err) { 1271 if (err == -EACCES) 1272 mlx4_info(dev, "non-primary physical function, skipping.\n"); 1273 else 1274 mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); 1275 return err; 1276 } 1277 1278 err = mlx4_load_fw(dev); 1279 if (err) { 1280 mlx4_err(dev, "Failed to start FW, aborting.\n"); 1281 return err; 1282 } 1283 1284 mlx4_cfg.log_pg_sz_m = 1; 1285 mlx4_cfg.log_pg_sz = 0; 1286 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1287 if (err) 1288 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1289 1290 err = mlx4_dev_cap(dev, &dev_cap); 1291 if (err) { 1292 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 1293 goto err_stop_fw; 1294 } 1295 1296 if (mlx4_is_master(dev)) 1297 mlx4_parav_master_pf_caps(dev); 1298 1299 priv->fs_hash_mode = MLX4_FS_L2_HASH; 1300 1301 switch (priv->fs_hash_mode) { 1302 case MLX4_FS_L2_HASH: 1303 init_hca.fs_hash_enable_bits = 0; 1304 break; 1305 1306 case MLX4_FS_L2_L3_L4_HASH: 1307 /* Enable flow steering with 1308 * udp unicast and tcp unicast 1309 */ 1310 init_hca.fs_hash_enable_bits = 1311 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN; 1312 break; 1313 } 1314 1315 profile = default_profile; 1316 if (dev->caps.steering_mode == 1317 MLX4_STEERING_MODE_DEVICE_MANAGED) 1318 profile.num_mcg = MLX4_FS_NUM_MCG; 1319 1320 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 1321 &init_hca); 1322 if ((long long) icm_size < 0) { 1323 err = icm_size; 1324 goto err_stop_fw; 1325 } 1326 1327 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 1328 1329 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 1330 init_hca.uar_page_sz = PAGE_SHIFT - 12; 1331 1332 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 1333 if (err) 1334 goto err_stop_fw; 1335 1336 err = mlx4_INIT_HCA(dev, &init_hca); 1337 if (err) { 1338 mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); 1339 goto err_free_icm; 1340 } 1341 } else { 1342 err = mlx4_init_slave(dev); 1343 if (err) { 1344 mlx4_err(dev, "Failed to initialize slave\n"); 1345 return err; 1346 } 1347 1348 err = mlx4_slave_cap(dev); 1349 if (err) { 1350 mlx4_err(dev, "Failed to obtain slave caps\n"); 1351 goto err_close; 1352 } 1353 } 1354 1355 if (map_bf_area(dev)) 1356 mlx4_dbg(dev, "Failed to map blue flame area\n"); 1357 1358 /*Only the master set the ports, all the rest got it from it.*/ 1359 if (!mlx4_is_slave(dev)) 1360 mlx4_set_port_mask(dev); 1361 1362 err = mlx4_QUERY_ADAPTER(dev, &adapter); 1363 if (err) { 1364 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); 1365 goto unmap_bf; 1366 } 1367 1368 priv->eq_table.inta_pin = adapter.inta_pin; 1369 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 1370 1371 return 0; 1372 1373 unmap_bf: 1374 unmap_bf_area(dev); 1375 1376 err_close: 1377 mlx4_close_hca(dev); 1378 1379 err_free_icm: 1380 if (!mlx4_is_slave(dev)) 1381 mlx4_free_icms(dev); 1382 1383 err_stop_fw: 1384 if (!mlx4_is_slave(dev)) { 1385 mlx4_UNMAP_FA(dev); 1386 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1387 } 1388 return err; 1389 } 1390 1391 static int mlx4_init_counters_table(struct mlx4_dev *dev) 1392 { 1393 struct mlx4_priv *priv = mlx4_priv(dev); 1394 int nent; 1395 1396 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1397 return -ENOENT; 1398 1399 nent = dev->caps.max_counters; 1400 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 1401 } 1402 1403 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 1404 { 1405 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 1406 } 1407 1408 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1409 { 1410 struct mlx4_priv *priv = mlx4_priv(dev); 1411 1412 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1413 return -ENOENT; 1414 1415 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 1416 if (*idx == -1) 1417 return -ENOMEM; 1418 1419 return 0; 1420 } 1421 1422 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1423 { 1424 u64 out_param; 1425 int err; 1426 1427 if (mlx4_is_mfunc(dev)) { 1428 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 1429 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 1430 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1431 if (!err) 1432 *idx = get_param_l(&out_param); 1433 1434 return err; 1435 } 1436 return __mlx4_counter_alloc(dev, idx); 1437 } 1438 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 1439 1440 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1441 { 1442 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx); 1443 return; 1444 } 1445 1446 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1447 { 1448 u64 in_param; 1449 1450 if (mlx4_is_mfunc(dev)) { 1451 set_param_l(&in_param, idx); 1452 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 1453 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 1454 MLX4_CMD_WRAPPED); 1455 return; 1456 } 1457 __mlx4_counter_free(dev, idx); 1458 } 1459 EXPORT_SYMBOL_GPL(mlx4_counter_free); 1460 1461 static int mlx4_setup_hca(struct mlx4_dev *dev) 1462 { 1463 struct mlx4_priv *priv = mlx4_priv(dev); 1464 int err; 1465 int port; 1466 __be32 ib_port_default_caps; 1467 1468 err = mlx4_init_uar_table(dev); 1469 if (err) { 1470 mlx4_err(dev, "Failed to initialize " 1471 "user access region table, aborting.\n"); 1472 return err; 1473 } 1474 1475 err = mlx4_uar_alloc(dev, &priv->driver_uar); 1476 if (err) { 1477 mlx4_err(dev, "Failed to allocate driver access region, " 1478 "aborting.\n"); 1479 goto err_uar_table_free; 1480 } 1481 1482 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 1483 if (!priv->kar) { 1484 mlx4_err(dev, "Couldn't map kernel access region, " 1485 "aborting.\n"); 1486 err = -ENOMEM; 1487 goto err_uar_free; 1488 } 1489 1490 err = mlx4_init_pd_table(dev); 1491 if (err) { 1492 mlx4_err(dev, "Failed to initialize " 1493 "protection domain table, aborting.\n"); 1494 goto err_kar_unmap; 1495 } 1496 1497 err = mlx4_init_xrcd_table(dev); 1498 if (err) { 1499 mlx4_err(dev, "Failed to initialize " 1500 "reliable connection domain table, aborting.\n"); 1501 goto err_pd_table_free; 1502 } 1503 1504 err = mlx4_init_mr_table(dev); 1505 if (err) { 1506 mlx4_err(dev, "Failed to initialize " 1507 "memory region table, aborting.\n"); 1508 goto err_xrcd_table_free; 1509 } 1510 1511 err = mlx4_init_eq_table(dev); 1512 if (err) { 1513 mlx4_err(dev, "Failed to initialize " 1514 "event queue table, aborting.\n"); 1515 goto err_mr_table_free; 1516 } 1517 1518 err = mlx4_cmd_use_events(dev); 1519 if (err) { 1520 mlx4_err(dev, "Failed to switch to event-driven " 1521 "firmware commands, aborting.\n"); 1522 goto err_eq_table_free; 1523 } 1524 1525 err = mlx4_NOP(dev); 1526 if (err) { 1527 if (dev->flags & MLX4_FLAG_MSI_X) { 1528 mlx4_warn(dev, "NOP command failed to generate MSI-X " 1529 "interrupt IRQ %d).\n", 1530 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1531 mlx4_warn(dev, "Trying again without MSI-X.\n"); 1532 } else { 1533 mlx4_err(dev, "NOP command failed to generate interrupt " 1534 "(IRQ %d), aborting.\n", 1535 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1536 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 1537 } 1538 1539 goto err_cmd_poll; 1540 } 1541 1542 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 1543 1544 err = mlx4_init_cq_table(dev); 1545 if (err) { 1546 mlx4_err(dev, "Failed to initialize " 1547 "completion queue table, aborting.\n"); 1548 goto err_cmd_poll; 1549 } 1550 1551 err = mlx4_init_srq_table(dev); 1552 if (err) { 1553 mlx4_err(dev, "Failed to initialize " 1554 "shared receive queue table, aborting.\n"); 1555 goto err_cq_table_free; 1556 } 1557 1558 err = mlx4_init_qp_table(dev); 1559 if (err) { 1560 mlx4_err(dev, "Failed to initialize " 1561 "queue pair table, aborting.\n"); 1562 goto err_srq_table_free; 1563 } 1564 1565 if (!mlx4_is_slave(dev)) { 1566 err = mlx4_init_mcg_table(dev); 1567 if (err) { 1568 mlx4_err(dev, "Failed to initialize " 1569 "multicast group table, aborting.\n"); 1570 goto err_qp_table_free; 1571 } 1572 } 1573 1574 err = mlx4_init_counters_table(dev); 1575 if (err && err != -ENOENT) { 1576 mlx4_err(dev, "Failed to initialize counters table, aborting.\n"); 1577 goto err_mcg_table_free; 1578 } 1579 1580 if (!mlx4_is_slave(dev)) { 1581 for (port = 1; port <= dev->caps.num_ports; port++) { 1582 ib_port_default_caps = 0; 1583 err = mlx4_get_port_ib_caps(dev, port, 1584 &ib_port_default_caps); 1585 if (err) 1586 mlx4_warn(dev, "failed to get port %d default " 1587 "ib capabilities (%d). Continuing " 1588 "with caps = 0\n", port, err); 1589 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 1590 1591 /* initialize per-slave default ib port capabilities */ 1592 if (mlx4_is_master(dev)) { 1593 int i; 1594 for (i = 0; i < dev->num_slaves; i++) { 1595 if (i == mlx4_master_func_num(dev)) 1596 continue; 1597 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 1598 ib_port_default_caps; 1599 } 1600 } 1601 1602 if (mlx4_is_mfunc(dev)) 1603 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 1604 else 1605 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 1606 1607 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 1608 dev->caps.pkey_table_len[port] : -1); 1609 if (err) { 1610 mlx4_err(dev, "Failed to set port %d, aborting\n", 1611 port); 1612 goto err_counters_table_free; 1613 } 1614 } 1615 } 1616 1617 return 0; 1618 1619 err_counters_table_free: 1620 mlx4_cleanup_counters_table(dev); 1621 1622 err_mcg_table_free: 1623 mlx4_cleanup_mcg_table(dev); 1624 1625 err_qp_table_free: 1626 mlx4_cleanup_qp_table(dev); 1627 1628 err_srq_table_free: 1629 mlx4_cleanup_srq_table(dev); 1630 1631 err_cq_table_free: 1632 mlx4_cleanup_cq_table(dev); 1633 1634 err_cmd_poll: 1635 mlx4_cmd_use_polling(dev); 1636 1637 err_eq_table_free: 1638 mlx4_cleanup_eq_table(dev); 1639 1640 err_mr_table_free: 1641 mlx4_cleanup_mr_table(dev); 1642 1643 err_xrcd_table_free: 1644 mlx4_cleanup_xrcd_table(dev); 1645 1646 err_pd_table_free: 1647 mlx4_cleanup_pd_table(dev); 1648 1649 err_kar_unmap: 1650 iounmap(priv->kar); 1651 1652 err_uar_free: 1653 mlx4_uar_free(dev, &priv->driver_uar); 1654 1655 err_uar_table_free: 1656 mlx4_cleanup_uar_table(dev); 1657 return err; 1658 } 1659 1660 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 1661 { 1662 struct mlx4_priv *priv = mlx4_priv(dev); 1663 struct msix_entry *entries; 1664 int nreq = min_t(int, dev->caps.num_ports * 1665 min_t(int, netif_get_num_default_rss_queues() + 1, 1666 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); 1667 int err; 1668 int i; 1669 1670 if (msi_x) { 1671 /* In multifunction mode each function gets 2 msi-X vectors 1672 * one for data path completions anf the other for asynch events 1673 * or command completions */ 1674 if (mlx4_is_mfunc(dev)) { 1675 nreq = 2; 1676 } else { 1677 nreq = min_t(int, dev->caps.num_eqs - 1678 dev->caps.reserved_eqs, nreq); 1679 } 1680 1681 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 1682 if (!entries) 1683 goto no_msi; 1684 1685 for (i = 0; i < nreq; ++i) 1686 entries[i].entry = i; 1687 1688 retry: 1689 err = pci_enable_msix(dev->pdev, entries, nreq); 1690 if (err) { 1691 /* Try again if at least 2 vectors are available */ 1692 if (err > 1) { 1693 mlx4_info(dev, "Requested %d vectors, " 1694 "but only %d MSI-X vectors available, " 1695 "trying again\n", nreq, err); 1696 nreq = err; 1697 goto retry; 1698 } 1699 kfree(entries); 1700 goto no_msi; 1701 } 1702 1703 if (nreq < 1704 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { 1705 /*Working in legacy mode , all EQ's shared*/ 1706 dev->caps.comp_pool = 0; 1707 dev->caps.num_comp_vectors = nreq - 1; 1708 } else { 1709 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 1710 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 1711 } 1712 for (i = 0; i < nreq; ++i) 1713 priv->eq_table.eq[i].irq = entries[i].vector; 1714 1715 dev->flags |= MLX4_FLAG_MSI_X; 1716 1717 kfree(entries); 1718 return; 1719 } 1720 1721 no_msi: 1722 dev->caps.num_comp_vectors = 1; 1723 dev->caps.comp_pool = 0; 1724 1725 for (i = 0; i < 2; ++i) 1726 priv->eq_table.eq[i].irq = dev->pdev->irq; 1727 } 1728 1729 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 1730 { 1731 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 1732 int err = 0; 1733 1734 info->dev = dev; 1735 info->port = port; 1736 if (!mlx4_is_slave(dev)) { 1737 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL); 1738 mlx4_init_mac_table(dev, &info->mac_table); 1739 mlx4_init_vlan_table(dev, &info->vlan_table); 1740 info->base_qpn = 1741 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + 1742 (port - 1) * (1 << log_num_mac); 1743 } 1744 1745 sprintf(info->dev_name, "mlx4_port%d", port); 1746 info->port_attr.attr.name = info->dev_name; 1747 if (mlx4_is_mfunc(dev)) 1748 info->port_attr.attr.mode = S_IRUGO; 1749 else { 1750 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 1751 info->port_attr.store = set_port_type; 1752 } 1753 info->port_attr.show = show_port_type; 1754 sysfs_attr_init(&info->port_attr.attr); 1755 1756 err = device_create_file(&dev->pdev->dev, &info->port_attr); 1757 if (err) { 1758 mlx4_err(dev, "Failed to create file for port %d\n", port); 1759 info->port = -1; 1760 } 1761 1762 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 1763 info->port_mtu_attr.attr.name = info->dev_mtu_name; 1764 if (mlx4_is_mfunc(dev)) 1765 info->port_mtu_attr.attr.mode = S_IRUGO; 1766 else { 1767 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 1768 info->port_mtu_attr.store = set_port_ib_mtu; 1769 } 1770 info->port_mtu_attr.show = show_port_ib_mtu; 1771 sysfs_attr_init(&info->port_mtu_attr.attr); 1772 1773 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 1774 if (err) { 1775 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 1776 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1777 info->port = -1; 1778 } 1779 1780 return err; 1781 } 1782 1783 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 1784 { 1785 if (info->port < 0) 1786 return; 1787 1788 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1789 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 1790 } 1791 1792 static int mlx4_init_steering(struct mlx4_dev *dev) 1793 { 1794 struct mlx4_priv *priv = mlx4_priv(dev); 1795 int num_entries = dev->caps.num_ports; 1796 int i, j; 1797 1798 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 1799 if (!priv->steer) 1800 return -ENOMEM; 1801 1802 for (i = 0; i < num_entries; i++) 1803 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1804 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 1805 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 1806 } 1807 return 0; 1808 } 1809 1810 static void mlx4_clear_steering(struct mlx4_dev *dev) 1811 { 1812 struct mlx4_priv *priv = mlx4_priv(dev); 1813 struct mlx4_steer_index *entry, *tmp_entry; 1814 struct mlx4_promisc_qp *pqp, *tmp_pqp; 1815 int num_entries = dev->caps.num_ports; 1816 int i, j; 1817 1818 for (i = 0; i < num_entries; i++) { 1819 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1820 list_for_each_entry_safe(pqp, tmp_pqp, 1821 &priv->steer[i].promisc_qps[j], 1822 list) { 1823 list_del(&pqp->list); 1824 kfree(pqp); 1825 } 1826 list_for_each_entry_safe(entry, tmp_entry, 1827 &priv->steer[i].steer_entries[j], 1828 list) { 1829 list_del(&entry->list); 1830 list_for_each_entry_safe(pqp, tmp_pqp, 1831 &entry->duplicates, 1832 list) { 1833 list_del(&pqp->list); 1834 kfree(pqp); 1835 } 1836 kfree(entry); 1837 } 1838 } 1839 } 1840 kfree(priv->steer); 1841 } 1842 1843 static int extended_func_num(struct pci_dev *pdev) 1844 { 1845 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 1846 } 1847 1848 #define MLX4_OWNER_BASE 0x8069c 1849 #define MLX4_OWNER_SIZE 4 1850 1851 static int mlx4_get_ownership(struct mlx4_dev *dev) 1852 { 1853 void __iomem *owner; 1854 u32 ret; 1855 1856 if (pci_channel_offline(dev->pdev)) 1857 return -EIO; 1858 1859 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 1860 MLX4_OWNER_SIZE); 1861 if (!owner) { 1862 mlx4_err(dev, "Failed to obtain ownership bit\n"); 1863 return -ENOMEM; 1864 } 1865 1866 ret = readl(owner); 1867 iounmap(owner); 1868 return (int) !!ret; 1869 } 1870 1871 static void mlx4_free_ownership(struct mlx4_dev *dev) 1872 { 1873 void __iomem *owner; 1874 1875 if (pci_channel_offline(dev->pdev)) 1876 return; 1877 1878 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 1879 MLX4_OWNER_SIZE); 1880 if (!owner) { 1881 mlx4_err(dev, "Failed to obtain ownership bit\n"); 1882 return; 1883 } 1884 writel(0, owner); 1885 msleep(1000); 1886 iounmap(owner); 1887 } 1888 1889 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1890 { 1891 struct mlx4_priv *priv; 1892 struct mlx4_dev *dev; 1893 int err; 1894 int port; 1895 1896 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 1897 1898 err = pci_enable_device(pdev); 1899 if (err) { 1900 dev_err(&pdev->dev, "Cannot enable PCI device, " 1901 "aborting.\n"); 1902 return err; 1903 } 1904 if (num_vfs > MLX4_MAX_NUM_VF) { 1905 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n", 1906 num_vfs, MLX4_MAX_NUM_VF); 1907 return -EINVAL; 1908 } 1909 /* 1910 * Check for BARs. 1911 */ 1912 if (((id == NULL) || !(id->driver_data & MLX4_VF)) && 1913 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 1914 dev_err(&pdev->dev, "Missing DCS, aborting." 1915 "(id == 0X%p, id->driver_data: 0x%lx," 1916 " pci_resource_flags(pdev, 0):0x%lx)\n", id, 1917 id ? id->driver_data : 0, pci_resource_flags(pdev, 0)); 1918 err = -ENODEV; 1919 goto err_disable_pdev; 1920 } 1921 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 1922 dev_err(&pdev->dev, "Missing UAR, aborting.\n"); 1923 err = -ENODEV; 1924 goto err_disable_pdev; 1925 } 1926 1927 err = pci_request_regions(pdev, DRV_NAME); 1928 if (err) { 1929 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 1930 goto err_disable_pdev; 1931 } 1932 1933 pci_set_master(pdev); 1934 1935 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1936 if (err) { 1937 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); 1938 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1939 if (err) { 1940 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); 1941 goto err_release_regions; 1942 } 1943 } 1944 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1945 if (err) { 1946 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " 1947 "consistent PCI DMA mask.\n"); 1948 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1949 if (err) { 1950 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " 1951 "aborting.\n"); 1952 goto err_release_regions; 1953 } 1954 } 1955 1956 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 1957 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 1958 1959 priv = kzalloc(sizeof *priv, GFP_KERNEL); 1960 if (!priv) { 1961 dev_err(&pdev->dev, "Device struct alloc failed, " 1962 "aborting.\n"); 1963 err = -ENOMEM; 1964 goto err_release_regions; 1965 } 1966 1967 dev = &priv->dev; 1968 dev->pdev = pdev; 1969 INIT_LIST_HEAD(&priv->ctx_list); 1970 spin_lock_init(&priv->ctx_lock); 1971 1972 mutex_init(&priv->port_mutex); 1973 1974 INIT_LIST_HEAD(&priv->pgdir_list); 1975 mutex_init(&priv->pgdir_mutex); 1976 1977 INIT_LIST_HEAD(&priv->bf_list); 1978 mutex_init(&priv->bf_mutex); 1979 1980 dev->rev_id = pdev->revision; 1981 /* Detect if this device is a virtual function */ 1982 if (id && id->driver_data & MLX4_VF) { 1983 /* When acting as pf, we normally skip vfs unless explicitly 1984 * requested to probe them. */ 1985 if (num_vfs && extended_func_num(pdev) > probe_vf) { 1986 mlx4_warn(dev, "Skipping virtual function:%d\n", 1987 extended_func_num(pdev)); 1988 err = -ENODEV; 1989 goto err_free_dev; 1990 } 1991 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 1992 dev->flags |= MLX4_FLAG_SLAVE; 1993 } else { 1994 /* We reset the device and enable SRIOV only for physical 1995 * devices. Try to claim ownership on the device; 1996 * if already taken, skip -- do not allow multiple PFs */ 1997 err = mlx4_get_ownership(dev); 1998 if (err) { 1999 if (err < 0) 2000 goto err_free_dev; 2001 else { 2002 mlx4_warn(dev, "Multiple PFs not yet supported." 2003 " Skipping PF.\n"); 2004 err = -EINVAL; 2005 goto err_free_dev; 2006 } 2007 } 2008 2009 if (num_vfs) { 2010 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs); 2011 err = pci_enable_sriov(pdev, num_vfs); 2012 if (err) { 2013 mlx4_err(dev, "Failed to enable sriov," 2014 "continuing without sriov enabled" 2015 " (err = %d).\n", err); 2016 err = 0; 2017 } else { 2018 mlx4_warn(dev, "Running in master mode\n"); 2019 dev->flags |= MLX4_FLAG_SRIOV | 2020 MLX4_FLAG_MASTER; 2021 dev->num_vfs = num_vfs; 2022 } 2023 } 2024 2025 /* 2026 * Now reset the HCA before we touch the PCI capabilities or 2027 * attempt a firmware command, since a boot ROM may have left 2028 * the HCA in an undefined state. 2029 */ 2030 err = mlx4_reset(dev); 2031 if (err) { 2032 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 2033 goto err_rel_own; 2034 } 2035 } 2036 2037 slave_start: 2038 err = mlx4_cmd_init(dev); 2039 if (err) { 2040 mlx4_err(dev, "Failed to init command interface, aborting.\n"); 2041 goto err_sriov; 2042 } 2043 2044 /* In slave functions, the communication channel must be initialized 2045 * before posting commands. Also, init num_slaves before calling 2046 * mlx4_init_hca */ 2047 if (mlx4_is_mfunc(dev)) { 2048 if (mlx4_is_master(dev)) 2049 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2050 else { 2051 dev->num_slaves = 0; 2052 if (mlx4_multi_func_init(dev)) { 2053 mlx4_err(dev, "Failed to init slave mfunc" 2054 " interface, aborting.\n"); 2055 goto err_cmd; 2056 } 2057 } 2058 } 2059 2060 err = mlx4_init_hca(dev); 2061 if (err) { 2062 if (err == -EACCES) { 2063 /* Not primary Physical function 2064 * Running in slave mode */ 2065 mlx4_cmd_cleanup(dev); 2066 dev->flags |= MLX4_FLAG_SLAVE; 2067 dev->flags &= ~MLX4_FLAG_MASTER; 2068 goto slave_start; 2069 } else 2070 goto err_mfunc; 2071 } 2072 2073 /* In master functions, the communication channel must be initialized 2074 * after obtaining its address from fw */ 2075 if (mlx4_is_master(dev)) { 2076 if (mlx4_multi_func_init(dev)) { 2077 mlx4_err(dev, "Failed to init master mfunc" 2078 "interface, aborting.\n"); 2079 goto err_close; 2080 } 2081 } 2082 2083 err = mlx4_alloc_eq_table(dev); 2084 if (err) 2085 goto err_master_mfunc; 2086 2087 priv->msix_ctl.pool_bm = 0; 2088 mutex_init(&priv->msix_ctl.pool_lock); 2089 2090 mlx4_enable_msi_x(dev); 2091 if ((mlx4_is_mfunc(dev)) && 2092 !(dev->flags & MLX4_FLAG_MSI_X)) { 2093 mlx4_err(dev, "INTx is not supported in multi-function mode." 2094 " aborting.\n"); 2095 goto err_free_eq; 2096 } 2097 2098 if (!mlx4_is_slave(dev)) { 2099 err = mlx4_init_steering(dev); 2100 if (err) 2101 goto err_free_eq; 2102 } 2103 2104 err = mlx4_setup_hca(dev); 2105 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 2106 !mlx4_is_mfunc(dev)) { 2107 dev->flags &= ~MLX4_FLAG_MSI_X; 2108 dev->caps.num_comp_vectors = 1; 2109 dev->caps.comp_pool = 0; 2110 pci_disable_msix(pdev); 2111 err = mlx4_setup_hca(dev); 2112 } 2113 2114 if (err) 2115 goto err_steer; 2116 2117 for (port = 1; port <= dev->caps.num_ports; port++) { 2118 err = mlx4_init_port_info(dev, port); 2119 if (err) 2120 goto err_port; 2121 } 2122 2123 err = mlx4_register_device(dev); 2124 if (err) 2125 goto err_port; 2126 2127 mlx4_sense_init(dev); 2128 mlx4_start_sense(dev); 2129 2130 pci_set_drvdata(pdev, dev); 2131 2132 return 0; 2133 2134 err_port: 2135 for (--port; port >= 1; --port) 2136 mlx4_cleanup_port_info(&priv->port[port]); 2137 2138 mlx4_cleanup_counters_table(dev); 2139 mlx4_cleanup_mcg_table(dev); 2140 mlx4_cleanup_qp_table(dev); 2141 mlx4_cleanup_srq_table(dev); 2142 mlx4_cleanup_cq_table(dev); 2143 mlx4_cmd_use_polling(dev); 2144 mlx4_cleanup_eq_table(dev); 2145 mlx4_cleanup_mr_table(dev); 2146 mlx4_cleanup_xrcd_table(dev); 2147 mlx4_cleanup_pd_table(dev); 2148 mlx4_cleanup_uar_table(dev); 2149 2150 err_steer: 2151 if (!mlx4_is_slave(dev)) 2152 mlx4_clear_steering(dev); 2153 2154 err_free_eq: 2155 mlx4_free_eq_table(dev); 2156 2157 err_master_mfunc: 2158 if (mlx4_is_master(dev)) 2159 mlx4_multi_func_cleanup(dev); 2160 2161 err_close: 2162 if (dev->flags & MLX4_FLAG_MSI_X) 2163 pci_disable_msix(pdev); 2164 2165 mlx4_close_hca(dev); 2166 2167 err_mfunc: 2168 if (mlx4_is_slave(dev)) 2169 mlx4_multi_func_cleanup(dev); 2170 2171 err_cmd: 2172 mlx4_cmd_cleanup(dev); 2173 2174 err_sriov: 2175 if (dev->flags & MLX4_FLAG_SRIOV) 2176 pci_disable_sriov(pdev); 2177 2178 err_rel_own: 2179 if (!mlx4_is_slave(dev)) 2180 mlx4_free_ownership(dev); 2181 2182 err_free_dev: 2183 kfree(priv); 2184 2185 err_release_regions: 2186 pci_release_regions(pdev); 2187 2188 err_disable_pdev: 2189 pci_disable_device(pdev); 2190 pci_set_drvdata(pdev, NULL); 2191 return err; 2192 } 2193 2194 static int __devinit mlx4_init_one(struct pci_dev *pdev, 2195 const struct pci_device_id *id) 2196 { 2197 printk_once(KERN_INFO "%s", mlx4_version); 2198 2199 return __mlx4_init_one(pdev, id); 2200 } 2201 2202 static void mlx4_remove_one(struct pci_dev *pdev) 2203 { 2204 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2205 struct mlx4_priv *priv = mlx4_priv(dev); 2206 int p; 2207 2208 if (dev) { 2209 /* in SRIOV it is not allowed to unload the pf's 2210 * driver while there are alive vf's */ 2211 if (mlx4_is_master(dev)) { 2212 if (mlx4_how_many_lives_vf(dev)) 2213 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); 2214 } 2215 mlx4_stop_sense(dev); 2216 mlx4_unregister_device(dev); 2217 2218 for (p = 1; p <= dev->caps.num_ports; p++) { 2219 mlx4_cleanup_port_info(&priv->port[p]); 2220 mlx4_CLOSE_PORT(dev, p); 2221 } 2222 2223 if (mlx4_is_master(dev)) 2224 mlx4_free_resource_tracker(dev, 2225 RES_TR_FREE_SLAVES_ONLY); 2226 2227 mlx4_cleanup_counters_table(dev); 2228 mlx4_cleanup_mcg_table(dev); 2229 mlx4_cleanup_qp_table(dev); 2230 mlx4_cleanup_srq_table(dev); 2231 mlx4_cleanup_cq_table(dev); 2232 mlx4_cmd_use_polling(dev); 2233 mlx4_cleanup_eq_table(dev); 2234 mlx4_cleanup_mr_table(dev); 2235 mlx4_cleanup_xrcd_table(dev); 2236 mlx4_cleanup_pd_table(dev); 2237 2238 if (mlx4_is_master(dev)) 2239 mlx4_free_resource_tracker(dev, 2240 RES_TR_FREE_STRUCTS_ONLY); 2241 2242 iounmap(priv->kar); 2243 mlx4_uar_free(dev, &priv->driver_uar); 2244 mlx4_cleanup_uar_table(dev); 2245 if (!mlx4_is_slave(dev)) 2246 mlx4_clear_steering(dev); 2247 mlx4_free_eq_table(dev); 2248 if (mlx4_is_master(dev)) 2249 mlx4_multi_func_cleanup(dev); 2250 mlx4_close_hca(dev); 2251 if (mlx4_is_slave(dev)) 2252 mlx4_multi_func_cleanup(dev); 2253 mlx4_cmd_cleanup(dev); 2254 2255 if (dev->flags & MLX4_FLAG_MSI_X) 2256 pci_disable_msix(pdev); 2257 if (dev->flags & MLX4_FLAG_SRIOV) { 2258 mlx4_warn(dev, "Disabling sriov\n"); 2259 pci_disable_sriov(pdev); 2260 } 2261 2262 if (!mlx4_is_slave(dev)) 2263 mlx4_free_ownership(dev); 2264 kfree(priv); 2265 pci_release_regions(pdev); 2266 pci_disable_device(pdev); 2267 pci_set_drvdata(pdev, NULL); 2268 } 2269 } 2270 2271 int mlx4_restart_one(struct pci_dev *pdev) 2272 { 2273 mlx4_remove_one(pdev); 2274 return __mlx4_init_one(pdev, NULL); 2275 } 2276 2277 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { 2278 /* MT25408 "Hermon" SDR */ 2279 { PCI_VDEVICE(MELLANOX, 0x6340), 0 }, 2280 /* MT25408 "Hermon" DDR */ 2281 { PCI_VDEVICE(MELLANOX, 0x634a), 0 }, 2282 /* MT25408 "Hermon" QDR */ 2283 { PCI_VDEVICE(MELLANOX, 0x6354), 0 }, 2284 /* MT25408 "Hermon" DDR PCIe gen2 */ 2285 { PCI_VDEVICE(MELLANOX, 0x6732), 0 }, 2286 /* MT25408 "Hermon" QDR PCIe gen2 */ 2287 { PCI_VDEVICE(MELLANOX, 0x673c), 0 }, 2288 /* MT25408 "Hermon" EN 10GigE */ 2289 { PCI_VDEVICE(MELLANOX, 0x6368), 0 }, 2290 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 2291 { PCI_VDEVICE(MELLANOX, 0x6750), 0 }, 2292 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 2293 { PCI_VDEVICE(MELLANOX, 0x6372), 0 }, 2294 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 2295 { PCI_VDEVICE(MELLANOX, 0x675a), 0 }, 2296 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 2297 { PCI_VDEVICE(MELLANOX, 0x6764), 0 }, 2298 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 2299 { PCI_VDEVICE(MELLANOX, 0x6746), 0 }, 2300 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 2301 { PCI_VDEVICE(MELLANOX, 0x676e), 0 }, 2302 /* MT25400 Family [ConnectX-2 Virtual Function] */ 2303 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF }, 2304 /* MT27500 Family [ConnectX-3] */ 2305 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 2306 /* MT27500 Family [ConnectX-3 Virtual Function] */ 2307 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF }, 2308 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 2309 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 2310 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 2311 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 2312 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 2313 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 2314 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 2315 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 2316 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 2317 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 2318 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 2319 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 2320 { 0, } 2321 }; 2322 2323 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 2324 2325 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 2326 pci_channel_state_t state) 2327 { 2328 mlx4_remove_one(pdev); 2329 2330 return state == pci_channel_io_perm_failure ? 2331 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2332 } 2333 2334 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 2335 { 2336 int ret = __mlx4_init_one(pdev, NULL); 2337 2338 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 2339 } 2340 2341 static struct pci_error_handlers mlx4_err_handler = { 2342 .error_detected = mlx4_pci_err_detected, 2343 .slot_reset = mlx4_pci_slot_reset, 2344 }; 2345 2346 static struct pci_driver mlx4_driver = { 2347 .name = DRV_NAME, 2348 .id_table = mlx4_pci_table, 2349 .probe = mlx4_init_one, 2350 .remove = __devexit_p(mlx4_remove_one), 2351 .err_handler = &mlx4_err_handler, 2352 }; 2353 2354 static int __init mlx4_verify_params(void) 2355 { 2356 if ((log_num_mac < 0) || (log_num_mac > 7)) { 2357 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); 2358 return -1; 2359 } 2360 2361 if (log_num_vlan != 0) 2362 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 2363 MLX4_LOG_NUM_VLANS); 2364 2365 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 2366 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); 2367 return -1; 2368 } 2369 2370 /* Check if module param for ports type has legal combination */ 2371 if (port_type_array[0] == false && port_type_array[1] == true) { 2372 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 2373 port_type_array[0] = true; 2374 } 2375 2376 return 0; 2377 } 2378 2379 static int __init mlx4_init(void) 2380 { 2381 int ret; 2382 2383 if (mlx4_verify_params()) 2384 return -EINVAL; 2385 2386 mlx4_catas_init(); 2387 2388 mlx4_wq = create_singlethread_workqueue("mlx4"); 2389 if (!mlx4_wq) 2390 return -ENOMEM; 2391 2392 ret = pci_register_driver(&mlx4_driver); 2393 return ret < 0 ? ret : 0; 2394 } 2395 2396 static void __exit mlx4_cleanup(void) 2397 { 2398 pci_unregister_driver(&mlx4_driver); 2399 destroy_workqueue(mlx4_wq); 2400 } 2401 2402 module_init(mlx4_init); 2403 module_exit(mlx4_cleanup); 2404