1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/errno.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/slab.h> 43 #include <linux/io-mapping.h> 44 #include <linux/delay.h> 45 #include <linux/kmod.h> 46 #include <linux/etherdevice.h> 47 #include <net/devlink.h> 48 49 #include <uapi/rdma/mlx4-abi.h> 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/doorbell.h> 52 53 #include "mlx4.h" 54 #include "fw.h" 55 #include "icm.h" 56 57 MODULE_AUTHOR("Roland Dreier"); 58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 MODULE_VERSION(DRV_VERSION); 61 62 struct workqueue_struct *mlx4_wq; 63 64 #ifdef CONFIG_MLX4_DEBUG 65 66 int mlx4_debug_level = 0; 67 module_param_named(debug_level, mlx4_debug_level, int, 0644); 68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 69 70 #endif /* CONFIG_MLX4_DEBUG */ 71 72 #ifdef CONFIG_PCI_MSI 73 74 static int msi_x = 1; 75 module_param(msi_x, int, 0444); 76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 77 78 #else /* CONFIG_PCI_MSI */ 79 80 #define msi_x (0) 81 82 #endif /* CONFIG_PCI_MSI */ 83 84 static uint8_t num_vfs[3] = {0, 0, 0}; 85 static int num_vfs_argc; 86 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 88 "num_vfs=port1,port2,port1+2"); 89 90 static uint8_t probe_vf[3] = {0, 0, 0}; 91 static int probe_vfs_argc; 92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 94 "probe_vf=port1,port2,port1+2"); 95 96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 97 module_param_named(log_num_mgm_entry_size, 98 mlx4_log_num_mgm_entry_size, int, 0444); 99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 100 " of qp per mcg, for example:" 101 " 10 gives 248.range: 7 <=" 102 " log_num_mgm_entry_size <= 12." 103 " To activate device managed" 104 " flow steering when available, set to -1"); 105 106 static bool enable_64b_cqe_eqe = true; 107 module_param(enable_64b_cqe_eqe, bool, 0444); 108 MODULE_PARM_DESC(enable_64b_cqe_eqe, 109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 110 111 static bool enable_4k_uar; 112 module_param(enable_4k_uar, bool, 0444); 113 MODULE_PARM_DESC(enable_4k_uar, 114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 115 116 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 118 MLX4_FUNC_CAP_DMFS_A0_STATIC) 119 120 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 121 122 static char mlx4_version[] = 123 DRV_NAME ": Mellanox ConnectX core driver v" 124 DRV_VERSION "\n"; 125 126 static const struct mlx4_profile default_profile = { 127 .num_qp = 1 << 18, 128 .num_srq = 1 << 16, 129 .rdmarc_per_qp = 1 << 4, 130 .num_cq = 1 << 16, 131 .num_mcg = 1 << 13, 132 .num_mpt = 1 << 19, 133 .num_mtt = 1 << 20, /* It is really num mtt segements */ 134 }; 135 136 static const struct mlx4_profile low_mem_profile = { 137 .num_qp = 1 << 17, 138 .num_srq = 1 << 6, 139 .rdmarc_per_qp = 1 << 4, 140 .num_cq = 1 << 8, 141 .num_mcg = 1 << 8, 142 .num_mpt = 1 << 9, 143 .num_mtt = 1 << 7, 144 }; 145 146 static int log_num_mac = 7; 147 module_param_named(log_num_mac, log_num_mac, int, 0444); 148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 149 150 static int log_num_vlan; 151 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 153 /* Log2 max number of VLANs per ETH port (0-7) */ 154 #define MLX4_LOG_NUM_VLANS 7 155 #define MLX4_MIN_LOG_NUM_VLANS 0 156 #define MLX4_MIN_LOG_NUM_MAC 1 157 158 static bool use_prio; 159 module_param_named(use_prio, use_prio, bool, 0444); 160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 161 162 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 165 166 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 167 static int arr_argc = 2; 168 module_param_array(port_type_array, int, &arr_argc, 0444); 169 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 170 "1 for IB, 2 for Ethernet"); 171 172 struct mlx4_port_config { 173 struct list_head list; 174 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 175 struct pci_dev *pdev; 176 }; 177 178 static atomic_t pf_loading = ATOMIC_INIT(0); 179 180 static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 181 struct devlink_param_gset_ctx *ctx) 182 { 183 ctx->val.vbool = !!mlx4_internal_err_reset; 184 return 0; 185 } 186 187 static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 188 struct devlink_param_gset_ctx *ctx) 189 { 190 mlx4_internal_err_reset = ctx->val.vbool; 191 return 0; 192 } 193 194 static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 195 struct devlink_param_gset_ctx *ctx) 196 { 197 struct mlx4_priv *priv = devlink_priv(devlink); 198 struct mlx4_dev *dev = &priv->dev; 199 200 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 201 return 0; 202 } 203 204 static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 205 struct devlink_param_gset_ctx *ctx) 206 { 207 struct mlx4_priv *priv = devlink_priv(devlink); 208 struct mlx4_dev *dev = &priv->dev; 209 210 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 211 return 0; 212 } 213 214 static int 215 mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 216 union devlink_param_value val, 217 struct netlink_ext_ack *extack) 218 { 219 u32 value = val.vu32; 220 221 if (value < 1 || value > 128) 222 return -ERANGE; 223 224 if (!is_power_of_2(value)) { 225 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 226 return -EINVAL; 227 } 228 229 return 0; 230 } 231 232 enum mlx4_devlink_param_id { 233 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 234 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 235 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 236 }; 237 238 static const struct devlink_param mlx4_devlink_params[] = { 239 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 240 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 241 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 242 mlx4_devlink_ierr_reset_get, 243 mlx4_devlink_ierr_reset_set, NULL), 244 DEVLINK_PARAM_GENERIC(MAX_MACS, 245 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 246 NULL, NULL, mlx4_devlink_max_macs_validate), 247 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 248 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 249 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 250 mlx4_devlink_crdump_snapshot_get, 251 mlx4_devlink_crdump_snapshot_set, NULL), 252 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 253 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 254 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 255 NULL, NULL, NULL), 256 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 257 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 258 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 259 NULL, NULL, NULL), 260 }; 261 262 static void mlx4_devlink_set_init_value(struct devlink *devlink, u32 param_id, 263 union devlink_param_value init_val) 264 { 265 struct mlx4_priv *priv = devlink_priv(devlink); 266 struct mlx4_dev *dev = &priv->dev; 267 int err; 268 269 err = devlink_param_driverinit_value_set(devlink, param_id, init_val); 270 if (err) 271 mlx4_warn(dev, 272 "devlink set parameter %u value failed (err = %d)", 273 param_id, err); 274 } 275 276 static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 277 { 278 union devlink_param_value value; 279 280 value.vbool = !!mlx4_internal_err_reset; 281 mlx4_devlink_set_init_value(devlink, 282 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 283 value); 284 285 value.vu32 = 1UL << log_num_mac; 286 mlx4_devlink_set_init_value(devlink, 287 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, value); 288 289 value.vbool = enable_64b_cqe_eqe; 290 mlx4_devlink_set_init_value(devlink, 291 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 292 value); 293 294 value.vbool = enable_4k_uar; 295 mlx4_devlink_set_init_value(devlink, 296 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 297 value); 298 299 value.vbool = false; 300 mlx4_devlink_set_init_value(devlink, 301 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 302 value); 303 } 304 305 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 306 struct mlx4_dev_cap *dev_cap) 307 { 308 /* The reserved_uars is calculated by system page size unit. 309 * Therefore, adjustment is added when the uar page size is less 310 * than the system page size 311 */ 312 dev->caps.reserved_uars = 313 max_t(int, 314 mlx4_get_num_reserved_uar(dev), 315 dev_cap->reserved_uars / 316 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 317 } 318 319 int mlx4_check_port_params(struct mlx4_dev *dev, 320 enum mlx4_port_type *port_type) 321 { 322 int i; 323 324 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 325 for (i = 0; i < dev->caps.num_ports - 1; i++) { 326 if (port_type[i] != port_type[i + 1]) { 327 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 328 return -EINVAL; 329 } 330 } 331 } 332 333 for (i = 0; i < dev->caps.num_ports; i++) { 334 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 335 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 336 i + 1); 337 return -EINVAL; 338 } 339 } 340 return 0; 341 } 342 343 static void mlx4_set_port_mask(struct mlx4_dev *dev) 344 { 345 int i; 346 347 for (i = 1; i <= dev->caps.num_ports; ++i) 348 dev->caps.port_mask[i] = dev->caps.port_type[i]; 349 } 350 351 enum { 352 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 353 }; 354 355 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 356 { 357 int err = 0; 358 struct mlx4_func func; 359 360 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 361 err = mlx4_QUERY_FUNC(dev, &func, 0); 362 if (err) { 363 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 364 return err; 365 } 366 dev_cap->max_eqs = func.max_eq; 367 dev_cap->reserved_eqs = func.rsvd_eqs; 368 dev_cap->reserved_uars = func.rsvd_uars; 369 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 370 } 371 return err; 372 } 373 374 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 375 { 376 struct mlx4_caps *dev_cap = &dev->caps; 377 378 /* FW not supporting or cancelled by user */ 379 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 380 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 381 return; 382 383 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 384 * When FW has NCSI it may decide not to report 64B CQE/EQEs 385 */ 386 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 387 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 388 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 389 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 390 return; 391 } 392 393 if (cache_line_size() == 128 || cache_line_size() == 256) { 394 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 395 /* Changing the real data inside CQE size to 32B */ 396 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 397 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 398 399 if (mlx4_is_master(dev)) 400 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 401 } else { 402 if (cache_line_size() != 32 && cache_line_size() != 64) 403 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 404 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 405 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 406 } 407 } 408 409 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 410 struct mlx4_port_cap *port_cap) 411 { 412 dev->caps.vl_cap[port] = port_cap->max_vl; 413 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 414 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 415 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 416 /* set gid and pkey table operating lengths by default 417 * to non-sriov values 418 */ 419 dev->caps.gid_table_len[port] = port_cap->max_gids; 420 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 421 dev->caps.port_width_cap[port] = port_cap->max_port_width; 422 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 423 dev->caps.max_tc_eth = port_cap->max_tc_eth; 424 dev->caps.def_mac[port] = port_cap->def_mac; 425 dev->caps.supported_type[port] = port_cap->supported_port_types; 426 dev->caps.suggested_type[port] = port_cap->suggested_type; 427 dev->caps.default_sense[port] = port_cap->default_sense; 428 dev->caps.trans_type[port] = port_cap->trans_type; 429 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 430 dev->caps.wavelength[port] = port_cap->wavelength; 431 dev->caps.trans_code[port] = port_cap->trans_code; 432 433 return 0; 434 } 435 436 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 437 struct mlx4_port_cap *port_cap) 438 { 439 int err = 0; 440 441 err = mlx4_QUERY_PORT(dev, port, port_cap); 442 443 if (err) 444 mlx4_err(dev, "QUERY_PORT command failed.\n"); 445 446 return err; 447 } 448 449 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 450 { 451 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 452 return; 453 454 if (mlx4_is_mfunc(dev)) { 455 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 456 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 457 return; 458 } 459 460 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 461 mlx4_dbg(dev, 462 "Keep FCS is not supported - Disabling Ignore FCS"); 463 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 464 return; 465 } 466 } 467 468 #define MLX4_A0_STEERING_TABLE_SIZE 256 469 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 470 { 471 int err; 472 int i; 473 474 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 475 if (err) { 476 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 477 return err; 478 } 479 mlx4_dev_cap_dump(dev, dev_cap); 480 481 if (dev_cap->min_page_sz > PAGE_SIZE) { 482 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 483 dev_cap->min_page_sz, PAGE_SIZE); 484 return -ENODEV; 485 } 486 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 487 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 488 dev_cap->num_ports, MLX4_MAX_PORTS); 489 return -ENODEV; 490 } 491 492 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 493 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 494 dev_cap->uar_size, 495 (unsigned long long) 496 pci_resource_len(dev->persist->pdev, 2)); 497 return -ENODEV; 498 } 499 500 dev->caps.num_ports = dev_cap->num_ports; 501 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 502 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 503 dev->caps.num_sys_eqs : 504 MLX4_MAX_EQ_NUM; 505 for (i = 1; i <= dev->caps.num_ports; ++i) { 506 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 507 if (err) { 508 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 509 return err; 510 } 511 } 512 513 dev->caps.uar_page_size = PAGE_SIZE; 514 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 515 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 516 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 517 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 518 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 519 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 520 dev->caps.max_wqes = dev_cap->max_qp_sz; 521 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 522 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 523 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 524 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 525 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 526 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 527 /* 528 * Subtract 1 from the limit because we need to allocate a 529 * spare CQE so the HCA HW can tell the difference between an 530 * empty CQ and a full CQ. 531 */ 532 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 533 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 534 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 535 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 536 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 537 538 dev->caps.reserved_pds = dev_cap->reserved_pds; 539 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 540 dev_cap->reserved_xrcds : 0; 541 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 542 dev_cap->max_xrcds : 0; 543 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 544 545 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 546 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 547 dev->caps.flags = dev_cap->flags; 548 dev->caps.flags2 = dev_cap->flags2; 549 dev->caps.bmme_flags = dev_cap->bmme_flags; 550 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 551 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 552 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 553 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 554 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 555 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 556 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 557 558 /* Save uar page shift */ 559 if (!mlx4_is_slave(dev)) { 560 /* Virtual PCI function needs to determine UAR page size from 561 * firmware. Only master PCI function can set the uar page size 562 */ 563 if (enable_4k_uar || !dev->persist->num_vfs) 564 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 565 else 566 dev->uar_page_shift = PAGE_SHIFT; 567 568 mlx4_set_num_reserved_uars(dev, dev_cap); 569 } 570 571 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 572 struct mlx4_init_hca_param hca_param; 573 574 memset(&hca_param, 0, sizeof(hca_param)); 575 err = mlx4_QUERY_HCA(dev, &hca_param); 576 /* Turn off PHV_EN flag in case phv_check_en is set. 577 * phv_check_en is a HW check that parse the packet and verify 578 * phv bit was reported correctly in the wqe. To allow QinQ 579 * PHV_EN flag should be set and phv_check_en must be cleared 580 * otherwise QinQ packets will be drop by the HW. 581 */ 582 if (err || hca_param.phv_check_en) 583 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 584 } 585 586 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 587 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 588 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 589 /* Don't do sense port on multifunction devices (for now at least) */ 590 if (mlx4_is_mfunc(dev)) 591 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 592 593 if (mlx4_low_memory_profile()) { 594 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 595 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 596 } else { 597 dev->caps.log_num_macs = log_num_mac; 598 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 599 } 600 601 for (i = 1; i <= dev->caps.num_ports; ++i) { 602 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 603 if (dev->caps.supported_type[i]) { 604 /* if only ETH is supported - assign ETH */ 605 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 606 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 607 /* if only IB is supported, assign IB */ 608 else if (dev->caps.supported_type[i] == 609 MLX4_PORT_TYPE_IB) 610 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 611 else { 612 /* if IB and ETH are supported, we set the port 613 * type according to user selection of port type; 614 * if user selected none, take the FW hint */ 615 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 616 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 617 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 618 else 619 dev->caps.port_type[i] = port_type_array[i - 1]; 620 } 621 } 622 /* 623 * Link sensing is allowed on the port if 3 conditions are true: 624 * 1. Both protocols are supported on the port. 625 * 2. Different types are supported on the port 626 * 3. FW declared that it supports link sensing 627 */ 628 mlx4_priv(dev)->sense.sense_allowed[i] = 629 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 630 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 631 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 632 633 /* 634 * If "default_sense" bit is set, we move the port to "AUTO" mode 635 * and perform sense_port FW command to try and set the correct 636 * port type from beginning 637 */ 638 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 639 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 640 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 641 mlx4_SENSE_PORT(dev, i, &sensed_port); 642 if (sensed_port != MLX4_PORT_TYPE_NONE) 643 dev->caps.port_type[i] = sensed_port; 644 } else { 645 dev->caps.possible_type[i] = dev->caps.port_type[i]; 646 } 647 648 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 649 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 650 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 651 i, 1 << dev->caps.log_num_macs); 652 } 653 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 654 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 655 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 656 i, 1 << dev->caps.log_num_vlans); 657 } 658 } 659 660 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 661 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 662 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 663 mlx4_warn(dev, 664 "Granular QoS per VF not supported with IB/Eth configuration\n"); 665 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 666 } 667 668 dev->caps.max_counters = dev_cap->max_counters; 669 670 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 672 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 673 (1 << dev->caps.log_num_macs) * 674 (1 << dev->caps.log_num_vlans) * 675 dev->caps.num_ports; 676 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 677 678 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 679 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 680 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 681 else 682 dev->caps.dmfs_high_rate_qpn_base = 683 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 684 685 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 686 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 687 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 688 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 689 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 690 } else { 691 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 692 dev->caps.dmfs_high_rate_qpn_base = 693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 694 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 695 } 696 697 dev->caps.rl_caps = dev_cap->rl_caps; 698 699 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 700 dev->caps.dmfs_high_rate_qpn_range; 701 702 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 703 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 704 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 705 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 706 707 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 708 709 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 710 if (dev_cap->flags & 711 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 712 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 713 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 714 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 715 } 716 717 if (dev_cap->flags2 & 718 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 719 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 720 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 721 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 722 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 723 } 724 } 725 726 if ((dev->caps.flags & 727 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 728 mlx4_is_master(dev)) 729 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 730 731 if (!mlx4_is_slave(dev)) { 732 mlx4_enable_cqe_eqe_stride(dev); 733 dev->caps.alloc_res_qp_mask = 734 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 735 MLX4_RESERVE_A0_QP; 736 737 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 738 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 739 mlx4_warn(dev, "Old device ETS support detected\n"); 740 mlx4_warn(dev, "Consider upgrading device FW.\n"); 741 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 742 } 743 744 } else { 745 dev->caps.alloc_res_qp_mask = 0; 746 } 747 748 mlx4_enable_ignore_fcs(dev); 749 750 return 0; 751 } 752 753 /*The function checks if there are live vf, return the num of them*/ 754 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 755 { 756 struct mlx4_priv *priv = mlx4_priv(dev); 757 struct mlx4_slave_state *s_state; 758 int i; 759 int ret = 0; 760 761 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 762 s_state = &priv->mfunc.master.slave_state[i]; 763 if (s_state->active && s_state->last_cmd != 764 MLX4_COMM_CMD_RESET) { 765 mlx4_warn(dev, "%s: slave: %d is still active\n", 766 __func__, i); 767 ret++; 768 } 769 } 770 return ret; 771 } 772 773 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 774 { 775 u32 qk = MLX4_RESERVED_QKEY_BASE; 776 777 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 778 qpn < dev->phys_caps.base_proxy_sqpn) 779 return -EINVAL; 780 781 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 782 /* tunnel qp */ 783 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 784 else 785 qk += qpn - dev->phys_caps.base_proxy_sqpn; 786 *qkey = qk; 787 return 0; 788 } 789 EXPORT_SYMBOL(mlx4_get_parav_qkey); 790 791 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 792 { 793 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 794 795 if (!mlx4_is_master(dev)) 796 return; 797 798 priv->virt2phys_pkey[slave][port - 1][i] = val; 799 } 800 EXPORT_SYMBOL(mlx4_sync_pkey_table); 801 802 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 803 { 804 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 805 806 if (!mlx4_is_master(dev)) 807 return; 808 809 priv->slave_node_guids[slave] = guid; 810 } 811 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 812 813 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 814 { 815 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 816 817 if (!mlx4_is_master(dev)) 818 return 0; 819 820 return priv->slave_node_guids[slave]; 821 } 822 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 823 824 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 825 { 826 struct mlx4_priv *priv = mlx4_priv(dev); 827 struct mlx4_slave_state *s_slave; 828 829 if (!mlx4_is_master(dev)) 830 return 0; 831 832 s_slave = &priv->mfunc.master.slave_state[slave]; 833 return !!s_slave->active; 834 } 835 EXPORT_SYMBOL(mlx4_is_slave_active); 836 837 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 838 struct _rule_hw *eth_header) 839 { 840 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 841 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 842 struct mlx4_net_trans_rule_hw_eth *eth = 843 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 844 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 845 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 846 next_rule->rsvd == 0; 847 848 if (last_rule) 849 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 850 } 851 } 852 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 853 854 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 855 struct mlx4_dev_cap *dev_cap, 856 struct mlx4_init_hca_param *hca_param) 857 { 858 dev->caps.steering_mode = hca_param->steering_mode; 859 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 860 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 861 dev->caps.fs_log_max_ucast_qp_range_size = 862 dev_cap->fs_log_max_ucast_qp_range_size; 863 } else 864 dev->caps.num_qp_per_mgm = 865 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 866 867 mlx4_dbg(dev, "Steering mode is: %s\n", 868 mlx4_steering_mode_str(dev->caps.steering_mode)); 869 } 870 871 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 872 { 873 kfree(dev->caps.spec_qps); 874 dev->caps.spec_qps = NULL; 875 } 876 877 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 878 { 879 struct mlx4_func_cap *func_cap = NULL; 880 struct mlx4_caps *caps = &dev->caps; 881 int i, err = 0; 882 883 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 884 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 885 886 if (!func_cap || !caps->spec_qps) { 887 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 888 err = -ENOMEM; 889 goto err_mem; 890 } 891 892 for (i = 1; i <= caps->num_ports; ++i) { 893 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 894 if (err) { 895 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 896 i, err); 897 goto err_mem; 898 } 899 caps->spec_qps[i - 1] = func_cap->spec_qps; 900 caps->port_mask[i] = caps->port_type[i]; 901 caps->phys_port_id[i] = func_cap->phys_port_id; 902 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 903 &caps->gid_table_len[i], 904 &caps->pkey_table_len[i]); 905 if (err) { 906 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 907 i, err); 908 goto err_mem; 909 } 910 } 911 912 err_mem: 913 if (err) 914 mlx4_slave_destroy_special_qp_cap(dev); 915 kfree(func_cap); 916 return err; 917 } 918 919 static int mlx4_slave_cap(struct mlx4_dev *dev) 920 { 921 int err; 922 u32 page_size; 923 struct mlx4_dev_cap *dev_cap = NULL; 924 struct mlx4_func_cap *func_cap = NULL; 925 struct mlx4_init_hca_param *hca_param = NULL; 926 927 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 928 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 929 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 930 if (!hca_param || !func_cap || !dev_cap) { 931 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 932 err = -ENOMEM; 933 goto free_mem; 934 } 935 936 err = mlx4_QUERY_HCA(dev, hca_param); 937 if (err) { 938 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 939 goto free_mem; 940 } 941 942 /* fail if the hca has an unknown global capability 943 * at this time global_caps should be always zeroed 944 */ 945 if (hca_param->global_caps) { 946 mlx4_err(dev, "Unknown hca global capabilities\n"); 947 err = -EINVAL; 948 goto free_mem; 949 } 950 951 dev->caps.hca_core_clock = hca_param->hca_core_clock; 952 953 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 954 err = mlx4_dev_cap(dev, dev_cap); 955 if (err) { 956 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 957 goto free_mem; 958 } 959 960 err = mlx4_QUERY_FW(dev); 961 if (err) 962 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 963 964 page_size = ~dev->caps.page_size_cap + 1; 965 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 966 if (page_size > PAGE_SIZE) { 967 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 968 page_size, PAGE_SIZE); 969 err = -ENODEV; 970 goto free_mem; 971 } 972 973 /* Set uar_page_shift for VF */ 974 dev->uar_page_shift = hca_param->uar_page_sz + 12; 975 976 /* Make sure the master uar page size is valid */ 977 if (dev->uar_page_shift > PAGE_SHIFT) { 978 mlx4_err(dev, 979 "Invalid configuration: uar page size is larger than system page size\n"); 980 err = -ENODEV; 981 goto free_mem; 982 } 983 984 /* Set reserved_uars based on the uar_page_shift */ 985 mlx4_set_num_reserved_uars(dev, dev_cap); 986 987 /* Although uar page size in FW differs from system page size, 988 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 989 * still works with assumption that uar page size == system page size 990 */ 991 dev->caps.uar_page_size = PAGE_SIZE; 992 993 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 994 if (err) { 995 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 996 err); 997 goto free_mem; 998 } 999 1000 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 1001 PF_CONTEXT_BEHAVIOUR_MASK) { 1002 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 1003 func_cap->pf_context_behaviour, 1004 PF_CONTEXT_BEHAVIOUR_MASK); 1005 err = -EINVAL; 1006 goto free_mem; 1007 } 1008 1009 dev->caps.num_ports = func_cap->num_ports; 1010 dev->quotas.qp = func_cap->qp_quota; 1011 dev->quotas.srq = func_cap->srq_quota; 1012 dev->quotas.cq = func_cap->cq_quota; 1013 dev->quotas.mpt = func_cap->mpt_quota; 1014 dev->quotas.mtt = func_cap->mtt_quota; 1015 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1016 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1017 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1018 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1019 dev->caps.num_eqs = func_cap->max_eq; 1020 dev->caps.reserved_eqs = func_cap->reserved_eq; 1021 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1022 dev->caps.num_pds = MLX4_NUM_PDS; 1023 dev->caps.num_mgms = 0; 1024 dev->caps.num_amgms = 0; 1025 1026 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1027 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1028 dev->caps.num_ports, MLX4_MAX_PORTS); 1029 err = -ENODEV; 1030 goto free_mem; 1031 } 1032 1033 mlx4_replace_zero_macs(dev); 1034 1035 err = mlx4_slave_special_qp_cap(dev); 1036 if (err) { 1037 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1038 goto free_mem; 1039 } 1040 1041 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1042 dev->caps.reserved_uars) > 1043 pci_resource_len(dev->persist->pdev, 1044 2)) { 1045 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1046 dev->caps.uar_page_size * dev->caps.num_uars, 1047 (unsigned long long) 1048 pci_resource_len(dev->persist->pdev, 2)); 1049 err = -ENOMEM; 1050 goto err_mem; 1051 } 1052 1053 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1054 dev->caps.eqe_size = 64; 1055 dev->caps.eqe_factor = 1; 1056 } else { 1057 dev->caps.eqe_size = 32; 1058 dev->caps.eqe_factor = 0; 1059 } 1060 1061 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1062 dev->caps.cqe_size = 64; 1063 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1064 } else { 1065 dev->caps.cqe_size = 32; 1066 } 1067 1068 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1069 dev->caps.eqe_size = hca_param->eqe_size; 1070 dev->caps.eqe_factor = 0; 1071 } 1072 1073 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1074 dev->caps.cqe_size = hca_param->cqe_size; 1075 /* User still need to know when CQE > 32B */ 1076 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1077 } 1078 1079 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1080 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1081 1082 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1083 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1084 1085 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1086 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1087 hca_param->rss_ip_frags ? "on" : "off"); 1088 1089 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1090 dev->caps.bf_reg_size) 1091 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1092 1093 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1094 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1095 1096 err_mem: 1097 if (err) 1098 mlx4_slave_destroy_special_qp_cap(dev); 1099 free_mem: 1100 kfree(hca_param); 1101 kfree(func_cap); 1102 kfree(dev_cap); 1103 return err; 1104 } 1105 1106 static void mlx4_request_modules(struct mlx4_dev *dev) 1107 { 1108 int port; 1109 int has_ib_port = false; 1110 int has_eth_port = false; 1111 #define EN_DRV_NAME "mlx4_en" 1112 #define IB_DRV_NAME "mlx4_ib" 1113 1114 for (port = 1; port <= dev->caps.num_ports; port++) { 1115 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1116 has_ib_port = true; 1117 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1118 has_eth_port = true; 1119 } 1120 1121 if (has_eth_port) 1122 request_module_nowait(EN_DRV_NAME); 1123 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1124 request_module_nowait(IB_DRV_NAME); 1125 } 1126 1127 /* 1128 * Change the port configuration of the device. 1129 * Every user of this function must hold the port mutex. 1130 */ 1131 int mlx4_change_port_types(struct mlx4_dev *dev, 1132 enum mlx4_port_type *port_types) 1133 { 1134 int err = 0; 1135 int change = 0; 1136 int port; 1137 1138 for (port = 0; port < dev->caps.num_ports; port++) { 1139 /* Change the port type only if the new type is different 1140 * from the current, and not set to Auto */ 1141 if (port_types[port] != dev->caps.port_type[port + 1]) 1142 change = 1; 1143 } 1144 if (change) { 1145 mlx4_unregister_device(dev); 1146 for (port = 1; port <= dev->caps.num_ports; port++) { 1147 mlx4_CLOSE_PORT(dev, port); 1148 dev->caps.port_type[port] = port_types[port - 1]; 1149 err = mlx4_SET_PORT(dev, port, -1); 1150 if (err) { 1151 mlx4_err(dev, "Failed to set port %d, aborting\n", 1152 port); 1153 goto out; 1154 } 1155 } 1156 mlx4_set_port_mask(dev); 1157 err = mlx4_register_device(dev); 1158 if (err) { 1159 mlx4_err(dev, "Failed to register device\n"); 1160 goto out; 1161 } 1162 mlx4_request_modules(dev); 1163 } 1164 1165 out: 1166 return err; 1167 } 1168 1169 static ssize_t show_port_type(struct device *dev, 1170 struct device_attribute *attr, 1171 char *buf) 1172 { 1173 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1174 port_attr); 1175 struct mlx4_dev *mdev = info->dev; 1176 char type[8]; 1177 1178 sprintf(type, "%s", 1179 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1180 "ib" : "eth"); 1181 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1182 sprintf(buf, "auto (%s)\n", type); 1183 else 1184 sprintf(buf, "%s\n", type); 1185 1186 return strlen(buf); 1187 } 1188 1189 static int __set_port_type(struct mlx4_port_info *info, 1190 enum mlx4_port_type port_type) 1191 { 1192 struct mlx4_dev *mdev = info->dev; 1193 struct mlx4_priv *priv = mlx4_priv(mdev); 1194 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1195 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1196 int i; 1197 int err = 0; 1198 1199 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1200 mlx4_err(mdev, 1201 "Requested port type for port %d is not supported on this HCA\n", 1202 info->port); 1203 err = -EINVAL; 1204 goto err_sup; 1205 } 1206 1207 mlx4_stop_sense(mdev); 1208 mutex_lock(&priv->port_mutex); 1209 info->tmp_type = port_type; 1210 1211 /* Possible type is always the one that was delivered */ 1212 mdev->caps.possible_type[info->port] = info->tmp_type; 1213 1214 for (i = 0; i < mdev->caps.num_ports; i++) { 1215 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1216 mdev->caps.possible_type[i+1]; 1217 if (types[i] == MLX4_PORT_TYPE_AUTO) 1218 types[i] = mdev->caps.port_type[i+1]; 1219 } 1220 1221 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1222 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1223 for (i = 1; i <= mdev->caps.num_ports; i++) { 1224 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1225 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1226 err = -EINVAL; 1227 } 1228 } 1229 } 1230 if (err) { 1231 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1232 goto out; 1233 } 1234 1235 mlx4_do_sense_ports(mdev, new_types, types); 1236 1237 err = mlx4_check_port_params(mdev, new_types); 1238 if (err) 1239 goto out; 1240 1241 /* We are about to apply the changes after the configuration 1242 * was verified, no need to remember the temporary types 1243 * any more */ 1244 for (i = 0; i < mdev->caps.num_ports; i++) 1245 priv->port[i + 1].tmp_type = 0; 1246 1247 err = mlx4_change_port_types(mdev, new_types); 1248 1249 out: 1250 mlx4_start_sense(mdev); 1251 mutex_unlock(&priv->port_mutex); 1252 err_sup: 1253 return err; 1254 } 1255 1256 static ssize_t set_port_type(struct device *dev, 1257 struct device_attribute *attr, 1258 const char *buf, size_t count) 1259 { 1260 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1261 port_attr); 1262 struct mlx4_dev *mdev = info->dev; 1263 enum mlx4_port_type port_type; 1264 static DEFINE_MUTEX(set_port_type_mutex); 1265 int err; 1266 1267 mutex_lock(&set_port_type_mutex); 1268 1269 if (!strcmp(buf, "ib\n")) { 1270 port_type = MLX4_PORT_TYPE_IB; 1271 } else if (!strcmp(buf, "eth\n")) { 1272 port_type = MLX4_PORT_TYPE_ETH; 1273 } else if (!strcmp(buf, "auto\n")) { 1274 port_type = MLX4_PORT_TYPE_AUTO; 1275 } else { 1276 mlx4_err(mdev, "%s is not supported port type\n", buf); 1277 err = -EINVAL; 1278 goto err_out; 1279 } 1280 1281 err = __set_port_type(info, port_type); 1282 1283 err_out: 1284 mutex_unlock(&set_port_type_mutex); 1285 1286 return err ? err : count; 1287 } 1288 1289 enum ibta_mtu { 1290 IB_MTU_256 = 1, 1291 IB_MTU_512 = 2, 1292 IB_MTU_1024 = 3, 1293 IB_MTU_2048 = 4, 1294 IB_MTU_4096 = 5 1295 }; 1296 1297 static inline int int_to_ibta_mtu(int mtu) 1298 { 1299 switch (mtu) { 1300 case 256: return IB_MTU_256; 1301 case 512: return IB_MTU_512; 1302 case 1024: return IB_MTU_1024; 1303 case 2048: return IB_MTU_2048; 1304 case 4096: return IB_MTU_4096; 1305 default: return -1; 1306 } 1307 } 1308 1309 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1310 { 1311 switch (mtu) { 1312 case IB_MTU_256: return 256; 1313 case IB_MTU_512: return 512; 1314 case IB_MTU_1024: return 1024; 1315 case IB_MTU_2048: return 2048; 1316 case IB_MTU_4096: return 4096; 1317 default: return -1; 1318 } 1319 } 1320 1321 static ssize_t show_port_ib_mtu(struct device *dev, 1322 struct device_attribute *attr, 1323 char *buf) 1324 { 1325 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1326 port_mtu_attr); 1327 struct mlx4_dev *mdev = info->dev; 1328 1329 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1330 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1331 1332 sprintf(buf, "%d\n", 1333 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1334 return strlen(buf); 1335 } 1336 1337 static ssize_t set_port_ib_mtu(struct device *dev, 1338 struct device_attribute *attr, 1339 const char *buf, size_t count) 1340 { 1341 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1342 port_mtu_attr); 1343 struct mlx4_dev *mdev = info->dev; 1344 struct mlx4_priv *priv = mlx4_priv(mdev); 1345 int err, port, mtu, ibta_mtu = -1; 1346 1347 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1348 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1349 return -EINVAL; 1350 } 1351 1352 err = kstrtoint(buf, 0, &mtu); 1353 if (!err) 1354 ibta_mtu = int_to_ibta_mtu(mtu); 1355 1356 if (err || ibta_mtu < 0) { 1357 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1358 return -EINVAL; 1359 } 1360 1361 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1362 1363 mlx4_stop_sense(mdev); 1364 mutex_lock(&priv->port_mutex); 1365 mlx4_unregister_device(mdev); 1366 for (port = 1; port <= mdev->caps.num_ports; port++) { 1367 mlx4_CLOSE_PORT(mdev, port); 1368 err = mlx4_SET_PORT(mdev, port, -1); 1369 if (err) { 1370 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1371 port); 1372 goto err_set_port; 1373 } 1374 } 1375 err = mlx4_register_device(mdev); 1376 err_set_port: 1377 mutex_unlock(&priv->port_mutex); 1378 mlx4_start_sense(mdev); 1379 return err ? err : count; 1380 } 1381 1382 /* bond for multi-function device */ 1383 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1384 static int mlx4_mf_bond(struct mlx4_dev *dev) 1385 { 1386 int err = 0; 1387 int nvfs; 1388 struct mlx4_slaves_pport slaves_port1; 1389 struct mlx4_slaves_pport slaves_port2; 1390 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1391 1392 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1393 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1394 bitmap_and(slaves_port_1_2, 1395 slaves_port1.slaves, slaves_port2.slaves, 1396 dev->persist->num_vfs + 1); 1397 1398 /* only single port vfs are allowed */ 1399 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1400 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1401 return -EINVAL; 1402 } 1403 1404 /* number of virtual functions is number of total functions minus one 1405 * physical function for each port. 1406 */ 1407 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1408 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1409 1410 /* limit on maximum allowed VFs */ 1411 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1412 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1413 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1414 return -EINVAL; 1415 } 1416 1417 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1418 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1419 return -EINVAL; 1420 } 1421 1422 err = mlx4_bond_mac_table(dev); 1423 if (err) 1424 return err; 1425 err = mlx4_bond_vlan_table(dev); 1426 if (err) 1427 goto err1; 1428 err = mlx4_bond_fs_rules(dev); 1429 if (err) 1430 goto err2; 1431 1432 return 0; 1433 err2: 1434 (void)mlx4_unbond_vlan_table(dev); 1435 err1: 1436 (void)mlx4_unbond_mac_table(dev); 1437 return err; 1438 } 1439 1440 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1441 { 1442 int ret, ret1; 1443 1444 ret = mlx4_unbond_fs_rules(dev); 1445 if (ret) 1446 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1447 ret1 = mlx4_unbond_mac_table(dev); 1448 if (ret1) { 1449 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1450 ret = ret1; 1451 } 1452 ret1 = mlx4_unbond_vlan_table(dev); 1453 if (ret1) { 1454 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1455 ret = ret1; 1456 } 1457 return ret; 1458 } 1459 1460 int mlx4_bond(struct mlx4_dev *dev) 1461 { 1462 int ret = 0; 1463 struct mlx4_priv *priv = mlx4_priv(dev); 1464 1465 mutex_lock(&priv->bond_mutex); 1466 1467 if (!mlx4_is_bonded(dev)) { 1468 ret = mlx4_do_bond(dev, true); 1469 if (ret) 1470 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1471 if (!ret && mlx4_is_master(dev)) { 1472 ret = mlx4_mf_bond(dev); 1473 if (ret) { 1474 mlx4_err(dev, "bond for multifunction failed\n"); 1475 mlx4_do_bond(dev, false); 1476 } 1477 } 1478 } 1479 1480 mutex_unlock(&priv->bond_mutex); 1481 if (!ret) 1482 mlx4_dbg(dev, "Device is bonded\n"); 1483 1484 return ret; 1485 } 1486 EXPORT_SYMBOL_GPL(mlx4_bond); 1487 1488 int mlx4_unbond(struct mlx4_dev *dev) 1489 { 1490 int ret = 0; 1491 struct mlx4_priv *priv = mlx4_priv(dev); 1492 1493 mutex_lock(&priv->bond_mutex); 1494 1495 if (mlx4_is_bonded(dev)) { 1496 int ret2 = 0; 1497 1498 ret = mlx4_do_bond(dev, false); 1499 if (ret) 1500 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1501 if (mlx4_is_master(dev)) 1502 ret2 = mlx4_mf_unbond(dev); 1503 if (ret2) { 1504 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1505 ret = ret2; 1506 } 1507 } 1508 1509 mutex_unlock(&priv->bond_mutex); 1510 if (!ret) 1511 mlx4_dbg(dev, "Device is unbonded\n"); 1512 1513 return ret; 1514 } 1515 EXPORT_SYMBOL_GPL(mlx4_unbond); 1516 1517 1518 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1519 { 1520 u8 port1 = v2p->port1; 1521 u8 port2 = v2p->port2; 1522 struct mlx4_priv *priv = mlx4_priv(dev); 1523 int err; 1524 1525 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1526 return -EOPNOTSUPP; 1527 1528 mutex_lock(&priv->bond_mutex); 1529 1530 /* zero means keep current mapping for this port */ 1531 if (port1 == 0) 1532 port1 = priv->v2p.port1; 1533 if (port2 == 0) 1534 port2 = priv->v2p.port2; 1535 1536 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1537 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1538 (port1 == 2 && port2 == 1)) { 1539 /* besides boundary checks cross mapping makes 1540 * no sense and therefore not allowed */ 1541 err = -EINVAL; 1542 } else if ((port1 == priv->v2p.port1) && 1543 (port2 == priv->v2p.port2)) { 1544 err = 0; 1545 } else { 1546 err = mlx4_virt2phy_port_map(dev, port1, port2); 1547 if (!err) { 1548 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1549 port1, port2); 1550 priv->v2p.port1 = port1; 1551 priv->v2p.port2 = port2; 1552 } else { 1553 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1554 } 1555 } 1556 1557 mutex_unlock(&priv->bond_mutex); 1558 return err; 1559 } 1560 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1561 1562 static int mlx4_load_fw(struct mlx4_dev *dev) 1563 { 1564 struct mlx4_priv *priv = mlx4_priv(dev); 1565 int err; 1566 1567 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1568 GFP_HIGHUSER | __GFP_NOWARN, 0); 1569 if (!priv->fw.fw_icm) { 1570 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1571 return -ENOMEM; 1572 } 1573 1574 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1575 if (err) { 1576 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1577 goto err_free; 1578 } 1579 1580 err = mlx4_RUN_FW(dev); 1581 if (err) { 1582 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1583 goto err_unmap_fa; 1584 } 1585 1586 return 0; 1587 1588 err_unmap_fa: 1589 mlx4_UNMAP_FA(dev); 1590 1591 err_free: 1592 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1593 return err; 1594 } 1595 1596 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1597 int cmpt_entry_sz) 1598 { 1599 struct mlx4_priv *priv = mlx4_priv(dev); 1600 int err; 1601 int num_eqs; 1602 1603 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1604 cmpt_base + 1605 ((u64) (MLX4_CMPT_TYPE_QP * 1606 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1607 cmpt_entry_sz, dev->caps.num_qps, 1608 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1609 0, 0); 1610 if (err) 1611 goto err; 1612 1613 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1614 cmpt_base + 1615 ((u64) (MLX4_CMPT_TYPE_SRQ * 1616 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1617 cmpt_entry_sz, dev->caps.num_srqs, 1618 dev->caps.reserved_srqs, 0, 0); 1619 if (err) 1620 goto err_qp; 1621 1622 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1623 cmpt_base + 1624 ((u64) (MLX4_CMPT_TYPE_CQ * 1625 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1626 cmpt_entry_sz, dev->caps.num_cqs, 1627 dev->caps.reserved_cqs, 0, 0); 1628 if (err) 1629 goto err_srq; 1630 1631 num_eqs = dev->phys_caps.num_phys_eqs; 1632 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1633 cmpt_base + 1634 ((u64) (MLX4_CMPT_TYPE_EQ * 1635 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1636 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1637 if (err) 1638 goto err_cq; 1639 1640 return 0; 1641 1642 err_cq: 1643 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1644 1645 err_srq: 1646 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1647 1648 err_qp: 1649 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1650 1651 err: 1652 return err; 1653 } 1654 1655 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1656 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1657 { 1658 struct mlx4_priv *priv = mlx4_priv(dev); 1659 u64 aux_pages; 1660 int num_eqs; 1661 int err; 1662 1663 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1664 if (err) { 1665 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1666 return err; 1667 } 1668 1669 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1670 (unsigned long long) icm_size >> 10, 1671 (unsigned long long) aux_pages << 2); 1672 1673 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1674 GFP_HIGHUSER | __GFP_NOWARN, 0); 1675 if (!priv->fw.aux_icm) { 1676 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1677 return -ENOMEM; 1678 } 1679 1680 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1681 if (err) { 1682 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1683 goto err_free_aux; 1684 } 1685 1686 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1687 if (err) { 1688 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1689 goto err_unmap_aux; 1690 } 1691 1692 1693 num_eqs = dev->phys_caps.num_phys_eqs; 1694 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1695 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1696 num_eqs, num_eqs, 0, 0); 1697 if (err) { 1698 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1699 goto err_unmap_cmpt; 1700 } 1701 1702 /* 1703 * Reserved MTT entries must be aligned up to a cacheline 1704 * boundary, since the FW will write to them, while the driver 1705 * writes to all other MTT entries. (The variable 1706 * dev->caps.mtt_entry_sz below is really the MTT segment 1707 * size, not the raw entry size) 1708 */ 1709 dev->caps.reserved_mtts = 1710 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1711 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1712 1713 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1714 init_hca->mtt_base, 1715 dev->caps.mtt_entry_sz, 1716 dev->caps.num_mtts, 1717 dev->caps.reserved_mtts, 1, 0); 1718 if (err) { 1719 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1720 goto err_unmap_eq; 1721 } 1722 1723 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1724 init_hca->dmpt_base, 1725 dev_cap->dmpt_entry_sz, 1726 dev->caps.num_mpts, 1727 dev->caps.reserved_mrws, 1, 1); 1728 if (err) { 1729 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1730 goto err_unmap_mtt; 1731 } 1732 1733 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1734 init_hca->qpc_base, 1735 dev_cap->qpc_entry_sz, 1736 dev->caps.num_qps, 1737 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1738 0, 0); 1739 if (err) { 1740 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1741 goto err_unmap_dmpt; 1742 } 1743 1744 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1745 init_hca->auxc_base, 1746 dev_cap->aux_entry_sz, 1747 dev->caps.num_qps, 1748 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1749 0, 0); 1750 if (err) { 1751 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1752 goto err_unmap_qp; 1753 } 1754 1755 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1756 init_hca->altc_base, 1757 dev_cap->altc_entry_sz, 1758 dev->caps.num_qps, 1759 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1760 0, 0); 1761 if (err) { 1762 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1763 goto err_unmap_auxc; 1764 } 1765 1766 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1767 init_hca->rdmarc_base, 1768 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1769 dev->caps.num_qps, 1770 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1771 0, 0); 1772 if (err) { 1773 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1774 goto err_unmap_altc; 1775 } 1776 1777 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1778 init_hca->cqc_base, 1779 dev_cap->cqc_entry_sz, 1780 dev->caps.num_cqs, 1781 dev->caps.reserved_cqs, 0, 0); 1782 if (err) { 1783 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1784 goto err_unmap_rdmarc; 1785 } 1786 1787 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1788 init_hca->srqc_base, 1789 dev_cap->srq_entry_sz, 1790 dev->caps.num_srqs, 1791 dev->caps.reserved_srqs, 0, 0); 1792 if (err) { 1793 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1794 goto err_unmap_cq; 1795 } 1796 1797 /* 1798 * For flow steering device managed mode it is required to use 1799 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1800 * required, but for simplicity just map the whole multicast 1801 * group table now. The table isn't very big and it's a lot 1802 * easier than trying to track ref counts. 1803 */ 1804 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1805 init_hca->mc_base, 1806 mlx4_get_mgm_entry_size(dev), 1807 dev->caps.num_mgms + dev->caps.num_amgms, 1808 dev->caps.num_mgms + dev->caps.num_amgms, 1809 0, 0); 1810 if (err) { 1811 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1812 goto err_unmap_srq; 1813 } 1814 1815 return 0; 1816 1817 err_unmap_srq: 1818 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1819 1820 err_unmap_cq: 1821 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1822 1823 err_unmap_rdmarc: 1824 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1825 1826 err_unmap_altc: 1827 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1828 1829 err_unmap_auxc: 1830 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1831 1832 err_unmap_qp: 1833 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1834 1835 err_unmap_dmpt: 1836 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1837 1838 err_unmap_mtt: 1839 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1840 1841 err_unmap_eq: 1842 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1843 1844 err_unmap_cmpt: 1845 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1846 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1847 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1848 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1849 1850 err_unmap_aux: 1851 mlx4_UNMAP_ICM_AUX(dev); 1852 1853 err_free_aux: 1854 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1855 1856 return err; 1857 } 1858 1859 static void mlx4_free_icms(struct mlx4_dev *dev) 1860 { 1861 struct mlx4_priv *priv = mlx4_priv(dev); 1862 1863 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1864 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1865 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1866 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1867 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1868 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1869 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1870 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1871 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1872 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1873 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1874 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1875 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1876 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1877 1878 mlx4_UNMAP_ICM_AUX(dev); 1879 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1880 } 1881 1882 static void mlx4_slave_exit(struct mlx4_dev *dev) 1883 { 1884 struct mlx4_priv *priv = mlx4_priv(dev); 1885 1886 mutex_lock(&priv->cmd.slave_cmd_mutex); 1887 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1888 MLX4_COMM_TIME)) 1889 mlx4_warn(dev, "Failed to close slave function\n"); 1890 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1891 } 1892 1893 static int map_bf_area(struct mlx4_dev *dev) 1894 { 1895 struct mlx4_priv *priv = mlx4_priv(dev); 1896 resource_size_t bf_start; 1897 resource_size_t bf_len; 1898 int err = 0; 1899 1900 if (!dev->caps.bf_reg_size) 1901 return -ENXIO; 1902 1903 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1904 (dev->caps.num_uars << PAGE_SHIFT); 1905 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1906 (dev->caps.num_uars << PAGE_SHIFT); 1907 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1908 if (!priv->bf_mapping) 1909 err = -ENOMEM; 1910 1911 return err; 1912 } 1913 1914 static void unmap_bf_area(struct mlx4_dev *dev) 1915 { 1916 if (mlx4_priv(dev)->bf_mapping) 1917 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1918 } 1919 1920 u64 mlx4_read_clock(struct mlx4_dev *dev) 1921 { 1922 u32 clockhi, clocklo, clockhi1; 1923 u64 cycles; 1924 int i; 1925 struct mlx4_priv *priv = mlx4_priv(dev); 1926 1927 for (i = 0; i < 10; i++) { 1928 clockhi = swab32(readl(priv->clock_mapping)); 1929 clocklo = swab32(readl(priv->clock_mapping + 4)); 1930 clockhi1 = swab32(readl(priv->clock_mapping)); 1931 if (clockhi == clockhi1) 1932 break; 1933 } 1934 1935 cycles = (u64) clockhi << 32 | (u64) clocklo; 1936 1937 return cycles; 1938 } 1939 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1940 1941 1942 static int map_internal_clock(struct mlx4_dev *dev) 1943 { 1944 struct mlx4_priv *priv = mlx4_priv(dev); 1945 1946 priv->clock_mapping = 1947 ioremap(pci_resource_start(dev->persist->pdev, 1948 priv->fw.clock_bar) + 1949 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1950 1951 if (!priv->clock_mapping) 1952 return -ENOMEM; 1953 1954 return 0; 1955 } 1956 1957 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1958 struct mlx4_clock_params *params) 1959 { 1960 struct mlx4_priv *priv = mlx4_priv(dev); 1961 1962 if (mlx4_is_slave(dev)) 1963 return -EOPNOTSUPP; 1964 1965 if (!params) 1966 return -EINVAL; 1967 1968 params->bar = priv->fw.clock_bar; 1969 params->offset = priv->fw.clock_offset; 1970 params->size = MLX4_CLOCK_SIZE; 1971 1972 return 0; 1973 } 1974 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1975 1976 static void unmap_internal_clock(struct mlx4_dev *dev) 1977 { 1978 struct mlx4_priv *priv = mlx4_priv(dev); 1979 1980 if (priv->clock_mapping) 1981 iounmap(priv->clock_mapping); 1982 } 1983 1984 static void mlx4_close_hca(struct mlx4_dev *dev) 1985 { 1986 unmap_internal_clock(dev); 1987 unmap_bf_area(dev); 1988 if (mlx4_is_slave(dev)) 1989 mlx4_slave_exit(dev); 1990 else { 1991 mlx4_CLOSE_HCA(dev, 0); 1992 mlx4_free_icms(dev); 1993 } 1994 } 1995 1996 static void mlx4_close_fw(struct mlx4_dev *dev) 1997 { 1998 if (!mlx4_is_slave(dev)) { 1999 mlx4_UNMAP_FA(dev); 2000 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 2001 } 2002 } 2003 2004 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 2005 { 2006 #define COMM_CHAN_OFFLINE_OFFSET 0x09 2007 2008 u32 comm_flags; 2009 u32 offline_bit; 2010 unsigned long end; 2011 struct mlx4_priv *priv = mlx4_priv(dev); 2012 2013 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2014 while (time_before(jiffies, end)) { 2015 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2016 MLX4_COMM_CHAN_FLAGS)); 2017 offline_bit = (comm_flags & 2018 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2019 if (!offline_bit) 2020 return 0; 2021 2022 /* If device removal has been requested, 2023 * do not continue retrying. 2024 */ 2025 if (dev->persist->interface_state & 2026 MLX4_INTERFACE_STATE_NOWAIT) 2027 break; 2028 2029 /* There are cases as part of AER/Reset flow that PF needs 2030 * around 100 msec to load. We therefore sleep for 100 msec 2031 * to allow other tasks to make use of that CPU during this 2032 * time interval. 2033 */ 2034 msleep(100); 2035 } 2036 mlx4_err(dev, "Communication channel is offline.\n"); 2037 return -EIO; 2038 } 2039 2040 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2041 { 2042 #define COMM_CHAN_RST_OFFSET 0x1e 2043 2044 struct mlx4_priv *priv = mlx4_priv(dev); 2045 u32 comm_rst; 2046 u32 comm_caps; 2047 2048 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2049 MLX4_COMM_CHAN_CAPS)); 2050 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2051 2052 if (comm_rst) 2053 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2054 } 2055 2056 static int mlx4_init_slave(struct mlx4_dev *dev) 2057 { 2058 struct mlx4_priv *priv = mlx4_priv(dev); 2059 u64 dma = (u64) priv->mfunc.vhcr_dma; 2060 int ret_from_reset = 0; 2061 u32 slave_read; 2062 u32 cmd_channel_ver; 2063 2064 if (atomic_read(&pf_loading)) { 2065 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2066 return -EPROBE_DEFER; 2067 } 2068 2069 mutex_lock(&priv->cmd.slave_cmd_mutex); 2070 priv->cmd.max_cmds = 1; 2071 if (mlx4_comm_check_offline(dev)) { 2072 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2073 goto err_offline; 2074 } 2075 2076 mlx4_reset_vf_support(dev); 2077 mlx4_warn(dev, "Sending reset\n"); 2078 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2079 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2080 /* if we are in the middle of flr the slave will try 2081 * NUM_OF_RESET_RETRIES times before leaving.*/ 2082 if (ret_from_reset) { 2083 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2084 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2085 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2086 return -EPROBE_DEFER; 2087 } else 2088 goto err; 2089 } 2090 2091 /* check the driver version - the slave I/F revision 2092 * must match the master's */ 2093 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2094 cmd_channel_ver = mlx4_comm_get_version(); 2095 2096 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2097 MLX4_COMM_GET_IF_REV(slave_read)) { 2098 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2099 goto err; 2100 } 2101 2102 mlx4_warn(dev, "Sending vhcr0\n"); 2103 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2104 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2105 goto err; 2106 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2107 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2108 goto err; 2109 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2110 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2111 goto err; 2112 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2113 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2114 goto err; 2115 2116 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2117 return 0; 2118 2119 err: 2120 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2121 err_offline: 2122 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2123 return -EIO; 2124 } 2125 2126 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2127 { 2128 int i; 2129 2130 for (i = 1; i <= dev->caps.num_ports; i++) { 2131 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2132 dev->caps.gid_table_len[i] = 2133 mlx4_get_slave_num_gids(dev, 0, i); 2134 else 2135 dev->caps.gid_table_len[i] = 1; 2136 dev->caps.pkey_table_len[i] = 2137 dev->phys_caps.pkey_phys_table_len[i] - 1; 2138 } 2139 } 2140 2141 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2142 { 2143 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2144 2145 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2146 i++) { 2147 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2148 break; 2149 } 2150 2151 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2152 } 2153 2154 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2155 { 2156 switch (dmfs_high_steer_mode) { 2157 case MLX4_STEERING_DMFS_A0_DEFAULT: 2158 return "default performance"; 2159 2160 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2161 return "dynamic hybrid mode"; 2162 2163 case MLX4_STEERING_DMFS_A0_STATIC: 2164 return "performance optimized for limited rule configuration (static)"; 2165 2166 case MLX4_STEERING_DMFS_A0_DISABLE: 2167 return "disabled performance optimized steering"; 2168 2169 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2170 return "performance optimized steering not supported"; 2171 2172 default: 2173 return "Unrecognized mode"; 2174 } 2175 } 2176 2177 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2178 2179 static void choose_steering_mode(struct mlx4_dev *dev, 2180 struct mlx4_dev_cap *dev_cap) 2181 { 2182 if (mlx4_log_num_mgm_entry_size <= 0) { 2183 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2184 if (dev->caps.dmfs_high_steer_mode == 2185 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2186 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2187 else 2188 dev->caps.dmfs_high_steer_mode = 2189 MLX4_STEERING_DMFS_A0_STATIC; 2190 } 2191 } 2192 2193 if (mlx4_log_num_mgm_entry_size <= 0 && 2194 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2195 (!mlx4_is_mfunc(dev) || 2196 (dev_cap->fs_max_num_qp_per_entry >= 2197 (dev->persist->num_vfs + 1))) && 2198 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2199 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2200 dev->oper_log_mgm_entry_size = 2201 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2202 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2203 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2204 dev->caps.fs_log_max_ucast_qp_range_size = 2205 dev_cap->fs_log_max_ucast_qp_range_size; 2206 } else { 2207 if (dev->caps.dmfs_high_steer_mode != 2208 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2209 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2210 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2211 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2212 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2213 else { 2214 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2215 2216 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2217 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2218 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2219 } 2220 dev->oper_log_mgm_entry_size = 2221 mlx4_log_num_mgm_entry_size > 0 ? 2222 mlx4_log_num_mgm_entry_size : 2223 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2224 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2225 } 2226 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2227 mlx4_steering_mode_str(dev->caps.steering_mode), 2228 dev->oper_log_mgm_entry_size, 2229 mlx4_log_num_mgm_entry_size); 2230 } 2231 2232 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2233 struct mlx4_dev_cap *dev_cap) 2234 { 2235 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2236 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2237 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2238 else 2239 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2240 2241 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2242 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2243 } 2244 2245 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2246 { 2247 int i; 2248 struct mlx4_port_cap port_cap; 2249 2250 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2251 return -EINVAL; 2252 2253 for (i = 1; i <= dev->caps.num_ports; i++) { 2254 if (mlx4_dev_port(dev, i, &port_cap)) { 2255 mlx4_err(dev, 2256 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 2257 } else if ((dev->caps.dmfs_high_steer_mode != 2258 MLX4_STEERING_DMFS_A0_DEFAULT) && 2259 (port_cap.dmfs_optimized_state == 2260 !!(dev->caps.dmfs_high_steer_mode == 2261 MLX4_STEERING_DMFS_A0_DISABLE))) { 2262 mlx4_err(dev, 2263 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2264 dmfs_high_rate_steering_mode_str( 2265 dev->caps.dmfs_high_steer_mode), 2266 (port_cap.dmfs_optimized_state ? 2267 "enabled" : "disabled")); 2268 } 2269 } 2270 2271 return 0; 2272 } 2273 2274 static int mlx4_init_fw(struct mlx4_dev *dev) 2275 { 2276 struct mlx4_mod_stat_cfg mlx4_cfg; 2277 int err = 0; 2278 2279 if (!mlx4_is_slave(dev)) { 2280 err = mlx4_QUERY_FW(dev); 2281 if (err) { 2282 if (err == -EACCES) 2283 mlx4_info(dev, "non-primary physical function, skipping\n"); 2284 else 2285 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2286 return err; 2287 } 2288 2289 err = mlx4_load_fw(dev); 2290 if (err) { 2291 mlx4_err(dev, "Failed to start FW, aborting\n"); 2292 return err; 2293 } 2294 2295 mlx4_cfg.log_pg_sz_m = 1; 2296 mlx4_cfg.log_pg_sz = 0; 2297 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2298 if (err) 2299 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2300 } 2301 2302 return err; 2303 } 2304 2305 static int mlx4_init_hca(struct mlx4_dev *dev) 2306 { 2307 struct mlx4_priv *priv = mlx4_priv(dev); 2308 struct mlx4_adapter adapter; 2309 struct mlx4_dev_cap dev_cap; 2310 struct mlx4_profile profile; 2311 struct mlx4_init_hca_param init_hca; 2312 u64 icm_size; 2313 struct mlx4_config_dev_params params; 2314 int err; 2315 2316 if (!mlx4_is_slave(dev)) { 2317 err = mlx4_dev_cap(dev, &dev_cap); 2318 if (err) { 2319 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2320 return err; 2321 } 2322 2323 choose_steering_mode(dev, &dev_cap); 2324 choose_tunnel_offload_mode(dev, &dev_cap); 2325 2326 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2327 mlx4_is_master(dev)) 2328 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2329 2330 err = mlx4_get_phys_port_id(dev); 2331 if (err) 2332 mlx4_err(dev, "Fail to get physical port id\n"); 2333 2334 if (mlx4_is_master(dev)) 2335 mlx4_parav_master_pf_caps(dev); 2336 2337 if (mlx4_low_memory_profile()) { 2338 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2339 profile = low_mem_profile; 2340 } else { 2341 profile = default_profile; 2342 } 2343 if (dev->caps.steering_mode == 2344 MLX4_STEERING_MODE_DEVICE_MANAGED) 2345 profile.num_mcg = MLX4_FS_NUM_MCG; 2346 2347 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2348 &init_hca); 2349 if ((long long) icm_size < 0) { 2350 err = icm_size; 2351 return err; 2352 } 2353 2354 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2355 2356 if (enable_4k_uar || !dev->persist->num_vfs) { 2357 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) + 2358 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2359 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2360 } else { 2361 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2362 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2363 } 2364 2365 init_hca.mw_enabled = 0; 2366 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2367 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2368 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2369 2370 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2371 if (err) 2372 return err; 2373 2374 err = mlx4_INIT_HCA(dev, &init_hca); 2375 if (err) { 2376 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2377 goto err_free_icm; 2378 } 2379 2380 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2381 err = mlx4_query_func(dev, &dev_cap); 2382 if (err < 0) { 2383 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2384 goto err_close; 2385 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2386 dev->caps.num_eqs = dev_cap.max_eqs; 2387 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2388 dev->caps.reserved_uars = dev_cap.reserved_uars; 2389 } 2390 } 2391 2392 /* 2393 * If TS is supported by FW 2394 * read HCA frequency by QUERY_HCA command 2395 */ 2396 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2397 memset(&init_hca, 0, sizeof(init_hca)); 2398 err = mlx4_QUERY_HCA(dev, &init_hca); 2399 if (err) { 2400 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2401 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2402 } else { 2403 dev->caps.hca_core_clock = 2404 init_hca.hca_core_clock; 2405 } 2406 2407 /* In case we got HCA frequency 0 - disable timestamping 2408 * to avoid dividing by zero 2409 */ 2410 if (!dev->caps.hca_core_clock) { 2411 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2412 mlx4_err(dev, 2413 "HCA frequency is 0 - timestamping is not supported\n"); 2414 } else if (map_internal_clock(dev)) { 2415 /* 2416 * Map internal clock, 2417 * in case of failure disable timestamping 2418 */ 2419 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2420 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2421 } 2422 } 2423 2424 if (dev->caps.dmfs_high_steer_mode != 2425 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2426 if (mlx4_validate_optimized_steering(dev)) 2427 mlx4_warn(dev, "Optimized steering validation failed\n"); 2428 2429 if (dev->caps.dmfs_high_steer_mode == 2430 MLX4_STEERING_DMFS_A0_DISABLE) { 2431 dev->caps.dmfs_high_rate_qpn_base = 2432 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2433 dev->caps.dmfs_high_rate_qpn_range = 2434 MLX4_A0_STEERING_TABLE_SIZE; 2435 } 2436 2437 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2438 dmfs_high_rate_steering_mode_str( 2439 dev->caps.dmfs_high_steer_mode)); 2440 } 2441 } else { 2442 err = mlx4_init_slave(dev); 2443 if (err) { 2444 if (err != -EPROBE_DEFER) 2445 mlx4_err(dev, "Failed to initialize slave\n"); 2446 return err; 2447 } 2448 2449 err = mlx4_slave_cap(dev); 2450 if (err) { 2451 mlx4_err(dev, "Failed to obtain slave caps\n"); 2452 goto err_close; 2453 } 2454 } 2455 2456 if (map_bf_area(dev)) 2457 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2458 2459 /*Only the master set the ports, all the rest got it from it.*/ 2460 if (!mlx4_is_slave(dev)) 2461 mlx4_set_port_mask(dev); 2462 2463 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2464 if (err) { 2465 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2466 goto unmap_bf; 2467 } 2468 2469 /* Query CONFIG_DEV parameters */ 2470 err = mlx4_config_dev_retrieval(dev, ¶ms); 2471 if (err && err != -EOPNOTSUPP) { 2472 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2473 } else if (!err) { 2474 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2475 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2476 } 2477 priv->eq_table.inta_pin = adapter.inta_pin; 2478 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2479 2480 return 0; 2481 2482 unmap_bf: 2483 unmap_internal_clock(dev); 2484 unmap_bf_area(dev); 2485 2486 if (mlx4_is_slave(dev)) 2487 mlx4_slave_destroy_special_qp_cap(dev); 2488 2489 err_close: 2490 if (mlx4_is_slave(dev)) 2491 mlx4_slave_exit(dev); 2492 else 2493 mlx4_CLOSE_HCA(dev, 0); 2494 2495 err_free_icm: 2496 if (!mlx4_is_slave(dev)) 2497 mlx4_free_icms(dev); 2498 2499 return err; 2500 } 2501 2502 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2503 { 2504 struct mlx4_priv *priv = mlx4_priv(dev); 2505 int nent_pow2; 2506 2507 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2508 return -ENOENT; 2509 2510 if (!dev->caps.max_counters) 2511 return -ENOSPC; 2512 2513 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2514 /* reserve last counter index for sink counter */ 2515 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2516 nent_pow2 - 1, 0, 2517 nent_pow2 - dev->caps.max_counters + 1); 2518 } 2519 2520 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2521 { 2522 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2523 return; 2524 2525 if (!dev->caps.max_counters) 2526 return; 2527 2528 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2529 } 2530 2531 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2532 { 2533 struct mlx4_priv *priv = mlx4_priv(dev); 2534 int port; 2535 2536 for (port = 0; port < dev->caps.num_ports; port++) 2537 if (priv->def_counter[port] != -1) 2538 mlx4_counter_free(dev, priv->def_counter[port]); 2539 } 2540 2541 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2542 { 2543 struct mlx4_priv *priv = mlx4_priv(dev); 2544 int port, err = 0; 2545 u32 idx; 2546 2547 for (port = 0; port < dev->caps.num_ports; port++) 2548 priv->def_counter[port] = -1; 2549 2550 for (port = 0; port < dev->caps.num_ports; port++) { 2551 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2552 2553 if (!err || err == -ENOSPC) { 2554 priv->def_counter[port] = idx; 2555 } else if (err == -ENOENT) { 2556 err = 0; 2557 continue; 2558 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2559 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2560 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2561 MLX4_SINK_COUNTER_INDEX(dev)); 2562 err = 0; 2563 } else { 2564 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2565 __func__, port + 1, err); 2566 mlx4_cleanup_default_counters(dev); 2567 return err; 2568 } 2569 2570 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2571 __func__, priv->def_counter[port], port + 1); 2572 } 2573 2574 return err; 2575 } 2576 2577 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2578 { 2579 struct mlx4_priv *priv = mlx4_priv(dev); 2580 2581 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2582 return -ENOENT; 2583 2584 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2585 if (*idx == -1) { 2586 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2587 return -ENOSPC; 2588 } 2589 2590 return 0; 2591 } 2592 2593 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2594 { 2595 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2596 u64 out_param; 2597 int err; 2598 2599 if (mlx4_is_mfunc(dev)) { 2600 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2601 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2602 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2603 if (!err) 2604 *idx = get_param_l(&out_param); 2605 2606 return err; 2607 } 2608 return __mlx4_counter_alloc(dev, idx); 2609 } 2610 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2611 2612 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2613 u8 counter_index) 2614 { 2615 struct mlx4_cmd_mailbox *if_stat_mailbox; 2616 int err; 2617 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2618 2619 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2620 if (IS_ERR(if_stat_mailbox)) 2621 return PTR_ERR(if_stat_mailbox); 2622 2623 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2624 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2625 MLX4_CMD_NATIVE); 2626 2627 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2628 return err; 2629 } 2630 2631 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2632 { 2633 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2634 return; 2635 2636 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2637 return; 2638 2639 __mlx4_clear_if_stat(dev, idx); 2640 2641 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2642 return; 2643 } 2644 2645 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2646 { 2647 u64 in_param = 0; 2648 2649 if (mlx4_is_mfunc(dev)) { 2650 set_param_l(&in_param, idx); 2651 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2652 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2653 MLX4_CMD_WRAPPED); 2654 return; 2655 } 2656 __mlx4_counter_free(dev, idx); 2657 } 2658 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2659 2660 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2661 { 2662 struct mlx4_priv *priv = mlx4_priv(dev); 2663 2664 return priv->def_counter[port - 1]; 2665 } 2666 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2667 2668 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2669 { 2670 struct mlx4_priv *priv = mlx4_priv(dev); 2671 2672 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2673 } 2674 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2675 2676 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2677 { 2678 struct mlx4_priv *priv = mlx4_priv(dev); 2679 2680 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2681 } 2682 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2683 2684 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2685 { 2686 struct mlx4_priv *priv = mlx4_priv(dev); 2687 __be64 guid; 2688 2689 /* hw GUID */ 2690 if (entry == 0) 2691 return; 2692 2693 get_random_bytes((char *)&guid, sizeof(guid)); 2694 guid &= ~(cpu_to_be64(1ULL << 56)); 2695 guid |= cpu_to_be64(1ULL << 57); 2696 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2697 } 2698 2699 static int mlx4_setup_hca(struct mlx4_dev *dev) 2700 { 2701 struct mlx4_priv *priv = mlx4_priv(dev); 2702 int err; 2703 int port; 2704 __be32 ib_port_default_caps; 2705 2706 err = mlx4_init_uar_table(dev); 2707 if (err) { 2708 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2709 return err; 2710 } 2711 2712 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2713 if (err) { 2714 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2715 goto err_uar_table_free; 2716 } 2717 2718 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2719 if (!priv->kar) { 2720 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2721 err = -ENOMEM; 2722 goto err_uar_free; 2723 } 2724 2725 err = mlx4_init_pd_table(dev); 2726 if (err) { 2727 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2728 goto err_kar_unmap; 2729 } 2730 2731 err = mlx4_init_xrcd_table(dev); 2732 if (err) { 2733 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2734 goto err_pd_table_free; 2735 } 2736 2737 err = mlx4_init_mr_table(dev); 2738 if (err) { 2739 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2740 goto err_xrcd_table_free; 2741 } 2742 2743 if (!mlx4_is_slave(dev)) { 2744 err = mlx4_init_mcg_table(dev); 2745 if (err) { 2746 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2747 goto err_mr_table_free; 2748 } 2749 err = mlx4_config_mad_demux(dev); 2750 if (err) { 2751 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2752 goto err_mcg_table_free; 2753 } 2754 } 2755 2756 err = mlx4_init_eq_table(dev); 2757 if (err) { 2758 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2759 goto err_mcg_table_free; 2760 } 2761 2762 err = mlx4_cmd_use_events(dev); 2763 if (err) { 2764 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2765 goto err_eq_table_free; 2766 } 2767 2768 err = mlx4_NOP(dev); 2769 if (err) { 2770 if (dev->flags & MLX4_FLAG_MSI_X) { 2771 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2772 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2773 mlx4_warn(dev, "Trying again without MSI-X\n"); 2774 } else { 2775 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2776 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2777 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2778 } 2779 2780 goto err_cmd_poll; 2781 } 2782 2783 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2784 2785 err = mlx4_init_cq_table(dev); 2786 if (err) { 2787 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2788 goto err_cmd_poll; 2789 } 2790 2791 err = mlx4_init_srq_table(dev); 2792 if (err) { 2793 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2794 goto err_cq_table_free; 2795 } 2796 2797 err = mlx4_init_qp_table(dev); 2798 if (err) { 2799 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2800 goto err_srq_table_free; 2801 } 2802 2803 if (!mlx4_is_slave(dev)) { 2804 err = mlx4_init_counters_table(dev); 2805 if (err && err != -ENOENT) { 2806 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2807 goto err_qp_table_free; 2808 } 2809 } 2810 2811 err = mlx4_allocate_default_counters(dev); 2812 if (err) { 2813 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2814 goto err_counters_table_free; 2815 } 2816 2817 if (!mlx4_is_slave(dev)) { 2818 for (port = 1; port <= dev->caps.num_ports; port++) { 2819 ib_port_default_caps = 0; 2820 err = mlx4_get_port_ib_caps(dev, port, 2821 &ib_port_default_caps); 2822 if (err) 2823 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2824 port, err); 2825 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2826 2827 /* initialize per-slave default ib port capabilities */ 2828 if (mlx4_is_master(dev)) { 2829 int i; 2830 for (i = 0; i < dev->num_slaves; i++) { 2831 if (i == mlx4_master_func_num(dev)) 2832 continue; 2833 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2834 ib_port_default_caps; 2835 } 2836 } 2837 2838 if (mlx4_is_mfunc(dev)) 2839 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2840 else 2841 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2842 2843 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2844 dev->caps.pkey_table_len[port] : -1); 2845 if (err) { 2846 mlx4_err(dev, "Failed to set port %d, aborting\n", 2847 port); 2848 goto err_default_countes_free; 2849 } 2850 } 2851 } 2852 2853 return 0; 2854 2855 err_default_countes_free: 2856 mlx4_cleanup_default_counters(dev); 2857 2858 err_counters_table_free: 2859 if (!mlx4_is_slave(dev)) 2860 mlx4_cleanup_counters_table(dev); 2861 2862 err_qp_table_free: 2863 mlx4_cleanup_qp_table(dev); 2864 2865 err_srq_table_free: 2866 mlx4_cleanup_srq_table(dev); 2867 2868 err_cq_table_free: 2869 mlx4_cleanup_cq_table(dev); 2870 2871 err_cmd_poll: 2872 mlx4_cmd_use_polling(dev); 2873 2874 err_eq_table_free: 2875 mlx4_cleanup_eq_table(dev); 2876 2877 err_mcg_table_free: 2878 if (!mlx4_is_slave(dev)) 2879 mlx4_cleanup_mcg_table(dev); 2880 2881 err_mr_table_free: 2882 mlx4_cleanup_mr_table(dev); 2883 2884 err_xrcd_table_free: 2885 mlx4_cleanup_xrcd_table(dev); 2886 2887 err_pd_table_free: 2888 mlx4_cleanup_pd_table(dev); 2889 2890 err_kar_unmap: 2891 iounmap(priv->kar); 2892 2893 err_uar_free: 2894 mlx4_uar_free(dev, &priv->driver_uar); 2895 2896 err_uar_table_free: 2897 mlx4_cleanup_uar_table(dev); 2898 return err; 2899 } 2900 2901 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2902 { 2903 int requested_cpu = 0; 2904 struct mlx4_priv *priv = mlx4_priv(dev); 2905 struct mlx4_eq *eq; 2906 int off = 0; 2907 int i; 2908 2909 if (eqn > dev->caps.num_comp_vectors) 2910 return -EINVAL; 2911 2912 for (i = 1; i < port; i++) 2913 off += mlx4_get_eqs_per_port(dev, i); 2914 2915 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2916 2917 /* Meaning EQs are shared, and this call comes from the second port */ 2918 if (requested_cpu < 0) 2919 return 0; 2920 2921 eq = &priv->eq_table.eq[eqn]; 2922 2923 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2924 return -ENOMEM; 2925 2926 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2927 2928 return 0; 2929 } 2930 2931 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2932 { 2933 struct mlx4_priv *priv = mlx4_priv(dev); 2934 struct msix_entry *entries; 2935 int i; 2936 int port = 0; 2937 2938 if (msi_x) { 2939 int nreq = min3(dev->caps.num_ports * 2940 (int)num_online_cpus() + 1, 2941 dev->caps.num_eqs - dev->caps.reserved_eqs, 2942 MAX_MSIX); 2943 2944 if (msi_x > 1) 2945 nreq = min_t(int, nreq, msi_x); 2946 2947 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2948 if (!entries) 2949 goto no_msi; 2950 2951 for (i = 0; i < nreq; ++i) 2952 entries[i].entry = i; 2953 2954 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2955 nreq); 2956 2957 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2958 kfree(entries); 2959 goto no_msi; 2960 } 2961 /* 1 is reserved for events (asyncrounous EQ) */ 2962 dev->caps.num_comp_vectors = nreq - 1; 2963 2964 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2965 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2966 dev->caps.num_ports); 2967 2968 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2969 if (i == MLX4_EQ_ASYNC) 2970 continue; 2971 2972 priv->eq_table.eq[i].irq = 2973 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2974 2975 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2976 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2977 dev->caps.num_ports); 2978 /* We don't set affinity hint when there 2979 * aren't enough EQs 2980 */ 2981 } else { 2982 set_bit(port, 2983 priv->eq_table.eq[i].actv_ports.ports); 2984 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2985 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2986 i); 2987 } 2988 /* We divide the Eqs evenly between the two ports. 2989 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2990 * refers to the number of Eqs per port 2991 * (i.e eqs_per_port). Theoretically, we would like to 2992 * write something like (i + 1) % eqs_per_port == 0. 2993 * However, since there's an asynchronous Eq, we have 2994 * to skip over it by comparing this condition to 2995 * !!((i + 1) > MLX4_EQ_ASYNC). 2996 */ 2997 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2998 ((i + 1) % 2999 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 3000 !!((i + 1) > MLX4_EQ_ASYNC)) 3001 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 3002 * everything is shared anyway. 3003 */ 3004 port++; 3005 } 3006 3007 dev->flags |= MLX4_FLAG_MSI_X; 3008 3009 kfree(entries); 3010 return; 3011 } 3012 3013 no_msi: 3014 dev->caps.num_comp_vectors = 1; 3015 3016 BUG_ON(MLX4_EQ_ASYNC >= 2); 3017 for (i = 0; i < 2; ++i) { 3018 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3019 if (i != MLX4_EQ_ASYNC) { 3020 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3021 dev->caps.num_ports); 3022 } 3023 } 3024 } 3025 3026 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3027 { 3028 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3029 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3030 int err; 3031 3032 err = devlink_port_register(devlink, &info->devlink_port, port); 3033 if (err) 3034 return err; 3035 3036 info->dev = dev; 3037 info->port = port; 3038 if (!mlx4_is_slave(dev)) { 3039 mlx4_init_mac_table(dev, &info->mac_table); 3040 mlx4_init_vlan_table(dev, &info->vlan_table); 3041 mlx4_init_roce_gid_table(dev, &info->gid_table); 3042 info->base_qpn = mlx4_get_base_qpn(dev, port); 3043 } 3044 3045 sprintf(info->dev_name, "mlx4_port%d", port); 3046 info->port_attr.attr.name = info->dev_name; 3047 if (mlx4_is_mfunc(dev)) { 3048 info->port_attr.attr.mode = 0444; 3049 } else { 3050 info->port_attr.attr.mode = 0644; 3051 info->port_attr.store = set_port_type; 3052 } 3053 info->port_attr.show = show_port_type; 3054 sysfs_attr_init(&info->port_attr.attr); 3055 3056 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3057 if (err) { 3058 mlx4_err(dev, "Failed to create file for port %d\n", port); 3059 devlink_port_unregister(&info->devlink_port); 3060 info->port = -1; 3061 return err; 3062 } 3063 3064 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3065 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3066 if (mlx4_is_mfunc(dev)) { 3067 info->port_mtu_attr.attr.mode = 0444; 3068 } else { 3069 info->port_mtu_attr.attr.mode = 0644; 3070 info->port_mtu_attr.store = set_port_ib_mtu; 3071 } 3072 info->port_mtu_attr.show = show_port_ib_mtu; 3073 sysfs_attr_init(&info->port_mtu_attr.attr); 3074 3075 err = device_create_file(&dev->persist->pdev->dev, 3076 &info->port_mtu_attr); 3077 if (err) { 3078 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3079 device_remove_file(&info->dev->persist->pdev->dev, 3080 &info->port_attr); 3081 devlink_port_unregister(&info->devlink_port); 3082 info->port = -1; 3083 return err; 3084 } 3085 3086 return 0; 3087 } 3088 3089 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3090 { 3091 if (info->port < 0) 3092 return; 3093 3094 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3095 device_remove_file(&info->dev->persist->pdev->dev, 3096 &info->port_mtu_attr); 3097 devlink_port_unregister(&info->devlink_port); 3098 3099 #ifdef CONFIG_RFS_ACCEL 3100 free_irq_cpu_rmap(info->rmap); 3101 info->rmap = NULL; 3102 #endif 3103 } 3104 3105 static int mlx4_init_steering(struct mlx4_dev *dev) 3106 { 3107 struct mlx4_priv *priv = mlx4_priv(dev); 3108 int num_entries = dev->caps.num_ports; 3109 int i, j; 3110 3111 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3112 GFP_KERNEL); 3113 if (!priv->steer) 3114 return -ENOMEM; 3115 3116 for (i = 0; i < num_entries; i++) 3117 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3118 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3119 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3120 } 3121 return 0; 3122 } 3123 3124 static void mlx4_clear_steering(struct mlx4_dev *dev) 3125 { 3126 struct mlx4_priv *priv = mlx4_priv(dev); 3127 struct mlx4_steer_index *entry, *tmp_entry; 3128 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3129 int num_entries = dev->caps.num_ports; 3130 int i, j; 3131 3132 for (i = 0; i < num_entries; i++) { 3133 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3134 list_for_each_entry_safe(pqp, tmp_pqp, 3135 &priv->steer[i].promisc_qps[j], 3136 list) { 3137 list_del(&pqp->list); 3138 kfree(pqp); 3139 } 3140 list_for_each_entry_safe(entry, tmp_entry, 3141 &priv->steer[i].steer_entries[j], 3142 list) { 3143 list_del(&entry->list); 3144 list_for_each_entry_safe(pqp, tmp_pqp, 3145 &entry->duplicates, 3146 list) { 3147 list_del(&pqp->list); 3148 kfree(pqp); 3149 } 3150 kfree(entry); 3151 } 3152 } 3153 } 3154 kfree(priv->steer); 3155 } 3156 3157 static int extended_func_num(struct pci_dev *pdev) 3158 { 3159 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3160 } 3161 3162 #define MLX4_OWNER_BASE 0x8069c 3163 #define MLX4_OWNER_SIZE 4 3164 3165 static int mlx4_get_ownership(struct mlx4_dev *dev) 3166 { 3167 void __iomem *owner; 3168 u32 ret; 3169 3170 if (pci_channel_offline(dev->persist->pdev)) 3171 return -EIO; 3172 3173 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3174 MLX4_OWNER_BASE, 3175 MLX4_OWNER_SIZE); 3176 if (!owner) { 3177 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3178 return -ENOMEM; 3179 } 3180 3181 ret = readl(owner); 3182 iounmap(owner); 3183 return (int) !!ret; 3184 } 3185 3186 static void mlx4_free_ownership(struct mlx4_dev *dev) 3187 { 3188 void __iomem *owner; 3189 3190 if (pci_channel_offline(dev->persist->pdev)) 3191 return; 3192 3193 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3194 MLX4_OWNER_BASE, 3195 MLX4_OWNER_SIZE); 3196 if (!owner) { 3197 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3198 return; 3199 } 3200 writel(0, owner); 3201 msleep(1000); 3202 iounmap(owner); 3203 } 3204 3205 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3206 !!((flags) & MLX4_FLAG_MASTER)) 3207 3208 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3209 u8 total_vfs, int existing_vfs, int reset_flow) 3210 { 3211 u64 dev_flags = dev->flags; 3212 int err = 0; 3213 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3214 MLX4_MAX_NUM_VF); 3215 3216 if (reset_flow) { 3217 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3218 GFP_KERNEL); 3219 if (!dev->dev_vfs) 3220 goto free_mem; 3221 return dev_flags; 3222 } 3223 3224 atomic_inc(&pf_loading); 3225 if (dev->flags & MLX4_FLAG_SRIOV) { 3226 if (existing_vfs != total_vfs) { 3227 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3228 existing_vfs, total_vfs); 3229 total_vfs = existing_vfs; 3230 } 3231 } 3232 3233 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3234 if (NULL == dev->dev_vfs) { 3235 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3236 goto disable_sriov; 3237 } 3238 3239 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3240 if (total_vfs > fw_enabled_sriov_vfs) { 3241 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3242 total_vfs, fw_enabled_sriov_vfs); 3243 err = -ENOMEM; 3244 goto disable_sriov; 3245 } 3246 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3247 err = pci_enable_sriov(pdev, total_vfs); 3248 } 3249 if (err) { 3250 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3251 err); 3252 goto disable_sriov; 3253 } else { 3254 mlx4_warn(dev, "Running in master mode\n"); 3255 dev_flags |= MLX4_FLAG_SRIOV | 3256 MLX4_FLAG_MASTER; 3257 dev_flags &= ~MLX4_FLAG_SLAVE; 3258 dev->persist->num_vfs = total_vfs; 3259 } 3260 return dev_flags; 3261 3262 disable_sriov: 3263 atomic_dec(&pf_loading); 3264 free_mem: 3265 dev->persist->num_vfs = 0; 3266 kfree(dev->dev_vfs); 3267 dev->dev_vfs = NULL; 3268 return dev_flags & ~MLX4_FLAG_MASTER; 3269 } 3270 3271 enum { 3272 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3273 }; 3274 3275 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3276 int *nvfs) 3277 { 3278 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3279 /* Checking for 64 VFs as a limitation of CX2 */ 3280 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3281 requested_vfs >= 64) { 3282 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3283 requested_vfs); 3284 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3285 } 3286 return 0; 3287 } 3288 3289 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3290 { 3291 struct pci_dev *pdev = dev->persist->pdev; 3292 int err = 0; 3293 3294 mutex_lock(&dev->persist->pci_status_mutex); 3295 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3296 err = pci_enable_device(pdev); 3297 if (!err) 3298 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3299 } 3300 mutex_unlock(&dev->persist->pci_status_mutex); 3301 3302 return err; 3303 } 3304 3305 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3306 { 3307 struct pci_dev *pdev = dev->persist->pdev; 3308 3309 mutex_lock(&dev->persist->pci_status_mutex); 3310 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3311 pci_disable_device(pdev); 3312 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3313 } 3314 mutex_unlock(&dev->persist->pci_status_mutex); 3315 } 3316 3317 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3318 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3319 int reset_flow) 3320 { 3321 struct mlx4_dev *dev; 3322 unsigned sum = 0; 3323 int err; 3324 int port; 3325 int i; 3326 struct mlx4_dev_cap *dev_cap = NULL; 3327 int existing_vfs = 0; 3328 3329 dev = &priv->dev; 3330 3331 INIT_LIST_HEAD(&priv->ctx_list); 3332 spin_lock_init(&priv->ctx_lock); 3333 3334 mutex_init(&priv->port_mutex); 3335 mutex_init(&priv->bond_mutex); 3336 3337 INIT_LIST_HEAD(&priv->pgdir_list); 3338 mutex_init(&priv->pgdir_mutex); 3339 spin_lock_init(&priv->cmd.context_lock); 3340 3341 INIT_LIST_HEAD(&priv->bf_list); 3342 mutex_init(&priv->bf_mutex); 3343 3344 dev->rev_id = pdev->revision; 3345 dev->numa_node = dev_to_node(&pdev->dev); 3346 3347 /* Detect if this device is a virtual function */ 3348 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3349 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3350 dev->flags |= MLX4_FLAG_SLAVE; 3351 } else { 3352 /* We reset the device and enable SRIOV only for physical 3353 * devices. Try to claim ownership on the device; 3354 * if already taken, skip -- do not allow multiple PFs */ 3355 err = mlx4_get_ownership(dev); 3356 if (err) { 3357 if (err < 0) 3358 return err; 3359 else { 3360 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3361 return -EINVAL; 3362 } 3363 } 3364 3365 atomic_set(&priv->opreq_count, 0); 3366 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3367 3368 /* 3369 * Now reset the HCA before we touch the PCI capabilities or 3370 * attempt a firmware command, since a boot ROM may have left 3371 * the HCA in an undefined state. 3372 */ 3373 err = mlx4_reset(dev); 3374 if (err) { 3375 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3376 goto err_sriov; 3377 } 3378 3379 if (total_vfs) { 3380 dev->flags = MLX4_FLAG_MASTER; 3381 existing_vfs = pci_num_vf(pdev); 3382 if (existing_vfs) 3383 dev->flags |= MLX4_FLAG_SRIOV; 3384 dev->persist->num_vfs = total_vfs; 3385 } 3386 } 3387 3388 /* on load remove any previous indication of internal error, 3389 * device is up. 3390 */ 3391 dev->persist->state = MLX4_DEVICE_STATE_UP; 3392 3393 slave_start: 3394 err = mlx4_cmd_init(dev); 3395 if (err) { 3396 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3397 goto err_sriov; 3398 } 3399 3400 /* In slave functions, the communication channel must be initialized 3401 * before posting commands. Also, init num_slaves before calling 3402 * mlx4_init_hca */ 3403 if (mlx4_is_mfunc(dev)) { 3404 if (mlx4_is_master(dev)) { 3405 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3406 3407 } else { 3408 dev->num_slaves = 0; 3409 err = mlx4_multi_func_init(dev); 3410 if (err) { 3411 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3412 goto err_cmd; 3413 } 3414 } 3415 } 3416 3417 err = mlx4_init_fw(dev); 3418 if (err) { 3419 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3420 goto err_mfunc; 3421 } 3422 3423 if (mlx4_is_master(dev)) { 3424 /* when we hit the goto slave_start below, dev_cap already initialized */ 3425 if (!dev_cap) { 3426 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3427 3428 if (!dev_cap) { 3429 err = -ENOMEM; 3430 goto err_fw; 3431 } 3432 3433 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3434 if (err) { 3435 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3436 goto err_fw; 3437 } 3438 3439 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3440 goto err_fw; 3441 3442 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3443 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3444 total_vfs, 3445 existing_vfs, 3446 reset_flow); 3447 3448 mlx4_close_fw(dev); 3449 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3450 dev->flags = dev_flags; 3451 if (!SRIOV_VALID_STATE(dev->flags)) { 3452 mlx4_err(dev, "Invalid SRIOV state\n"); 3453 goto err_sriov; 3454 } 3455 err = mlx4_reset(dev); 3456 if (err) { 3457 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3458 goto err_sriov; 3459 } 3460 goto slave_start; 3461 } 3462 } else { 3463 /* Legacy mode FW requires SRIOV to be enabled before 3464 * doing QUERY_DEV_CAP, since max_eq's value is different if 3465 * SRIOV is enabled. 3466 */ 3467 memset(dev_cap, 0, sizeof(*dev_cap)); 3468 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3469 if (err) { 3470 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3471 goto err_fw; 3472 } 3473 3474 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3475 goto err_fw; 3476 } 3477 } 3478 3479 err = mlx4_init_hca(dev); 3480 if (err) { 3481 if (err == -EACCES) { 3482 /* Not primary Physical function 3483 * Running in slave mode */ 3484 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3485 /* We're not a PF */ 3486 if (dev->flags & MLX4_FLAG_SRIOV) { 3487 if (!existing_vfs) 3488 pci_disable_sriov(pdev); 3489 if (mlx4_is_master(dev) && !reset_flow) 3490 atomic_dec(&pf_loading); 3491 dev->flags &= ~MLX4_FLAG_SRIOV; 3492 } 3493 if (!mlx4_is_slave(dev)) 3494 mlx4_free_ownership(dev); 3495 dev->flags |= MLX4_FLAG_SLAVE; 3496 dev->flags &= ~MLX4_FLAG_MASTER; 3497 goto slave_start; 3498 } else 3499 goto err_fw; 3500 } 3501 3502 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3503 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3504 existing_vfs, reset_flow); 3505 3506 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3507 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3508 dev->flags = dev_flags; 3509 err = mlx4_cmd_init(dev); 3510 if (err) { 3511 /* Only VHCR is cleaned up, so could still 3512 * send FW commands 3513 */ 3514 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3515 goto err_close; 3516 } 3517 } else { 3518 dev->flags = dev_flags; 3519 } 3520 3521 if (!SRIOV_VALID_STATE(dev->flags)) { 3522 mlx4_err(dev, "Invalid SRIOV state\n"); 3523 goto err_close; 3524 } 3525 } 3526 3527 /* check if the device is functioning at its maximum possible speed. 3528 * No return code for this call, just warn the user in case of PCI 3529 * express device capabilities are under-satisfied by the bus. 3530 */ 3531 if (!mlx4_is_slave(dev)) 3532 pcie_print_link_status(dev->persist->pdev); 3533 3534 /* In master functions, the communication channel must be initialized 3535 * after obtaining its address from fw */ 3536 if (mlx4_is_master(dev)) { 3537 if (dev->caps.num_ports < 2 && 3538 num_vfs_argc > 1) { 3539 err = -EINVAL; 3540 mlx4_err(dev, 3541 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3542 dev->caps.num_ports); 3543 goto err_close; 3544 } 3545 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3546 3547 for (i = 0; 3548 i < sizeof(dev->persist->nvfs)/ 3549 sizeof(dev->persist->nvfs[0]); i++) { 3550 unsigned j; 3551 3552 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3553 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3554 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3555 dev->caps.num_ports; 3556 } 3557 } 3558 3559 /* In master functions, the communication channel 3560 * must be initialized after obtaining its address from fw 3561 */ 3562 err = mlx4_multi_func_init(dev); 3563 if (err) { 3564 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3565 goto err_close; 3566 } 3567 } 3568 3569 err = mlx4_alloc_eq_table(dev); 3570 if (err) 3571 goto err_master_mfunc; 3572 3573 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3574 mutex_init(&priv->msix_ctl.pool_lock); 3575 3576 mlx4_enable_msi_x(dev); 3577 if ((mlx4_is_mfunc(dev)) && 3578 !(dev->flags & MLX4_FLAG_MSI_X)) { 3579 err = -EOPNOTSUPP; 3580 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3581 goto err_free_eq; 3582 } 3583 3584 if (!mlx4_is_slave(dev)) { 3585 err = mlx4_init_steering(dev); 3586 if (err) 3587 goto err_disable_msix; 3588 } 3589 3590 mlx4_init_quotas(dev); 3591 3592 err = mlx4_setup_hca(dev); 3593 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3594 !mlx4_is_mfunc(dev)) { 3595 dev->flags &= ~MLX4_FLAG_MSI_X; 3596 dev->caps.num_comp_vectors = 1; 3597 pci_disable_msix(pdev); 3598 err = mlx4_setup_hca(dev); 3599 } 3600 3601 if (err) 3602 goto err_steer; 3603 3604 /* When PF resources are ready arm its comm channel to enable 3605 * getting commands 3606 */ 3607 if (mlx4_is_master(dev)) { 3608 err = mlx4_ARM_COMM_CHANNEL(dev); 3609 if (err) { 3610 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3611 err); 3612 goto err_steer; 3613 } 3614 } 3615 3616 for (port = 1; port <= dev->caps.num_ports; port++) { 3617 err = mlx4_init_port_info(dev, port); 3618 if (err) 3619 goto err_port; 3620 } 3621 3622 priv->v2p.port1 = 1; 3623 priv->v2p.port2 = 2; 3624 3625 err = mlx4_register_device(dev); 3626 if (err) 3627 goto err_port; 3628 3629 mlx4_request_modules(dev); 3630 3631 mlx4_sense_init(dev); 3632 mlx4_start_sense(dev); 3633 3634 priv->removed = 0; 3635 3636 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3637 atomic_dec(&pf_loading); 3638 3639 kfree(dev_cap); 3640 return 0; 3641 3642 err_port: 3643 for (--port; port >= 1; --port) 3644 mlx4_cleanup_port_info(&priv->port[port]); 3645 3646 mlx4_cleanup_default_counters(dev); 3647 if (!mlx4_is_slave(dev)) 3648 mlx4_cleanup_counters_table(dev); 3649 mlx4_cleanup_qp_table(dev); 3650 mlx4_cleanup_srq_table(dev); 3651 mlx4_cleanup_cq_table(dev); 3652 mlx4_cmd_use_polling(dev); 3653 mlx4_cleanup_eq_table(dev); 3654 mlx4_cleanup_mcg_table(dev); 3655 mlx4_cleanup_mr_table(dev); 3656 mlx4_cleanup_xrcd_table(dev); 3657 mlx4_cleanup_pd_table(dev); 3658 mlx4_cleanup_uar_table(dev); 3659 3660 err_steer: 3661 if (!mlx4_is_slave(dev)) 3662 mlx4_clear_steering(dev); 3663 3664 err_disable_msix: 3665 if (dev->flags & MLX4_FLAG_MSI_X) 3666 pci_disable_msix(pdev); 3667 3668 err_free_eq: 3669 mlx4_free_eq_table(dev); 3670 3671 err_master_mfunc: 3672 if (mlx4_is_master(dev)) { 3673 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3674 mlx4_multi_func_cleanup(dev); 3675 } 3676 3677 if (mlx4_is_slave(dev)) 3678 mlx4_slave_destroy_special_qp_cap(dev); 3679 3680 err_close: 3681 mlx4_close_hca(dev); 3682 3683 err_fw: 3684 mlx4_close_fw(dev); 3685 3686 err_mfunc: 3687 if (mlx4_is_slave(dev)) 3688 mlx4_multi_func_cleanup(dev); 3689 3690 err_cmd: 3691 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3692 3693 err_sriov: 3694 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3695 pci_disable_sriov(pdev); 3696 dev->flags &= ~MLX4_FLAG_SRIOV; 3697 } 3698 3699 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3700 atomic_dec(&pf_loading); 3701 3702 kfree(priv->dev.dev_vfs); 3703 3704 if (!mlx4_is_slave(dev)) 3705 mlx4_free_ownership(dev); 3706 3707 kfree(dev_cap); 3708 return err; 3709 } 3710 3711 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3712 struct mlx4_priv *priv) 3713 { 3714 int err; 3715 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3716 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3717 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3718 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3719 unsigned total_vfs = 0; 3720 unsigned int i; 3721 3722 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3723 3724 err = mlx4_pci_enable_device(&priv->dev); 3725 if (err) { 3726 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3727 return err; 3728 } 3729 3730 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3731 * per port, we must limit the number of VFs to 63 (since their are 3732 * 128 MACs) 3733 */ 3734 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3735 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3736 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3737 if (nvfs[i] < 0) { 3738 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3739 err = -EINVAL; 3740 goto err_disable_pdev; 3741 } 3742 } 3743 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3744 i++) { 3745 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3746 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3747 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3748 err = -EINVAL; 3749 goto err_disable_pdev; 3750 } 3751 } 3752 if (total_vfs > MLX4_MAX_NUM_VF) { 3753 dev_err(&pdev->dev, 3754 "Requested more VF's (%d) than allowed by hw (%d)\n", 3755 total_vfs, MLX4_MAX_NUM_VF); 3756 err = -EINVAL; 3757 goto err_disable_pdev; 3758 } 3759 3760 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3761 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3762 dev_err(&pdev->dev, 3763 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3764 nvfs[i] + nvfs[2], i + 1, 3765 MLX4_MAX_NUM_VF_P_PORT); 3766 err = -EINVAL; 3767 goto err_disable_pdev; 3768 } 3769 } 3770 3771 /* Check for BARs. */ 3772 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3773 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3774 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3775 pci_dev_data, pci_resource_flags(pdev, 0)); 3776 err = -ENODEV; 3777 goto err_disable_pdev; 3778 } 3779 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3780 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3781 err = -ENODEV; 3782 goto err_disable_pdev; 3783 } 3784 3785 err = pci_request_regions(pdev, DRV_NAME); 3786 if (err) { 3787 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3788 goto err_disable_pdev; 3789 } 3790 3791 pci_set_master(pdev); 3792 3793 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3794 if (err) { 3795 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3796 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3797 if (err) { 3798 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3799 goto err_release_regions; 3800 } 3801 } 3802 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3803 if (err) { 3804 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3805 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3806 if (err) { 3807 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3808 goto err_release_regions; 3809 } 3810 } 3811 3812 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3813 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3814 /* Detect if this device is a virtual function */ 3815 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3816 /* When acting as pf, we normally skip vfs unless explicitly 3817 * requested to probe them. 3818 */ 3819 if (total_vfs) { 3820 unsigned vfs_offset = 0; 3821 3822 for (i = 0; i < ARRAY_SIZE(nvfs) && 3823 vfs_offset + nvfs[i] < extended_func_num(pdev); 3824 vfs_offset += nvfs[i], i++) 3825 ; 3826 if (i == ARRAY_SIZE(nvfs)) { 3827 err = -ENODEV; 3828 goto err_release_regions; 3829 } 3830 if ((extended_func_num(pdev) - vfs_offset) 3831 > prb_vf[i]) { 3832 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3833 extended_func_num(pdev)); 3834 err = -ENODEV; 3835 goto err_release_regions; 3836 } 3837 } 3838 } 3839 3840 err = mlx4_crdump_init(&priv->dev); 3841 if (err) 3842 goto err_release_regions; 3843 3844 err = mlx4_catas_init(&priv->dev); 3845 if (err) 3846 goto err_crdump; 3847 3848 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3849 if (err) 3850 goto err_catas; 3851 3852 return 0; 3853 3854 err_catas: 3855 mlx4_catas_end(&priv->dev); 3856 3857 err_crdump: 3858 mlx4_crdump_end(&priv->dev); 3859 3860 err_release_regions: 3861 pci_release_regions(pdev); 3862 3863 err_disable_pdev: 3864 mlx4_pci_disable_device(&priv->dev); 3865 return err; 3866 } 3867 3868 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3869 enum devlink_port_type port_type) 3870 { 3871 struct mlx4_port_info *info = container_of(devlink_port, 3872 struct mlx4_port_info, 3873 devlink_port); 3874 enum mlx4_port_type mlx4_port_type; 3875 3876 switch (port_type) { 3877 case DEVLINK_PORT_TYPE_AUTO: 3878 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3879 break; 3880 case DEVLINK_PORT_TYPE_ETH: 3881 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3882 break; 3883 case DEVLINK_PORT_TYPE_IB: 3884 mlx4_port_type = MLX4_PORT_TYPE_IB; 3885 break; 3886 default: 3887 return -EOPNOTSUPP; 3888 } 3889 3890 return __set_port_type(info, mlx4_port_type); 3891 } 3892 3893 static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3894 { 3895 struct mlx4_priv *priv = devlink_priv(devlink); 3896 struct mlx4_dev *dev = &priv->dev; 3897 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3898 union devlink_param_value saved_value; 3899 int err; 3900 3901 err = devlink_param_driverinit_value_get(devlink, 3902 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3903 &saved_value); 3904 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3905 mlx4_internal_err_reset = saved_value.vbool; 3906 /* Notify on value changed on runtime configuration mode */ 3907 devlink_param_value_changed(devlink, 3908 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3909 } 3910 err = devlink_param_driverinit_value_get(devlink, 3911 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3912 &saved_value); 3913 if (!err) 3914 log_num_mac = order_base_2(saved_value.vu32); 3915 err = devlink_param_driverinit_value_get(devlink, 3916 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3917 &saved_value); 3918 if (!err) 3919 enable_64b_cqe_eqe = saved_value.vbool; 3920 err = devlink_param_driverinit_value_get(devlink, 3921 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3922 &saved_value); 3923 if (!err) 3924 enable_4k_uar = saved_value.vbool; 3925 err = devlink_param_driverinit_value_get(devlink, 3926 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3927 &saved_value); 3928 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3929 crdump->snapshot_enable = saved_value.vbool; 3930 devlink_param_value_changed(devlink, 3931 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3932 } 3933 } 3934 3935 static int mlx4_devlink_reload(struct devlink *devlink, 3936 struct netlink_ext_ack *extack) 3937 { 3938 struct mlx4_priv *priv = devlink_priv(devlink); 3939 struct mlx4_dev *dev = &priv->dev; 3940 struct mlx4_dev_persistent *persist = dev->persist; 3941 int err; 3942 3943 if (persist->num_vfs) 3944 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 3945 err = mlx4_restart_one(persist->pdev, true, devlink); 3946 if (err) 3947 mlx4_err(persist->dev, "mlx4_restart_one failed, ret=%d\n", err); 3948 3949 return err; 3950 } 3951 3952 static const struct devlink_ops mlx4_devlink_ops = { 3953 .port_type_set = mlx4_devlink_port_type_set, 3954 .reload = mlx4_devlink_reload, 3955 }; 3956 3957 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3958 { 3959 struct devlink *devlink; 3960 struct mlx4_priv *priv; 3961 struct mlx4_dev *dev; 3962 int ret; 3963 3964 printk_once(KERN_INFO "%s", mlx4_version); 3965 3966 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3967 if (!devlink) 3968 return -ENOMEM; 3969 priv = devlink_priv(devlink); 3970 3971 dev = &priv->dev; 3972 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3973 if (!dev->persist) { 3974 ret = -ENOMEM; 3975 goto err_devlink_free; 3976 } 3977 dev->persist->pdev = pdev; 3978 dev->persist->dev = dev; 3979 pci_set_drvdata(pdev, dev->persist); 3980 priv->pci_dev_data = id->driver_data; 3981 mutex_init(&dev->persist->device_state_mutex); 3982 mutex_init(&dev->persist->interface_state_mutex); 3983 mutex_init(&dev->persist->pci_status_mutex); 3984 3985 ret = devlink_register(devlink, &pdev->dev); 3986 if (ret) 3987 goto err_persist_free; 3988 ret = devlink_params_register(devlink, mlx4_devlink_params, 3989 ARRAY_SIZE(mlx4_devlink_params)); 3990 if (ret) 3991 goto err_devlink_unregister; 3992 mlx4_devlink_set_params_init_values(devlink); 3993 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3994 if (ret) 3995 goto err_params_unregister; 3996 3997 pci_save_state(pdev); 3998 return 0; 3999 4000 err_params_unregister: 4001 devlink_params_unregister(devlink, mlx4_devlink_params, 4002 ARRAY_SIZE(mlx4_devlink_params)); 4003 err_devlink_unregister: 4004 devlink_unregister(devlink); 4005 err_persist_free: 4006 kfree(dev->persist); 4007 err_devlink_free: 4008 devlink_free(devlink); 4009 return ret; 4010 } 4011 4012 static void mlx4_clean_dev(struct mlx4_dev *dev) 4013 { 4014 struct mlx4_dev_persistent *persist = dev->persist; 4015 struct mlx4_priv *priv = mlx4_priv(dev); 4016 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4017 4018 memset(priv, 0, sizeof(*priv)); 4019 priv->dev.persist = persist; 4020 priv->dev.flags = flags; 4021 } 4022 4023 static void mlx4_unload_one(struct pci_dev *pdev) 4024 { 4025 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4026 struct mlx4_dev *dev = persist->dev; 4027 struct mlx4_priv *priv = mlx4_priv(dev); 4028 int pci_dev_data; 4029 int p, i; 4030 4031 if (priv->removed) 4032 return; 4033 4034 /* saving current ports type for further use */ 4035 for (i = 0; i < dev->caps.num_ports; i++) { 4036 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4037 dev->persist->curr_port_poss_type[i] = dev->caps. 4038 possible_type[i + 1]; 4039 } 4040 4041 pci_dev_data = priv->pci_dev_data; 4042 4043 mlx4_stop_sense(dev); 4044 mlx4_unregister_device(dev); 4045 4046 for (p = 1; p <= dev->caps.num_ports; p++) { 4047 mlx4_cleanup_port_info(&priv->port[p]); 4048 mlx4_CLOSE_PORT(dev, p); 4049 } 4050 4051 if (mlx4_is_master(dev)) 4052 mlx4_free_resource_tracker(dev, 4053 RES_TR_FREE_SLAVES_ONLY); 4054 4055 mlx4_cleanup_default_counters(dev); 4056 if (!mlx4_is_slave(dev)) 4057 mlx4_cleanup_counters_table(dev); 4058 mlx4_cleanup_qp_table(dev); 4059 mlx4_cleanup_srq_table(dev); 4060 mlx4_cleanup_cq_table(dev); 4061 mlx4_cmd_use_polling(dev); 4062 mlx4_cleanup_eq_table(dev); 4063 mlx4_cleanup_mcg_table(dev); 4064 mlx4_cleanup_mr_table(dev); 4065 mlx4_cleanup_xrcd_table(dev); 4066 mlx4_cleanup_pd_table(dev); 4067 4068 if (mlx4_is_master(dev)) 4069 mlx4_free_resource_tracker(dev, 4070 RES_TR_FREE_STRUCTS_ONLY); 4071 4072 iounmap(priv->kar); 4073 mlx4_uar_free(dev, &priv->driver_uar); 4074 mlx4_cleanup_uar_table(dev); 4075 if (!mlx4_is_slave(dev)) 4076 mlx4_clear_steering(dev); 4077 mlx4_free_eq_table(dev); 4078 if (mlx4_is_master(dev)) 4079 mlx4_multi_func_cleanup(dev); 4080 mlx4_close_hca(dev); 4081 mlx4_close_fw(dev); 4082 if (mlx4_is_slave(dev)) 4083 mlx4_multi_func_cleanup(dev); 4084 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4085 4086 if (dev->flags & MLX4_FLAG_MSI_X) 4087 pci_disable_msix(pdev); 4088 4089 if (!mlx4_is_slave(dev)) 4090 mlx4_free_ownership(dev); 4091 4092 mlx4_slave_destroy_special_qp_cap(dev); 4093 kfree(dev->dev_vfs); 4094 4095 mlx4_clean_dev(dev); 4096 priv->pci_dev_data = pci_dev_data; 4097 priv->removed = 1; 4098 } 4099 4100 static void mlx4_remove_one(struct pci_dev *pdev) 4101 { 4102 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4103 struct mlx4_dev *dev = persist->dev; 4104 struct mlx4_priv *priv = mlx4_priv(dev); 4105 struct devlink *devlink = priv_to_devlink(priv); 4106 int active_vfs = 0; 4107 4108 if (mlx4_is_slave(dev)) 4109 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4110 4111 mutex_lock(&persist->interface_state_mutex); 4112 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4113 mutex_unlock(&persist->interface_state_mutex); 4114 4115 /* Disabling SR-IOV is not allowed while there are active vf's */ 4116 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4117 active_vfs = mlx4_how_many_lives_vf(dev); 4118 if (active_vfs) { 4119 pr_warn("Removing PF when there are active VF's !!\n"); 4120 pr_warn("Will not disable SR-IOV.\n"); 4121 } 4122 } 4123 4124 /* device marked to be under deletion running now without the lock 4125 * letting other tasks to be terminated 4126 */ 4127 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4128 mlx4_unload_one(pdev); 4129 else 4130 mlx4_info(dev, "%s: interface is down\n", __func__); 4131 mlx4_catas_end(dev); 4132 mlx4_crdump_end(dev); 4133 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4134 mlx4_warn(dev, "Disabling SR-IOV\n"); 4135 pci_disable_sriov(pdev); 4136 } 4137 4138 pci_release_regions(pdev); 4139 mlx4_pci_disable_device(dev); 4140 devlink_params_unregister(devlink, mlx4_devlink_params, 4141 ARRAY_SIZE(mlx4_devlink_params)); 4142 devlink_unregister(devlink); 4143 kfree(dev->persist); 4144 devlink_free(devlink); 4145 } 4146 4147 static int restore_current_port_types(struct mlx4_dev *dev, 4148 enum mlx4_port_type *types, 4149 enum mlx4_port_type *poss_types) 4150 { 4151 struct mlx4_priv *priv = mlx4_priv(dev); 4152 int err, i; 4153 4154 mlx4_stop_sense(dev); 4155 4156 mutex_lock(&priv->port_mutex); 4157 for (i = 0; i < dev->caps.num_ports; i++) 4158 dev->caps.possible_type[i + 1] = poss_types[i]; 4159 err = mlx4_change_port_types(dev, types); 4160 mlx4_start_sense(dev); 4161 mutex_unlock(&priv->port_mutex); 4162 4163 return err; 4164 } 4165 4166 int mlx4_restart_one(struct pci_dev *pdev, bool reload, struct devlink *devlink) 4167 { 4168 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4169 struct mlx4_dev *dev = persist->dev; 4170 struct mlx4_priv *priv = mlx4_priv(dev); 4171 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4172 int pci_dev_data, err, total_vfs; 4173 4174 pci_dev_data = priv->pci_dev_data; 4175 total_vfs = dev->persist->num_vfs; 4176 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4177 4178 mlx4_unload_one(pdev); 4179 if (reload) 4180 mlx4_devlink_param_load_driverinit_values(devlink); 4181 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4182 if (err) { 4183 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4184 __func__, pci_name(pdev), err); 4185 return err; 4186 } 4187 4188 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4189 dev->persist->curr_port_poss_type); 4190 if (err) 4191 mlx4_err(dev, "could not restore original port types (%d)\n", 4192 err); 4193 4194 return err; 4195 } 4196 4197 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4198 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4199 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4200 4201 static const struct pci_device_id mlx4_pci_table[] = { 4202 #ifdef CONFIG_MLX4_CORE_GEN2 4203 /* MT25408 "Hermon" */ 4204 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4205 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4206 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4207 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4208 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4209 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4210 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4211 /* MT25458 ConnectX EN 10GBASE-T */ 4212 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4213 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4214 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4215 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4216 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4217 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4218 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4219 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4220 /* MT25400 Family [ConnectX-2] */ 4221 MLX_VF(0x1002), /* Virtual Function */ 4222 #endif /* CONFIG_MLX4_CORE_GEN2 */ 4223 /* MT27500 Family [ConnectX-3] */ 4224 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4225 MLX_VF(0x1004), /* Virtual Function */ 4226 MLX_GN(0x1005), /* MT27510 Family */ 4227 MLX_GN(0x1006), /* MT27511 Family */ 4228 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4229 MLX_GN(0x1008), /* MT27521 Family */ 4230 MLX_GN(0x1009), /* MT27530 Family */ 4231 MLX_GN(0x100a), /* MT27531 Family */ 4232 MLX_GN(0x100b), /* MT27540 Family */ 4233 MLX_GN(0x100c), /* MT27541 Family */ 4234 MLX_GN(0x100d), /* MT27550 Family */ 4235 MLX_GN(0x100e), /* MT27551 Family */ 4236 MLX_GN(0x100f), /* MT27560 Family */ 4237 MLX_GN(0x1010), /* MT27561 Family */ 4238 4239 /* 4240 * See the mellanox_check_broken_intx_masking() quirk when 4241 * adding devices 4242 */ 4243 4244 { 0, } 4245 }; 4246 4247 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4248 4249 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4250 pci_channel_state_t state) 4251 { 4252 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4253 4254 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4255 mlx4_enter_error_state(persist); 4256 4257 mutex_lock(&persist->interface_state_mutex); 4258 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4259 mlx4_unload_one(pdev); 4260 4261 mutex_unlock(&persist->interface_state_mutex); 4262 if (state == pci_channel_io_perm_failure) 4263 return PCI_ERS_RESULT_DISCONNECT; 4264 4265 mlx4_pci_disable_device(persist->dev); 4266 return PCI_ERS_RESULT_NEED_RESET; 4267 } 4268 4269 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4270 { 4271 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4272 struct mlx4_dev *dev = persist->dev; 4273 int err; 4274 4275 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4276 err = mlx4_pci_enable_device(dev); 4277 if (err) { 4278 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4279 return PCI_ERS_RESULT_DISCONNECT; 4280 } 4281 4282 pci_set_master(pdev); 4283 pci_restore_state(pdev); 4284 pci_save_state(pdev); 4285 return PCI_ERS_RESULT_RECOVERED; 4286 } 4287 4288 static void mlx4_pci_resume(struct pci_dev *pdev) 4289 { 4290 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4291 struct mlx4_dev *dev = persist->dev; 4292 struct mlx4_priv *priv = mlx4_priv(dev); 4293 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4294 int total_vfs; 4295 int err; 4296 4297 mlx4_err(dev, "%s was called\n", __func__); 4298 total_vfs = dev->persist->num_vfs; 4299 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4300 4301 mutex_lock(&persist->interface_state_mutex); 4302 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4303 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4304 priv, 1); 4305 if (err) { 4306 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4307 __func__, err); 4308 goto end; 4309 } 4310 4311 err = restore_current_port_types(dev, dev->persist-> 4312 curr_port_type, dev->persist-> 4313 curr_port_poss_type); 4314 if (err) 4315 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4316 } 4317 end: 4318 mutex_unlock(&persist->interface_state_mutex); 4319 4320 } 4321 4322 static void mlx4_shutdown(struct pci_dev *pdev) 4323 { 4324 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4325 4326 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4327 mutex_lock(&persist->interface_state_mutex); 4328 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4329 mlx4_unload_one(pdev); 4330 mutex_unlock(&persist->interface_state_mutex); 4331 } 4332 4333 static const struct pci_error_handlers mlx4_err_handler = { 4334 .error_detected = mlx4_pci_err_detected, 4335 .slot_reset = mlx4_pci_slot_reset, 4336 .resume = mlx4_pci_resume, 4337 }; 4338 4339 static int mlx4_suspend(struct pci_dev *pdev, pm_message_t state) 4340 { 4341 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4342 struct mlx4_dev *dev = persist->dev; 4343 4344 mlx4_err(dev, "suspend was called\n"); 4345 mutex_lock(&persist->interface_state_mutex); 4346 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4347 mlx4_unload_one(pdev); 4348 mutex_unlock(&persist->interface_state_mutex); 4349 4350 return 0; 4351 } 4352 4353 static int mlx4_resume(struct pci_dev *pdev) 4354 { 4355 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4356 struct mlx4_dev *dev = persist->dev; 4357 struct mlx4_priv *priv = mlx4_priv(dev); 4358 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4359 int total_vfs; 4360 int ret = 0; 4361 4362 mlx4_err(dev, "resume was called\n"); 4363 total_vfs = dev->persist->num_vfs; 4364 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4365 4366 mutex_lock(&persist->interface_state_mutex); 4367 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4368 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4369 nvfs, priv, 1); 4370 if (!ret) { 4371 ret = restore_current_port_types(dev, 4372 dev->persist->curr_port_type, 4373 dev->persist->curr_port_poss_type); 4374 if (ret) 4375 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4376 } 4377 } 4378 mutex_unlock(&persist->interface_state_mutex); 4379 4380 return ret; 4381 } 4382 4383 static struct pci_driver mlx4_driver = { 4384 .name = DRV_NAME, 4385 .id_table = mlx4_pci_table, 4386 .probe = mlx4_init_one, 4387 .shutdown = mlx4_shutdown, 4388 .remove = mlx4_remove_one, 4389 .suspend = mlx4_suspend, 4390 .resume = mlx4_resume, 4391 .err_handler = &mlx4_err_handler, 4392 }; 4393 4394 static int __init mlx4_verify_params(void) 4395 { 4396 if (msi_x < 0) { 4397 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4398 return -1; 4399 } 4400 4401 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4402 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4403 return -1; 4404 } 4405 4406 if (log_num_vlan != 0) 4407 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4408 MLX4_LOG_NUM_VLANS); 4409 4410 if (use_prio != 0) 4411 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4412 4413 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 4414 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4415 log_mtts_per_seg); 4416 return -1; 4417 } 4418 4419 /* Check if module param for ports type has legal combination */ 4420 if (port_type_array[0] == false && port_type_array[1] == true) { 4421 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4422 port_type_array[0] = true; 4423 } 4424 4425 if (mlx4_log_num_mgm_entry_size < -7 || 4426 (mlx4_log_num_mgm_entry_size > 0 && 4427 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4428 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4429 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4430 mlx4_log_num_mgm_entry_size, 4431 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4432 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4433 return -1; 4434 } 4435 4436 return 0; 4437 } 4438 4439 static int __init mlx4_init(void) 4440 { 4441 int ret; 4442 4443 if (mlx4_verify_params()) 4444 return -EINVAL; 4445 4446 4447 mlx4_wq = create_singlethread_workqueue("mlx4"); 4448 if (!mlx4_wq) 4449 return -ENOMEM; 4450 4451 ret = pci_register_driver(&mlx4_driver); 4452 if (ret < 0) 4453 destroy_workqueue(mlx4_wq); 4454 return ret < 0 ? ret : 0; 4455 } 4456 4457 static void __exit mlx4_cleanup(void) 4458 { 4459 pci_unregister_driver(&mlx4_driver); 4460 destroy_workqueue(mlx4_wq); 4461 } 4462 4463 module_init(mlx4_init); 4464 module_exit(mlx4_cleanup); 4465