1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 #include <linux/etherdevice.h> 46 #include <net/devlink.h> 47 48 #include <linux/mlx4/device.h> 49 #include <linux/mlx4/doorbell.h> 50 51 #include "mlx4.h" 52 #include "fw.h" 53 #include "icm.h" 54 55 MODULE_AUTHOR("Roland Dreier"); 56 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 57 MODULE_LICENSE("Dual BSD/GPL"); 58 MODULE_VERSION(DRV_VERSION); 59 60 struct workqueue_struct *mlx4_wq; 61 62 #ifdef CONFIG_MLX4_DEBUG 63 64 int mlx4_debug_level = 0; 65 module_param_named(debug_level, mlx4_debug_level, int, 0644); 66 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 67 68 #endif /* CONFIG_MLX4_DEBUG */ 69 70 #ifdef CONFIG_PCI_MSI 71 72 static int msi_x = 1; 73 module_param(msi_x, int, 0444); 74 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 75 76 #else /* CONFIG_PCI_MSI */ 77 78 #define msi_x (0) 79 80 #endif /* CONFIG_PCI_MSI */ 81 82 static uint8_t num_vfs[3] = {0, 0, 0}; 83 static int num_vfs_argc; 84 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 85 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 86 "num_vfs=port1,port2,port1+2"); 87 88 static uint8_t probe_vf[3] = {0, 0, 0}; 89 static int probe_vfs_argc; 90 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 91 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 92 "probe_vf=port1,port2,port1+2"); 93 94 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 95 module_param_named(log_num_mgm_entry_size, 96 mlx4_log_num_mgm_entry_size, int, 0444); 97 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 98 " of qp per mcg, for example:" 99 " 10 gives 248.range: 7 <=" 100 " log_num_mgm_entry_size <= 12." 101 " To activate device managed" 102 " flow steering when available, set to -1"); 103 104 static bool enable_64b_cqe_eqe = true; 105 module_param(enable_64b_cqe_eqe, bool, 0444); 106 MODULE_PARM_DESC(enable_64b_cqe_eqe, 107 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 108 109 static bool enable_4k_uar; 110 module_param(enable_4k_uar, bool, 0444); 111 MODULE_PARM_DESC(enable_4k_uar, 112 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 113 114 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 115 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 116 MLX4_FUNC_CAP_DMFS_A0_STATIC) 117 118 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 119 120 static char mlx4_version[] = 121 DRV_NAME ": Mellanox ConnectX core driver v" 122 DRV_VERSION " (" DRV_RELDATE ")\n"; 123 124 static struct mlx4_profile default_profile = { 125 .num_qp = 1 << 18, 126 .num_srq = 1 << 16, 127 .rdmarc_per_qp = 1 << 4, 128 .num_cq = 1 << 16, 129 .num_mcg = 1 << 13, 130 .num_mpt = 1 << 19, 131 .num_mtt = 1 << 20, /* It is really num mtt segements */ 132 }; 133 134 static struct mlx4_profile low_mem_profile = { 135 .num_qp = 1 << 17, 136 .num_srq = 1 << 6, 137 .rdmarc_per_qp = 1 << 4, 138 .num_cq = 1 << 8, 139 .num_mcg = 1 << 8, 140 .num_mpt = 1 << 9, 141 .num_mtt = 1 << 7, 142 }; 143 144 static int log_num_mac = 7; 145 module_param_named(log_num_mac, log_num_mac, int, 0444); 146 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 147 148 static int log_num_vlan; 149 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 150 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 151 /* Log2 max number of VLANs per ETH port (0-7) */ 152 #define MLX4_LOG_NUM_VLANS 7 153 #define MLX4_MIN_LOG_NUM_VLANS 0 154 #define MLX4_MIN_LOG_NUM_MAC 1 155 156 static bool use_prio; 157 module_param_named(use_prio, use_prio, bool, 0444); 158 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 159 160 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 161 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 162 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 163 164 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 165 static int arr_argc = 2; 166 module_param_array(port_type_array, int, &arr_argc, 0444); 167 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 168 "1 for IB, 2 for Ethernet"); 169 170 struct mlx4_port_config { 171 struct list_head list; 172 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 173 struct pci_dev *pdev; 174 }; 175 176 static atomic_t pf_loading = ATOMIC_INIT(0); 177 178 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 179 struct mlx4_dev_cap *dev_cap) 180 { 181 /* The reserved_uars is calculated by system page size unit. 182 * Therefore, adjustment is added when the uar page size is less 183 * than the system page size 184 */ 185 dev->caps.reserved_uars = 186 max_t(int, 187 mlx4_get_num_reserved_uar(dev), 188 dev_cap->reserved_uars / 189 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 190 } 191 192 int mlx4_check_port_params(struct mlx4_dev *dev, 193 enum mlx4_port_type *port_type) 194 { 195 int i; 196 197 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 198 for (i = 0; i < dev->caps.num_ports - 1; i++) { 199 if (port_type[i] != port_type[i + 1]) { 200 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 201 return -EINVAL; 202 } 203 } 204 } 205 206 for (i = 0; i < dev->caps.num_ports; i++) { 207 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 208 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 209 i + 1); 210 return -EINVAL; 211 } 212 } 213 return 0; 214 } 215 216 static void mlx4_set_port_mask(struct mlx4_dev *dev) 217 { 218 int i; 219 220 for (i = 1; i <= dev->caps.num_ports; ++i) 221 dev->caps.port_mask[i] = dev->caps.port_type[i]; 222 } 223 224 enum { 225 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 226 }; 227 228 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 229 { 230 int err = 0; 231 struct mlx4_func func; 232 233 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 234 err = mlx4_QUERY_FUNC(dev, &func, 0); 235 if (err) { 236 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 237 return err; 238 } 239 dev_cap->max_eqs = func.max_eq; 240 dev_cap->reserved_eqs = func.rsvd_eqs; 241 dev_cap->reserved_uars = func.rsvd_uars; 242 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 243 } 244 return err; 245 } 246 247 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 248 { 249 struct mlx4_caps *dev_cap = &dev->caps; 250 251 /* FW not supporting or cancelled by user */ 252 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 253 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 254 return; 255 256 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 257 * When FW has NCSI it may decide not to report 64B CQE/EQEs 258 */ 259 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 260 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 261 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 262 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 263 return; 264 } 265 266 if (cache_line_size() == 128 || cache_line_size() == 256) { 267 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 268 /* Changing the real data inside CQE size to 32B */ 269 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 270 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 271 272 if (mlx4_is_master(dev)) 273 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 274 } else { 275 if (cache_line_size() != 32 && cache_line_size() != 64) 276 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 277 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 278 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 279 } 280 } 281 282 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 283 struct mlx4_port_cap *port_cap) 284 { 285 dev->caps.vl_cap[port] = port_cap->max_vl; 286 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 287 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 288 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 289 /* set gid and pkey table operating lengths by default 290 * to non-sriov values 291 */ 292 dev->caps.gid_table_len[port] = port_cap->max_gids; 293 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 294 dev->caps.port_width_cap[port] = port_cap->max_port_width; 295 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 296 dev->caps.max_tc_eth = port_cap->max_tc_eth; 297 dev->caps.def_mac[port] = port_cap->def_mac; 298 dev->caps.supported_type[port] = port_cap->supported_port_types; 299 dev->caps.suggested_type[port] = port_cap->suggested_type; 300 dev->caps.default_sense[port] = port_cap->default_sense; 301 dev->caps.trans_type[port] = port_cap->trans_type; 302 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 303 dev->caps.wavelength[port] = port_cap->wavelength; 304 dev->caps.trans_code[port] = port_cap->trans_code; 305 306 return 0; 307 } 308 309 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 310 struct mlx4_port_cap *port_cap) 311 { 312 int err = 0; 313 314 err = mlx4_QUERY_PORT(dev, port, port_cap); 315 316 if (err) 317 mlx4_err(dev, "QUERY_PORT command failed.\n"); 318 319 return err; 320 } 321 322 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 323 { 324 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 325 return; 326 327 if (mlx4_is_mfunc(dev)) { 328 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 329 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 330 return; 331 } 332 333 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 334 mlx4_dbg(dev, 335 "Keep FCS is not supported - Disabling Ignore FCS"); 336 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 337 return; 338 } 339 } 340 341 #define MLX4_A0_STEERING_TABLE_SIZE 256 342 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 343 { 344 int err; 345 int i; 346 347 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 348 if (err) { 349 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 350 return err; 351 } 352 mlx4_dev_cap_dump(dev, dev_cap); 353 354 if (dev_cap->min_page_sz > PAGE_SIZE) { 355 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 356 dev_cap->min_page_sz, PAGE_SIZE); 357 return -ENODEV; 358 } 359 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 360 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 361 dev_cap->num_ports, MLX4_MAX_PORTS); 362 return -ENODEV; 363 } 364 365 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 366 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 367 dev_cap->uar_size, 368 (unsigned long long) 369 pci_resource_len(dev->persist->pdev, 2)); 370 return -ENODEV; 371 } 372 373 dev->caps.num_ports = dev_cap->num_ports; 374 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 375 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 376 dev->caps.num_sys_eqs : 377 MLX4_MAX_EQ_NUM; 378 for (i = 1; i <= dev->caps.num_ports; ++i) { 379 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 380 if (err) { 381 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 382 return err; 383 } 384 } 385 386 dev->caps.uar_page_size = PAGE_SIZE; 387 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 388 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 389 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 390 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 391 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 392 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 393 dev->caps.max_wqes = dev_cap->max_qp_sz; 394 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 395 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 396 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 397 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 398 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 399 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 400 /* 401 * Subtract 1 from the limit because we need to allocate a 402 * spare CQE so the HCA HW can tell the difference between an 403 * empty CQ and a full CQ. 404 */ 405 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 406 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 407 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 408 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 409 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 410 411 dev->caps.reserved_pds = dev_cap->reserved_pds; 412 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 413 dev_cap->reserved_xrcds : 0; 414 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 415 dev_cap->max_xrcds : 0; 416 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 417 418 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 419 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 420 dev->caps.flags = dev_cap->flags; 421 dev->caps.flags2 = dev_cap->flags2; 422 dev->caps.bmme_flags = dev_cap->bmme_flags; 423 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 424 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 425 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 426 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 427 428 /* Save uar page shift */ 429 if (!mlx4_is_slave(dev)) { 430 /* Virtual PCI function needs to determine UAR page size from 431 * firmware. Only master PCI function can set the uar page size 432 */ 433 if (enable_4k_uar) 434 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 435 else 436 dev->uar_page_shift = PAGE_SHIFT; 437 438 mlx4_set_num_reserved_uars(dev, dev_cap); 439 } 440 441 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 442 struct mlx4_init_hca_param hca_param; 443 444 memset(&hca_param, 0, sizeof(hca_param)); 445 err = mlx4_QUERY_HCA(dev, &hca_param); 446 /* Turn off PHV_EN flag in case phv_check_en is set. 447 * phv_check_en is a HW check that parse the packet and verify 448 * phv bit was reported correctly in the wqe. To allow QinQ 449 * PHV_EN flag should be set and phv_check_en must be cleared 450 * otherwise QinQ packets will be drop by the HW. 451 */ 452 if (err || hca_param.phv_check_en) 453 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 454 } 455 456 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 457 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 458 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 459 /* Don't do sense port on multifunction devices (for now at least) */ 460 if (mlx4_is_mfunc(dev)) 461 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 462 463 if (mlx4_low_memory_profile()) { 464 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 465 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 466 } else { 467 dev->caps.log_num_macs = log_num_mac; 468 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 469 } 470 471 for (i = 1; i <= dev->caps.num_ports; ++i) { 472 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 473 if (dev->caps.supported_type[i]) { 474 /* if only ETH is supported - assign ETH */ 475 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 476 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 477 /* if only IB is supported, assign IB */ 478 else if (dev->caps.supported_type[i] == 479 MLX4_PORT_TYPE_IB) 480 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 481 else { 482 /* if IB and ETH are supported, we set the port 483 * type according to user selection of port type; 484 * if user selected none, take the FW hint */ 485 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 486 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 487 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 488 else 489 dev->caps.port_type[i] = port_type_array[i - 1]; 490 } 491 } 492 /* 493 * Link sensing is allowed on the port if 3 conditions are true: 494 * 1. Both protocols are supported on the port. 495 * 2. Different types are supported on the port 496 * 3. FW declared that it supports link sensing 497 */ 498 mlx4_priv(dev)->sense.sense_allowed[i] = 499 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 500 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 501 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 502 503 /* 504 * If "default_sense" bit is set, we move the port to "AUTO" mode 505 * and perform sense_port FW command to try and set the correct 506 * port type from beginning 507 */ 508 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 509 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 510 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 511 mlx4_SENSE_PORT(dev, i, &sensed_port); 512 if (sensed_port != MLX4_PORT_TYPE_NONE) 513 dev->caps.port_type[i] = sensed_port; 514 } else { 515 dev->caps.possible_type[i] = dev->caps.port_type[i]; 516 } 517 518 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 519 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 520 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 521 i, 1 << dev->caps.log_num_macs); 522 } 523 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 524 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 525 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 526 i, 1 << dev->caps.log_num_vlans); 527 } 528 } 529 530 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 531 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 532 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 533 mlx4_warn(dev, 534 "Granular QoS per VF not supported with IB/Eth configuration\n"); 535 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 536 } 537 538 dev->caps.max_counters = dev_cap->max_counters; 539 540 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 541 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 542 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 543 (1 << dev->caps.log_num_macs) * 544 (1 << dev->caps.log_num_vlans) * 545 dev->caps.num_ports; 546 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 547 548 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 549 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 550 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 551 else 552 dev->caps.dmfs_high_rate_qpn_base = 553 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 554 555 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 556 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 557 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 558 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 559 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 560 } else { 561 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 562 dev->caps.dmfs_high_rate_qpn_base = 563 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 564 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 565 } 566 567 dev->caps.rl_caps = dev_cap->rl_caps; 568 569 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 570 dev->caps.dmfs_high_rate_qpn_range; 571 572 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 573 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 574 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 575 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 576 577 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 578 579 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 580 if (dev_cap->flags & 581 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 582 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 583 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 584 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 585 } 586 587 if (dev_cap->flags2 & 588 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 589 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 590 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 591 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 592 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 593 } 594 } 595 596 if ((dev->caps.flags & 597 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 598 mlx4_is_master(dev)) 599 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 600 601 if (!mlx4_is_slave(dev)) { 602 mlx4_enable_cqe_eqe_stride(dev); 603 dev->caps.alloc_res_qp_mask = 604 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 605 MLX4_RESERVE_A0_QP; 606 607 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 608 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 609 mlx4_warn(dev, "Old device ETS support detected\n"); 610 mlx4_warn(dev, "Consider upgrading device FW.\n"); 611 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 612 } 613 614 } else { 615 dev->caps.alloc_res_qp_mask = 0; 616 } 617 618 mlx4_enable_ignore_fcs(dev); 619 620 return 0; 621 } 622 623 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 624 enum pci_bus_speed *speed, 625 enum pcie_link_width *width) 626 { 627 u32 lnkcap1, lnkcap2; 628 int err1, err2; 629 630 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 631 632 *speed = PCI_SPEED_UNKNOWN; 633 *width = PCIE_LNK_WIDTH_UNKNOWN; 634 635 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP, 636 &lnkcap1); 637 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2, 638 &lnkcap2); 639 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 640 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 641 *speed = PCIE_SPEED_8_0GT; 642 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 643 *speed = PCIE_SPEED_5_0GT; 644 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 645 *speed = PCIE_SPEED_2_5GT; 646 } 647 if (!err1) { 648 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 649 if (!lnkcap2) { /* pre-r3.0 */ 650 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 651 *speed = PCIE_SPEED_5_0GT; 652 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 653 *speed = PCIE_SPEED_2_5GT; 654 } 655 } 656 657 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 658 return err1 ? err1 : 659 err2 ? err2 : -EINVAL; 660 } 661 return 0; 662 } 663 664 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 665 { 666 enum pcie_link_width width, width_cap; 667 enum pci_bus_speed speed, speed_cap; 668 int err; 669 670 #define PCIE_SPEED_STR(speed) \ 671 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 672 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 673 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 674 "Unknown") 675 676 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 677 if (err) { 678 mlx4_warn(dev, 679 "Unable to determine PCIe device BW capabilities\n"); 680 return; 681 } 682 683 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width); 684 if (err || speed == PCI_SPEED_UNKNOWN || 685 width == PCIE_LNK_WIDTH_UNKNOWN) { 686 mlx4_warn(dev, 687 "Unable to determine PCI device chain minimum BW\n"); 688 return; 689 } 690 691 if (width != width_cap || speed != speed_cap) 692 mlx4_warn(dev, 693 "PCIe BW is different than device's capability\n"); 694 695 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 696 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 697 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 698 width, width_cap); 699 return; 700 } 701 702 /*The function checks if there are live vf, return the num of them*/ 703 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 704 { 705 struct mlx4_priv *priv = mlx4_priv(dev); 706 struct mlx4_slave_state *s_state; 707 int i; 708 int ret = 0; 709 710 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 711 s_state = &priv->mfunc.master.slave_state[i]; 712 if (s_state->active && s_state->last_cmd != 713 MLX4_COMM_CMD_RESET) { 714 mlx4_warn(dev, "%s: slave: %d is still active\n", 715 __func__, i); 716 ret++; 717 } 718 } 719 return ret; 720 } 721 722 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 723 { 724 u32 qk = MLX4_RESERVED_QKEY_BASE; 725 726 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 727 qpn < dev->phys_caps.base_proxy_sqpn) 728 return -EINVAL; 729 730 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 731 /* tunnel qp */ 732 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 733 else 734 qk += qpn - dev->phys_caps.base_proxy_sqpn; 735 *qkey = qk; 736 return 0; 737 } 738 EXPORT_SYMBOL(mlx4_get_parav_qkey); 739 740 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 741 { 742 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 743 744 if (!mlx4_is_master(dev)) 745 return; 746 747 priv->virt2phys_pkey[slave][port - 1][i] = val; 748 } 749 EXPORT_SYMBOL(mlx4_sync_pkey_table); 750 751 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 752 { 753 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 754 755 if (!mlx4_is_master(dev)) 756 return; 757 758 priv->slave_node_guids[slave] = guid; 759 } 760 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 761 762 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 763 { 764 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 765 766 if (!mlx4_is_master(dev)) 767 return 0; 768 769 return priv->slave_node_guids[slave]; 770 } 771 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 772 773 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 774 { 775 struct mlx4_priv *priv = mlx4_priv(dev); 776 struct mlx4_slave_state *s_slave; 777 778 if (!mlx4_is_master(dev)) 779 return 0; 780 781 s_slave = &priv->mfunc.master.slave_state[slave]; 782 return !!s_slave->active; 783 } 784 EXPORT_SYMBOL(mlx4_is_slave_active); 785 786 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 787 struct _rule_hw *eth_header) 788 { 789 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 790 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 791 struct mlx4_net_trans_rule_hw_eth *eth = 792 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 793 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 794 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 795 next_rule->rsvd == 0; 796 797 if (last_rule) 798 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 799 } 800 } 801 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 802 803 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 804 struct mlx4_dev_cap *dev_cap, 805 struct mlx4_init_hca_param *hca_param) 806 { 807 dev->caps.steering_mode = hca_param->steering_mode; 808 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 809 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 810 dev->caps.fs_log_max_ucast_qp_range_size = 811 dev_cap->fs_log_max_ucast_qp_range_size; 812 } else 813 dev->caps.num_qp_per_mgm = 814 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 815 816 mlx4_dbg(dev, "Steering mode is: %s\n", 817 mlx4_steering_mode_str(dev->caps.steering_mode)); 818 } 819 820 static int mlx4_slave_cap(struct mlx4_dev *dev) 821 { 822 int err; 823 u32 page_size; 824 struct mlx4_dev_cap dev_cap; 825 struct mlx4_func_cap func_cap; 826 struct mlx4_init_hca_param hca_param; 827 u8 i; 828 829 memset(&hca_param, 0, sizeof(hca_param)); 830 err = mlx4_QUERY_HCA(dev, &hca_param); 831 if (err) { 832 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 833 return err; 834 } 835 836 /* fail if the hca has an unknown global capability 837 * at this time global_caps should be always zeroed 838 */ 839 if (hca_param.global_caps) { 840 mlx4_err(dev, "Unknown hca global capabilities\n"); 841 return -ENOSYS; 842 } 843 844 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 845 846 dev->caps.hca_core_clock = hca_param.hca_core_clock; 847 848 memset(&dev_cap, 0, sizeof(dev_cap)); 849 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 850 err = mlx4_dev_cap(dev, &dev_cap); 851 if (err) { 852 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 853 return err; 854 } 855 856 err = mlx4_QUERY_FW(dev); 857 if (err) 858 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 859 860 page_size = ~dev->caps.page_size_cap + 1; 861 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 862 if (page_size > PAGE_SIZE) { 863 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 864 page_size, PAGE_SIZE); 865 return -ENODEV; 866 } 867 868 /* Set uar_page_shift for VF */ 869 dev->uar_page_shift = hca_param.uar_page_sz + 12; 870 871 /* Make sure the master uar page size is valid */ 872 if (dev->uar_page_shift > PAGE_SHIFT) { 873 mlx4_err(dev, 874 "Invalid configuration: uar page size is larger than system page size\n"); 875 return -ENODEV; 876 } 877 878 /* Set reserved_uars based on the uar_page_shift */ 879 mlx4_set_num_reserved_uars(dev, &dev_cap); 880 881 /* Although uar page size in FW differs from system page size, 882 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 883 * still works with assumption that uar page size == system page size 884 */ 885 dev->caps.uar_page_size = PAGE_SIZE; 886 887 memset(&func_cap, 0, sizeof(func_cap)); 888 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 889 if (err) { 890 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 891 err); 892 return err; 893 } 894 895 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 896 PF_CONTEXT_BEHAVIOUR_MASK) { 897 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 898 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK); 899 return -ENOSYS; 900 } 901 902 dev->caps.num_ports = func_cap.num_ports; 903 dev->quotas.qp = func_cap.qp_quota; 904 dev->quotas.srq = func_cap.srq_quota; 905 dev->quotas.cq = func_cap.cq_quota; 906 dev->quotas.mpt = func_cap.mpt_quota; 907 dev->quotas.mtt = func_cap.mtt_quota; 908 dev->caps.num_qps = 1 << hca_param.log_num_qps; 909 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 910 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 911 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 912 dev->caps.num_eqs = func_cap.max_eq; 913 dev->caps.reserved_eqs = func_cap.reserved_eq; 914 dev->caps.reserved_lkey = func_cap.reserved_lkey; 915 dev->caps.num_pds = MLX4_NUM_PDS; 916 dev->caps.num_mgms = 0; 917 dev->caps.num_amgms = 0; 918 919 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 920 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 921 dev->caps.num_ports, MLX4_MAX_PORTS); 922 return -ENODEV; 923 } 924 925 mlx4_replace_zero_macs(dev); 926 927 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); 928 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 929 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 930 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 931 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 932 933 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 934 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || 935 !dev->caps.qp0_qkey) { 936 err = -ENOMEM; 937 goto err_mem; 938 } 939 940 for (i = 1; i <= dev->caps.num_ports; ++i) { 941 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap); 942 if (err) { 943 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 944 i, err); 945 goto err_mem; 946 } 947 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; 948 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 949 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 950 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 951 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 952 dev->caps.port_mask[i] = dev->caps.port_type[i]; 953 dev->caps.phys_port_id[i] = func_cap.phys_port_id; 954 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 955 &dev->caps.gid_table_len[i], 956 &dev->caps.pkey_table_len[i]); 957 if (err) 958 goto err_mem; 959 } 960 961 if (dev->caps.uar_page_size * (dev->caps.num_uars - 962 dev->caps.reserved_uars) > 963 pci_resource_len(dev->persist->pdev, 964 2)) { 965 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 966 dev->caps.uar_page_size * dev->caps.num_uars, 967 (unsigned long long) 968 pci_resource_len(dev->persist->pdev, 2)); 969 err = -ENOMEM; 970 goto err_mem; 971 } 972 973 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 974 dev->caps.eqe_size = 64; 975 dev->caps.eqe_factor = 1; 976 } else { 977 dev->caps.eqe_size = 32; 978 dev->caps.eqe_factor = 0; 979 } 980 981 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 982 dev->caps.cqe_size = 64; 983 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 984 } else { 985 dev->caps.cqe_size = 32; 986 } 987 988 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 989 dev->caps.eqe_size = hca_param.eqe_size; 990 dev->caps.eqe_factor = 0; 991 } 992 993 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 994 dev->caps.cqe_size = hca_param.cqe_size; 995 /* User still need to know when CQE > 32B */ 996 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 997 } 998 999 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1000 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1001 1002 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 1003 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1004 hca_param.rss_ip_frags ? "on" : "off"); 1005 1006 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1007 dev->caps.bf_reg_size) 1008 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1009 1010 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1011 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1012 1013 return 0; 1014 1015 err_mem: 1016 kfree(dev->caps.qp0_qkey); 1017 kfree(dev->caps.qp0_tunnel); 1018 kfree(dev->caps.qp0_proxy); 1019 kfree(dev->caps.qp1_tunnel); 1020 kfree(dev->caps.qp1_proxy); 1021 dev->caps.qp0_qkey = NULL; 1022 dev->caps.qp0_tunnel = NULL; 1023 dev->caps.qp0_proxy = NULL; 1024 dev->caps.qp1_tunnel = NULL; 1025 dev->caps.qp1_proxy = NULL; 1026 1027 return err; 1028 } 1029 1030 static void mlx4_request_modules(struct mlx4_dev *dev) 1031 { 1032 int port; 1033 int has_ib_port = false; 1034 int has_eth_port = false; 1035 #define EN_DRV_NAME "mlx4_en" 1036 #define IB_DRV_NAME "mlx4_ib" 1037 1038 for (port = 1; port <= dev->caps.num_ports; port++) { 1039 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1040 has_ib_port = true; 1041 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1042 has_eth_port = true; 1043 } 1044 1045 if (has_eth_port) 1046 request_module_nowait(EN_DRV_NAME); 1047 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1048 request_module_nowait(IB_DRV_NAME); 1049 } 1050 1051 /* 1052 * Change the port configuration of the device. 1053 * Every user of this function must hold the port mutex. 1054 */ 1055 int mlx4_change_port_types(struct mlx4_dev *dev, 1056 enum mlx4_port_type *port_types) 1057 { 1058 int err = 0; 1059 int change = 0; 1060 int port; 1061 1062 for (port = 0; port < dev->caps.num_ports; port++) { 1063 /* Change the port type only if the new type is different 1064 * from the current, and not set to Auto */ 1065 if (port_types[port] != dev->caps.port_type[port + 1]) 1066 change = 1; 1067 } 1068 if (change) { 1069 mlx4_unregister_device(dev); 1070 for (port = 1; port <= dev->caps.num_ports; port++) { 1071 mlx4_CLOSE_PORT(dev, port); 1072 dev->caps.port_type[port] = port_types[port - 1]; 1073 err = mlx4_SET_PORT(dev, port, -1); 1074 if (err) { 1075 mlx4_err(dev, "Failed to set port %d, aborting\n", 1076 port); 1077 goto out; 1078 } 1079 } 1080 mlx4_set_port_mask(dev); 1081 err = mlx4_register_device(dev); 1082 if (err) { 1083 mlx4_err(dev, "Failed to register device\n"); 1084 goto out; 1085 } 1086 mlx4_request_modules(dev); 1087 } 1088 1089 out: 1090 return err; 1091 } 1092 1093 static ssize_t show_port_type(struct device *dev, 1094 struct device_attribute *attr, 1095 char *buf) 1096 { 1097 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1098 port_attr); 1099 struct mlx4_dev *mdev = info->dev; 1100 char type[8]; 1101 1102 sprintf(type, "%s", 1103 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1104 "ib" : "eth"); 1105 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1106 sprintf(buf, "auto (%s)\n", type); 1107 else 1108 sprintf(buf, "%s\n", type); 1109 1110 return strlen(buf); 1111 } 1112 1113 static int __set_port_type(struct mlx4_port_info *info, 1114 enum mlx4_port_type port_type) 1115 { 1116 struct mlx4_dev *mdev = info->dev; 1117 struct mlx4_priv *priv = mlx4_priv(mdev); 1118 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1119 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1120 int i; 1121 int err = 0; 1122 1123 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1124 mlx4_err(mdev, 1125 "Requested port type for port %d is not supported on this HCA\n", 1126 info->port); 1127 err = -EINVAL; 1128 goto err_sup; 1129 } 1130 1131 mlx4_stop_sense(mdev); 1132 mutex_lock(&priv->port_mutex); 1133 info->tmp_type = port_type; 1134 1135 /* Possible type is always the one that was delivered */ 1136 mdev->caps.possible_type[info->port] = info->tmp_type; 1137 1138 for (i = 0; i < mdev->caps.num_ports; i++) { 1139 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1140 mdev->caps.possible_type[i+1]; 1141 if (types[i] == MLX4_PORT_TYPE_AUTO) 1142 types[i] = mdev->caps.port_type[i+1]; 1143 } 1144 1145 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1146 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1147 for (i = 1; i <= mdev->caps.num_ports; i++) { 1148 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1149 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1150 err = -EINVAL; 1151 } 1152 } 1153 } 1154 if (err) { 1155 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1156 goto out; 1157 } 1158 1159 mlx4_do_sense_ports(mdev, new_types, types); 1160 1161 err = mlx4_check_port_params(mdev, new_types); 1162 if (err) 1163 goto out; 1164 1165 /* We are about to apply the changes after the configuration 1166 * was verified, no need to remember the temporary types 1167 * any more */ 1168 for (i = 0; i < mdev->caps.num_ports; i++) 1169 priv->port[i + 1].tmp_type = 0; 1170 1171 err = mlx4_change_port_types(mdev, new_types); 1172 1173 out: 1174 mlx4_start_sense(mdev); 1175 mutex_unlock(&priv->port_mutex); 1176 err_sup: 1177 return err; 1178 } 1179 1180 static ssize_t set_port_type(struct device *dev, 1181 struct device_attribute *attr, 1182 const char *buf, size_t count) 1183 { 1184 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1185 port_attr); 1186 struct mlx4_dev *mdev = info->dev; 1187 enum mlx4_port_type port_type; 1188 static DEFINE_MUTEX(set_port_type_mutex); 1189 int err; 1190 1191 mutex_lock(&set_port_type_mutex); 1192 1193 if (!strcmp(buf, "ib\n")) { 1194 port_type = MLX4_PORT_TYPE_IB; 1195 } else if (!strcmp(buf, "eth\n")) { 1196 port_type = MLX4_PORT_TYPE_ETH; 1197 } else if (!strcmp(buf, "auto\n")) { 1198 port_type = MLX4_PORT_TYPE_AUTO; 1199 } else { 1200 mlx4_err(mdev, "%s is not supported port type\n", buf); 1201 err = -EINVAL; 1202 goto err_out; 1203 } 1204 1205 err = __set_port_type(info, port_type); 1206 1207 err_out: 1208 mutex_unlock(&set_port_type_mutex); 1209 1210 return err ? err : count; 1211 } 1212 1213 enum ibta_mtu { 1214 IB_MTU_256 = 1, 1215 IB_MTU_512 = 2, 1216 IB_MTU_1024 = 3, 1217 IB_MTU_2048 = 4, 1218 IB_MTU_4096 = 5 1219 }; 1220 1221 static inline int int_to_ibta_mtu(int mtu) 1222 { 1223 switch (mtu) { 1224 case 256: return IB_MTU_256; 1225 case 512: return IB_MTU_512; 1226 case 1024: return IB_MTU_1024; 1227 case 2048: return IB_MTU_2048; 1228 case 4096: return IB_MTU_4096; 1229 default: return -1; 1230 } 1231 } 1232 1233 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1234 { 1235 switch (mtu) { 1236 case IB_MTU_256: return 256; 1237 case IB_MTU_512: return 512; 1238 case IB_MTU_1024: return 1024; 1239 case IB_MTU_2048: return 2048; 1240 case IB_MTU_4096: return 4096; 1241 default: return -1; 1242 } 1243 } 1244 1245 static ssize_t show_port_ib_mtu(struct device *dev, 1246 struct device_attribute *attr, 1247 char *buf) 1248 { 1249 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1250 port_mtu_attr); 1251 struct mlx4_dev *mdev = info->dev; 1252 1253 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1254 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1255 1256 sprintf(buf, "%d\n", 1257 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1258 return strlen(buf); 1259 } 1260 1261 static ssize_t set_port_ib_mtu(struct device *dev, 1262 struct device_attribute *attr, 1263 const char *buf, size_t count) 1264 { 1265 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1266 port_mtu_attr); 1267 struct mlx4_dev *mdev = info->dev; 1268 struct mlx4_priv *priv = mlx4_priv(mdev); 1269 int err, port, mtu, ibta_mtu = -1; 1270 1271 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1272 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1273 return -EINVAL; 1274 } 1275 1276 err = kstrtoint(buf, 0, &mtu); 1277 if (!err) 1278 ibta_mtu = int_to_ibta_mtu(mtu); 1279 1280 if (err || ibta_mtu < 0) { 1281 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1282 return -EINVAL; 1283 } 1284 1285 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1286 1287 mlx4_stop_sense(mdev); 1288 mutex_lock(&priv->port_mutex); 1289 mlx4_unregister_device(mdev); 1290 for (port = 1; port <= mdev->caps.num_ports; port++) { 1291 mlx4_CLOSE_PORT(mdev, port); 1292 err = mlx4_SET_PORT(mdev, port, -1); 1293 if (err) { 1294 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1295 port); 1296 goto err_set_port; 1297 } 1298 } 1299 err = mlx4_register_device(mdev); 1300 err_set_port: 1301 mutex_unlock(&priv->port_mutex); 1302 mlx4_start_sense(mdev); 1303 return err ? err : count; 1304 } 1305 1306 /* bond for multi-function device */ 1307 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1308 static int mlx4_mf_bond(struct mlx4_dev *dev) 1309 { 1310 int err = 0; 1311 int nvfs; 1312 struct mlx4_slaves_pport slaves_port1; 1313 struct mlx4_slaves_pport slaves_port2; 1314 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1315 1316 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1317 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1318 bitmap_and(slaves_port_1_2, 1319 slaves_port1.slaves, slaves_port2.slaves, 1320 dev->persist->num_vfs + 1); 1321 1322 /* only single port vfs are allowed */ 1323 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1324 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1325 return -EINVAL; 1326 } 1327 1328 /* number of virtual functions is number of total functions minus one 1329 * physical function for each port. 1330 */ 1331 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1332 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1333 1334 /* limit on maximum allowed VFs */ 1335 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1336 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1337 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1338 return -EINVAL; 1339 } 1340 1341 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1342 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1343 return -EINVAL; 1344 } 1345 1346 err = mlx4_bond_mac_table(dev); 1347 if (err) 1348 return err; 1349 err = mlx4_bond_vlan_table(dev); 1350 if (err) 1351 goto err1; 1352 err = mlx4_bond_fs_rules(dev); 1353 if (err) 1354 goto err2; 1355 1356 return 0; 1357 err2: 1358 (void)mlx4_unbond_vlan_table(dev); 1359 err1: 1360 (void)mlx4_unbond_mac_table(dev); 1361 return err; 1362 } 1363 1364 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1365 { 1366 int ret, ret1; 1367 1368 ret = mlx4_unbond_fs_rules(dev); 1369 if (ret) 1370 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret); 1371 ret1 = mlx4_unbond_mac_table(dev); 1372 if (ret1) { 1373 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1374 ret = ret1; 1375 } 1376 ret1 = mlx4_unbond_vlan_table(dev); 1377 if (ret1) { 1378 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1379 ret = ret1; 1380 } 1381 return ret; 1382 } 1383 1384 int mlx4_bond(struct mlx4_dev *dev) 1385 { 1386 int ret = 0; 1387 struct mlx4_priv *priv = mlx4_priv(dev); 1388 1389 mutex_lock(&priv->bond_mutex); 1390 1391 if (!mlx4_is_bonded(dev)) { 1392 ret = mlx4_do_bond(dev, true); 1393 if (ret) 1394 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1395 if (!ret && mlx4_is_master(dev)) { 1396 ret = mlx4_mf_bond(dev); 1397 if (ret) { 1398 mlx4_err(dev, "bond for multifunction failed\n"); 1399 mlx4_do_bond(dev, false); 1400 } 1401 } 1402 } 1403 1404 mutex_unlock(&priv->bond_mutex); 1405 if (!ret) 1406 mlx4_dbg(dev, "Device is bonded\n"); 1407 1408 return ret; 1409 } 1410 EXPORT_SYMBOL_GPL(mlx4_bond); 1411 1412 int mlx4_unbond(struct mlx4_dev *dev) 1413 { 1414 int ret = 0; 1415 struct mlx4_priv *priv = mlx4_priv(dev); 1416 1417 mutex_lock(&priv->bond_mutex); 1418 1419 if (mlx4_is_bonded(dev)) { 1420 int ret2 = 0; 1421 1422 ret = mlx4_do_bond(dev, false); 1423 if (ret) 1424 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1425 if (mlx4_is_master(dev)) 1426 ret2 = mlx4_mf_unbond(dev); 1427 if (ret2) { 1428 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1429 ret = ret2; 1430 } 1431 } 1432 1433 mutex_unlock(&priv->bond_mutex); 1434 if (!ret) 1435 mlx4_dbg(dev, "Device is unbonded\n"); 1436 1437 return ret; 1438 } 1439 EXPORT_SYMBOL_GPL(mlx4_unbond); 1440 1441 1442 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1443 { 1444 u8 port1 = v2p->port1; 1445 u8 port2 = v2p->port2; 1446 struct mlx4_priv *priv = mlx4_priv(dev); 1447 int err; 1448 1449 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1450 return -ENOTSUPP; 1451 1452 mutex_lock(&priv->bond_mutex); 1453 1454 /* zero means keep current mapping for this port */ 1455 if (port1 == 0) 1456 port1 = priv->v2p.port1; 1457 if (port2 == 0) 1458 port2 = priv->v2p.port2; 1459 1460 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1461 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1462 (port1 == 2 && port2 == 1)) { 1463 /* besides boundary checks cross mapping makes 1464 * no sense and therefore not allowed */ 1465 err = -EINVAL; 1466 } else if ((port1 == priv->v2p.port1) && 1467 (port2 == priv->v2p.port2)) { 1468 err = 0; 1469 } else { 1470 err = mlx4_virt2phy_port_map(dev, port1, port2); 1471 if (!err) { 1472 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1473 port1, port2); 1474 priv->v2p.port1 = port1; 1475 priv->v2p.port2 = port2; 1476 } else { 1477 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1478 } 1479 } 1480 1481 mutex_unlock(&priv->bond_mutex); 1482 return err; 1483 } 1484 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1485 1486 static int mlx4_load_fw(struct mlx4_dev *dev) 1487 { 1488 struct mlx4_priv *priv = mlx4_priv(dev); 1489 int err; 1490 1491 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1492 GFP_HIGHUSER | __GFP_NOWARN, 0); 1493 if (!priv->fw.fw_icm) { 1494 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1495 return -ENOMEM; 1496 } 1497 1498 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1499 if (err) { 1500 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1501 goto err_free; 1502 } 1503 1504 err = mlx4_RUN_FW(dev); 1505 if (err) { 1506 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1507 goto err_unmap_fa; 1508 } 1509 1510 return 0; 1511 1512 err_unmap_fa: 1513 mlx4_UNMAP_FA(dev); 1514 1515 err_free: 1516 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1517 return err; 1518 } 1519 1520 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1521 int cmpt_entry_sz) 1522 { 1523 struct mlx4_priv *priv = mlx4_priv(dev); 1524 int err; 1525 int num_eqs; 1526 1527 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1528 cmpt_base + 1529 ((u64) (MLX4_CMPT_TYPE_QP * 1530 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1531 cmpt_entry_sz, dev->caps.num_qps, 1532 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1533 0, 0); 1534 if (err) 1535 goto err; 1536 1537 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1538 cmpt_base + 1539 ((u64) (MLX4_CMPT_TYPE_SRQ * 1540 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1541 cmpt_entry_sz, dev->caps.num_srqs, 1542 dev->caps.reserved_srqs, 0, 0); 1543 if (err) 1544 goto err_qp; 1545 1546 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1547 cmpt_base + 1548 ((u64) (MLX4_CMPT_TYPE_CQ * 1549 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1550 cmpt_entry_sz, dev->caps.num_cqs, 1551 dev->caps.reserved_cqs, 0, 0); 1552 if (err) 1553 goto err_srq; 1554 1555 num_eqs = dev->phys_caps.num_phys_eqs; 1556 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1557 cmpt_base + 1558 ((u64) (MLX4_CMPT_TYPE_EQ * 1559 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1560 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1561 if (err) 1562 goto err_cq; 1563 1564 return 0; 1565 1566 err_cq: 1567 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1568 1569 err_srq: 1570 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1571 1572 err_qp: 1573 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1574 1575 err: 1576 return err; 1577 } 1578 1579 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1580 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1581 { 1582 struct mlx4_priv *priv = mlx4_priv(dev); 1583 u64 aux_pages; 1584 int num_eqs; 1585 int err; 1586 1587 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1588 if (err) { 1589 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1590 return err; 1591 } 1592 1593 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1594 (unsigned long long) icm_size >> 10, 1595 (unsigned long long) aux_pages << 2); 1596 1597 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1598 GFP_HIGHUSER | __GFP_NOWARN, 0); 1599 if (!priv->fw.aux_icm) { 1600 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1601 return -ENOMEM; 1602 } 1603 1604 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1605 if (err) { 1606 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1607 goto err_free_aux; 1608 } 1609 1610 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1611 if (err) { 1612 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1613 goto err_unmap_aux; 1614 } 1615 1616 1617 num_eqs = dev->phys_caps.num_phys_eqs; 1618 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1619 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1620 num_eqs, num_eqs, 0, 0); 1621 if (err) { 1622 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1623 goto err_unmap_cmpt; 1624 } 1625 1626 /* 1627 * Reserved MTT entries must be aligned up to a cacheline 1628 * boundary, since the FW will write to them, while the driver 1629 * writes to all other MTT entries. (The variable 1630 * dev->caps.mtt_entry_sz below is really the MTT segment 1631 * size, not the raw entry size) 1632 */ 1633 dev->caps.reserved_mtts = 1634 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1635 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1636 1637 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1638 init_hca->mtt_base, 1639 dev->caps.mtt_entry_sz, 1640 dev->caps.num_mtts, 1641 dev->caps.reserved_mtts, 1, 0); 1642 if (err) { 1643 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1644 goto err_unmap_eq; 1645 } 1646 1647 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1648 init_hca->dmpt_base, 1649 dev_cap->dmpt_entry_sz, 1650 dev->caps.num_mpts, 1651 dev->caps.reserved_mrws, 1, 1); 1652 if (err) { 1653 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1654 goto err_unmap_mtt; 1655 } 1656 1657 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1658 init_hca->qpc_base, 1659 dev_cap->qpc_entry_sz, 1660 dev->caps.num_qps, 1661 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1662 0, 0); 1663 if (err) { 1664 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1665 goto err_unmap_dmpt; 1666 } 1667 1668 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1669 init_hca->auxc_base, 1670 dev_cap->aux_entry_sz, 1671 dev->caps.num_qps, 1672 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1673 0, 0); 1674 if (err) { 1675 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1676 goto err_unmap_qp; 1677 } 1678 1679 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1680 init_hca->altc_base, 1681 dev_cap->altc_entry_sz, 1682 dev->caps.num_qps, 1683 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1684 0, 0); 1685 if (err) { 1686 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1687 goto err_unmap_auxc; 1688 } 1689 1690 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1691 init_hca->rdmarc_base, 1692 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1693 dev->caps.num_qps, 1694 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1695 0, 0); 1696 if (err) { 1697 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1698 goto err_unmap_altc; 1699 } 1700 1701 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1702 init_hca->cqc_base, 1703 dev_cap->cqc_entry_sz, 1704 dev->caps.num_cqs, 1705 dev->caps.reserved_cqs, 0, 0); 1706 if (err) { 1707 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1708 goto err_unmap_rdmarc; 1709 } 1710 1711 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1712 init_hca->srqc_base, 1713 dev_cap->srq_entry_sz, 1714 dev->caps.num_srqs, 1715 dev->caps.reserved_srqs, 0, 0); 1716 if (err) { 1717 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1718 goto err_unmap_cq; 1719 } 1720 1721 /* 1722 * For flow steering device managed mode it is required to use 1723 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1724 * required, but for simplicity just map the whole multicast 1725 * group table now. The table isn't very big and it's a lot 1726 * easier than trying to track ref counts. 1727 */ 1728 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1729 init_hca->mc_base, 1730 mlx4_get_mgm_entry_size(dev), 1731 dev->caps.num_mgms + dev->caps.num_amgms, 1732 dev->caps.num_mgms + dev->caps.num_amgms, 1733 0, 0); 1734 if (err) { 1735 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1736 goto err_unmap_srq; 1737 } 1738 1739 return 0; 1740 1741 err_unmap_srq: 1742 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1743 1744 err_unmap_cq: 1745 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1746 1747 err_unmap_rdmarc: 1748 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1749 1750 err_unmap_altc: 1751 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1752 1753 err_unmap_auxc: 1754 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1755 1756 err_unmap_qp: 1757 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1758 1759 err_unmap_dmpt: 1760 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1761 1762 err_unmap_mtt: 1763 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1764 1765 err_unmap_eq: 1766 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1767 1768 err_unmap_cmpt: 1769 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1770 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1771 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1772 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1773 1774 err_unmap_aux: 1775 mlx4_UNMAP_ICM_AUX(dev); 1776 1777 err_free_aux: 1778 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1779 1780 return err; 1781 } 1782 1783 static void mlx4_free_icms(struct mlx4_dev *dev) 1784 { 1785 struct mlx4_priv *priv = mlx4_priv(dev); 1786 1787 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1788 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1789 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1790 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1791 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1792 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1793 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1794 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1795 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1796 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1797 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1798 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1799 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1800 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1801 1802 mlx4_UNMAP_ICM_AUX(dev); 1803 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1804 } 1805 1806 static void mlx4_slave_exit(struct mlx4_dev *dev) 1807 { 1808 struct mlx4_priv *priv = mlx4_priv(dev); 1809 1810 mutex_lock(&priv->cmd.slave_cmd_mutex); 1811 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1812 MLX4_COMM_TIME)) 1813 mlx4_warn(dev, "Failed to close slave function\n"); 1814 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1815 } 1816 1817 static int map_bf_area(struct mlx4_dev *dev) 1818 { 1819 struct mlx4_priv *priv = mlx4_priv(dev); 1820 resource_size_t bf_start; 1821 resource_size_t bf_len; 1822 int err = 0; 1823 1824 if (!dev->caps.bf_reg_size) 1825 return -ENXIO; 1826 1827 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1828 (dev->caps.num_uars << PAGE_SHIFT); 1829 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1830 (dev->caps.num_uars << PAGE_SHIFT); 1831 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1832 if (!priv->bf_mapping) 1833 err = -ENOMEM; 1834 1835 return err; 1836 } 1837 1838 static void unmap_bf_area(struct mlx4_dev *dev) 1839 { 1840 if (mlx4_priv(dev)->bf_mapping) 1841 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1842 } 1843 1844 u64 mlx4_read_clock(struct mlx4_dev *dev) 1845 { 1846 u32 clockhi, clocklo, clockhi1; 1847 u64 cycles; 1848 int i; 1849 struct mlx4_priv *priv = mlx4_priv(dev); 1850 1851 for (i = 0; i < 10; i++) { 1852 clockhi = swab32(readl(priv->clock_mapping)); 1853 clocklo = swab32(readl(priv->clock_mapping + 4)); 1854 clockhi1 = swab32(readl(priv->clock_mapping)); 1855 if (clockhi == clockhi1) 1856 break; 1857 } 1858 1859 cycles = (u64) clockhi << 32 | (u64) clocklo; 1860 1861 return cycles; 1862 } 1863 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1864 1865 1866 static int map_internal_clock(struct mlx4_dev *dev) 1867 { 1868 struct mlx4_priv *priv = mlx4_priv(dev); 1869 1870 priv->clock_mapping = 1871 ioremap(pci_resource_start(dev->persist->pdev, 1872 priv->fw.clock_bar) + 1873 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1874 1875 if (!priv->clock_mapping) 1876 return -ENOMEM; 1877 1878 return 0; 1879 } 1880 1881 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1882 struct mlx4_clock_params *params) 1883 { 1884 struct mlx4_priv *priv = mlx4_priv(dev); 1885 1886 if (mlx4_is_slave(dev)) 1887 return -ENOTSUPP; 1888 1889 if (!params) 1890 return -EINVAL; 1891 1892 params->bar = priv->fw.clock_bar; 1893 params->offset = priv->fw.clock_offset; 1894 params->size = MLX4_CLOCK_SIZE; 1895 1896 return 0; 1897 } 1898 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1899 1900 static void unmap_internal_clock(struct mlx4_dev *dev) 1901 { 1902 struct mlx4_priv *priv = mlx4_priv(dev); 1903 1904 if (priv->clock_mapping) 1905 iounmap(priv->clock_mapping); 1906 } 1907 1908 static void mlx4_close_hca(struct mlx4_dev *dev) 1909 { 1910 unmap_internal_clock(dev); 1911 unmap_bf_area(dev); 1912 if (mlx4_is_slave(dev)) 1913 mlx4_slave_exit(dev); 1914 else { 1915 mlx4_CLOSE_HCA(dev, 0); 1916 mlx4_free_icms(dev); 1917 } 1918 } 1919 1920 static void mlx4_close_fw(struct mlx4_dev *dev) 1921 { 1922 if (!mlx4_is_slave(dev)) { 1923 mlx4_UNMAP_FA(dev); 1924 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1925 } 1926 } 1927 1928 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1929 { 1930 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1931 1932 u32 comm_flags; 1933 u32 offline_bit; 1934 unsigned long end; 1935 struct mlx4_priv *priv = mlx4_priv(dev); 1936 1937 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 1938 while (time_before(jiffies, end)) { 1939 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 1940 MLX4_COMM_CHAN_FLAGS)); 1941 offline_bit = (comm_flags & 1942 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 1943 if (!offline_bit) 1944 return 0; 1945 /* There are cases as part of AER/Reset flow that PF needs 1946 * around 100 msec to load. We therefore sleep for 100 msec 1947 * to allow other tasks to make use of that CPU during this 1948 * time interval. 1949 */ 1950 msleep(100); 1951 } 1952 mlx4_err(dev, "Communication channel is offline.\n"); 1953 return -EIO; 1954 } 1955 1956 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 1957 { 1958 #define COMM_CHAN_RST_OFFSET 0x1e 1959 1960 struct mlx4_priv *priv = mlx4_priv(dev); 1961 u32 comm_rst; 1962 u32 comm_caps; 1963 1964 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 1965 MLX4_COMM_CHAN_CAPS)); 1966 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 1967 1968 if (comm_rst) 1969 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 1970 } 1971 1972 static int mlx4_init_slave(struct mlx4_dev *dev) 1973 { 1974 struct mlx4_priv *priv = mlx4_priv(dev); 1975 u64 dma = (u64) priv->mfunc.vhcr_dma; 1976 int ret_from_reset = 0; 1977 u32 slave_read; 1978 u32 cmd_channel_ver; 1979 1980 if (atomic_read(&pf_loading)) { 1981 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 1982 return -EPROBE_DEFER; 1983 } 1984 1985 mutex_lock(&priv->cmd.slave_cmd_mutex); 1986 priv->cmd.max_cmds = 1; 1987 if (mlx4_comm_check_offline(dev)) { 1988 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 1989 goto err_offline; 1990 } 1991 1992 mlx4_reset_vf_support(dev); 1993 mlx4_warn(dev, "Sending reset\n"); 1994 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1995 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 1996 /* if we are in the middle of flr the slave will try 1997 * NUM_OF_RESET_RETRIES times before leaving.*/ 1998 if (ret_from_reset) { 1999 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2000 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2001 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2002 return -EPROBE_DEFER; 2003 } else 2004 goto err; 2005 } 2006 2007 /* check the driver version - the slave I/F revision 2008 * must match the master's */ 2009 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2010 cmd_channel_ver = mlx4_comm_get_version(); 2011 2012 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2013 MLX4_COMM_GET_IF_REV(slave_read)) { 2014 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2015 goto err; 2016 } 2017 2018 mlx4_warn(dev, "Sending vhcr0\n"); 2019 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2020 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2021 goto err; 2022 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2023 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2024 goto err; 2025 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2026 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2027 goto err; 2028 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2029 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2030 goto err; 2031 2032 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2033 return 0; 2034 2035 err: 2036 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2037 err_offline: 2038 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2039 return -EIO; 2040 } 2041 2042 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2043 { 2044 int i; 2045 2046 for (i = 1; i <= dev->caps.num_ports; i++) { 2047 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2048 dev->caps.gid_table_len[i] = 2049 mlx4_get_slave_num_gids(dev, 0, i); 2050 else 2051 dev->caps.gid_table_len[i] = 1; 2052 dev->caps.pkey_table_len[i] = 2053 dev->phys_caps.pkey_phys_table_len[i] - 1; 2054 } 2055 } 2056 2057 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2058 { 2059 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2060 2061 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2062 i++) { 2063 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2064 break; 2065 } 2066 2067 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2068 } 2069 2070 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2071 { 2072 switch (dmfs_high_steer_mode) { 2073 case MLX4_STEERING_DMFS_A0_DEFAULT: 2074 return "default performance"; 2075 2076 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2077 return "dynamic hybrid mode"; 2078 2079 case MLX4_STEERING_DMFS_A0_STATIC: 2080 return "performance optimized for limited rule configuration (static)"; 2081 2082 case MLX4_STEERING_DMFS_A0_DISABLE: 2083 return "disabled performance optimized steering"; 2084 2085 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2086 return "performance optimized steering not supported"; 2087 2088 default: 2089 return "Unrecognized mode"; 2090 } 2091 } 2092 2093 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2094 2095 static void choose_steering_mode(struct mlx4_dev *dev, 2096 struct mlx4_dev_cap *dev_cap) 2097 { 2098 if (mlx4_log_num_mgm_entry_size <= 0) { 2099 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2100 if (dev->caps.dmfs_high_steer_mode == 2101 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2102 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2103 else 2104 dev->caps.dmfs_high_steer_mode = 2105 MLX4_STEERING_DMFS_A0_STATIC; 2106 } 2107 } 2108 2109 if (mlx4_log_num_mgm_entry_size <= 0 && 2110 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2111 (!mlx4_is_mfunc(dev) || 2112 (dev_cap->fs_max_num_qp_per_entry >= 2113 (dev->persist->num_vfs + 1))) && 2114 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2115 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2116 dev->oper_log_mgm_entry_size = 2117 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2118 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2119 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2120 dev->caps.fs_log_max_ucast_qp_range_size = 2121 dev_cap->fs_log_max_ucast_qp_range_size; 2122 } else { 2123 if (dev->caps.dmfs_high_steer_mode != 2124 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2125 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2126 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2127 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2128 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2129 else { 2130 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2131 2132 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2133 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2134 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2135 } 2136 dev->oper_log_mgm_entry_size = 2137 mlx4_log_num_mgm_entry_size > 0 ? 2138 mlx4_log_num_mgm_entry_size : 2139 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2140 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2141 } 2142 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2143 mlx4_steering_mode_str(dev->caps.steering_mode), 2144 dev->oper_log_mgm_entry_size, 2145 mlx4_log_num_mgm_entry_size); 2146 } 2147 2148 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2149 struct mlx4_dev_cap *dev_cap) 2150 { 2151 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2152 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2153 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2154 else 2155 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2156 2157 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2158 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2159 } 2160 2161 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2162 { 2163 int i; 2164 struct mlx4_port_cap port_cap; 2165 2166 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2167 return -EINVAL; 2168 2169 for (i = 1; i <= dev->caps.num_ports; i++) { 2170 if (mlx4_dev_port(dev, i, &port_cap)) { 2171 mlx4_err(dev, 2172 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 2173 } else if ((dev->caps.dmfs_high_steer_mode != 2174 MLX4_STEERING_DMFS_A0_DEFAULT) && 2175 (port_cap.dmfs_optimized_state == 2176 !!(dev->caps.dmfs_high_steer_mode == 2177 MLX4_STEERING_DMFS_A0_DISABLE))) { 2178 mlx4_err(dev, 2179 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2180 dmfs_high_rate_steering_mode_str( 2181 dev->caps.dmfs_high_steer_mode), 2182 (port_cap.dmfs_optimized_state ? 2183 "enabled" : "disabled")); 2184 } 2185 } 2186 2187 return 0; 2188 } 2189 2190 static int mlx4_init_fw(struct mlx4_dev *dev) 2191 { 2192 struct mlx4_mod_stat_cfg mlx4_cfg; 2193 int err = 0; 2194 2195 if (!mlx4_is_slave(dev)) { 2196 err = mlx4_QUERY_FW(dev); 2197 if (err) { 2198 if (err == -EACCES) 2199 mlx4_info(dev, "non-primary physical function, skipping\n"); 2200 else 2201 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2202 return err; 2203 } 2204 2205 err = mlx4_load_fw(dev); 2206 if (err) { 2207 mlx4_err(dev, "Failed to start FW, aborting\n"); 2208 return err; 2209 } 2210 2211 mlx4_cfg.log_pg_sz_m = 1; 2212 mlx4_cfg.log_pg_sz = 0; 2213 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2214 if (err) 2215 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2216 } 2217 2218 return err; 2219 } 2220 2221 static int mlx4_init_hca(struct mlx4_dev *dev) 2222 { 2223 struct mlx4_priv *priv = mlx4_priv(dev); 2224 struct mlx4_adapter adapter; 2225 struct mlx4_dev_cap dev_cap; 2226 struct mlx4_profile profile; 2227 struct mlx4_init_hca_param init_hca; 2228 u64 icm_size; 2229 struct mlx4_config_dev_params params; 2230 int err; 2231 2232 if (!mlx4_is_slave(dev)) { 2233 err = mlx4_dev_cap(dev, &dev_cap); 2234 if (err) { 2235 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2236 return err; 2237 } 2238 2239 choose_steering_mode(dev, &dev_cap); 2240 choose_tunnel_offload_mode(dev, &dev_cap); 2241 2242 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2243 mlx4_is_master(dev)) 2244 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2245 2246 err = mlx4_get_phys_port_id(dev); 2247 if (err) 2248 mlx4_err(dev, "Fail to get physical port id\n"); 2249 2250 if (mlx4_is_master(dev)) 2251 mlx4_parav_master_pf_caps(dev); 2252 2253 if (mlx4_low_memory_profile()) { 2254 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2255 profile = low_mem_profile; 2256 } else { 2257 profile = default_profile; 2258 } 2259 if (dev->caps.steering_mode == 2260 MLX4_STEERING_MODE_DEVICE_MANAGED) 2261 profile.num_mcg = MLX4_FS_NUM_MCG; 2262 2263 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2264 &init_hca); 2265 if ((long long) icm_size < 0) { 2266 err = icm_size; 2267 return err; 2268 } 2269 2270 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2271 2272 if (enable_4k_uar) { 2273 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) + 2274 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2275 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2276 } else { 2277 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2278 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2279 } 2280 2281 init_hca.mw_enabled = 0; 2282 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2283 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2284 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2285 2286 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2287 if (err) 2288 return err; 2289 2290 err = mlx4_INIT_HCA(dev, &init_hca); 2291 if (err) { 2292 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2293 goto err_free_icm; 2294 } 2295 2296 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2297 err = mlx4_query_func(dev, &dev_cap); 2298 if (err < 0) { 2299 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2300 goto err_close; 2301 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2302 dev->caps.num_eqs = dev_cap.max_eqs; 2303 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2304 dev->caps.reserved_uars = dev_cap.reserved_uars; 2305 } 2306 } 2307 2308 /* 2309 * If TS is supported by FW 2310 * read HCA frequency by QUERY_HCA command 2311 */ 2312 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2313 memset(&init_hca, 0, sizeof(init_hca)); 2314 err = mlx4_QUERY_HCA(dev, &init_hca); 2315 if (err) { 2316 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2317 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2318 } else { 2319 dev->caps.hca_core_clock = 2320 init_hca.hca_core_clock; 2321 } 2322 2323 /* In case we got HCA frequency 0 - disable timestamping 2324 * to avoid dividing by zero 2325 */ 2326 if (!dev->caps.hca_core_clock) { 2327 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2328 mlx4_err(dev, 2329 "HCA frequency is 0 - timestamping is not supported\n"); 2330 } else if (map_internal_clock(dev)) { 2331 /* 2332 * Map internal clock, 2333 * in case of failure disable timestamping 2334 */ 2335 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2336 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2337 } 2338 } 2339 2340 if (dev->caps.dmfs_high_steer_mode != 2341 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2342 if (mlx4_validate_optimized_steering(dev)) 2343 mlx4_warn(dev, "Optimized steering validation failed\n"); 2344 2345 if (dev->caps.dmfs_high_steer_mode == 2346 MLX4_STEERING_DMFS_A0_DISABLE) { 2347 dev->caps.dmfs_high_rate_qpn_base = 2348 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2349 dev->caps.dmfs_high_rate_qpn_range = 2350 MLX4_A0_STEERING_TABLE_SIZE; 2351 } 2352 2353 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n", 2354 dmfs_high_rate_steering_mode_str( 2355 dev->caps.dmfs_high_steer_mode)); 2356 } 2357 } else { 2358 err = mlx4_init_slave(dev); 2359 if (err) { 2360 if (err != -EPROBE_DEFER) 2361 mlx4_err(dev, "Failed to initialize slave\n"); 2362 return err; 2363 } 2364 2365 err = mlx4_slave_cap(dev); 2366 if (err) { 2367 mlx4_err(dev, "Failed to obtain slave caps\n"); 2368 goto err_close; 2369 } 2370 } 2371 2372 if (map_bf_area(dev)) 2373 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2374 2375 /*Only the master set the ports, all the rest got it from it.*/ 2376 if (!mlx4_is_slave(dev)) 2377 mlx4_set_port_mask(dev); 2378 2379 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2380 if (err) { 2381 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2382 goto unmap_bf; 2383 } 2384 2385 /* Query CONFIG_DEV parameters */ 2386 err = mlx4_config_dev_retrieval(dev, ¶ms); 2387 if (err && err != -ENOTSUPP) { 2388 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2389 } else if (!err) { 2390 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2391 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2392 } 2393 priv->eq_table.inta_pin = adapter.inta_pin; 2394 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 2395 2396 return 0; 2397 2398 unmap_bf: 2399 unmap_internal_clock(dev); 2400 unmap_bf_area(dev); 2401 2402 if (mlx4_is_slave(dev)) { 2403 kfree(dev->caps.qp0_qkey); 2404 kfree(dev->caps.qp0_tunnel); 2405 kfree(dev->caps.qp0_proxy); 2406 kfree(dev->caps.qp1_tunnel); 2407 kfree(dev->caps.qp1_proxy); 2408 } 2409 2410 err_close: 2411 if (mlx4_is_slave(dev)) 2412 mlx4_slave_exit(dev); 2413 else 2414 mlx4_CLOSE_HCA(dev, 0); 2415 2416 err_free_icm: 2417 if (!mlx4_is_slave(dev)) 2418 mlx4_free_icms(dev); 2419 2420 return err; 2421 } 2422 2423 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2424 { 2425 struct mlx4_priv *priv = mlx4_priv(dev); 2426 int nent_pow2; 2427 2428 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2429 return -ENOENT; 2430 2431 if (!dev->caps.max_counters) 2432 return -ENOSPC; 2433 2434 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2435 /* reserve last counter index for sink counter */ 2436 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2437 nent_pow2 - 1, 0, 2438 nent_pow2 - dev->caps.max_counters + 1); 2439 } 2440 2441 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2442 { 2443 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2444 return; 2445 2446 if (!dev->caps.max_counters) 2447 return; 2448 2449 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2450 } 2451 2452 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2453 { 2454 struct mlx4_priv *priv = mlx4_priv(dev); 2455 int port; 2456 2457 for (port = 0; port < dev->caps.num_ports; port++) 2458 if (priv->def_counter[port] != -1) 2459 mlx4_counter_free(dev, priv->def_counter[port]); 2460 } 2461 2462 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2463 { 2464 struct mlx4_priv *priv = mlx4_priv(dev); 2465 int port, err = 0; 2466 u32 idx; 2467 2468 for (port = 0; port < dev->caps.num_ports; port++) 2469 priv->def_counter[port] = -1; 2470 2471 for (port = 0; port < dev->caps.num_ports; port++) { 2472 err = mlx4_counter_alloc(dev, &idx); 2473 2474 if (!err || err == -ENOSPC) { 2475 priv->def_counter[port] = idx; 2476 } else if (err == -ENOENT) { 2477 err = 0; 2478 continue; 2479 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2480 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2481 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2482 MLX4_SINK_COUNTER_INDEX(dev)); 2483 err = 0; 2484 } else { 2485 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2486 __func__, port + 1, err); 2487 mlx4_cleanup_default_counters(dev); 2488 return err; 2489 } 2490 2491 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2492 __func__, priv->def_counter[port], port + 1); 2493 } 2494 2495 return err; 2496 } 2497 2498 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2499 { 2500 struct mlx4_priv *priv = mlx4_priv(dev); 2501 2502 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2503 return -ENOENT; 2504 2505 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2506 if (*idx == -1) { 2507 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2508 return -ENOSPC; 2509 } 2510 2511 return 0; 2512 } 2513 2514 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2515 { 2516 u64 out_param; 2517 int err; 2518 2519 if (mlx4_is_mfunc(dev)) { 2520 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 2521 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2522 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2523 if (!err) 2524 *idx = get_param_l(&out_param); 2525 2526 return err; 2527 } 2528 return __mlx4_counter_alloc(dev, idx); 2529 } 2530 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2531 2532 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2533 u8 counter_index) 2534 { 2535 struct mlx4_cmd_mailbox *if_stat_mailbox; 2536 int err; 2537 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2538 2539 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2540 if (IS_ERR(if_stat_mailbox)) 2541 return PTR_ERR(if_stat_mailbox); 2542 2543 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2544 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2545 MLX4_CMD_NATIVE); 2546 2547 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2548 return err; 2549 } 2550 2551 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2552 { 2553 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2554 return; 2555 2556 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2557 return; 2558 2559 __mlx4_clear_if_stat(dev, idx); 2560 2561 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2562 return; 2563 } 2564 2565 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2566 { 2567 u64 in_param = 0; 2568 2569 if (mlx4_is_mfunc(dev)) { 2570 set_param_l(&in_param, idx); 2571 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2572 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2573 MLX4_CMD_WRAPPED); 2574 return; 2575 } 2576 __mlx4_counter_free(dev, idx); 2577 } 2578 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2579 2580 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2581 { 2582 struct mlx4_priv *priv = mlx4_priv(dev); 2583 2584 return priv->def_counter[port - 1]; 2585 } 2586 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2587 2588 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2589 { 2590 struct mlx4_priv *priv = mlx4_priv(dev); 2591 2592 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2593 } 2594 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2595 2596 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2597 { 2598 struct mlx4_priv *priv = mlx4_priv(dev); 2599 2600 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2601 } 2602 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2603 2604 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2605 { 2606 struct mlx4_priv *priv = mlx4_priv(dev); 2607 __be64 guid; 2608 2609 /* hw GUID */ 2610 if (entry == 0) 2611 return; 2612 2613 get_random_bytes((char *)&guid, sizeof(guid)); 2614 guid &= ~(cpu_to_be64(1ULL << 56)); 2615 guid |= cpu_to_be64(1ULL << 57); 2616 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2617 } 2618 2619 static int mlx4_setup_hca(struct mlx4_dev *dev) 2620 { 2621 struct mlx4_priv *priv = mlx4_priv(dev); 2622 int err; 2623 int port; 2624 __be32 ib_port_default_caps; 2625 2626 err = mlx4_init_uar_table(dev); 2627 if (err) { 2628 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2629 return err; 2630 } 2631 2632 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2633 if (err) { 2634 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2635 goto err_uar_table_free; 2636 } 2637 2638 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2639 if (!priv->kar) { 2640 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2641 err = -ENOMEM; 2642 goto err_uar_free; 2643 } 2644 2645 err = mlx4_init_pd_table(dev); 2646 if (err) { 2647 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2648 goto err_kar_unmap; 2649 } 2650 2651 err = mlx4_init_xrcd_table(dev); 2652 if (err) { 2653 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2654 goto err_pd_table_free; 2655 } 2656 2657 err = mlx4_init_mr_table(dev); 2658 if (err) { 2659 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2660 goto err_xrcd_table_free; 2661 } 2662 2663 if (!mlx4_is_slave(dev)) { 2664 err = mlx4_init_mcg_table(dev); 2665 if (err) { 2666 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2667 goto err_mr_table_free; 2668 } 2669 err = mlx4_config_mad_demux(dev); 2670 if (err) { 2671 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2672 goto err_mcg_table_free; 2673 } 2674 } 2675 2676 err = mlx4_init_eq_table(dev); 2677 if (err) { 2678 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2679 goto err_mcg_table_free; 2680 } 2681 2682 err = mlx4_cmd_use_events(dev); 2683 if (err) { 2684 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2685 goto err_eq_table_free; 2686 } 2687 2688 err = mlx4_NOP(dev); 2689 if (err) { 2690 if (dev->flags & MLX4_FLAG_MSI_X) { 2691 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2692 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2693 mlx4_warn(dev, "Trying again without MSI-X\n"); 2694 } else { 2695 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2696 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2697 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2698 } 2699 2700 goto err_cmd_poll; 2701 } 2702 2703 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2704 2705 err = mlx4_init_cq_table(dev); 2706 if (err) { 2707 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2708 goto err_cmd_poll; 2709 } 2710 2711 err = mlx4_init_srq_table(dev); 2712 if (err) { 2713 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2714 goto err_cq_table_free; 2715 } 2716 2717 err = mlx4_init_qp_table(dev); 2718 if (err) { 2719 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2720 goto err_srq_table_free; 2721 } 2722 2723 if (!mlx4_is_slave(dev)) { 2724 err = mlx4_init_counters_table(dev); 2725 if (err && err != -ENOENT) { 2726 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2727 goto err_qp_table_free; 2728 } 2729 } 2730 2731 err = mlx4_allocate_default_counters(dev); 2732 if (err) { 2733 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2734 goto err_counters_table_free; 2735 } 2736 2737 if (!mlx4_is_slave(dev)) { 2738 for (port = 1; port <= dev->caps.num_ports; port++) { 2739 ib_port_default_caps = 0; 2740 err = mlx4_get_port_ib_caps(dev, port, 2741 &ib_port_default_caps); 2742 if (err) 2743 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2744 port, err); 2745 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2746 2747 /* initialize per-slave default ib port capabilities */ 2748 if (mlx4_is_master(dev)) { 2749 int i; 2750 for (i = 0; i < dev->num_slaves; i++) { 2751 if (i == mlx4_master_func_num(dev)) 2752 continue; 2753 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2754 ib_port_default_caps; 2755 } 2756 } 2757 2758 if (mlx4_is_mfunc(dev)) 2759 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2760 else 2761 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2762 2763 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2764 dev->caps.pkey_table_len[port] : -1); 2765 if (err) { 2766 mlx4_err(dev, "Failed to set port %d, aborting\n", 2767 port); 2768 goto err_default_countes_free; 2769 } 2770 } 2771 } 2772 2773 return 0; 2774 2775 err_default_countes_free: 2776 mlx4_cleanup_default_counters(dev); 2777 2778 err_counters_table_free: 2779 if (!mlx4_is_slave(dev)) 2780 mlx4_cleanup_counters_table(dev); 2781 2782 err_qp_table_free: 2783 mlx4_cleanup_qp_table(dev); 2784 2785 err_srq_table_free: 2786 mlx4_cleanup_srq_table(dev); 2787 2788 err_cq_table_free: 2789 mlx4_cleanup_cq_table(dev); 2790 2791 err_cmd_poll: 2792 mlx4_cmd_use_polling(dev); 2793 2794 err_eq_table_free: 2795 mlx4_cleanup_eq_table(dev); 2796 2797 err_mcg_table_free: 2798 if (!mlx4_is_slave(dev)) 2799 mlx4_cleanup_mcg_table(dev); 2800 2801 err_mr_table_free: 2802 mlx4_cleanup_mr_table(dev); 2803 2804 err_xrcd_table_free: 2805 mlx4_cleanup_xrcd_table(dev); 2806 2807 err_pd_table_free: 2808 mlx4_cleanup_pd_table(dev); 2809 2810 err_kar_unmap: 2811 iounmap(priv->kar); 2812 2813 err_uar_free: 2814 mlx4_uar_free(dev, &priv->driver_uar); 2815 2816 err_uar_table_free: 2817 mlx4_cleanup_uar_table(dev); 2818 return err; 2819 } 2820 2821 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2822 { 2823 int requested_cpu = 0; 2824 struct mlx4_priv *priv = mlx4_priv(dev); 2825 struct mlx4_eq *eq; 2826 int off = 0; 2827 int i; 2828 2829 if (eqn > dev->caps.num_comp_vectors) 2830 return -EINVAL; 2831 2832 for (i = 1; i < port; i++) 2833 off += mlx4_get_eqs_per_port(dev, i); 2834 2835 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2836 2837 /* Meaning EQs are shared, and this call comes from the second port */ 2838 if (requested_cpu < 0) 2839 return 0; 2840 2841 eq = &priv->eq_table.eq[eqn]; 2842 2843 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2844 return -ENOMEM; 2845 2846 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2847 2848 return 0; 2849 } 2850 2851 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2852 { 2853 struct mlx4_priv *priv = mlx4_priv(dev); 2854 struct msix_entry *entries; 2855 int i; 2856 int port = 0; 2857 2858 if (msi_x) { 2859 int nreq = dev->caps.num_ports * num_online_cpus() + 1; 2860 2861 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2862 nreq); 2863 if (nreq > MAX_MSIX) 2864 nreq = MAX_MSIX; 2865 2866 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2867 if (!entries) 2868 goto no_msi; 2869 2870 for (i = 0; i < nreq; ++i) 2871 entries[i].entry = i; 2872 2873 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2874 nreq); 2875 2876 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2877 kfree(entries); 2878 goto no_msi; 2879 } 2880 /* 1 is reserved for events (asyncrounous EQ) */ 2881 dev->caps.num_comp_vectors = nreq - 1; 2882 2883 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2884 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2885 dev->caps.num_ports); 2886 2887 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2888 if (i == MLX4_EQ_ASYNC) 2889 continue; 2890 2891 priv->eq_table.eq[i].irq = 2892 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2893 2894 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2895 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2896 dev->caps.num_ports); 2897 /* We don't set affinity hint when there 2898 * aren't enough EQs 2899 */ 2900 } else { 2901 set_bit(port, 2902 priv->eq_table.eq[i].actv_ports.ports); 2903 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2904 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2905 i); 2906 } 2907 /* We divide the Eqs evenly between the two ports. 2908 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2909 * refers to the number of Eqs per port 2910 * (i.e eqs_per_port). Theoretically, we would like to 2911 * write something like (i + 1) % eqs_per_port == 0. 2912 * However, since there's an asynchronous Eq, we have 2913 * to skip over it by comparing this condition to 2914 * !!((i + 1) > MLX4_EQ_ASYNC). 2915 */ 2916 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2917 ((i + 1) % 2918 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 2919 !!((i + 1) > MLX4_EQ_ASYNC)) 2920 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 2921 * everything is shared anyway. 2922 */ 2923 port++; 2924 } 2925 2926 dev->flags |= MLX4_FLAG_MSI_X; 2927 2928 kfree(entries); 2929 return; 2930 } 2931 2932 no_msi: 2933 dev->caps.num_comp_vectors = 1; 2934 2935 BUG_ON(MLX4_EQ_ASYNC >= 2); 2936 for (i = 0; i < 2; ++i) { 2937 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 2938 if (i != MLX4_EQ_ASYNC) { 2939 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2940 dev->caps.num_ports); 2941 } 2942 } 2943 } 2944 2945 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2946 { 2947 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 2948 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2949 int err; 2950 2951 err = devlink_port_register(devlink, &info->devlink_port, port); 2952 if (err) 2953 return err; 2954 2955 info->dev = dev; 2956 info->port = port; 2957 if (!mlx4_is_slave(dev)) { 2958 mlx4_init_mac_table(dev, &info->mac_table); 2959 mlx4_init_vlan_table(dev, &info->vlan_table); 2960 mlx4_init_roce_gid_table(dev, &info->gid_table); 2961 info->base_qpn = mlx4_get_base_qpn(dev, port); 2962 } 2963 2964 sprintf(info->dev_name, "mlx4_port%d", port); 2965 info->port_attr.attr.name = info->dev_name; 2966 if (mlx4_is_mfunc(dev)) 2967 info->port_attr.attr.mode = S_IRUGO; 2968 else { 2969 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2970 info->port_attr.store = set_port_type; 2971 } 2972 info->port_attr.show = show_port_type; 2973 sysfs_attr_init(&info->port_attr.attr); 2974 2975 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 2976 if (err) { 2977 mlx4_err(dev, "Failed to create file for port %d\n", port); 2978 devlink_port_unregister(&info->devlink_port); 2979 info->port = -1; 2980 } 2981 2982 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2983 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2984 if (mlx4_is_mfunc(dev)) 2985 info->port_mtu_attr.attr.mode = S_IRUGO; 2986 else { 2987 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2988 info->port_mtu_attr.store = set_port_ib_mtu; 2989 } 2990 info->port_mtu_attr.show = show_port_ib_mtu; 2991 sysfs_attr_init(&info->port_mtu_attr.attr); 2992 2993 err = device_create_file(&dev->persist->pdev->dev, 2994 &info->port_mtu_attr); 2995 if (err) { 2996 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2997 device_remove_file(&info->dev->persist->pdev->dev, 2998 &info->port_attr); 2999 devlink_port_unregister(&info->devlink_port); 3000 info->port = -1; 3001 } 3002 3003 return err; 3004 } 3005 3006 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3007 { 3008 if (info->port < 0) 3009 return; 3010 3011 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3012 device_remove_file(&info->dev->persist->pdev->dev, 3013 &info->port_mtu_attr); 3014 devlink_port_unregister(&info->devlink_port); 3015 3016 #ifdef CONFIG_RFS_ACCEL 3017 free_irq_cpu_rmap(info->rmap); 3018 info->rmap = NULL; 3019 #endif 3020 } 3021 3022 static int mlx4_init_steering(struct mlx4_dev *dev) 3023 { 3024 struct mlx4_priv *priv = mlx4_priv(dev); 3025 int num_entries = dev->caps.num_ports; 3026 int i, j; 3027 3028 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 3029 if (!priv->steer) 3030 return -ENOMEM; 3031 3032 for (i = 0; i < num_entries; i++) 3033 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3034 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3035 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3036 } 3037 return 0; 3038 } 3039 3040 static void mlx4_clear_steering(struct mlx4_dev *dev) 3041 { 3042 struct mlx4_priv *priv = mlx4_priv(dev); 3043 struct mlx4_steer_index *entry, *tmp_entry; 3044 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3045 int num_entries = dev->caps.num_ports; 3046 int i, j; 3047 3048 for (i = 0; i < num_entries; i++) { 3049 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3050 list_for_each_entry_safe(pqp, tmp_pqp, 3051 &priv->steer[i].promisc_qps[j], 3052 list) { 3053 list_del(&pqp->list); 3054 kfree(pqp); 3055 } 3056 list_for_each_entry_safe(entry, tmp_entry, 3057 &priv->steer[i].steer_entries[j], 3058 list) { 3059 list_del(&entry->list); 3060 list_for_each_entry_safe(pqp, tmp_pqp, 3061 &entry->duplicates, 3062 list) { 3063 list_del(&pqp->list); 3064 kfree(pqp); 3065 } 3066 kfree(entry); 3067 } 3068 } 3069 } 3070 kfree(priv->steer); 3071 } 3072 3073 static int extended_func_num(struct pci_dev *pdev) 3074 { 3075 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3076 } 3077 3078 #define MLX4_OWNER_BASE 0x8069c 3079 #define MLX4_OWNER_SIZE 4 3080 3081 static int mlx4_get_ownership(struct mlx4_dev *dev) 3082 { 3083 void __iomem *owner; 3084 u32 ret; 3085 3086 if (pci_channel_offline(dev->persist->pdev)) 3087 return -EIO; 3088 3089 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3090 MLX4_OWNER_BASE, 3091 MLX4_OWNER_SIZE); 3092 if (!owner) { 3093 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3094 return -ENOMEM; 3095 } 3096 3097 ret = readl(owner); 3098 iounmap(owner); 3099 return (int) !!ret; 3100 } 3101 3102 static void mlx4_free_ownership(struct mlx4_dev *dev) 3103 { 3104 void __iomem *owner; 3105 3106 if (pci_channel_offline(dev->persist->pdev)) 3107 return; 3108 3109 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3110 MLX4_OWNER_BASE, 3111 MLX4_OWNER_SIZE); 3112 if (!owner) { 3113 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3114 return; 3115 } 3116 writel(0, owner); 3117 msleep(1000); 3118 iounmap(owner); 3119 } 3120 3121 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3122 !!((flags) & MLX4_FLAG_MASTER)) 3123 3124 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3125 u8 total_vfs, int existing_vfs, int reset_flow) 3126 { 3127 u64 dev_flags = dev->flags; 3128 int err = 0; 3129 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3130 MLX4_MAX_NUM_VF); 3131 3132 if (reset_flow) { 3133 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3134 GFP_KERNEL); 3135 if (!dev->dev_vfs) 3136 goto free_mem; 3137 return dev_flags; 3138 } 3139 3140 atomic_inc(&pf_loading); 3141 if (dev->flags & MLX4_FLAG_SRIOV) { 3142 if (existing_vfs != total_vfs) { 3143 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3144 existing_vfs, total_vfs); 3145 total_vfs = existing_vfs; 3146 } 3147 } 3148 3149 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL); 3150 if (NULL == dev->dev_vfs) { 3151 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3152 goto disable_sriov; 3153 } 3154 3155 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3156 if (total_vfs > fw_enabled_sriov_vfs) { 3157 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3158 total_vfs, fw_enabled_sriov_vfs); 3159 err = -ENOMEM; 3160 goto disable_sriov; 3161 } 3162 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3163 err = pci_enable_sriov(pdev, total_vfs); 3164 } 3165 if (err) { 3166 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3167 err); 3168 goto disable_sriov; 3169 } else { 3170 mlx4_warn(dev, "Running in master mode\n"); 3171 dev_flags |= MLX4_FLAG_SRIOV | 3172 MLX4_FLAG_MASTER; 3173 dev_flags &= ~MLX4_FLAG_SLAVE; 3174 dev->persist->num_vfs = total_vfs; 3175 } 3176 return dev_flags; 3177 3178 disable_sriov: 3179 atomic_dec(&pf_loading); 3180 free_mem: 3181 dev->persist->num_vfs = 0; 3182 kfree(dev->dev_vfs); 3183 dev->dev_vfs = NULL; 3184 return dev_flags & ~MLX4_FLAG_MASTER; 3185 } 3186 3187 enum { 3188 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3189 }; 3190 3191 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3192 int *nvfs) 3193 { 3194 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3195 /* Checking for 64 VFs as a limitation of CX2 */ 3196 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3197 requested_vfs >= 64) { 3198 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3199 requested_vfs); 3200 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3201 } 3202 return 0; 3203 } 3204 3205 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3206 { 3207 struct pci_dev *pdev = dev->persist->pdev; 3208 int err = 0; 3209 3210 mutex_lock(&dev->persist->pci_status_mutex); 3211 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3212 err = pci_enable_device(pdev); 3213 if (!err) 3214 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3215 } 3216 mutex_unlock(&dev->persist->pci_status_mutex); 3217 3218 return err; 3219 } 3220 3221 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3222 { 3223 struct pci_dev *pdev = dev->persist->pdev; 3224 3225 mutex_lock(&dev->persist->pci_status_mutex); 3226 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3227 pci_disable_device(pdev); 3228 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3229 } 3230 mutex_unlock(&dev->persist->pci_status_mutex); 3231 } 3232 3233 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3234 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3235 int reset_flow) 3236 { 3237 struct mlx4_dev *dev; 3238 unsigned sum = 0; 3239 int err; 3240 int port; 3241 int i; 3242 struct mlx4_dev_cap *dev_cap = NULL; 3243 int existing_vfs = 0; 3244 3245 dev = &priv->dev; 3246 3247 INIT_LIST_HEAD(&priv->ctx_list); 3248 spin_lock_init(&priv->ctx_lock); 3249 3250 mutex_init(&priv->port_mutex); 3251 mutex_init(&priv->bond_mutex); 3252 3253 INIT_LIST_HEAD(&priv->pgdir_list); 3254 mutex_init(&priv->pgdir_mutex); 3255 spin_lock_init(&priv->cmd.context_lock); 3256 3257 INIT_LIST_HEAD(&priv->bf_list); 3258 mutex_init(&priv->bf_mutex); 3259 3260 dev->rev_id = pdev->revision; 3261 dev->numa_node = dev_to_node(&pdev->dev); 3262 3263 /* Detect if this device is a virtual function */ 3264 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3265 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3266 dev->flags |= MLX4_FLAG_SLAVE; 3267 } else { 3268 /* We reset the device and enable SRIOV only for physical 3269 * devices. Try to claim ownership on the device; 3270 * if already taken, skip -- do not allow multiple PFs */ 3271 err = mlx4_get_ownership(dev); 3272 if (err) { 3273 if (err < 0) 3274 return err; 3275 else { 3276 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3277 return -EINVAL; 3278 } 3279 } 3280 3281 atomic_set(&priv->opreq_count, 0); 3282 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3283 3284 /* 3285 * Now reset the HCA before we touch the PCI capabilities or 3286 * attempt a firmware command, since a boot ROM may have left 3287 * the HCA in an undefined state. 3288 */ 3289 err = mlx4_reset(dev); 3290 if (err) { 3291 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3292 goto err_sriov; 3293 } 3294 3295 if (total_vfs) { 3296 dev->flags = MLX4_FLAG_MASTER; 3297 existing_vfs = pci_num_vf(pdev); 3298 if (existing_vfs) 3299 dev->flags |= MLX4_FLAG_SRIOV; 3300 dev->persist->num_vfs = total_vfs; 3301 } 3302 } 3303 3304 /* on load remove any previous indication of internal error, 3305 * device is up. 3306 */ 3307 dev->persist->state = MLX4_DEVICE_STATE_UP; 3308 3309 slave_start: 3310 err = mlx4_cmd_init(dev); 3311 if (err) { 3312 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3313 goto err_sriov; 3314 } 3315 3316 /* In slave functions, the communication channel must be initialized 3317 * before posting commands. Also, init num_slaves before calling 3318 * mlx4_init_hca */ 3319 if (mlx4_is_mfunc(dev)) { 3320 if (mlx4_is_master(dev)) { 3321 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3322 3323 } else { 3324 dev->num_slaves = 0; 3325 err = mlx4_multi_func_init(dev); 3326 if (err) { 3327 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3328 goto err_cmd; 3329 } 3330 } 3331 } 3332 3333 err = mlx4_init_fw(dev); 3334 if (err) { 3335 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3336 goto err_mfunc; 3337 } 3338 3339 if (mlx4_is_master(dev)) { 3340 /* when we hit the goto slave_start below, dev_cap already initialized */ 3341 if (!dev_cap) { 3342 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3343 3344 if (!dev_cap) { 3345 err = -ENOMEM; 3346 goto err_fw; 3347 } 3348 3349 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3350 if (err) { 3351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3352 goto err_fw; 3353 } 3354 3355 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3356 goto err_fw; 3357 3358 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3359 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3360 total_vfs, 3361 existing_vfs, 3362 reset_flow); 3363 3364 mlx4_close_fw(dev); 3365 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3366 dev->flags = dev_flags; 3367 if (!SRIOV_VALID_STATE(dev->flags)) { 3368 mlx4_err(dev, "Invalid SRIOV state\n"); 3369 goto err_sriov; 3370 } 3371 err = mlx4_reset(dev); 3372 if (err) { 3373 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3374 goto err_sriov; 3375 } 3376 goto slave_start; 3377 } 3378 } else { 3379 /* Legacy mode FW requires SRIOV to be enabled before 3380 * doing QUERY_DEV_CAP, since max_eq's value is different if 3381 * SRIOV is enabled. 3382 */ 3383 memset(dev_cap, 0, sizeof(*dev_cap)); 3384 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3385 if (err) { 3386 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3387 goto err_fw; 3388 } 3389 3390 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3391 goto err_fw; 3392 } 3393 } 3394 3395 err = mlx4_init_hca(dev); 3396 if (err) { 3397 if (err == -EACCES) { 3398 /* Not primary Physical function 3399 * Running in slave mode */ 3400 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3401 /* We're not a PF */ 3402 if (dev->flags & MLX4_FLAG_SRIOV) { 3403 if (!existing_vfs) 3404 pci_disable_sriov(pdev); 3405 if (mlx4_is_master(dev) && !reset_flow) 3406 atomic_dec(&pf_loading); 3407 dev->flags &= ~MLX4_FLAG_SRIOV; 3408 } 3409 if (!mlx4_is_slave(dev)) 3410 mlx4_free_ownership(dev); 3411 dev->flags |= MLX4_FLAG_SLAVE; 3412 dev->flags &= ~MLX4_FLAG_MASTER; 3413 goto slave_start; 3414 } else 3415 goto err_fw; 3416 } 3417 3418 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3419 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3420 existing_vfs, reset_flow); 3421 3422 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3423 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3424 dev->flags = dev_flags; 3425 err = mlx4_cmd_init(dev); 3426 if (err) { 3427 /* Only VHCR is cleaned up, so could still 3428 * send FW commands 3429 */ 3430 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3431 goto err_close; 3432 } 3433 } else { 3434 dev->flags = dev_flags; 3435 } 3436 3437 if (!SRIOV_VALID_STATE(dev->flags)) { 3438 mlx4_err(dev, "Invalid SRIOV state\n"); 3439 goto err_close; 3440 } 3441 } 3442 3443 /* check if the device is functioning at its maximum possible speed. 3444 * No return code for this call, just warn the user in case of PCI 3445 * express device capabilities are under-satisfied by the bus. 3446 */ 3447 if (!mlx4_is_slave(dev)) 3448 mlx4_check_pcie_caps(dev); 3449 3450 /* In master functions, the communication channel must be initialized 3451 * after obtaining its address from fw */ 3452 if (mlx4_is_master(dev)) { 3453 if (dev->caps.num_ports < 2 && 3454 num_vfs_argc > 1) { 3455 err = -EINVAL; 3456 mlx4_err(dev, 3457 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3458 dev->caps.num_ports); 3459 goto err_close; 3460 } 3461 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3462 3463 for (i = 0; 3464 i < sizeof(dev->persist->nvfs)/ 3465 sizeof(dev->persist->nvfs[0]); i++) { 3466 unsigned j; 3467 3468 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3469 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3470 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3471 dev->caps.num_ports; 3472 } 3473 } 3474 3475 /* In master functions, the communication channel 3476 * must be initialized after obtaining its address from fw 3477 */ 3478 err = mlx4_multi_func_init(dev); 3479 if (err) { 3480 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3481 goto err_close; 3482 } 3483 } 3484 3485 err = mlx4_alloc_eq_table(dev); 3486 if (err) 3487 goto err_master_mfunc; 3488 3489 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3490 mutex_init(&priv->msix_ctl.pool_lock); 3491 3492 mlx4_enable_msi_x(dev); 3493 if ((mlx4_is_mfunc(dev)) && 3494 !(dev->flags & MLX4_FLAG_MSI_X)) { 3495 err = -ENOSYS; 3496 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3497 goto err_free_eq; 3498 } 3499 3500 if (!mlx4_is_slave(dev)) { 3501 err = mlx4_init_steering(dev); 3502 if (err) 3503 goto err_disable_msix; 3504 } 3505 3506 err = mlx4_setup_hca(dev); 3507 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3508 !mlx4_is_mfunc(dev)) { 3509 dev->flags &= ~MLX4_FLAG_MSI_X; 3510 dev->caps.num_comp_vectors = 1; 3511 pci_disable_msix(pdev); 3512 err = mlx4_setup_hca(dev); 3513 } 3514 3515 if (err) 3516 goto err_steer; 3517 3518 mlx4_init_quotas(dev); 3519 /* When PF resources are ready arm its comm channel to enable 3520 * getting commands 3521 */ 3522 if (mlx4_is_master(dev)) { 3523 err = mlx4_ARM_COMM_CHANNEL(dev); 3524 if (err) { 3525 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3526 err); 3527 goto err_steer; 3528 } 3529 } 3530 3531 for (port = 1; port <= dev->caps.num_ports; port++) { 3532 err = mlx4_init_port_info(dev, port); 3533 if (err) 3534 goto err_port; 3535 } 3536 3537 priv->v2p.port1 = 1; 3538 priv->v2p.port2 = 2; 3539 3540 err = mlx4_register_device(dev); 3541 if (err) 3542 goto err_port; 3543 3544 mlx4_request_modules(dev); 3545 3546 mlx4_sense_init(dev); 3547 mlx4_start_sense(dev); 3548 3549 priv->removed = 0; 3550 3551 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3552 atomic_dec(&pf_loading); 3553 3554 kfree(dev_cap); 3555 return 0; 3556 3557 err_port: 3558 for (--port; port >= 1; --port) 3559 mlx4_cleanup_port_info(&priv->port[port]); 3560 3561 mlx4_cleanup_default_counters(dev); 3562 if (!mlx4_is_slave(dev)) 3563 mlx4_cleanup_counters_table(dev); 3564 mlx4_cleanup_qp_table(dev); 3565 mlx4_cleanup_srq_table(dev); 3566 mlx4_cleanup_cq_table(dev); 3567 mlx4_cmd_use_polling(dev); 3568 mlx4_cleanup_eq_table(dev); 3569 mlx4_cleanup_mcg_table(dev); 3570 mlx4_cleanup_mr_table(dev); 3571 mlx4_cleanup_xrcd_table(dev); 3572 mlx4_cleanup_pd_table(dev); 3573 mlx4_cleanup_uar_table(dev); 3574 3575 err_steer: 3576 if (!mlx4_is_slave(dev)) 3577 mlx4_clear_steering(dev); 3578 3579 err_disable_msix: 3580 if (dev->flags & MLX4_FLAG_MSI_X) 3581 pci_disable_msix(pdev); 3582 3583 err_free_eq: 3584 mlx4_free_eq_table(dev); 3585 3586 err_master_mfunc: 3587 if (mlx4_is_master(dev)) { 3588 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3589 mlx4_multi_func_cleanup(dev); 3590 } 3591 3592 if (mlx4_is_slave(dev)) { 3593 kfree(dev->caps.qp0_qkey); 3594 kfree(dev->caps.qp0_tunnel); 3595 kfree(dev->caps.qp0_proxy); 3596 kfree(dev->caps.qp1_tunnel); 3597 kfree(dev->caps.qp1_proxy); 3598 } 3599 3600 err_close: 3601 mlx4_close_hca(dev); 3602 3603 err_fw: 3604 mlx4_close_fw(dev); 3605 3606 err_mfunc: 3607 if (mlx4_is_slave(dev)) 3608 mlx4_multi_func_cleanup(dev); 3609 3610 err_cmd: 3611 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3612 3613 err_sriov: 3614 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3615 pci_disable_sriov(pdev); 3616 dev->flags &= ~MLX4_FLAG_SRIOV; 3617 } 3618 3619 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3620 atomic_dec(&pf_loading); 3621 3622 kfree(priv->dev.dev_vfs); 3623 3624 if (!mlx4_is_slave(dev)) 3625 mlx4_free_ownership(dev); 3626 3627 kfree(dev_cap); 3628 return err; 3629 } 3630 3631 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3632 struct mlx4_priv *priv) 3633 { 3634 int err; 3635 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3636 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3637 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3638 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3639 unsigned total_vfs = 0; 3640 unsigned int i; 3641 3642 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3643 3644 err = mlx4_pci_enable_device(&priv->dev); 3645 if (err) { 3646 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3647 return err; 3648 } 3649 3650 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3651 * per port, we must limit the number of VFs to 63 (since their are 3652 * 128 MACs) 3653 */ 3654 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 3655 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3656 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3657 if (nvfs[i] < 0) { 3658 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3659 err = -EINVAL; 3660 goto err_disable_pdev; 3661 } 3662 } 3663 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 3664 i++) { 3665 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3666 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3667 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3668 err = -EINVAL; 3669 goto err_disable_pdev; 3670 } 3671 } 3672 if (total_vfs > MLX4_MAX_NUM_VF) { 3673 dev_err(&pdev->dev, 3674 "Requested more VF's (%d) than allowed by hw (%d)\n", 3675 total_vfs, MLX4_MAX_NUM_VF); 3676 err = -EINVAL; 3677 goto err_disable_pdev; 3678 } 3679 3680 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3681 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3682 dev_err(&pdev->dev, 3683 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3684 nvfs[i] + nvfs[2], i + 1, 3685 MLX4_MAX_NUM_VF_P_PORT); 3686 err = -EINVAL; 3687 goto err_disable_pdev; 3688 } 3689 } 3690 3691 /* Check for BARs. */ 3692 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3693 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3694 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3695 pci_dev_data, pci_resource_flags(pdev, 0)); 3696 err = -ENODEV; 3697 goto err_disable_pdev; 3698 } 3699 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3700 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3701 err = -ENODEV; 3702 goto err_disable_pdev; 3703 } 3704 3705 err = pci_request_regions(pdev, DRV_NAME); 3706 if (err) { 3707 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3708 goto err_disable_pdev; 3709 } 3710 3711 pci_set_master(pdev); 3712 3713 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3714 if (err) { 3715 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3716 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3717 if (err) { 3718 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3719 goto err_release_regions; 3720 } 3721 } 3722 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3723 if (err) { 3724 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3725 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3726 if (err) { 3727 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3728 goto err_release_regions; 3729 } 3730 } 3731 3732 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3733 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3734 /* Detect if this device is a virtual function */ 3735 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3736 /* When acting as pf, we normally skip vfs unless explicitly 3737 * requested to probe them. 3738 */ 3739 if (total_vfs) { 3740 unsigned vfs_offset = 0; 3741 3742 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 3743 vfs_offset + nvfs[i] < extended_func_num(pdev); 3744 vfs_offset += nvfs[i], i++) 3745 ; 3746 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 3747 err = -ENODEV; 3748 goto err_release_regions; 3749 } 3750 if ((extended_func_num(pdev) - vfs_offset) 3751 > prb_vf[i]) { 3752 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3753 extended_func_num(pdev)); 3754 err = -ENODEV; 3755 goto err_release_regions; 3756 } 3757 } 3758 } 3759 3760 err = mlx4_catas_init(&priv->dev); 3761 if (err) 3762 goto err_release_regions; 3763 3764 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3765 if (err) 3766 goto err_catas; 3767 3768 return 0; 3769 3770 err_catas: 3771 mlx4_catas_end(&priv->dev); 3772 3773 err_release_regions: 3774 pci_release_regions(pdev); 3775 3776 err_disable_pdev: 3777 mlx4_pci_disable_device(&priv->dev); 3778 pci_set_drvdata(pdev, NULL); 3779 return err; 3780 } 3781 3782 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3783 enum devlink_port_type port_type) 3784 { 3785 struct mlx4_port_info *info = container_of(devlink_port, 3786 struct mlx4_port_info, 3787 devlink_port); 3788 enum mlx4_port_type mlx4_port_type; 3789 3790 switch (port_type) { 3791 case DEVLINK_PORT_TYPE_AUTO: 3792 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3793 break; 3794 case DEVLINK_PORT_TYPE_ETH: 3795 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3796 break; 3797 case DEVLINK_PORT_TYPE_IB: 3798 mlx4_port_type = MLX4_PORT_TYPE_IB; 3799 break; 3800 default: 3801 return -EOPNOTSUPP; 3802 } 3803 3804 return __set_port_type(info, mlx4_port_type); 3805 } 3806 3807 static const struct devlink_ops mlx4_devlink_ops = { 3808 .port_type_set = mlx4_devlink_port_type_set, 3809 }; 3810 3811 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3812 { 3813 struct devlink *devlink; 3814 struct mlx4_priv *priv; 3815 struct mlx4_dev *dev; 3816 int ret; 3817 3818 printk_once(KERN_INFO "%s", mlx4_version); 3819 3820 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3821 if (!devlink) 3822 return -ENOMEM; 3823 priv = devlink_priv(devlink); 3824 3825 dev = &priv->dev; 3826 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3827 if (!dev->persist) { 3828 ret = -ENOMEM; 3829 goto err_devlink_free; 3830 } 3831 dev->persist->pdev = pdev; 3832 dev->persist->dev = dev; 3833 pci_set_drvdata(pdev, dev->persist); 3834 priv->pci_dev_data = id->driver_data; 3835 mutex_init(&dev->persist->device_state_mutex); 3836 mutex_init(&dev->persist->interface_state_mutex); 3837 mutex_init(&dev->persist->pci_status_mutex); 3838 3839 ret = devlink_register(devlink, &pdev->dev); 3840 if (ret) 3841 goto err_persist_free; 3842 3843 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3844 if (ret) 3845 goto err_devlink_unregister; 3846 3847 pci_save_state(pdev); 3848 return 0; 3849 3850 err_devlink_unregister: 3851 devlink_unregister(devlink); 3852 err_persist_free: 3853 kfree(dev->persist); 3854 err_devlink_free: 3855 devlink_free(devlink); 3856 return ret; 3857 } 3858 3859 static void mlx4_clean_dev(struct mlx4_dev *dev) 3860 { 3861 struct mlx4_dev_persistent *persist = dev->persist; 3862 struct mlx4_priv *priv = mlx4_priv(dev); 3863 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 3864 3865 memset(priv, 0, sizeof(*priv)); 3866 priv->dev.persist = persist; 3867 priv->dev.flags = flags; 3868 } 3869 3870 static void mlx4_unload_one(struct pci_dev *pdev) 3871 { 3872 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3873 struct mlx4_dev *dev = persist->dev; 3874 struct mlx4_priv *priv = mlx4_priv(dev); 3875 int pci_dev_data; 3876 int p, i; 3877 3878 if (priv->removed) 3879 return; 3880 3881 /* saving current ports type for further use */ 3882 for (i = 0; i < dev->caps.num_ports; i++) { 3883 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 3884 dev->persist->curr_port_poss_type[i] = dev->caps. 3885 possible_type[i + 1]; 3886 } 3887 3888 pci_dev_data = priv->pci_dev_data; 3889 3890 mlx4_stop_sense(dev); 3891 mlx4_unregister_device(dev); 3892 3893 for (p = 1; p <= dev->caps.num_ports; p++) { 3894 mlx4_cleanup_port_info(&priv->port[p]); 3895 mlx4_CLOSE_PORT(dev, p); 3896 } 3897 3898 if (mlx4_is_master(dev)) 3899 mlx4_free_resource_tracker(dev, 3900 RES_TR_FREE_SLAVES_ONLY); 3901 3902 mlx4_cleanup_default_counters(dev); 3903 if (!mlx4_is_slave(dev)) 3904 mlx4_cleanup_counters_table(dev); 3905 mlx4_cleanup_qp_table(dev); 3906 mlx4_cleanup_srq_table(dev); 3907 mlx4_cleanup_cq_table(dev); 3908 mlx4_cmd_use_polling(dev); 3909 mlx4_cleanup_eq_table(dev); 3910 mlx4_cleanup_mcg_table(dev); 3911 mlx4_cleanup_mr_table(dev); 3912 mlx4_cleanup_xrcd_table(dev); 3913 mlx4_cleanup_pd_table(dev); 3914 3915 if (mlx4_is_master(dev)) 3916 mlx4_free_resource_tracker(dev, 3917 RES_TR_FREE_STRUCTS_ONLY); 3918 3919 iounmap(priv->kar); 3920 mlx4_uar_free(dev, &priv->driver_uar); 3921 mlx4_cleanup_uar_table(dev); 3922 if (!mlx4_is_slave(dev)) 3923 mlx4_clear_steering(dev); 3924 mlx4_free_eq_table(dev); 3925 if (mlx4_is_master(dev)) 3926 mlx4_multi_func_cleanup(dev); 3927 mlx4_close_hca(dev); 3928 mlx4_close_fw(dev); 3929 if (mlx4_is_slave(dev)) 3930 mlx4_multi_func_cleanup(dev); 3931 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3932 3933 if (dev->flags & MLX4_FLAG_MSI_X) 3934 pci_disable_msix(pdev); 3935 3936 if (!mlx4_is_slave(dev)) 3937 mlx4_free_ownership(dev); 3938 3939 kfree(dev->caps.qp0_qkey); 3940 kfree(dev->caps.qp0_tunnel); 3941 kfree(dev->caps.qp0_proxy); 3942 kfree(dev->caps.qp1_tunnel); 3943 kfree(dev->caps.qp1_proxy); 3944 kfree(dev->dev_vfs); 3945 3946 mlx4_clean_dev(dev); 3947 priv->pci_dev_data = pci_dev_data; 3948 priv->removed = 1; 3949 } 3950 3951 static void mlx4_remove_one(struct pci_dev *pdev) 3952 { 3953 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3954 struct mlx4_dev *dev = persist->dev; 3955 struct mlx4_priv *priv = mlx4_priv(dev); 3956 struct devlink *devlink = priv_to_devlink(priv); 3957 int active_vfs = 0; 3958 3959 mutex_lock(&persist->interface_state_mutex); 3960 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 3961 mutex_unlock(&persist->interface_state_mutex); 3962 3963 /* Disabling SR-IOV is not allowed while there are active vf's */ 3964 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 3965 active_vfs = mlx4_how_many_lives_vf(dev); 3966 if (active_vfs) { 3967 pr_warn("Removing PF when there are active VF's !!\n"); 3968 pr_warn("Will not disable SR-IOV.\n"); 3969 } 3970 } 3971 3972 /* device marked to be under deletion running now without the lock 3973 * letting other tasks to be terminated 3974 */ 3975 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3976 mlx4_unload_one(pdev); 3977 else 3978 mlx4_info(dev, "%s: interface is down\n", __func__); 3979 mlx4_catas_end(dev); 3980 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 3981 mlx4_warn(dev, "Disabling SR-IOV\n"); 3982 pci_disable_sriov(pdev); 3983 } 3984 3985 pci_release_regions(pdev); 3986 mlx4_pci_disable_device(dev); 3987 devlink_unregister(devlink); 3988 kfree(dev->persist); 3989 devlink_free(devlink); 3990 pci_set_drvdata(pdev, NULL); 3991 } 3992 3993 static int restore_current_port_types(struct mlx4_dev *dev, 3994 enum mlx4_port_type *types, 3995 enum mlx4_port_type *poss_types) 3996 { 3997 struct mlx4_priv *priv = mlx4_priv(dev); 3998 int err, i; 3999 4000 mlx4_stop_sense(dev); 4001 4002 mutex_lock(&priv->port_mutex); 4003 for (i = 0; i < dev->caps.num_ports; i++) 4004 dev->caps.possible_type[i + 1] = poss_types[i]; 4005 err = mlx4_change_port_types(dev, types); 4006 mlx4_start_sense(dev); 4007 mutex_unlock(&priv->port_mutex); 4008 4009 return err; 4010 } 4011 4012 int mlx4_restart_one(struct pci_dev *pdev) 4013 { 4014 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4015 struct mlx4_dev *dev = persist->dev; 4016 struct mlx4_priv *priv = mlx4_priv(dev); 4017 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4018 int pci_dev_data, err, total_vfs; 4019 4020 pci_dev_data = priv->pci_dev_data; 4021 total_vfs = dev->persist->num_vfs; 4022 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4023 4024 mlx4_unload_one(pdev); 4025 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4026 if (err) { 4027 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4028 __func__, pci_name(pdev), err); 4029 return err; 4030 } 4031 4032 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4033 dev->persist->curr_port_poss_type); 4034 if (err) 4035 mlx4_err(dev, "could not restore original port types (%d)\n", 4036 err); 4037 4038 return err; 4039 } 4040 4041 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4042 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4043 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4044 4045 static const struct pci_device_id mlx4_pci_table[] = { 4046 /* MT25408 "Hermon" */ 4047 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4048 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4049 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4050 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4051 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4052 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4053 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4054 /* MT25458 ConnectX EN 10GBASE-T */ 4055 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4056 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4057 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4058 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4059 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4060 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4061 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4062 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4063 /* MT25400 Family [ConnectX-2] */ 4064 MLX_VF(0x1002), /* Virtual Function */ 4065 /* MT27500 Family [ConnectX-3] */ 4066 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4067 MLX_VF(0x1004), /* Virtual Function */ 4068 MLX_GN(0x1005), /* MT27510 Family */ 4069 MLX_GN(0x1006), /* MT27511 Family */ 4070 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4071 MLX_GN(0x1008), /* MT27521 Family */ 4072 MLX_GN(0x1009), /* MT27530 Family */ 4073 MLX_GN(0x100a), /* MT27531 Family */ 4074 MLX_GN(0x100b), /* MT27540 Family */ 4075 MLX_GN(0x100c), /* MT27541 Family */ 4076 MLX_GN(0x100d), /* MT27550 Family */ 4077 MLX_GN(0x100e), /* MT27551 Family */ 4078 MLX_GN(0x100f), /* MT27560 Family */ 4079 MLX_GN(0x1010), /* MT27561 Family */ 4080 4081 /* 4082 * See the mellanox_check_broken_intx_masking() quirk when 4083 * adding devices 4084 */ 4085 4086 { 0, } 4087 }; 4088 4089 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4090 4091 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4092 pci_channel_state_t state) 4093 { 4094 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4095 4096 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4097 mlx4_enter_error_state(persist); 4098 4099 mutex_lock(&persist->interface_state_mutex); 4100 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4101 mlx4_unload_one(pdev); 4102 4103 mutex_unlock(&persist->interface_state_mutex); 4104 if (state == pci_channel_io_perm_failure) 4105 return PCI_ERS_RESULT_DISCONNECT; 4106 4107 mlx4_pci_disable_device(persist->dev); 4108 return PCI_ERS_RESULT_NEED_RESET; 4109 } 4110 4111 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4112 { 4113 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4114 struct mlx4_dev *dev = persist->dev; 4115 int err; 4116 4117 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4118 err = mlx4_pci_enable_device(dev); 4119 if (err) { 4120 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4121 return PCI_ERS_RESULT_DISCONNECT; 4122 } 4123 4124 pci_set_master(pdev); 4125 pci_restore_state(pdev); 4126 pci_save_state(pdev); 4127 return PCI_ERS_RESULT_RECOVERED; 4128 } 4129 4130 static void mlx4_pci_resume(struct pci_dev *pdev) 4131 { 4132 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4133 struct mlx4_dev *dev = persist->dev; 4134 struct mlx4_priv *priv = mlx4_priv(dev); 4135 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4136 int total_vfs; 4137 int err; 4138 4139 mlx4_err(dev, "%s was called\n", __func__); 4140 total_vfs = dev->persist->num_vfs; 4141 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4142 4143 mutex_lock(&persist->interface_state_mutex); 4144 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4145 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4146 priv, 1); 4147 if (err) { 4148 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4149 __func__, err); 4150 goto end; 4151 } 4152 4153 err = restore_current_port_types(dev, dev->persist-> 4154 curr_port_type, dev->persist-> 4155 curr_port_poss_type); 4156 if (err) 4157 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4158 } 4159 end: 4160 mutex_unlock(&persist->interface_state_mutex); 4161 4162 } 4163 4164 static void mlx4_shutdown(struct pci_dev *pdev) 4165 { 4166 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4167 4168 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4169 mutex_lock(&persist->interface_state_mutex); 4170 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4171 mlx4_unload_one(pdev); 4172 mutex_unlock(&persist->interface_state_mutex); 4173 } 4174 4175 static const struct pci_error_handlers mlx4_err_handler = { 4176 .error_detected = mlx4_pci_err_detected, 4177 .slot_reset = mlx4_pci_slot_reset, 4178 .resume = mlx4_pci_resume, 4179 }; 4180 4181 static struct pci_driver mlx4_driver = { 4182 .name = DRV_NAME, 4183 .id_table = mlx4_pci_table, 4184 .probe = mlx4_init_one, 4185 .shutdown = mlx4_shutdown, 4186 .remove = mlx4_remove_one, 4187 .err_handler = &mlx4_err_handler, 4188 }; 4189 4190 static int __init mlx4_verify_params(void) 4191 { 4192 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4193 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4194 return -1; 4195 } 4196 4197 if (log_num_vlan != 0) 4198 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4199 MLX4_LOG_NUM_VLANS); 4200 4201 if (use_prio != 0) 4202 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4203 4204 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 4205 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4206 log_mtts_per_seg); 4207 return -1; 4208 } 4209 4210 /* Check if module param for ports type has legal combination */ 4211 if (port_type_array[0] == false && port_type_array[1] == true) { 4212 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4213 port_type_array[0] = true; 4214 } 4215 4216 if (mlx4_log_num_mgm_entry_size < -7 || 4217 (mlx4_log_num_mgm_entry_size > 0 && 4218 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4219 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4220 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4221 mlx4_log_num_mgm_entry_size, 4222 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4223 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4224 return -1; 4225 } 4226 4227 return 0; 4228 } 4229 4230 static int __init mlx4_init(void) 4231 { 4232 int ret; 4233 4234 if (mlx4_verify_params()) 4235 return -EINVAL; 4236 4237 4238 mlx4_wq = create_singlethread_workqueue("mlx4"); 4239 if (!mlx4_wq) 4240 return -ENOMEM; 4241 4242 ret = pci_register_driver(&mlx4_driver); 4243 if (ret < 0) 4244 destroy_workqueue(mlx4_wq); 4245 return ret < 0 ? ret : 0; 4246 } 4247 4248 static void __exit mlx4_cleanup(void) 4249 { 4250 pci_unregister_driver(&mlx4_driver); 4251 destroy_workqueue(mlx4_wq); 4252 } 4253 4254 module_init(mlx4_init); 4255 module_exit(mlx4_cleanup); 4256