1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static uint8_t num_vfs[3] = {0, 0, 0}; 81 static int num_vfs_argc; 82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 84 "num_vfs=port1,port2,port1+2"); 85 86 static uint8_t probe_vf[3] = {0, 0, 0}; 87 static int probe_vfs_argc; 88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 90 "probe_vf=port1,port2,port1+2"); 91 92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 93 module_param_named(log_num_mgm_entry_size, 94 mlx4_log_num_mgm_entry_size, int, 0444); 95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 96 " of qp per mcg, for example:" 97 " 10 gives 248.range: 7 <=" 98 " log_num_mgm_entry_size <= 12." 99 " To activate device managed" 100 " flow steering when available, set to -1"); 101 102 static bool enable_64b_cqe_eqe = true; 103 module_param(enable_64b_cqe_eqe, bool, 0444); 104 MODULE_PARM_DESC(enable_64b_cqe_eqe, 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 106 107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 109 MLX4_FUNC_CAP_DMFS_A0_STATIC) 110 111 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 112 113 static char mlx4_version[] = 114 DRV_NAME ": Mellanox ConnectX core driver v" 115 DRV_VERSION " (" DRV_RELDATE ")\n"; 116 117 static struct mlx4_profile default_profile = { 118 .num_qp = 1 << 18, 119 .num_srq = 1 << 16, 120 .rdmarc_per_qp = 1 << 4, 121 .num_cq = 1 << 16, 122 .num_mcg = 1 << 13, 123 .num_mpt = 1 << 19, 124 .num_mtt = 1 << 20, /* It is really num mtt segements */ 125 }; 126 127 static struct mlx4_profile low_mem_profile = { 128 .num_qp = 1 << 17, 129 .num_srq = 1 << 6, 130 .rdmarc_per_qp = 1 << 4, 131 .num_cq = 1 << 8, 132 .num_mcg = 1 << 8, 133 .num_mpt = 1 << 9, 134 .num_mtt = 1 << 7, 135 }; 136 137 static int log_num_mac = 7; 138 module_param_named(log_num_mac, log_num_mac, int, 0444); 139 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 140 141 static int log_num_vlan; 142 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 143 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 144 /* Log2 max number of VLANs per ETH port (0-7) */ 145 #define MLX4_LOG_NUM_VLANS 7 146 #define MLX4_MIN_LOG_NUM_VLANS 0 147 #define MLX4_MIN_LOG_NUM_MAC 1 148 149 static bool use_prio; 150 module_param_named(use_prio, use_prio, bool, 0444); 151 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 152 153 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 154 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 155 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 156 157 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 158 static int arr_argc = 2; 159 module_param_array(port_type_array, int, &arr_argc, 0444); 160 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 161 "1 for IB, 2 for Ethernet"); 162 163 struct mlx4_port_config { 164 struct list_head list; 165 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 166 struct pci_dev *pdev; 167 }; 168 169 static atomic_t pf_loading = ATOMIC_INIT(0); 170 171 int mlx4_check_port_params(struct mlx4_dev *dev, 172 enum mlx4_port_type *port_type) 173 { 174 int i; 175 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 177 for (i = 0; i < dev->caps.num_ports - 1; i++) { 178 if (port_type[i] != port_type[i + 1]) { 179 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 180 return -EINVAL; 181 } 182 } 183 } 184 185 for (i = 0; i < dev->caps.num_ports; i++) { 186 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 187 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 188 i + 1); 189 return -EINVAL; 190 } 191 } 192 return 0; 193 } 194 195 static void mlx4_set_port_mask(struct mlx4_dev *dev) 196 { 197 int i; 198 199 for (i = 1; i <= dev->caps.num_ports; ++i) 200 dev->caps.port_mask[i] = dev->caps.port_type[i]; 201 } 202 203 enum { 204 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 205 }; 206 207 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 208 { 209 int err = 0; 210 struct mlx4_func func; 211 212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 213 err = mlx4_QUERY_FUNC(dev, &func, 0); 214 if (err) { 215 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 216 return err; 217 } 218 dev_cap->max_eqs = func.max_eq; 219 dev_cap->reserved_eqs = func.rsvd_eqs; 220 dev_cap->reserved_uars = func.rsvd_uars; 221 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 222 } 223 return err; 224 } 225 226 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 227 { 228 struct mlx4_caps *dev_cap = &dev->caps; 229 230 /* FW not supporting or cancelled by user */ 231 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 232 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 233 return; 234 235 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 236 * When FW has NCSI it may decide not to report 64B CQE/EQEs 237 */ 238 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 239 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 240 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 241 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 242 return; 243 } 244 245 if (cache_line_size() == 128 || cache_line_size() == 256) { 246 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 247 /* Changing the real data inside CQE size to 32B */ 248 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 249 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 250 251 if (mlx4_is_master(dev)) 252 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 253 } else { 254 if (cache_line_size() != 32 && cache_line_size() != 64) 255 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 256 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 257 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 258 } 259 } 260 261 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 262 struct mlx4_port_cap *port_cap) 263 { 264 dev->caps.vl_cap[port] = port_cap->max_vl; 265 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 266 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 267 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 268 /* set gid and pkey table operating lengths by default 269 * to non-sriov values 270 */ 271 dev->caps.gid_table_len[port] = port_cap->max_gids; 272 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 273 dev->caps.port_width_cap[port] = port_cap->max_port_width; 274 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 275 dev->caps.def_mac[port] = port_cap->def_mac; 276 dev->caps.supported_type[port] = port_cap->supported_port_types; 277 dev->caps.suggested_type[port] = port_cap->suggested_type; 278 dev->caps.default_sense[port] = port_cap->default_sense; 279 dev->caps.trans_type[port] = port_cap->trans_type; 280 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 281 dev->caps.wavelength[port] = port_cap->wavelength; 282 dev->caps.trans_code[port] = port_cap->trans_code; 283 284 return 0; 285 } 286 287 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 288 struct mlx4_port_cap *port_cap) 289 { 290 int err = 0; 291 292 err = mlx4_QUERY_PORT(dev, port, port_cap); 293 294 if (err) 295 mlx4_err(dev, "QUERY_PORT command failed.\n"); 296 297 return err; 298 } 299 300 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 301 { 302 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 303 return; 304 305 if (mlx4_is_mfunc(dev)) { 306 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 307 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 308 return; 309 } 310 311 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 312 mlx4_dbg(dev, 313 "Keep FCS is not supported - Disabling Ignore FCS"); 314 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 315 return; 316 } 317 } 318 319 #define MLX4_A0_STEERING_TABLE_SIZE 256 320 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 321 { 322 int err; 323 int i; 324 325 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 326 if (err) { 327 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 328 return err; 329 } 330 mlx4_dev_cap_dump(dev, dev_cap); 331 332 if (dev_cap->min_page_sz > PAGE_SIZE) { 333 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 334 dev_cap->min_page_sz, PAGE_SIZE); 335 return -ENODEV; 336 } 337 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 338 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 339 dev_cap->num_ports, MLX4_MAX_PORTS); 340 return -ENODEV; 341 } 342 343 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 344 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 345 dev_cap->uar_size, 346 (unsigned long long) 347 pci_resource_len(dev->persist->pdev, 2)); 348 return -ENODEV; 349 } 350 351 dev->caps.num_ports = dev_cap->num_ports; 352 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 353 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 354 dev->caps.num_sys_eqs : 355 MLX4_MAX_EQ_NUM; 356 for (i = 1; i <= dev->caps.num_ports; ++i) { 357 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 358 if (err) { 359 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 360 return err; 361 } 362 } 363 364 dev->caps.uar_page_size = PAGE_SIZE; 365 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 366 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 367 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 368 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 369 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 370 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 371 dev->caps.max_wqes = dev_cap->max_qp_sz; 372 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 373 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 374 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 375 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 376 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 377 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 378 /* 379 * Subtract 1 from the limit because we need to allocate a 380 * spare CQE so the HCA HW can tell the difference between an 381 * empty CQ and a full CQ. 382 */ 383 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 384 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 385 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 386 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 387 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 388 389 /* The first 128 UARs are used for EQ doorbells */ 390 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 391 dev->caps.reserved_pds = dev_cap->reserved_pds; 392 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 393 dev_cap->reserved_xrcds : 0; 394 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 395 dev_cap->max_xrcds : 0; 396 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 397 398 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 399 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 400 dev->caps.flags = dev_cap->flags; 401 dev->caps.flags2 = dev_cap->flags2; 402 dev->caps.bmme_flags = dev_cap->bmme_flags; 403 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 404 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 405 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 406 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 407 408 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 409 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 410 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 411 /* Don't do sense port on multifunction devices (for now at least) */ 412 if (mlx4_is_mfunc(dev)) 413 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 414 415 if (mlx4_low_memory_profile()) { 416 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 417 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 418 } else { 419 dev->caps.log_num_macs = log_num_mac; 420 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 421 } 422 423 for (i = 1; i <= dev->caps.num_ports; ++i) { 424 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 425 if (dev->caps.supported_type[i]) { 426 /* if only ETH is supported - assign ETH */ 427 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 428 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 429 /* if only IB is supported, assign IB */ 430 else if (dev->caps.supported_type[i] == 431 MLX4_PORT_TYPE_IB) 432 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 433 else { 434 /* if IB and ETH are supported, we set the port 435 * type according to user selection of port type; 436 * if user selected none, take the FW hint */ 437 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 438 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 439 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 440 else 441 dev->caps.port_type[i] = port_type_array[i - 1]; 442 } 443 } 444 /* 445 * Link sensing is allowed on the port if 3 conditions are true: 446 * 1. Both protocols are supported on the port. 447 * 2. Different types are supported on the port 448 * 3. FW declared that it supports link sensing 449 */ 450 mlx4_priv(dev)->sense.sense_allowed[i] = 451 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 452 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 453 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 454 455 /* 456 * If "default_sense" bit is set, we move the port to "AUTO" mode 457 * and perform sense_port FW command to try and set the correct 458 * port type from beginning 459 */ 460 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 461 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 462 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 463 mlx4_SENSE_PORT(dev, i, &sensed_port); 464 if (sensed_port != MLX4_PORT_TYPE_NONE) 465 dev->caps.port_type[i] = sensed_port; 466 } else { 467 dev->caps.possible_type[i] = dev->caps.port_type[i]; 468 } 469 470 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 471 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 472 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 473 i, 1 << dev->caps.log_num_macs); 474 } 475 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 476 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 477 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 478 i, 1 << dev->caps.log_num_vlans); 479 } 480 } 481 482 dev->caps.max_counters = dev_cap->max_counters; 483 484 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 485 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 486 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 487 (1 << dev->caps.log_num_macs) * 488 (1 << dev->caps.log_num_vlans) * 489 dev->caps.num_ports; 490 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 491 492 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 493 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 494 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 495 else 496 dev->caps.dmfs_high_rate_qpn_base = 497 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 498 499 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 500 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 501 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 502 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 503 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 504 } else { 505 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 506 dev->caps.dmfs_high_rate_qpn_base = 507 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 508 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 509 } 510 511 dev->caps.rl_caps = dev_cap->rl_caps; 512 513 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 514 dev->caps.dmfs_high_rate_qpn_range; 515 516 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 517 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 518 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 519 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 520 521 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 522 523 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 524 if (dev_cap->flags & 525 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 526 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 527 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 528 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 529 } 530 531 if (dev_cap->flags2 & 532 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 533 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 534 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 535 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 536 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 537 } 538 } 539 540 if ((dev->caps.flags & 541 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 542 mlx4_is_master(dev)) 543 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 544 545 if (!mlx4_is_slave(dev)) { 546 mlx4_enable_cqe_eqe_stride(dev); 547 dev->caps.alloc_res_qp_mask = 548 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 549 MLX4_RESERVE_A0_QP; 550 551 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 552 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 553 mlx4_warn(dev, "Old device ETS support detected\n"); 554 mlx4_warn(dev, "Consider upgrading device FW.\n"); 555 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 556 } 557 558 } else { 559 dev->caps.alloc_res_qp_mask = 0; 560 } 561 562 mlx4_enable_ignore_fcs(dev); 563 564 return 0; 565 } 566 567 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 568 enum pci_bus_speed *speed, 569 enum pcie_link_width *width) 570 { 571 u32 lnkcap1, lnkcap2; 572 int err1, err2; 573 574 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 575 576 *speed = PCI_SPEED_UNKNOWN; 577 *width = PCIE_LNK_WIDTH_UNKNOWN; 578 579 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP, 580 &lnkcap1); 581 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2, 582 &lnkcap2); 583 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 584 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 585 *speed = PCIE_SPEED_8_0GT; 586 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 587 *speed = PCIE_SPEED_5_0GT; 588 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 589 *speed = PCIE_SPEED_2_5GT; 590 } 591 if (!err1) { 592 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 593 if (!lnkcap2) { /* pre-r3.0 */ 594 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 595 *speed = PCIE_SPEED_5_0GT; 596 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 597 *speed = PCIE_SPEED_2_5GT; 598 } 599 } 600 601 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 602 return err1 ? err1 : 603 err2 ? err2 : -EINVAL; 604 } 605 return 0; 606 } 607 608 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 609 { 610 enum pcie_link_width width, width_cap; 611 enum pci_bus_speed speed, speed_cap; 612 int err; 613 614 #define PCIE_SPEED_STR(speed) \ 615 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 616 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 617 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 618 "Unknown") 619 620 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 621 if (err) { 622 mlx4_warn(dev, 623 "Unable to determine PCIe device BW capabilities\n"); 624 return; 625 } 626 627 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width); 628 if (err || speed == PCI_SPEED_UNKNOWN || 629 width == PCIE_LNK_WIDTH_UNKNOWN) { 630 mlx4_warn(dev, 631 "Unable to determine PCI device chain minimum BW\n"); 632 return; 633 } 634 635 if (width != width_cap || speed != speed_cap) 636 mlx4_warn(dev, 637 "PCIe BW is different than device's capability\n"); 638 639 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 640 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 641 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 642 width, width_cap); 643 return; 644 } 645 646 /*The function checks if there are live vf, return the num of them*/ 647 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 648 { 649 struct mlx4_priv *priv = mlx4_priv(dev); 650 struct mlx4_slave_state *s_state; 651 int i; 652 int ret = 0; 653 654 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 655 s_state = &priv->mfunc.master.slave_state[i]; 656 if (s_state->active && s_state->last_cmd != 657 MLX4_COMM_CMD_RESET) { 658 mlx4_warn(dev, "%s: slave: %d is still active\n", 659 __func__, i); 660 ret++; 661 } 662 } 663 return ret; 664 } 665 666 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 667 { 668 u32 qk = MLX4_RESERVED_QKEY_BASE; 669 670 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 671 qpn < dev->phys_caps.base_proxy_sqpn) 672 return -EINVAL; 673 674 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 675 /* tunnel qp */ 676 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 677 else 678 qk += qpn - dev->phys_caps.base_proxy_sqpn; 679 *qkey = qk; 680 return 0; 681 } 682 EXPORT_SYMBOL(mlx4_get_parav_qkey); 683 684 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 685 { 686 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 687 688 if (!mlx4_is_master(dev)) 689 return; 690 691 priv->virt2phys_pkey[slave][port - 1][i] = val; 692 } 693 EXPORT_SYMBOL(mlx4_sync_pkey_table); 694 695 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 696 { 697 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 698 699 if (!mlx4_is_master(dev)) 700 return; 701 702 priv->slave_node_guids[slave] = guid; 703 } 704 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 705 706 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 707 { 708 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 709 710 if (!mlx4_is_master(dev)) 711 return 0; 712 713 return priv->slave_node_guids[slave]; 714 } 715 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 716 717 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 718 { 719 struct mlx4_priv *priv = mlx4_priv(dev); 720 struct mlx4_slave_state *s_slave; 721 722 if (!mlx4_is_master(dev)) 723 return 0; 724 725 s_slave = &priv->mfunc.master.slave_state[slave]; 726 return !!s_slave->active; 727 } 728 EXPORT_SYMBOL(mlx4_is_slave_active); 729 730 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 731 struct mlx4_dev_cap *dev_cap, 732 struct mlx4_init_hca_param *hca_param) 733 { 734 dev->caps.steering_mode = hca_param->steering_mode; 735 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 736 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 737 dev->caps.fs_log_max_ucast_qp_range_size = 738 dev_cap->fs_log_max_ucast_qp_range_size; 739 } else 740 dev->caps.num_qp_per_mgm = 741 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 742 743 mlx4_dbg(dev, "Steering mode is: %s\n", 744 mlx4_steering_mode_str(dev->caps.steering_mode)); 745 } 746 747 static int mlx4_slave_cap(struct mlx4_dev *dev) 748 { 749 int err; 750 u32 page_size; 751 struct mlx4_dev_cap dev_cap; 752 struct mlx4_func_cap func_cap; 753 struct mlx4_init_hca_param hca_param; 754 u8 i; 755 756 memset(&hca_param, 0, sizeof(hca_param)); 757 err = mlx4_QUERY_HCA(dev, &hca_param); 758 if (err) { 759 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 760 return err; 761 } 762 763 /* fail if the hca has an unknown global capability 764 * at this time global_caps should be always zeroed 765 */ 766 if (hca_param.global_caps) { 767 mlx4_err(dev, "Unknown hca global capabilities\n"); 768 return -ENOSYS; 769 } 770 771 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 772 773 dev->caps.hca_core_clock = hca_param.hca_core_clock; 774 775 memset(&dev_cap, 0, sizeof(dev_cap)); 776 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 777 err = mlx4_dev_cap(dev, &dev_cap); 778 if (err) { 779 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 780 return err; 781 } 782 783 err = mlx4_QUERY_FW(dev); 784 if (err) 785 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 786 787 page_size = ~dev->caps.page_size_cap + 1; 788 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 789 if (page_size > PAGE_SIZE) { 790 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 791 page_size, PAGE_SIZE); 792 return -ENODEV; 793 } 794 795 /* slave gets uar page size from QUERY_HCA fw command */ 796 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 797 798 /* TODO: relax this assumption */ 799 if (dev->caps.uar_page_size != PAGE_SIZE) { 800 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 801 dev->caps.uar_page_size, PAGE_SIZE); 802 return -ENODEV; 803 } 804 805 memset(&func_cap, 0, sizeof(func_cap)); 806 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 807 if (err) { 808 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 809 err); 810 return err; 811 } 812 813 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 814 PF_CONTEXT_BEHAVIOUR_MASK) { 815 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 816 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK); 817 return -ENOSYS; 818 } 819 820 dev->caps.num_ports = func_cap.num_ports; 821 dev->quotas.qp = func_cap.qp_quota; 822 dev->quotas.srq = func_cap.srq_quota; 823 dev->quotas.cq = func_cap.cq_quota; 824 dev->quotas.mpt = func_cap.mpt_quota; 825 dev->quotas.mtt = func_cap.mtt_quota; 826 dev->caps.num_qps = 1 << hca_param.log_num_qps; 827 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 828 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 829 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 830 dev->caps.num_eqs = func_cap.max_eq; 831 dev->caps.reserved_eqs = func_cap.reserved_eq; 832 dev->caps.reserved_lkey = func_cap.reserved_lkey; 833 dev->caps.num_pds = MLX4_NUM_PDS; 834 dev->caps.num_mgms = 0; 835 dev->caps.num_amgms = 0; 836 837 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 838 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 839 dev->caps.num_ports, MLX4_MAX_PORTS); 840 return -ENODEV; 841 } 842 843 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); 844 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 845 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 846 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 847 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 848 849 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 850 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || 851 !dev->caps.qp0_qkey) { 852 err = -ENOMEM; 853 goto err_mem; 854 } 855 856 for (i = 1; i <= dev->caps.num_ports; ++i) { 857 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap); 858 if (err) { 859 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 860 i, err); 861 goto err_mem; 862 } 863 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; 864 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 865 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 866 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 867 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 868 dev->caps.port_mask[i] = dev->caps.port_type[i]; 869 dev->caps.phys_port_id[i] = func_cap.phys_port_id; 870 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 871 &dev->caps.gid_table_len[i], 872 &dev->caps.pkey_table_len[i])) 873 goto err_mem; 874 } 875 876 if (dev->caps.uar_page_size * (dev->caps.num_uars - 877 dev->caps.reserved_uars) > 878 pci_resource_len(dev->persist->pdev, 879 2)) { 880 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 881 dev->caps.uar_page_size * dev->caps.num_uars, 882 (unsigned long long) 883 pci_resource_len(dev->persist->pdev, 2)); 884 goto err_mem; 885 } 886 887 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 888 dev->caps.eqe_size = 64; 889 dev->caps.eqe_factor = 1; 890 } else { 891 dev->caps.eqe_size = 32; 892 dev->caps.eqe_factor = 0; 893 } 894 895 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 896 dev->caps.cqe_size = 64; 897 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 898 } else { 899 dev->caps.cqe_size = 32; 900 } 901 902 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 903 dev->caps.eqe_size = hca_param.eqe_size; 904 dev->caps.eqe_factor = 0; 905 } 906 907 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 908 dev->caps.cqe_size = hca_param.cqe_size; 909 /* User still need to know when CQE > 32B */ 910 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 911 } 912 913 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 914 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 915 916 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 917 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 918 hca_param.rss_ip_frags ? "on" : "off"); 919 920 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 921 dev->caps.bf_reg_size) 922 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 923 924 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 925 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 926 927 return 0; 928 929 err_mem: 930 kfree(dev->caps.qp0_qkey); 931 kfree(dev->caps.qp0_tunnel); 932 kfree(dev->caps.qp0_proxy); 933 kfree(dev->caps.qp1_tunnel); 934 kfree(dev->caps.qp1_proxy); 935 dev->caps.qp0_qkey = NULL; 936 dev->caps.qp0_tunnel = NULL; 937 dev->caps.qp0_proxy = NULL; 938 dev->caps.qp1_tunnel = NULL; 939 dev->caps.qp1_proxy = NULL; 940 941 return err; 942 } 943 944 static void mlx4_request_modules(struct mlx4_dev *dev) 945 { 946 int port; 947 int has_ib_port = false; 948 int has_eth_port = false; 949 #define EN_DRV_NAME "mlx4_en" 950 #define IB_DRV_NAME "mlx4_ib" 951 952 for (port = 1; port <= dev->caps.num_ports; port++) { 953 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 954 has_ib_port = true; 955 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 956 has_eth_port = true; 957 } 958 959 if (has_eth_port) 960 request_module_nowait(EN_DRV_NAME); 961 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 962 request_module_nowait(IB_DRV_NAME); 963 } 964 965 /* 966 * Change the port configuration of the device. 967 * Every user of this function must hold the port mutex. 968 */ 969 int mlx4_change_port_types(struct mlx4_dev *dev, 970 enum mlx4_port_type *port_types) 971 { 972 int err = 0; 973 int change = 0; 974 int port; 975 976 for (port = 0; port < dev->caps.num_ports; port++) { 977 /* Change the port type only if the new type is different 978 * from the current, and not set to Auto */ 979 if (port_types[port] != dev->caps.port_type[port + 1]) 980 change = 1; 981 } 982 if (change) { 983 mlx4_unregister_device(dev); 984 for (port = 1; port <= dev->caps.num_ports; port++) { 985 mlx4_CLOSE_PORT(dev, port); 986 dev->caps.port_type[port] = port_types[port - 1]; 987 err = mlx4_SET_PORT(dev, port, -1); 988 if (err) { 989 mlx4_err(dev, "Failed to set port %d, aborting\n", 990 port); 991 goto out; 992 } 993 } 994 mlx4_set_port_mask(dev); 995 err = mlx4_register_device(dev); 996 if (err) { 997 mlx4_err(dev, "Failed to register device\n"); 998 goto out; 999 } 1000 mlx4_request_modules(dev); 1001 } 1002 1003 out: 1004 return err; 1005 } 1006 1007 static ssize_t show_port_type(struct device *dev, 1008 struct device_attribute *attr, 1009 char *buf) 1010 { 1011 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1012 port_attr); 1013 struct mlx4_dev *mdev = info->dev; 1014 char type[8]; 1015 1016 sprintf(type, "%s", 1017 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1018 "ib" : "eth"); 1019 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1020 sprintf(buf, "auto (%s)\n", type); 1021 else 1022 sprintf(buf, "%s\n", type); 1023 1024 return strlen(buf); 1025 } 1026 1027 static ssize_t set_port_type(struct device *dev, 1028 struct device_attribute *attr, 1029 const char *buf, size_t count) 1030 { 1031 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1032 port_attr); 1033 struct mlx4_dev *mdev = info->dev; 1034 struct mlx4_priv *priv = mlx4_priv(mdev); 1035 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1036 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1037 static DEFINE_MUTEX(set_port_type_mutex); 1038 int i; 1039 int err = 0; 1040 1041 mutex_lock(&set_port_type_mutex); 1042 1043 if (!strcmp(buf, "ib\n")) 1044 info->tmp_type = MLX4_PORT_TYPE_IB; 1045 else if (!strcmp(buf, "eth\n")) 1046 info->tmp_type = MLX4_PORT_TYPE_ETH; 1047 else if (!strcmp(buf, "auto\n")) 1048 info->tmp_type = MLX4_PORT_TYPE_AUTO; 1049 else { 1050 mlx4_err(mdev, "%s is not supported port type\n", buf); 1051 err = -EINVAL; 1052 goto err_out; 1053 } 1054 1055 mlx4_stop_sense(mdev); 1056 mutex_lock(&priv->port_mutex); 1057 /* Possible type is always the one that was delivered */ 1058 mdev->caps.possible_type[info->port] = info->tmp_type; 1059 1060 for (i = 0; i < mdev->caps.num_ports; i++) { 1061 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1062 mdev->caps.possible_type[i+1]; 1063 if (types[i] == MLX4_PORT_TYPE_AUTO) 1064 types[i] = mdev->caps.port_type[i+1]; 1065 } 1066 1067 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1068 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1069 for (i = 1; i <= mdev->caps.num_ports; i++) { 1070 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1071 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1072 err = -EINVAL; 1073 } 1074 } 1075 } 1076 if (err) { 1077 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1078 goto out; 1079 } 1080 1081 mlx4_do_sense_ports(mdev, new_types, types); 1082 1083 err = mlx4_check_port_params(mdev, new_types); 1084 if (err) 1085 goto out; 1086 1087 /* We are about to apply the changes after the configuration 1088 * was verified, no need to remember the temporary types 1089 * any more */ 1090 for (i = 0; i < mdev->caps.num_ports; i++) 1091 priv->port[i + 1].tmp_type = 0; 1092 1093 err = mlx4_change_port_types(mdev, new_types); 1094 1095 out: 1096 mlx4_start_sense(mdev); 1097 mutex_unlock(&priv->port_mutex); 1098 err_out: 1099 mutex_unlock(&set_port_type_mutex); 1100 1101 return err ? err : count; 1102 } 1103 1104 enum ibta_mtu { 1105 IB_MTU_256 = 1, 1106 IB_MTU_512 = 2, 1107 IB_MTU_1024 = 3, 1108 IB_MTU_2048 = 4, 1109 IB_MTU_4096 = 5 1110 }; 1111 1112 static inline int int_to_ibta_mtu(int mtu) 1113 { 1114 switch (mtu) { 1115 case 256: return IB_MTU_256; 1116 case 512: return IB_MTU_512; 1117 case 1024: return IB_MTU_1024; 1118 case 2048: return IB_MTU_2048; 1119 case 4096: return IB_MTU_4096; 1120 default: return -1; 1121 } 1122 } 1123 1124 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1125 { 1126 switch (mtu) { 1127 case IB_MTU_256: return 256; 1128 case IB_MTU_512: return 512; 1129 case IB_MTU_1024: return 1024; 1130 case IB_MTU_2048: return 2048; 1131 case IB_MTU_4096: return 4096; 1132 default: return -1; 1133 } 1134 } 1135 1136 static ssize_t show_port_ib_mtu(struct device *dev, 1137 struct device_attribute *attr, 1138 char *buf) 1139 { 1140 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1141 port_mtu_attr); 1142 struct mlx4_dev *mdev = info->dev; 1143 1144 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1145 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1146 1147 sprintf(buf, "%d\n", 1148 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1149 return strlen(buf); 1150 } 1151 1152 static ssize_t set_port_ib_mtu(struct device *dev, 1153 struct device_attribute *attr, 1154 const char *buf, size_t count) 1155 { 1156 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1157 port_mtu_attr); 1158 struct mlx4_dev *mdev = info->dev; 1159 struct mlx4_priv *priv = mlx4_priv(mdev); 1160 int err, port, mtu, ibta_mtu = -1; 1161 1162 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1163 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1164 return -EINVAL; 1165 } 1166 1167 err = kstrtoint(buf, 0, &mtu); 1168 if (!err) 1169 ibta_mtu = int_to_ibta_mtu(mtu); 1170 1171 if (err || ibta_mtu < 0) { 1172 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1173 return -EINVAL; 1174 } 1175 1176 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1177 1178 mlx4_stop_sense(mdev); 1179 mutex_lock(&priv->port_mutex); 1180 mlx4_unregister_device(mdev); 1181 for (port = 1; port <= mdev->caps.num_ports; port++) { 1182 mlx4_CLOSE_PORT(mdev, port); 1183 err = mlx4_SET_PORT(mdev, port, -1); 1184 if (err) { 1185 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1186 port); 1187 goto err_set_port; 1188 } 1189 } 1190 err = mlx4_register_device(mdev); 1191 err_set_port: 1192 mutex_unlock(&priv->port_mutex); 1193 mlx4_start_sense(mdev); 1194 return err ? err : count; 1195 } 1196 1197 int mlx4_bond(struct mlx4_dev *dev) 1198 { 1199 int ret = 0; 1200 struct mlx4_priv *priv = mlx4_priv(dev); 1201 1202 mutex_lock(&priv->bond_mutex); 1203 1204 if (!mlx4_is_bonded(dev)) 1205 ret = mlx4_do_bond(dev, true); 1206 else 1207 ret = 0; 1208 1209 mutex_unlock(&priv->bond_mutex); 1210 if (ret) 1211 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1212 else 1213 mlx4_dbg(dev, "Device is bonded\n"); 1214 return ret; 1215 } 1216 EXPORT_SYMBOL_GPL(mlx4_bond); 1217 1218 int mlx4_unbond(struct mlx4_dev *dev) 1219 { 1220 int ret = 0; 1221 struct mlx4_priv *priv = mlx4_priv(dev); 1222 1223 mutex_lock(&priv->bond_mutex); 1224 1225 if (mlx4_is_bonded(dev)) 1226 ret = mlx4_do_bond(dev, false); 1227 1228 mutex_unlock(&priv->bond_mutex); 1229 if (ret) 1230 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1231 else 1232 mlx4_dbg(dev, "Device is unbonded\n"); 1233 return ret; 1234 } 1235 EXPORT_SYMBOL_GPL(mlx4_unbond); 1236 1237 1238 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1239 { 1240 u8 port1 = v2p->port1; 1241 u8 port2 = v2p->port2; 1242 struct mlx4_priv *priv = mlx4_priv(dev); 1243 int err; 1244 1245 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1246 return -ENOTSUPP; 1247 1248 mutex_lock(&priv->bond_mutex); 1249 1250 /* zero means keep current mapping for this port */ 1251 if (port1 == 0) 1252 port1 = priv->v2p.port1; 1253 if (port2 == 0) 1254 port2 = priv->v2p.port2; 1255 1256 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1257 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1258 (port1 == 2 && port2 == 1)) { 1259 /* besides boundary checks cross mapping makes 1260 * no sense and therefore not allowed */ 1261 err = -EINVAL; 1262 } else if ((port1 == priv->v2p.port1) && 1263 (port2 == priv->v2p.port2)) { 1264 err = 0; 1265 } else { 1266 err = mlx4_virt2phy_port_map(dev, port1, port2); 1267 if (!err) { 1268 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1269 port1, port2); 1270 priv->v2p.port1 = port1; 1271 priv->v2p.port2 = port2; 1272 } else { 1273 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1274 } 1275 } 1276 1277 mutex_unlock(&priv->bond_mutex); 1278 return err; 1279 } 1280 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1281 1282 static int mlx4_load_fw(struct mlx4_dev *dev) 1283 { 1284 struct mlx4_priv *priv = mlx4_priv(dev); 1285 int err; 1286 1287 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1288 GFP_HIGHUSER | __GFP_NOWARN, 0); 1289 if (!priv->fw.fw_icm) { 1290 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1291 return -ENOMEM; 1292 } 1293 1294 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1295 if (err) { 1296 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1297 goto err_free; 1298 } 1299 1300 err = mlx4_RUN_FW(dev); 1301 if (err) { 1302 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1303 goto err_unmap_fa; 1304 } 1305 1306 return 0; 1307 1308 err_unmap_fa: 1309 mlx4_UNMAP_FA(dev); 1310 1311 err_free: 1312 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1313 return err; 1314 } 1315 1316 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1317 int cmpt_entry_sz) 1318 { 1319 struct mlx4_priv *priv = mlx4_priv(dev); 1320 int err; 1321 int num_eqs; 1322 1323 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1324 cmpt_base + 1325 ((u64) (MLX4_CMPT_TYPE_QP * 1326 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1327 cmpt_entry_sz, dev->caps.num_qps, 1328 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1329 0, 0); 1330 if (err) 1331 goto err; 1332 1333 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1334 cmpt_base + 1335 ((u64) (MLX4_CMPT_TYPE_SRQ * 1336 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1337 cmpt_entry_sz, dev->caps.num_srqs, 1338 dev->caps.reserved_srqs, 0, 0); 1339 if (err) 1340 goto err_qp; 1341 1342 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1343 cmpt_base + 1344 ((u64) (MLX4_CMPT_TYPE_CQ * 1345 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1346 cmpt_entry_sz, dev->caps.num_cqs, 1347 dev->caps.reserved_cqs, 0, 0); 1348 if (err) 1349 goto err_srq; 1350 1351 num_eqs = dev->phys_caps.num_phys_eqs; 1352 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1353 cmpt_base + 1354 ((u64) (MLX4_CMPT_TYPE_EQ * 1355 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1356 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1357 if (err) 1358 goto err_cq; 1359 1360 return 0; 1361 1362 err_cq: 1363 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1364 1365 err_srq: 1366 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1367 1368 err_qp: 1369 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1370 1371 err: 1372 return err; 1373 } 1374 1375 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1376 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1377 { 1378 struct mlx4_priv *priv = mlx4_priv(dev); 1379 u64 aux_pages; 1380 int num_eqs; 1381 int err; 1382 1383 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1384 if (err) { 1385 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1386 return err; 1387 } 1388 1389 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1390 (unsigned long long) icm_size >> 10, 1391 (unsigned long long) aux_pages << 2); 1392 1393 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1394 GFP_HIGHUSER | __GFP_NOWARN, 0); 1395 if (!priv->fw.aux_icm) { 1396 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1397 return -ENOMEM; 1398 } 1399 1400 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1401 if (err) { 1402 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1403 goto err_free_aux; 1404 } 1405 1406 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1407 if (err) { 1408 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1409 goto err_unmap_aux; 1410 } 1411 1412 1413 num_eqs = dev->phys_caps.num_phys_eqs; 1414 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1415 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1416 num_eqs, num_eqs, 0, 0); 1417 if (err) { 1418 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1419 goto err_unmap_cmpt; 1420 } 1421 1422 /* 1423 * Reserved MTT entries must be aligned up to a cacheline 1424 * boundary, since the FW will write to them, while the driver 1425 * writes to all other MTT entries. (The variable 1426 * dev->caps.mtt_entry_sz below is really the MTT segment 1427 * size, not the raw entry size) 1428 */ 1429 dev->caps.reserved_mtts = 1430 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1431 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1432 1433 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1434 init_hca->mtt_base, 1435 dev->caps.mtt_entry_sz, 1436 dev->caps.num_mtts, 1437 dev->caps.reserved_mtts, 1, 0); 1438 if (err) { 1439 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1440 goto err_unmap_eq; 1441 } 1442 1443 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1444 init_hca->dmpt_base, 1445 dev_cap->dmpt_entry_sz, 1446 dev->caps.num_mpts, 1447 dev->caps.reserved_mrws, 1, 1); 1448 if (err) { 1449 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1450 goto err_unmap_mtt; 1451 } 1452 1453 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1454 init_hca->qpc_base, 1455 dev_cap->qpc_entry_sz, 1456 dev->caps.num_qps, 1457 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1458 0, 0); 1459 if (err) { 1460 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1461 goto err_unmap_dmpt; 1462 } 1463 1464 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1465 init_hca->auxc_base, 1466 dev_cap->aux_entry_sz, 1467 dev->caps.num_qps, 1468 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1469 0, 0); 1470 if (err) { 1471 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1472 goto err_unmap_qp; 1473 } 1474 1475 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1476 init_hca->altc_base, 1477 dev_cap->altc_entry_sz, 1478 dev->caps.num_qps, 1479 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1480 0, 0); 1481 if (err) { 1482 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1483 goto err_unmap_auxc; 1484 } 1485 1486 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1487 init_hca->rdmarc_base, 1488 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1489 dev->caps.num_qps, 1490 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1491 0, 0); 1492 if (err) { 1493 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1494 goto err_unmap_altc; 1495 } 1496 1497 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1498 init_hca->cqc_base, 1499 dev_cap->cqc_entry_sz, 1500 dev->caps.num_cqs, 1501 dev->caps.reserved_cqs, 0, 0); 1502 if (err) { 1503 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1504 goto err_unmap_rdmarc; 1505 } 1506 1507 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1508 init_hca->srqc_base, 1509 dev_cap->srq_entry_sz, 1510 dev->caps.num_srqs, 1511 dev->caps.reserved_srqs, 0, 0); 1512 if (err) { 1513 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1514 goto err_unmap_cq; 1515 } 1516 1517 /* 1518 * For flow steering device managed mode it is required to use 1519 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1520 * required, but for simplicity just map the whole multicast 1521 * group table now. The table isn't very big and it's a lot 1522 * easier than trying to track ref counts. 1523 */ 1524 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1525 init_hca->mc_base, 1526 mlx4_get_mgm_entry_size(dev), 1527 dev->caps.num_mgms + dev->caps.num_amgms, 1528 dev->caps.num_mgms + dev->caps.num_amgms, 1529 0, 0); 1530 if (err) { 1531 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1532 goto err_unmap_srq; 1533 } 1534 1535 return 0; 1536 1537 err_unmap_srq: 1538 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1539 1540 err_unmap_cq: 1541 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1542 1543 err_unmap_rdmarc: 1544 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1545 1546 err_unmap_altc: 1547 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1548 1549 err_unmap_auxc: 1550 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1551 1552 err_unmap_qp: 1553 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1554 1555 err_unmap_dmpt: 1556 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1557 1558 err_unmap_mtt: 1559 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1560 1561 err_unmap_eq: 1562 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1563 1564 err_unmap_cmpt: 1565 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1566 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1567 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1568 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1569 1570 err_unmap_aux: 1571 mlx4_UNMAP_ICM_AUX(dev); 1572 1573 err_free_aux: 1574 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1575 1576 return err; 1577 } 1578 1579 static void mlx4_free_icms(struct mlx4_dev *dev) 1580 { 1581 struct mlx4_priv *priv = mlx4_priv(dev); 1582 1583 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1584 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1585 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1586 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1587 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1588 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1589 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1590 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1591 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1592 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1593 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1594 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1595 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1596 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1597 1598 mlx4_UNMAP_ICM_AUX(dev); 1599 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1600 } 1601 1602 static void mlx4_slave_exit(struct mlx4_dev *dev) 1603 { 1604 struct mlx4_priv *priv = mlx4_priv(dev); 1605 1606 mutex_lock(&priv->cmd.slave_cmd_mutex); 1607 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1608 MLX4_COMM_TIME)) 1609 mlx4_warn(dev, "Failed to close slave function\n"); 1610 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1611 } 1612 1613 static int map_bf_area(struct mlx4_dev *dev) 1614 { 1615 struct mlx4_priv *priv = mlx4_priv(dev); 1616 resource_size_t bf_start; 1617 resource_size_t bf_len; 1618 int err = 0; 1619 1620 if (!dev->caps.bf_reg_size) 1621 return -ENXIO; 1622 1623 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1624 (dev->caps.num_uars << PAGE_SHIFT); 1625 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1626 (dev->caps.num_uars << PAGE_SHIFT); 1627 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1628 if (!priv->bf_mapping) 1629 err = -ENOMEM; 1630 1631 return err; 1632 } 1633 1634 static void unmap_bf_area(struct mlx4_dev *dev) 1635 { 1636 if (mlx4_priv(dev)->bf_mapping) 1637 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1638 } 1639 1640 cycle_t mlx4_read_clock(struct mlx4_dev *dev) 1641 { 1642 u32 clockhi, clocklo, clockhi1; 1643 cycle_t cycles; 1644 int i; 1645 struct mlx4_priv *priv = mlx4_priv(dev); 1646 1647 for (i = 0; i < 10; i++) { 1648 clockhi = swab32(readl(priv->clock_mapping)); 1649 clocklo = swab32(readl(priv->clock_mapping + 4)); 1650 clockhi1 = swab32(readl(priv->clock_mapping)); 1651 if (clockhi == clockhi1) 1652 break; 1653 } 1654 1655 cycles = (u64) clockhi << 32 | (u64) clocklo; 1656 1657 return cycles; 1658 } 1659 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1660 1661 1662 static int map_internal_clock(struct mlx4_dev *dev) 1663 { 1664 struct mlx4_priv *priv = mlx4_priv(dev); 1665 1666 priv->clock_mapping = 1667 ioremap(pci_resource_start(dev->persist->pdev, 1668 priv->fw.clock_bar) + 1669 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1670 1671 if (!priv->clock_mapping) 1672 return -ENOMEM; 1673 1674 return 0; 1675 } 1676 1677 static void unmap_internal_clock(struct mlx4_dev *dev) 1678 { 1679 struct mlx4_priv *priv = mlx4_priv(dev); 1680 1681 if (priv->clock_mapping) 1682 iounmap(priv->clock_mapping); 1683 } 1684 1685 static void mlx4_close_hca(struct mlx4_dev *dev) 1686 { 1687 unmap_internal_clock(dev); 1688 unmap_bf_area(dev); 1689 if (mlx4_is_slave(dev)) 1690 mlx4_slave_exit(dev); 1691 else { 1692 mlx4_CLOSE_HCA(dev, 0); 1693 mlx4_free_icms(dev); 1694 } 1695 } 1696 1697 static void mlx4_close_fw(struct mlx4_dev *dev) 1698 { 1699 if (!mlx4_is_slave(dev)) { 1700 mlx4_UNMAP_FA(dev); 1701 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1702 } 1703 } 1704 1705 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1706 { 1707 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1708 1709 u32 comm_flags; 1710 u32 offline_bit; 1711 unsigned long end; 1712 struct mlx4_priv *priv = mlx4_priv(dev); 1713 1714 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 1715 while (time_before(jiffies, end)) { 1716 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 1717 MLX4_COMM_CHAN_FLAGS)); 1718 offline_bit = (comm_flags & 1719 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 1720 if (!offline_bit) 1721 return 0; 1722 /* There are cases as part of AER/Reset flow that PF needs 1723 * around 100 msec to load. We therefore sleep for 100 msec 1724 * to allow other tasks to make use of that CPU during this 1725 * time interval. 1726 */ 1727 msleep(100); 1728 } 1729 mlx4_err(dev, "Communication channel is offline.\n"); 1730 return -EIO; 1731 } 1732 1733 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 1734 { 1735 #define COMM_CHAN_RST_OFFSET 0x1e 1736 1737 struct mlx4_priv *priv = mlx4_priv(dev); 1738 u32 comm_rst; 1739 u32 comm_caps; 1740 1741 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 1742 MLX4_COMM_CHAN_CAPS)); 1743 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 1744 1745 if (comm_rst) 1746 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 1747 } 1748 1749 static int mlx4_init_slave(struct mlx4_dev *dev) 1750 { 1751 struct mlx4_priv *priv = mlx4_priv(dev); 1752 u64 dma = (u64) priv->mfunc.vhcr_dma; 1753 int ret_from_reset = 0; 1754 u32 slave_read; 1755 u32 cmd_channel_ver; 1756 1757 if (atomic_read(&pf_loading)) { 1758 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 1759 return -EPROBE_DEFER; 1760 } 1761 1762 mutex_lock(&priv->cmd.slave_cmd_mutex); 1763 priv->cmd.max_cmds = 1; 1764 if (mlx4_comm_check_offline(dev)) { 1765 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 1766 goto err_offline; 1767 } 1768 1769 mlx4_reset_vf_support(dev); 1770 mlx4_warn(dev, "Sending reset\n"); 1771 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1772 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 1773 /* if we are in the middle of flr the slave will try 1774 * NUM_OF_RESET_RETRIES times before leaving.*/ 1775 if (ret_from_reset) { 1776 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1777 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 1778 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1779 return -EPROBE_DEFER; 1780 } else 1781 goto err; 1782 } 1783 1784 /* check the driver version - the slave I/F revision 1785 * must match the master's */ 1786 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1787 cmd_channel_ver = mlx4_comm_get_version(); 1788 1789 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1790 MLX4_COMM_GET_IF_REV(slave_read)) { 1791 mlx4_err(dev, "slave driver version is not supported by the master\n"); 1792 goto err; 1793 } 1794 1795 mlx4_warn(dev, "Sending vhcr0\n"); 1796 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1797 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1798 goto err; 1799 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1800 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1801 goto err; 1802 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1803 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1804 goto err; 1805 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 1806 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 1807 goto err; 1808 1809 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1810 return 0; 1811 1812 err: 1813 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 1814 err_offline: 1815 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1816 return -EIO; 1817 } 1818 1819 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1820 { 1821 int i; 1822 1823 for (i = 1; i <= dev->caps.num_ports; i++) { 1824 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1825 dev->caps.gid_table_len[i] = 1826 mlx4_get_slave_num_gids(dev, 0, i); 1827 else 1828 dev->caps.gid_table_len[i] = 1; 1829 dev->caps.pkey_table_len[i] = 1830 dev->phys_caps.pkey_phys_table_len[i] - 1; 1831 } 1832 } 1833 1834 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1835 { 1836 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1837 1838 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1839 i++) { 1840 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1841 break; 1842 } 1843 1844 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1845 } 1846 1847 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 1848 { 1849 switch (dmfs_high_steer_mode) { 1850 case MLX4_STEERING_DMFS_A0_DEFAULT: 1851 return "default performance"; 1852 1853 case MLX4_STEERING_DMFS_A0_DYNAMIC: 1854 return "dynamic hybrid mode"; 1855 1856 case MLX4_STEERING_DMFS_A0_STATIC: 1857 return "performance optimized for limited rule configuration (static)"; 1858 1859 case MLX4_STEERING_DMFS_A0_DISABLE: 1860 return "disabled performance optimized steering"; 1861 1862 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 1863 return "performance optimized steering not supported"; 1864 1865 default: 1866 return "Unrecognized mode"; 1867 } 1868 } 1869 1870 #define MLX4_DMFS_A0_STEERING (1UL << 2) 1871 1872 static void choose_steering_mode(struct mlx4_dev *dev, 1873 struct mlx4_dev_cap *dev_cap) 1874 { 1875 if (mlx4_log_num_mgm_entry_size <= 0) { 1876 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 1877 if (dev->caps.dmfs_high_steer_mode == 1878 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1879 mlx4_err(dev, "DMFS high rate mode not supported\n"); 1880 else 1881 dev->caps.dmfs_high_steer_mode = 1882 MLX4_STEERING_DMFS_A0_STATIC; 1883 } 1884 } 1885 1886 if (mlx4_log_num_mgm_entry_size <= 0 && 1887 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1888 (!mlx4_is_mfunc(dev) || 1889 (dev_cap->fs_max_num_qp_per_entry >= 1890 (dev->persist->num_vfs + 1))) && 1891 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1892 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1893 dev->oper_log_mgm_entry_size = 1894 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1895 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1896 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1897 dev->caps.fs_log_max_ucast_qp_range_size = 1898 dev_cap->fs_log_max_ucast_qp_range_size; 1899 } else { 1900 if (dev->caps.dmfs_high_steer_mode != 1901 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1902 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 1903 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1904 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1905 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1906 else { 1907 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1908 1909 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1910 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1911 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 1912 } 1913 dev->oper_log_mgm_entry_size = 1914 mlx4_log_num_mgm_entry_size > 0 ? 1915 mlx4_log_num_mgm_entry_size : 1916 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1917 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1918 } 1919 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 1920 mlx4_steering_mode_str(dev->caps.steering_mode), 1921 dev->oper_log_mgm_entry_size, 1922 mlx4_log_num_mgm_entry_size); 1923 } 1924 1925 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 1926 struct mlx4_dev_cap *dev_cap) 1927 { 1928 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 1929 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 1930 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 1931 else 1932 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 1933 1934 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 1935 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 1936 } 1937 1938 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 1939 { 1940 int i; 1941 struct mlx4_port_cap port_cap; 1942 1943 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1944 return -EINVAL; 1945 1946 for (i = 1; i <= dev->caps.num_ports; i++) { 1947 if (mlx4_dev_port(dev, i, &port_cap)) { 1948 mlx4_err(dev, 1949 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 1950 } else if ((dev->caps.dmfs_high_steer_mode != 1951 MLX4_STEERING_DMFS_A0_DEFAULT) && 1952 (port_cap.dmfs_optimized_state == 1953 !!(dev->caps.dmfs_high_steer_mode == 1954 MLX4_STEERING_DMFS_A0_DISABLE))) { 1955 mlx4_err(dev, 1956 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 1957 dmfs_high_rate_steering_mode_str( 1958 dev->caps.dmfs_high_steer_mode), 1959 (port_cap.dmfs_optimized_state ? 1960 "enabled" : "disabled")); 1961 } 1962 } 1963 1964 return 0; 1965 } 1966 1967 static int mlx4_init_fw(struct mlx4_dev *dev) 1968 { 1969 struct mlx4_mod_stat_cfg mlx4_cfg; 1970 int err = 0; 1971 1972 if (!mlx4_is_slave(dev)) { 1973 err = mlx4_QUERY_FW(dev); 1974 if (err) { 1975 if (err == -EACCES) 1976 mlx4_info(dev, "non-primary physical function, skipping\n"); 1977 else 1978 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 1979 return err; 1980 } 1981 1982 err = mlx4_load_fw(dev); 1983 if (err) { 1984 mlx4_err(dev, "Failed to start FW, aborting\n"); 1985 return err; 1986 } 1987 1988 mlx4_cfg.log_pg_sz_m = 1; 1989 mlx4_cfg.log_pg_sz = 0; 1990 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1991 if (err) 1992 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1993 } 1994 1995 return err; 1996 } 1997 1998 static int mlx4_init_hca(struct mlx4_dev *dev) 1999 { 2000 struct mlx4_priv *priv = mlx4_priv(dev); 2001 struct mlx4_adapter adapter; 2002 struct mlx4_dev_cap dev_cap; 2003 struct mlx4_profile profile; 2004 struct mlx4_init_hca_param init_hca; 2005 u64 icm_size; 2006 struct mlx4_config_dev_params params; 2007 int err; 2008 2009 if (!mlx4_is_slave(dev)) { 2010 err = mlx4_dev_cap(dev, &dev_cap); 2011 if (err) { 2012 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2013 return err; 2014 } 2015 2016 choose_steering_mode(dev, &dev_cap); 2017 choose_tunnel_offload_mode(dev, &dev_cap); 2018 2019 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2020 mlx4_is_master(dev)) 2021 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2022 2023 err = mlx4_get_phys_port_id(dev); 2024 if (err) 2025 mlx4_err(dev, "Fail to get physical port id\n"); 2026 2027 if (mlx4_is_master(dev)) 2028 mlx4_parav_master_pf_caps(dev); 2029 2030 if (mlx4_low_memory_profile()) { 2031 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2032 profile = low_mem_profile; 2033 } else { 2034 profile = default_profile; 2035 } 2036 if (dev->caps.steering_mode == 2037 MLX4_STEERING_MODE_DEVICE_MANAGED) 2038 profile.num_mcg = MLX4_FS_NUM_MCG; 2039 2040 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2041 &init_hca); 2042 if ((long long) icm_size < 0) { 2043 err = icm_size; 2044 return err; 2045 } 2046 2047 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2048 2049 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2050 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2051 init_hca.mw_enabled = 0; 2052 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2053 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2054 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2055 2056 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2057 if (err) 2058 return err; 2059 2060 err = mlx4_INIT_HCA(dev, &init_hca); 2061 if (err) { 2062 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2063 goto err_free_icm; 2064 } 2065 2066 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2067 err = mlx4_query_func(dev, &dev_cap); 2068 if (err < 0) { 2069 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2070 goto err_close; 2071 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2072 dev->caps.num_eqs = dev_cap.max_eqs; 2073 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2074 dev->caps.reserved_uars = dev_cap.reserved_uars; 2075 } 2076 } 2077 2078 /* 2079 * If TS is supported by FW 2080 * read HCA frequency by QUERY_HCA command 2081 */ 2082 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2083 memset(&init_hca, 0, sizeof(init_hca)); 2084 err = mlx4_QUERY_HCA(dev, &init_hca); 2085 if (err) { 2086 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2087 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2088 } else { 2089 dev->caps.hca_core_clock = 2090 init_hca.hca_core_clock; 2091 } 2092 2093 /* In case we got HCA frequency 0 - disable timestamping 2094 * to avoid dividing by zero 2095 */ 2096 if (!dev->caps.hca_core_clock) { 2097 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2098 mlx4_err(dev, 2099 "HCA frequency is 0 - timestamping is not supported\n"); 2100 } else if (map_internal_clock(dev)) { 2101 /* 2102 * Map internal clock, 2103 * in case of failure disable timestamping 2104 */ 2105 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2106 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2107 } 2108 } 2109 2110 if (dev->caps.dmfs_high_steer_mode != 2111 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2112 if (mlx4_validate_optimized_steering(dev)) 2113 mlx4_warn(dev, "Optimized steering validation failed\n"); 2114 2115 if (dev->caps.dmfs_high_steer_mode == 2116 MLX4_STEERING_DMFS_A0_DISABLE) { 2117 dev->caps.dmfs_high_rate_qpn_base = 2118 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2119 dev->caps.dmfs_high_rate_qpn_range = 2120 MLX4_A0_STEERING_TABLE_SIZE; 2121 } 2122 2123 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n", 2124 dmfs_high_rate_steering_mode_str( 2125 dev->caps.dmfs_high_steer_mode)); 2126 } 2127 } else { 2128 err = mlx4_init_slave(dev); 2129 if (err) { 2130 if (err != -EPROBE_DEFER) 2131 mlx4_err(dev, "Failed to initialize slave\n"); 2132 return err; 2133 } 2134 2135 err = mlx4_slave_cap(dev); 2136 if (err) { 2137 mlx4_err(dev, "Failed to obtain slave caps\n"); 2138 goto err_close; 2139 } 2140 } 2141 2142 if (map_bf_area(dev)) 2143 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2144 2145 /*Only the master set the ports, all the rest got it from it.*/ 2146 if (!mlx4_is_slave(dev)) 2147 mlx4_set_port_mask(dev); 2148 2149 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2150 if (err) { 2151 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2152 goto unmap_bf; 2153 } 2154 2155 /* Query CONFIG_DEV parameters */ 2156 err = mlx4_config_dev_retrieval(dev, ¶ms); 2157 if (err && err != -ENOTSUPP) { 2158 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2159 } else if (!err) { 2160 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2161 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2162 } 2163 priv->eq_table.inta_pin = adapter.inta_pin; 2164 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 2165 2166 return 0; 2167 2168 unmap_bf: 2169 unmap_internal_clock(dev); 2170 unmap_bf_area(dev); 2171 2172 if (mlx4_is_slave(dev)) { 2173 kfree(dev->caps.qp0_qkey); 2174 kfree(dev->caps.qp0_tunnel); 2175 kfree(dev->caps.qp0_proxy); 2176 kfree(dev->caps.qp1_tunnel); 2177 kfree(dev->caps.qp1_proxy); 2178 } 2179 2180 err_close: 2181 if (mlx4_is_slave(dev)) 2182 mlx4_slave_exit(dev); 2183 else 2184 mlx4_CLOSE_HCA(dev, 0); 2185 2186 err_free_icm: 2187 if (!mlx4_is_slave(dev)) 2188 mlx4_free_icms(dev); 2189 2190 return err; 2191 } 2192 2193 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2194 { 2195 struct mlx4_priv *priv = mlx4_priv(dev); 2196 int nent_pow2; 2197 2198 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2199 return -ENOENT; 2200 2201 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2202 /* reserve last counter index for sink counter */ 2203 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2204 nent_pow2 - 1, 0, 2205 nent_pow2 - dev->caps.max_counters + 1); 2206 } 2207 2208 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2209 { 2210 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2211 return; 2212 2213 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2214 } 2215 2216 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2217 { 2218 struct mlx4_priv *priv = mlx4_priv(dev); 2219 2220 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2221 return -ENOENT; 2222 2223 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2224 if (*idx == -1) 2225 return -ENOMEM; 2226 2227 return 0; 2228 } 2229 2230 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2231 { 2232 u64 out_param; 2233 int err; 2234 2235 if (mlx4_is_mfunc(dev)) { 2236 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 2237 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2238 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2239 if (!err) 2240 *idx = get_param_l(&out_param); 2241 2242 return err; 2243 } 2244 return __mlx4_counter_alloc(dev, idx); 2245 } 2246 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2247 2248 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2249 u8 counter_index) 2250 { 2251 struct mlx4_cmd_mailbox *if_stat_mailbox; 2252 int err; 2253 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2254 2255 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2256 if (IS_ERR(if_stat_mailbox)) 2257 return PTR_ERR(if_stat_mailbox); 2258 2259 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2260 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2261 MLX4_CMD_NATIVE); 2262 2263 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2264 return err; 2265 } 2266 2267 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2268 { 2269 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2270 return; 2271 2272 __mlx4_clear_if_stat(dev, idx); 2273 2274 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2275 return; 2276 } 2277 2278 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2279 { 2280 u64 in_param = 0; 2281 2282 if (mlx4_is_mfunc(dev)) { 2283 set_param_l(&in_param, idx); 2284 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2285 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2286 MLX4_CMD_WRAPPED); 2287 return; 2288 } 2289 __mlx4_counter_free(dev, idx); 2290 } 2291 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2292 2293 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2294 { 2295 struct mlx4_priv *priv = mlx4_priv(dev); 2296 2297 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2298 } 2299 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2300 2301 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2302 { 2303 struct mlx4_priv *priv = mlx4_priv(dev); 2304 2305 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2306 } 2307 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2308 2309 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2310 { 2311 struct mlx4_priv *priv = mlx4_priv(dev); 2312 __be64 guid; 2313 2314 /* hw GUID */ 2315 if (entry == 0) 2316 return; 2317 2318 get_random_bytes((char *)&guid, sizeof(guid)); 2319 guid &= ~(cpu_to_be64(1ULL << 56)); 2320 guid |= cpu_to_be64(1ULL << 57); 2321 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2322 } 2323 2324 static int mlx4_setup_hca(struct mlx4_dev *dev) 2325 { 2326 struct mlx4_priv *priv = mlx4_priv(dev); 2327 int err; 2328 int port; 2329 __be32 ib_port_default_caps; 2330 2331 err = mlx4_init_uar_table(dev); 2332 if (err) { 2333 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2334 return err; 2335 } 2336 2337 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2338 if (err) { 2339 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2340 goto err_uar_table_free; 2341 } 2342 2343 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2344 if (!priv->kar) { 2345 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2346 err = -ENOMEM; 2347 goto err_uar_free; 2348 } 2349 2350 err = mlx4_init_pd_table(dev); 2351 if (err) { 2352 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2353 goto err_kar_unmap; 2354 } 2355 2356 err = mlx4_init_xrcd_table(dev); 2357 if (err) { 2358 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2359 goto err_pd_table_free; 2360 } 2361 2362 err = mlx4_init_mr_table(dev); 2363 if (err) { 2364 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2365 goto err_xrcd_table_free; 2366 } 2367 2368 if (!mlx4_is_slave(dev)) { 2369 err = mlx4_init_mcg_table(dev); 2370 if (err) { 2371 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2372 goto err_mr_table_free; 2373 } 2374 err = mlx4_config_mad_demux(dev); 2375 if (err) { 2376 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2377 goto err_mcg_table_free; 2378 } 2379 } 2380 2381 err = mlx4_init_eq_table(dev); 2382 if (err) { 2383 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2384 goto err_mcg_table_free; 2385 } 2386 2387 err = mlx4_cmd_use_events(dev); 2388 if (err) { 2389 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2390 goto err_eq_table_free; 2391 } 2392 2393 err = mlx4_NOP(dev); 2394 if (err) { 2395 if (dev->flags & MLX4_FLAG_MSI_X) { 2396 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2397 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2398 mlx4_warn(dev, "Trying again without MSI-X\n"); 2399 } else { 2400 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2401 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2402 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2403 } 2404 2405 goto err_cmd_poll; 2406 } 2407 2408 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2409 2410 err = mlx4_init_cq_table(dev); 2411 if (err) { 2412 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2413 goto err_cmd_poll; 2414 } 2415 2416 err = mlx4_init_srq_table(dev); 2417 if (err) { 2418 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2419 goto err_cq_table_free; 2420 } 2421 2422 err = mlx4_init_qp_table(dev); 2423 if (err) { 2424 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2425 goto err_srq_table_free; 2426 } 2427 2428 err = mlx4_init_counters_table(dev); 2429 if (err && err != -ENOENT) { 2430 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2431 goto err_qp_table_free; 2432 } 2433 2434 if (!mlx4_is_slave(dev)) { 2435 for (port = 1; port <= dev->caps.num_ports; port++) { 2436 ib_port_default_caps = 0; 2437 err = mlx4_get_port_ib_caps(dev, port, 2438 &ib_port_default_caps); 2439 if (err) 2440 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2441 port, err); 2442 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2443 2444 /* initialize per-slave default ib port capabilities */ 2445 if (mlx4_is_master(dev)) { 2446 int i; 2447 for (i = 0; i < dev->num_slaves; i++) { 2448 if (i == mlx4_master_func_num(dev)) 2449 continue; 2450 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2451 ib_port_default_caps; 2452 } 2453 } 2454 2455 if (mlx4_is_mfunc(dev)) 2456 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2457 else 2458 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2459 2460 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2461 dev->caps.pkey_table_len[port] : -1); 2462 if (err) { 2463 mlx4_err(dev, "Failed to set port %d, aborting\n", 2464 port); 2465 goto err_counters_table_free; 2466 } 2467 } 2468 } 2469 2470 return 0; 2471 2472 err_counters_table_free: 2473 mlx4_cleanup_counters_table(dev); 2474 2475 err_qp_table_free: 2476 mlx4_cleanup_qp_table(dev); 2477 2478 err_srq_table_free: 2479 mlx4_cleanup_srq_table(dev); 2480 2481 err_cq_table_free: 2482 mlx4_cleanup_cq_table(dev); 2483 2484 err_cmd_poll: 2485 mlx4_cmd_use_polling(dev); 2486 2487 err_eq_table_free: 2488 mlx4_cleanup_eq_table(dev); 2489 2490 err_mcg_table_free: 2491 if (!mlx4_is_slave(dev)) 2492 mlx4_cleanup_mcg_table(dev); 2493 2494 err_mr_table_free: 2495 mlx4_cleanup_mr_table(dev); 2496 2497 err_xrcd_table_free: 2498 mlx4_cleanup_xrcd_table(dev); 2499 2500 err_pd_table_free: 2501 mlx4_cleanup_pd_table(dev); 2502 2503 err_kar_unmap: 2504 iounmap(priv->kar); 2505 2506 err_uar_free: 2507 mlx4_uar_free(dev, &priv->driver_uar); 2508 2509 err_uar_table_free: 2510 mlx4_cleanup_uar_table(dev); 2511 return err; 2512 } 2513 2514 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2515 { 2516 int requested_cpu = 0; 2517 struct mlx4_priv *priv = mlx4_priv(dev); 2518 struct mlx4_eq *eq; 2519 int off = 0; 2520 int i; 2521 2522 if (eqn > dev->caps.num_comp_vectors) 2523 return -EINVAL; 2524 2525 for (i = 1; i < port; i++) 2526 off += mlx4_get_eqs_per_port(dev, i); 2527 2528 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2529 2530 /* Meaning EQs are shared, and this call comes from the second port */ 2531 if (requested_cpu < 0) 2532 return 0; 2533 2534 eq = &priv->eq_table.eq[eqn]; 2535 2536 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2537 return -ENOMEM; 2538 2539 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2540 2541 return 0; 2542 } 2543 2544 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2545 { 2546 struct mlx4_priv *priv = mlx4_priv(dev); 2547 struct msix_entry *entries; 2548 int i; 2549 int port = 0; 2550 2551 if (msi_x) { 2552 int nreq = dev->caps.num_ports * num_online_cpus() + 1; 2553 2554 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2555 nreq); 2556 2557 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2558 if (!entries) 2559 goto no_msi; 2560 2561 for (i = 0; i < nreq; ++i) 2562 entries[i].entry = i; 2563 2564 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2565 nreq); 2566 2567 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2568 kfree(entries); 2569 goto no_msi; 2570 } 2571 /* 1 is reserved for events (asyncrounous EQ) */ 2572 dev->caps.num_comp_vectors = nreq - 1; 2573 2574 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2575 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2576 dev->caps.num_ports); 2577 2578 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2579 if (i == MLX4_EQ_ASYNC) 2580 continue; 2581 2582 priv->eq_table.eq[i].irq = 2583 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2584 2585 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2586 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2587 dev->caps.num_ports); 2588 /* We don't set affinity hint when there 2589 * aren't enough EQs 2590 */ 2591 } else { 2592 set_bit(port, 2593 priv->eq_table.eq[i].actv_ports.ports); 2594 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2595 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2596 i); 2597 } 2598 /* We divide the Eqs evenly between the two ports. 2599 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2600 * refers to the number of Eqs per port 2601 * (i.e eqs_per_port). Theoretically, we would like to 2602 * write something like (i + 1) % eqs_per_port == 0. 2603 * However, since there's an asynchronous Eq, we have 2604 * to skip over it by comparing this condition to 2605 * !!((i + 1) > MLX4_EQ_ASYNC). 2606 */ 2607 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2608 ((i + 1) % 2609 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 2610 !!((i + 1) > MLX4_EQ_ASYNC)) 2611 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 2612 * everything is shared anyway. 2613 */ 2614 port++; 2615 } 2616 2617 dev->flags |= MLX4_FLAG_MSI_X; 2618 2619 kfree(entries); 2620 return; 2621 } 2622 2623 no_msi: 2624 dev->caps.num_comp_vectors = 1; 2625 2626 BUG_ON(MLX4_EQ_ASYNC >= 2); 2627 for (i = 0; i < 2; ++i) { 2628 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 2629 if (i != MLX4_EQ_ASYNC) { 2630 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2631 dev->caps.num_ports); 2632 } 2633 } 2634 } 2635 2636 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2637 { 2638 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2639 int err = 0; 2640 2641 info->dev = dev; 2642 info->port = port; 2643 if (!mlx4_is_slave(dev)) { 2644 mlx4_init_mac_table(dev, &info->mac_table); 2645 mlx4_init_vlan_table(dev, &info->vlan_table); 2646 mlx4_init_roce_gid_table(dev, &info->gid_table); 2647 info->base_qpn = mlx4_get_base_qpn(dev, port); 2648 } 2649 2650 sprintf(info->dev_name, "mlx4_port%d", port); 2651 info->port_attr.attr.name = info->dev_name; 2652 if (mlx4_is_mfunc(dev)) 2653 info->port_attr.attr.mode = S_IRUGO; 2654 else { 2655 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2656 info->port_attr.store = set_port_type; 2657 } 2658 info->port_attr.show = show_port_type; 2659 sysfs_attr_init(&info->port_attr.attr); 2660 2661 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 2662 if (err) { 2663 mlx4_err(dev, "Failed to create file for port %d\n", port); 2664 info->port = -1; 2665 } 2666 2667 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2668 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2669 if (mlx4_is_mfunc(dev)) 2670 info->port_mtu_attr.attr.mode = S_IRUGO; 2671 else { 2672 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2673 info->port_mtu_attr.store = set_port_ib_mtu; 2674 } 2675 info->port_mtu_attr.show = show_port_ib_mtu; 2676 sysfs_attr_init(&info->port_mtu_attr.attr); 2677 2678 err = device_create_file(&dev->persist->pdev->dev, 2679 &info->port_mtu_attr); 2680 if (err) { 2681 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2682 device_remove_file(&info->dev->persist->pdev->dev, 2683 &info->port_attr); 2684 info->port = -1; 2685 } 2686 2687 return err; 2688 } 2689 2690 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 2691 { 2692 if (info->port < 0) 2693 return; 2694 2695 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 2696 device_remove_file(&info->dev->persist->pdev->dev, 2697 &info->port_mtu_attr); 2698 #ifdef CONFIG_RFS_ACCEL 2699 free_irq_cpu_rmap(info->rmap); 2700 info->rmap = NULL; 2701 #endif 2702 } 2703 2704 static int mlx4_init_steering(struct mlx4_dev *dev) 2705 { 2706 struct mlx4_priv *priv = mlx4_priv(dev); 2707 int num_entries = dev->caps.num_ports; 2708 int i, j; 2709 2710 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 2711 if (!priv->steer) 2712 return -ENOMEM; 2713 2714 for (i = 0; i < num_entries; i++) 2715 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2716 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 2717 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 2718 } 2719 return 0; 2720 } 2721 2722 static void mlx4_clear_steering(struct mlx4_dev *dev) 2723 { 2724 struct mlx4_priv *priv = mlx4_priv(dev); 2725 struct mlx4_steer_index *entry, *tmp_entry; 2726 struct mlx4_promisc_qp *pqp, *tmp_pqp; 2727 int num_entries = dev->caps.num_ports; 2728 int i, j; 2729 2730 for (i = 0; i < num_entries; i++) { 2731 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2732 list_for_each_entry_safe(pqp, tmp_pqp, 2733 &priv->steer[i].promisc_qps[j], 2734 list) { 2735 list_del(&pqp->list); 2736 kfree(pqp); 2737 } 2738 list_for_each_entry_safe(entry, tmp_entry, 2739 &priv->steer[i].steer_entries[j], 2740 list) { 2741 list_del(&entry->list); 2742 list_for_each_entry_safe(pqp, tmp_pqp, 2743 &entry->duplicates, 2744 list) { 2745 list_del(&pqp->list); 2746 kfree(pqp); 2747 } 2748 kfree(entry); 2749 } 2750 } 2751 } 2752 kfree(priv->steer); 2753 } 2754 2755 static int extended_func_num(struct pci_dev *pdev) 2756 { 2757 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 2758 } 2759 2760 #define MLX4_OWNER_BASE 0x8069c 2761 #define MLX4_OWNER_SIZE 4 2762 2763 static int mlx4_get_ownership(struct mlx4_dev *dev) 2764 { 2765 void __iomem *owner; 2766 u32 ret; 2767 2768 if (pci_channel_offline(dev->persist->pdev)) 2769 return -EIO; 2770 2771 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 2772 MLX4_OWNER_BASE, 2773 MLX4_OWNER_SIZE); 2774 if (!owner) { 2775 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2776 return -ENOMEM; 2777 } 2778 2779 ret = readl(owner); 2780 iounmap(owner); 2781 return (int) !!ret; 2782 } 2783 2784 static void mlx4_free_ownership(struct mlx4_dev *dev) 2785 { 2786 void __iomem *owner; 2787 2788 if (pci_channel_offline(dev->persist->pdev)) 2789 return; 2790 2791 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 2792 MLX4_OWNER_BASE, 2793 MLX4_OWNER_SIZE); 2794 if (!owner) { 2795 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2796 return; 2797 } 2798 writel(0, owner); 2799 msleep(1000); 2800 iounmap(owner); 2801 } 2802 2803 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 2804 !!((flags) & MLX4_FLAG_MASTER)) 2805 2806 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 2807 u8 total_vfs, int existing_vfs, int reset_flow) 2808 { 2809 u64 dev_flags = dev->flags; 2810 int err = 0; 2811 2812 if (reset_flow) { 2813 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 2814 GFP_KERNEL); 2815 if (!dev->dev_vfs) 2816 goto free_mem; 2817 return dev_flags; 2818 } 2819 2820 atomic_inc(&pf_loading); 2821 if (dev->flags & MLX4_FLAG_SRIOV) { 2822 if (existing_vfs != total_vfs) { 2823 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 2824 existing_vfs, total_vfs); 2825 total_vfs = existing_vfs; 2826 } 2827 } 2828 2829 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL); 2830 if (NULL == dev->dev_vfs) { 2831 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 2832 goto disable_sriov; 2833 } 2834 2835 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 2836 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 2837 err = pci_enable_sriov(pdev, total_vfs); 2838 } 2839 if (err) { 2840 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 2841 err); 2842 goto disable_sriov; 2843 } else { 2844 mlx4_warn(dev, "Running in master mode\n"); 2845 dev_flags |= MLX4_FLAG_SRIOV | 2846 MLX4_FLAG_MASTER; 2847 dev_flags &= ~MLX4_FLAG_SLAVE; 2848 dev->persist->num_vfs = total_vfs; 2849 } 2850 return dev_flags; 2851 2852 disable_sriov: 2853 atomic_dec(&pf_loading); 2854 free_mem: 2855 dev->persist->num_vfs = 0; 2856 kfree(dev->dev_vfs); 2857 dev->dev_vfs = NULL; 2858 return dev_flags & ~MLX4_FLAG_MASTER; 2859 } 2860 2861 enum { 2862 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 2863 }; 2864 2865 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 2866 int *nvfs) 2867 { 2868 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 2869 /* Checking for 64 VFs as a limitation of CX2 */ 2870 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 2871 requested_vfs >= 64) { 2872 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 2873 requested_vfs); 2874 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 2875 } 2876 return 0; 2877 } 2878 2879 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 2880 int total_vfs, int *nvfs, struct mlx4_priv *priv, 2881 int reset_flow) 2882 { 2883 struct mlx4_dev *dev; 2884 unsigned sum = 0; 2885 int err; 2886 int port; 2887 int i; 2888 struct mlx4_dev_cap *dev_cap = NULL; 2889 int existing_vfs = 0; 2890 2891 dev = &priv->dev; 2892 2893 INIT_LIST_HEAD(&priv->ctx_list); 2894 spin_lock_init(&priv->ctx_lock); 2895 2896 mutex_init(&priv->port_mutex); 2897 mutex_init(&priv->bond_mutex); 2898 2899 INIT_LIST_HEAD(&priv->pgdir_list); 2900 mutex_init(&priv->pgdir_mutex); 2901 2902 INIT_LIST_HEAD(&priv->bf_list); 2903 mutex_init(&priv->bf_mutex); 2904 2905 dev->rev_id = pdev->revision; 2906 dev->numa_node = dev_to_node(&pdev->dev); 2907 2908 /* Detect if this device is a virtual function */ 2909 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2910 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 2911 dev->flags |= MLX4_FLAG_SLAVE; 2912 } else { 2913 /* We reset the device and enable SRIOV only for physical 2914 * devices. Try to claim ownership on the device; 2915 * if already taken, skip -- do not allow multiple PFs */ 2916 err = mlx4_get_ownership(dev); 2917 if (err) { 2918 if (err < 0) 2919 return err; 2920 else { 2921 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 2922 return -EINVAL; 2923 } 2924 } 2925 2926 atomic_set(&priv->opreq_count, 0); 2927 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 2928 2929 /* 2930 * Now reset the HCA before we touch the PCI capabilities or 2931 * attempt a firmware command, since a boot ROM may have left 2932 * the HCA in an undefined state. 2933 */ 2934 err = mlx4_reset(dev); 2935 if (err) { 2936 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 2937 goto err_sriov; 2938 } 2939 2940 if (total_vfs) { 2941 dev->flags = MLX4_FLAG_MASTER; 2942 existing_vfs = pci_num_vf(pdev); 2943 if (existing_vfs) 2944 dev->flags |= MLX4_FLAG_SRIOV; 2945 dev->persist->num_vfs = total_vfs; 2946 } 2947 } 2948 2949 /* on load remove any previous indication of internal error, 2950 * device is up. 2951 */ 2952 dev->persist->state = MLX4_DEVICE_STATE_UP; 2953 2954 slave_start: 2955 err = mlx4_cmd_init(dev); 2956 if (err) { 2957 mlx4_err(dev, "Failed to init command interface, aborting\n"); 2958 goto err_sriov; 2959 } 2960 2961 /* In slave functions, the communication channel must be initialized 2962 * before posting commands. Also, init num_slaves before calling 2963 * mlx4_init_hca */ 2964 if (mlx4_is_mfunc(dev)) { 2965 if (mlx4_is_master(dev)) { 2966 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2967 2968 } else { 2969 dev->num_slaves = 0; 2970 err = mlx4_multi_func_init(dev); 2971 if (err) { 2972 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 2973 goto err_cmd; 2974 } 2975 } 2976 } 2977 2978 err = mlx4_init_fw(dev); 2979 if (err) { 2980 mlx4_err(dev, "Failed to init fw, aborting.\n"); 2981 goto err_mfunc; 2982 } 2983 2984 if (mlx4_is_master(dev)) { 2985 /* when we hit the goto slave_start below, dev_cap already initialized */ 2986 if (!dev_cap) { 2987 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2988 2989 if (!dev_cap) { 2990 err = -ENOMEM; 2991 goto err_fw; 2992 } 2993 2994 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 2995 if (err) { 2996 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2997 goto err_fw; 2998 } 2999 3000 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3001 goto err_fw; 3002 3003 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3004 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3005 total_vfs, 3006 existing_vfs, 3007 reset_flow); 3008 3009 mlx4_close_fw(dev); 3010 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3011 dev->flags = dev_flags; 3012 if (!SRIOV_VALID_STATE(dev->flags)) { 3013 mlx4_err(dev, "Invalid SRIOV state\n"); 3014 goto err_sriov; 3015 } 3016 err = mlx4_reset(dev); 3017 if (err) { 3018 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3019 goto err_sriov; 3020 } 3021 goto slave_start; 3022 } 3023 } else { 3024 /* Legacy mode FW requires SRIOV to be enabled before 3025 * doing QUERY_DEV_CAP, since max_eq's value is different if 3026 * SRIOV is enabled. 3027 */ 3028 memset(dev_cap, 0, sizeof(*dev_cap)); 3029 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3030 if (err) { 3031 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3032 goto err_fw; 3033 } 3034 3035 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3036 goto err_fw; 3037 } 3038 } 3039 3040 err = mlx4_init_hca(dev); 3041 if (err) { 3042 if (err == -EACCES) { 3043 /* Not primary Physical function 3044 * Running in slave mode */ 3045 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3046 /* We're not a PF */ 3047 if (dev->flags & MLX4_FLAG_SRIOV) { 3048 if (!existing_vfs) 3049 pci_disable_sriov(pdev); 3050 if (mlx4_is_master(dev) && !reset_flow) 3051 atomic_dec(&pf_loading); 3052 dev->flags &= ~MLX4_FLAG_SRIOV; 3053 } 3054 if (!mlx4_is_slave(dev)) 3055 mlx4_free_ownership(dev); 3056 dev->flags |= MLX4_FLAG_SLAVE; 3057 dev->flags &= ~MLX4_FLAG_MASTER; 3058 goto slave_start; 3059 } else 3060 goto err_fw; 3061 } 3062 3063 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3064 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3065 existing_vfs, reset_flow); 3066 3067 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3068 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3069 dev->flags = dev_flags; 3070 err = mlx4_cmd_init(dev); 3071 if (err) { 3072 /* Only VHCR is cleaned up, so could still 3073 * send FW commands 3074 */ 3075 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3076 goto err_close; 3077 } 3078 } else { 3079 dev->flags = dev_flags; 3080 } 3081 3082 if (!SRIOV_VALID_STATE(dev->flags)) { 3083 mlx4_err(dev, "Invalid SRIOV state\n"); 3084 goto err_close; 3085 } 3086 } 3087 3088 /* check if the device is functioning at its maximum possible speed. 3089 * No return code for this call, just warn the user in case of PCI 3090 * express device capabilities are under-satisfied by the bus. 3091 */ 3092 if (!mlx4_is_slave(dev)) 3093 mlx4_check_pcie_caps(dev); 3094 3095 /* In master functions, the communication channel must be initialized 3096 * after obtaining its address from fw */ 3097 if (mlx4_is_master(dev)) { 3098 if (dev->caps.num_ports < 2 && 3099 num_vfs_argc > 1) { 3100 err = -EINVAL; 3101 mlx4_err(dev, 3102 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3103 dev->caps.num_ports); 3104 goto err_close; 3105 } 3106 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3107 3108 for (i = 0; 3109 i < sizeof(dev->persist->nvfs)/ 3110 sizeof(dev->persist->nvfs[0]); i++) { 3111 unsigned j; 3112 3113 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3114 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3115 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3116 dev->caps.num_ports; 3117 } 3118 } 3119 3120 /* In master functions, the communication channel 3121 * must be initialized after obtaining its address from fw 3122 */ 3123 err = mlx4_multi_func_init(dev); 3124 if (err) { 3125 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3126 goto err_close; 3127 } 3128 } 3129 3130 err = mlx4_alloc_eq_table(dev); 3131 if (err) 3132 goto err_master_mfunc; 3133 3134 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3135 mutex_init(&priv->msix_ctl.pool_lock); 3136 3137 mlx4_enable_msi_x(dev); 3138 if ((mlx4_is_mfunc(dev)) && 3139 !(dev->flags & MLX4_FLAG_MSI_X)) { 3140 err = -ENOSYS; 3141 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3142 goto err_free_eq; 3143 } 3144 3145 if (!mlx4_is_slave(dev)) { 3146 err = mlx4_init_steering(dev); 3147 if (err) 3148 goto err_disable_msix; 3149 } 3150 3151 err = mlx4_setup_hca(dev); 3152 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3153 !mlx4_is_mfunc(dev)) { 3154 dev->flags &= ~MLX4_FLAG_MSI_X; 3155 dev->caps.num_comp_vectors = 1; 3156 pci_disable_msix(pdev); 3157 err = mlx4_setup_hca(dev); 3158 } 3159 3160 if (err) 3161 goto err_steer; 3162 3163 mlx4_init_quotas(dev); 3164 /* When PF resources are ready arm its comm channel to enable 3165 * getting commands 3166 */ 3167 if (mlx4_is_master(dev)) { 3168 err = mlx4_ARM_COMM_CHANNEL(dev); 3169 if (err) { 3170 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3171 err); 3172 goto err_steer; 3173 } 3174 } 3175 3176 for (port = 1; port <= dev->caps.num_ports; port++) { 3177 err = mlx4_init_port_info(dev, port); 3178 if (err) 3179 goto err_port; 3180 } 3181 3182 priv->v2p.port1 = 1; 3183 priv->v2p.port2 = 2; 3184 3185 err = mlx4_register_device(dev); 3186 if (err) 3187 goto err_port; 3188 3189 mlx4_request_modules(dev); 3190 3191 mlx4_sense_init(dev); 3192 mlx4_start_sense(dev); 3193 3194 priv->removed = 0; 3195 3196 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3197 atomic_dec(&pf_loading); 3198 3199 kfree(dev_cap); 3200 return 0; 3201 3202 err_port: 3203 for (--port; port >= 1; --port) 3204 mlx4_cleanup_port_info(&priv->port[port]); 3205 3206 mlx4_cleanup_counters_table(dev); 3207 mlx4_cleanup_qp_table(dev); 3208 mlx4_cleanup_srq_table(dev); 3209 mlx4_cleanup_cq_table(dev); 3210 mlx4_cmd_use_polling(dev); 3211 mlx4_cleanup_eq_table(dev); 3212 mlx4_cleanup_mcg_table(dev); 3213 mlx4_cleanup_mr_table(dev); 3214 mlx4_cleanup_xrcd_table(dev); 3215 mlx4_cleanup_pd_table(dev); 3216 mlx4_cleanup_uar_table(dev); 3217 3218 err_steer: 3219 if (!mlx4_is_slave(dev)) 3220 mlx4_clear_steering(dev); 3221 3222 err_disable_msix: 3223 if (dev->flags & MLX4_FLAG_MSI_X) 3224 pci_disable_msix(pdev); 3225 3226 err_free_eq: 3227 mlx4_free_eq_table(dev); 3228 3229 err_master_mfunc: 3230 if (mlx4_is_master(dev)) { 3231 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3232 mlx4_multi_func_cleanup(dev); 3233 } 3234 3235 if (mlx4_is_slave(dev)) { 3236 kfree(dev->caps.qp0_qkey); 3237 kfree(dev->caps.qp0_tunnel); 3238 kfree(dev->caps.qp0_proxy); 3239 kfree(dev->caps.qp1_tunnel); 3240 kfree(dev->caps.qp1_proxy); 3241 } 3242 3243 err_close: 3244 mlx4_close_hca(dev); 3245 3246 err_fw: 3247 mlx4_close_fw(dev); 3248 3249 err_mfunc: 3250 if (mlx4_is_slave(dev)) 3251 mlx4_multi_func_cleanup(dev); 3252 3253 err_cmd: 3254 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3255 3256 err_sriov: 3257 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3258 pci_disable_sriov(pdev); 3259 dev->flags &= ~MLX4_FLAG_SRIOV; 3260 } 3261 3262 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3263 atomic_dec(&pf_loading); 3264 3265 kfree(priv->dev.dev_vfs); 3266 3267 if (!mlx4_is_slave(dev)) 3268 mlx4_free_ownership(dev); 3269 3270 kfree(dev_cap); 3271 return err; 3272 } 3273 3274 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3275 struct mlx4_priv *priv) 3276 { 3277 int err; 3278 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3279 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3280 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3281 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3282 unsigned total_vfs = 0; 3283 unsigned int i; 3284 3285 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3286 3287 err = pci_enable_device(pdev); 3288 if (err) { 3289 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3290 return err; 3291 } 3292 3293 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3294 * per port, we must limit the number of VFs to 63 (since their are 3295 * 128 MACs) 3296 */ 3297 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 3298 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3299 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3300 if (nvfs[i] < 0) { 3301 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3302 err = -EINVAL; 3303 goto err_disable_pdev; 3304 } 3305 } 3306 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 3307 i++) { 3308 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3309 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3310 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3311 err = -EINVAL; 3312 goto err_disable_pdev; 3313 } 3314 } 3315 if (total_vfs >= MLX4_MAX_NUM_VF) { 3316 dev_err(&pdev->dev, 3317 "Requested more VF's (%d) than allowed (%d)\n", 3318 total_vfs, MLX4_MAX_NUM_VF - 1); 3319 err = -EINVAL; 3320 goto err_disable_pdev; 3321 } 3322 3323 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3324 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { 3325 dev_err(&pdev->dev, 3326 "Requested more VF's (%d) for port (%d) than allowed (%d)\n", 3327 nvfs[i] + nvfs[2], i + 1, 3328 MLX4_MAX_NUM_VF_P_PORT - 1); 3329 err = -EINVAL; 3330 goto err_disable_pdev; 3331 } 3332 } 3333 3334 /* Check for BARs. */ 3335 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3336 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3337 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3338 pci_dev_data, pci_resource_flags(pdev, 0)); 3339 err = -ENODEV; 3340 goto err_disable_pdev; 3341 } 3342 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3343 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3344 err = -ENODEV; 3345 goto err_disable_pdev; 3346 } 3347 3348 err = pci_request_regions(pdev, DRV_NAME); 3349 if (err) { 3350 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3351 goto err_disable_pdev; 3352 } 3353 3354 pci_set_master(pdev); 3355 3356 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3357 if (err) { 3358 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3359 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3360 if (err) { 3361 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3362 goto err_release_regions; 3363 } 3364 } 3365 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3366 if (err) { 3367 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3368 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3369 if (err) { 3370 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3371 goto err_release_regions; 3372 } 3373 } 3374 3375 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3376 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3377 /* Detect if this device is a virtual function */ 3378 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3379 /* When acting as pf, we normally skip vfs unless explicitly 3380 * requested to probe them. 3381 */ 3382 if (total_vfs) { 3383 unsigned vfs_offset = 0; 3384 3385 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 3386 vfs_offset + nvfs[i] < extended_func_num(pdev); 3387 vfs_offset += nvfs[i], i++) 3388 ; 3389 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 3390 err = -ENODEV; 3391 goto err_release_regions; 3392 } 3393 if ((extended_func_num(pdev) - vfs_offset) 3394 > prb_vf[i]) { 3395 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3396 extended_func_num(pdev)); 3397 err = -ENODEV; 3398 goto err_release_regions; 3399 } 3400 } 3401 } 3402 3403 err = mlx4_catas_init(&priv->dev); 3404 if (err) 3405 goto err_release_regions; 3406 3407 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3408 if (err) 3409 goto err_catas; 3410 3411 return 0; 3412 3413 err_catas: 3414 mlx4_catas_end(&priv->dev); 3415 3416 err_release_regions: 3417 pci_release_regions(pdev); 3418 3419 err_disable_pdev: 3420 pci_disable_device(pdev); 3421 pci_set_drvdata(pdev, NULL); 3422 return err; 3423 } 3424 3425 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3426 { 3427 struct mlx4_priv *priv; 3428 struct mlx4_dev *dev; 3429 int ret; 3430 3431 printk_once(KERN_INFO "%s", mlx4_version); 3432 3433 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 3434 if (!priv) 3435 return -ENOMEM; 3436 3437 dev = &priv->dev; 3438 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3439 if (!dev->persist) { 3440 kfree(priv); 3441 return -ENOMEM; 3442 } 3443 dev->persist->pdev = pdev; 3444 dev->persist->dev = dev; 3445 pci_set_drvdata(pdev, dev->persist); 3446 priv->pci_dev_data = id->driver_data; 3447 mutex_init(&dev->persist->device_state_mutex); 3448 mutex_init(&dev->persist->interface_state_mutex); 3449 3450 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3451 if (ret) { 3452 kfree(dev->persist); 3453 kfree(priv); 3454 } else { 3455 pci_save_state(pdev); 3456 } 3457 3458 return ret; 3459 } 3460 3461 static void mlx4_clean_dev(struct mlx4_dev *dev) 3462 { 3463 struct mlx4_dev_persistent *persist = dev->persist; 3464 struct mlx4_priv *priv = mlx4_priv(dev); 3465 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 3466 3467 memset(priv, 0, sizeof(*priv)); 3468 priv->dev.persist = persist; 3469 priv->dev.flags = flags; 3470 } 3471 3472 static void mlx4_unload_one(struct pci_dev *pdev) 3473 { 3474 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3475 struct mlx4_dev *dev = persist->dev; 3476 struct mlx4_priv *priv = mlx4_priv(dev); 3477 int pci_dev_data; 3478 int p, i; 3479 3480 if (priv->removed) 3481 return; 3482 3483 /* saving current ports type for further use */ 3484 for (i = 0; i < dev->caps.num_ports; i++) { 3485 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 3486 dev->persist->curr_port_poss_type[i] = dev->caps. 3487 possible_type[i + 1]; 3488 } 3489 3490 pci_dev_data = priv->pci_dev_data; 3491 3492 mlx4_stop_sense(dev); 3493 mlx4_unregister_device(dev); 3494 3495 for (p = 1; p <= dev->caps.num_ports; p++) { 3496 mlx4_cleanup_port_info(&priv->port[p]); 3497 mlx4_CLOSE_PORT(dev, p); 3498 } 3499 3500 if (mlx4_is_master(dev)) 3501 mlx4_free_resource_tracker(dev, 3502 RES_TR_FREE_SLAVES_ONLY); 3503 3504 mlx4_cleanup_counters_table(dev); 3505 mlx4_cleanup_qp_table(dev); 3506 mlx4_cleanup_srq_table(dev); 3507 mlx4_cleanup_cq_table(dev); 3508 mlx4_cmd_use_polling(dev); 3509 mlx4_cleanup_eq_table(dev); 3510 mlx4_cleanup_mcg_table(dev); 3511 mlx4_cleanup_mr_table(dev); 3512 mlx4_cleanup_xrcd_table(dev); 3513 mlx4_cleanup_pd_table(dev); 3514 3515 if (mlx4_is_master(dev)) 3516 mlx4_free_resource_tracker(dev, 3517 RES_TR_FREE_STRUCTS_ONLY); 3518 3519 iounmap(priv->kar); 3520 mlx4_uar_free(dev, &priv->driver_uar); 3521 mlx4_cleanup_uar_table(dev); 3522 if (!mlx4_is_slave(dev)) 3523 mlx4_clear_steering(dev); 3524 mlx4_free_eq_table(dev); 3525 if (mlx4_is_master(dev)) 3526 mlx4_multi_func_cleanup(dev); 3527 mlx4_close_hca(dev); 3528 mlx4_close_fw(dev); 3529 if (mlx4_is_slave(dev)) 3530 mlx4_multi_func_cleanup(dev); 3531 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3532 3533 if (dev->flags & MLX4_FLAG_MSI_X) 3534 pci_disable_msix(pdev); 3535 3536 if (!mlx4_is_slave(dev)) 3537 mlx4_free_ownership(dev); 3538 3539 kfree(dev->caps.qp0_qkey); 3540 kfree(dev->caps.qp0_tunnel); 3541 kfree(dev->caps.qp0_proxy); 3542 kfree(dev->caps.qp1_tunnel); 3543 kfree(dev->caps.qp1_proxy); 3544 kfree(dev->dev_vfs); 3545 3546 mlx4_clean_dev(dev); 3547 priv->pci_dev_data = pci_dev_data; 3548 priv->removed = 1; 3549 } 3550 3551 static void mlx4_remove_one(struct pci_dev *pdev) 3552 { 3553 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3554 struct mlx4_dev *dev = persist->dev; 3555 struct mlx4_priv *priv = mlx4_priv(dev); 3556 int active_vfs = 0; 3557 3558 mutex_lock(&persist->interface_state_mutex); 3559 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 3560 mutex_unlock(&persist->interface_state_mutex); 3561 3562 /* Disabling SR-IOV is not allowed while there are active vf's */ 3563 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 3564 active_vfs = mlx4_how_many_lives_vf(dev); 3565 if (active_vfs) { 3566 pr_warn("Removing PF when there are active VF's !!\n"); 3567 pr_warn("Will not disable SR-IOV.\n"); 3568 } 3569 } 3570 3571 /* device marked to be under deletion running now without the lock 3572 * letting other tasks to be terminated 3573 */ 3574 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3575 mlx4_unload_one(pdev); 3576 else 3577 mlx4_info(dev, "%s: interface is down\n", __func__); 3578 mlx4_catas_end(dev); 3579 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 3580 mlx4_warn(dev, "Disabling SR-IOV\n"); 3581 pci_disable_sriov(pdev); 3582 } 3583 3584 pci_release_regions(pdev); 3585 pci_disable_device(pdev); 3586 kfree(dev->persist); 3587 kfree(priv); 3588 pci_set_drvdata(pdev, NULL); 3589 } 3590 3591 static int restore_current_port_types(struct mlx4_dev *dev, 3592 enum mlx4_port_type *types, 3593 enum mlx4_port_type *poss_types) 3594 { 3595 struct mlx4_priv *priv = mlx4_priv(dev); 3596 int err, i; 3597 3598 mlx4_stop_sense(dev); 3599 3600 mutex_lock(&priv->port_mutex); 3601 for (i = 0; i < dev->caps.num_ports; i++) 3602 dev->caps.possible_type[i + 1] = poss_types[i]; 3603 err = mlx4_change_port_types(dev, types); 3604 mlx4_start_sense(dev); 3605 mutex_unlock(&priv->port_mutex); 3606 3607 return err; 3608 } 3609 3610 int mlx4_restart_one(struct pci_dev *pdev) 3611 { 3612 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3613 struct mlx4_dev *dev = persist->dev; 3614 struct mlx4_priv *priv = mlx4_priv(dev); 3615 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3616 int pci_dev_data, err, total_vfs; 3617 3618 pci_dev_data = priv->pci_dev_data; 3619 total_vfs = dev->persist->num_vfs; 3620 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 3621 3622 mlx4_unload_one(pdev); 3623 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 3624 if (err) { 3625 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 3626 __func__, pci_name(pdev), err); 3627 return err; 3628 } 3629 3630 err = restore_current_port_types(dev, dev->persist->curr_port_type, 3631 dev->persist->curr_port_poss_type); 3632 if (err) 3633 mlx4_err(dev, "could not restore original port types (%d)\n", 3634 err); 3635 3636 return err; 3637 } 3638 3639 static const struct pci_device_id mlx4_pci_table[] = { 3640 /* MT25408 "Hermon" SDR */ 3641 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3642 /* MT25408 "Hermon" DDR */ 3643 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3644 /* MT25408 "Hermon" QDR */ 3645 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3646 /* MT25408 "Hermon" DDR PCIe gen2 */ 3647 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3648 /* MT25408 "Hermon" QDR PCIe gen2 */ 3649 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3650 /* MT25408 "Hermon" EN 10GigE */ 3651 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3652 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 3653 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3654 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 3655 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3656 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 3657 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3658 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 3659 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3660 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 3661 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3662 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 3663 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3664 /* MT25400 Family [ConnectX-2 Virtual Function] */ 3665 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 3666 /* MT27500 Family [ConnectX-3] */ 3667 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 3668 /* MT27500 Family [ConnectX-3 Virtual Function] */ 3669 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 3670 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 3671 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 3672 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 3673 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 3674 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 3675 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 3676 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 3677 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 3678 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 3679 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 3680 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 3681 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 3682 { 0, } 3683 }; 3684 3685 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 3686 3687 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 3688 pci_channel_state_t state) 3689 { 3690 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3691 3692 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 3693 mlx4_enter_error_state(persist); 3694 3695 mutex_lock(&persist->interface_state_mutex); 3696 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3697 mlx4_unload_one(pdev); 3698 3699 mutex_unlock(&persist->interface_state_mutex); 3700 if (state == pci_channel_io_perm_failure) 3701 return PCI_ERS_RESULT_DISCONNECT; 3702 3703 pci_disable_device(pdev); 3704 return PCI_ERS_RESULT_NEED_RESET; 3705 } 3706 3707 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 3708 { 3709 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3710 struct mlx4_dev *dev = persist->dev; 3711 struct mlx4_priv *priv = mlx4_priv(dev); 3712 int ret; 3713 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3714 int total_vfs; 3715 3716 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 3717 ret = pci_enable_device(pdev); 3718 if (ret) { 3719 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret); 3720 return PCI_ERS_RESULT_DISCONNECT; 3721 } 3722 3723 pci_set_master(pdev); 3724 pci_restore_state(pdev); 3725 pci_save_state(pdev); 3726 3727 total_vfs = dev->persist->num_vfs; 3728 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 3729 3730 mutex_lock(&persist->interface_state_mutex); 3731 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 3732 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 3733 priv, 1); 3734 if (ret) { 3735 mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n", 3736 __func__, ret); 3737 goto end; 3738 } 3739 3740 ret = restore_current_port_types(dev, dev->persist-> 3741 curr_port_type, dev->persist-> 3742 curr_port_poss_type); 3743 if (ret) 3744 mlx4_err(dev, "could not restore original port types (%d)\n", ret); 3745 } 3746 end: 3747 mutex_unlock(&persist->interface_state_mutex); 3748 3749 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 3750 } 3751 3752 static void mlx4_shutdown(struct pci_dev *pdev) 3753 { 3754 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 3755 3756 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 3757 mutex_lock(&persist->interface_state_mutex); 3758 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 3759 mlx4_unload_one(pdev); 3760 mutex_unlock(&persist->interface_state_mutex); 3761 } 3762 3763 static const struct pci_error_handlers mlx4_err_handler = { 3764 .error_detected = mlx4_pci_err_detected, 3765 .slot_reset = mlx4_pci_slot_reset, 3766 }; 3767 3768 static struct pci_driver mlx4_driver = { 3769 .name = DRV_NAME, 3770 .id_table = mlx4_pci_table, 3771 .probe = mlx4_init_one, 3772 .shutdown = mlx4_shutdown, 3773 .remove = mlx4_remove_one, 3774 .err_handler = &mlx4_err_handler, 3775 }; 3776 3777 static int __init mlx4_verify_params(void) 3778 { 3779 if ((log_num_mac < 0) || (log_num_mac > 7)) { 3780 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 3781 return -1; 3782 } 3783 3784 if (log_num_vlan != 0) 3785 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 3786 MLX4_LOG_NUM_VLANS); 3787 3788 if (use_prio != 0) 3789 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 3790 3791 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 3792 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 3793 log_mtts_per_seg); 3794 return -1; 3795 } 3796 3797 /* Check if module param for ports type has legal combination */ 3798 if (port_type_array[0] == false && port_type_array[1] == true) { 3799 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 3800 port_type_array[0] = true; 3801 } 3802 3803 if (mlx4_log_num_mgm_entry_size < -7 || 3804 (mlx4_log_num_mgm_entry_size > 0 && 3805 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 3806 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 3807 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 3808 mlx4_log_num_mgm_entry_size, 3809 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 3810 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 3811 return -1; 3812 } 3813 3814 return 0; 3815 } 3816 3817 static int __init mlx4_init(void) 3818 { 3819 int ret; 3820 3821 if (mlx4_verify_params()) 3822 return -EINVAL; 3823 3824 3825 mlx4_wq = create_singlethread_workqueue("mlx4"); 3826 if (!mlx4_wq) 3827 return -ENOMEM; 3828 3829 ret = pci_register_driver(&mlx4_driver); 3830 if (ret < 0) 3831 destroy_workqueue(mlx4_wq); 3832 return ret < 0 ? ret : 0; 3833 } 3834 3835 static void __exit mlx4_cleanup(void) 3836 { 3837 pci_unregister_driver(&mlx4_driver); 3838 destroy_workqueue(mlx4_wq); 3839 } 3840 3841 module_init(mlx4_init); 3842 module_exit(mlx4_cleanup); 3843