1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static uint8_t num_vfs[3] = {0, 0, 0}; 81 static int num_vfs_argc = 3; 82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 84 "num_vfs=port1,port2,port1+2"); 85 86 static uint8_t probe_vf[3] = {0, 0, 0}; 87 static int probe_vfs_argc = 3; 88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 90 "probe_vf=port1,port2,port1+2"); 91 92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 93 module_param_named(log_num_mgm_entry_size, 94 mlx4_log_num_mgm_entry_size, int, 0444); 95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 96 " of qp per mcg, for example:" 97 " 10 gives 248.range: 7 <=" 98 " log_num_mgm_entry_size <= 12." 99 " To activate device managed" 100 " flow steering when available, set to -1"); 101 102 static bool enable_64b_cqe_eqe = true; 103 module_param(enable_64b_cqe_eqe, bool, 0444); 104 MODULE_PARM_DESC(enable_64b_cqe_eqe, 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 106 107 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE 108 109 static char mlx4_version[] = 110 DRV_NAME ": Mellanox ConnectX core driver v" 111 DRV_VERSION " (" DRV_RELDATE ")\n"; 112 113 static struct mlx4_profile default_profile = { 114 .num_qp = 1 << 18, 115 .num_srq = 1 << 16, 116 .rdmarc_per_qp = 1 << 4, 117 .num_cq = 1 << 16, 118 .num_mcg = 1 << 13, 119 .num_mpt = 1 << 19, 120 .num_mtt = 1 << 20, /* It is really num mtt segements */ 121 }; 122 123 static struct mlx4_profile low_mem_profile = { 124 .num_qp = 1 << 17, 125 .num_srq = 1 << 6, 126 .rdmarc_per_qp = 1 << 4, 127 .num_cq = 1 << 8, 128 .num_mcg = 1 << 8, 129 .num_mpt = 1 << 9, 130 .num_mtt = 1 << 7, 131 }; 132 133 static int log_num_mac = 7; 134 module_param_named(log_num_mac, log_num_mac, int, 0444); 135 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 136 137 static int log_num_vlan; 138 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 139 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 140 /* Log2 max number of VLANs per ETH port (0-7) */ 141 #define MLX4_LOG_NUM_VLANS 7 142 #define MLX4_MIN_LOG_NUM_VLANS 0 143 #define MLX4_MIN_LOG_NUM_MAC 1 144 145 static bool use_prio; 146 module_param_named(use_prio, use_prio, bool, 0444); 147 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 148 149 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 150 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 151 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 152 153 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 154 static int arr_argc = 2; 155 module_param_array(port_type_array, int, &arr_argc, 0444); 156 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 157 "1 for IB, 2 for Ethernet"); 158 159 struct mlx4_port_config { 160 struct list_head list; 161 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 162 struct pci_dev *pdev; 163 }; 164 165 static atomic_t pf_loading = ATOMIC_INIT(0); 166 167 int mlx4_check_port_params(struct mlx4_dev *dev, 168 enum mlx4_port_type *port_type) 169 { 170 int i; 171 172 for (i = 0; i < dev->caps.num_ports - 1; i++) { 173 if (port_type[i] != port_type[i + 1]) { 174 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 175 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 176 return -EINVAL; 177 } 178 } 179 } 180 181 for (i = 0; i < dev->caps.num_ports; i++) { 182 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 183 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 184 i + 1); 185 return -EINVAL; 186 } 187 } 188 return 0; 189 } 190 191 static void mlx4_set_port_mask(struct mlx4_dev *dev) 192 { 193 int i; 194 195 for (i = 1; i <= dev->caps.num_ports; ++i) 196 dev->caps.port_mask[i] = dev->caps.port_type[i]; 197 } 198 199 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 200 { 201 int err; 202 int i; 203 204 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 205 if (err) { 206 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 207 return err; 208 } 209 210 if (dev_cap->min_page_sz > PAGE_SIZE) { 211 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 212 dev_cap->min_page_sz, PAGE_SIZE); 213 return -ENODEV; 214 } 215 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 216 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 217 dev_cap->num_ports, MLX4_MAX_PORTS); 218 return -ENODEV; 219 } 220 221 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 222 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 223 dev_cap->uar_size, 224 (unsigned long long) pci_resource_len(dev->pdev, 2)); 225 return -ENODEV; 226 } 227 228 dev->caps.num_ports = dev_cap->num_ports; 229 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; 230 for (i = 1; i <= dev->caps.num_ports; ++i) { 231 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 232 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 233 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 234 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 235 /* set gid and pkey table operating lengths by default 236 * to non-sriov values */ 237 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 238 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 239 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 240 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 241 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 242 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 243 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 244 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 245 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 246 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 247 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 248 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 249 } 250 251 dev->caps.uar_page_size = PAGE_SIZE; 252 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 253 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 254 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 255 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 256 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 257 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 258 dev->caps.max_wqes = dev_cap->max_qp_sz; 259 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 260 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 261 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 262 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 263 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 264 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 265 /* 266 * Subtract 1 from the limit because we need to allocate a 267 * spare CQE so the HCA HW can tell the difference between an 268 * empty CQ and a full CQ. 269 */ 270 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 271 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 272 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 273 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 274 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 275 276 /* The first 128 UARs are used for EQ doorbells */ 277 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 278 dev->caps.reserved_pds = dev_cap->reserved_pds; 279 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 280 dev_cap->reserved_xrcds : 0; 281 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 282 dev_cap->max_xrcds : 0; 283 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 284 285 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 286 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 287 dev->caps.flags = dev_cap->flags; 288 dev->caps.flags2 = dev_cap->flags2; 289 dev->caps.bmme_flags = dev_cap->bmme_flags; 290 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 291 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 292 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 293 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 294 295 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 296 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 297 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 298 /* Don't do sense port on multifunction devices (for now at least) */ 299 if (mlx4_is_mfunc(dev)) 300 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 301 302 if (mlx4_low_memory_profile()) { 303 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 304 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 305 } else { 306 dev->caps.log_num_macs = log_num_mac; 307 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 308 } 309 310 for (i = 1; i <= dev->caps.num_ports; ++i) { 311 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 312 if (dev->caps.supported_type[i]) { 313 /* if only ETH is supported - assign ETH */ 314 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 315 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 316 /* if only IB is supported, assign IB */ 317 else if (dev->caps.supported_type[i] == 318 MLX4_PORT_TYPE_IB) 319 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 320 else { 321 /* if IB and ETH are supported, we set the port 322 * type according to user selection of port type; 323 * if user selected none, take the FW hint */ 324 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 325 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 326 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 327 else 328 dev->caps.port_type[i] = port_type_array[i - 1]; 329 } 330 } 331 /* 332 * Link sensing is allowed on the port if 3 conditions are true: 333 * 1. Both protocols are supported on the port. 334 * 2. Different types are supported on the port 335 * 3. FW declared that it supports link sensing 336 */ 337 mlx4_priv(dev)->sense.sense_allowed[i] = 338 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 339 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 340 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 341 342 /* 343 * If "default_sense" bit is set, we move the port to "AUTO" mode 344 * and perform sense_port FW command to try and set the correct 345 * port type from beginning 346 */ 347 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 348 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 349 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 350 mlx4_SENSE_PORT(dev, i, &sensed_port); 351 if (sensed_port != MLX4_PORT_TYPE_NONE) 352 dev->caps.port_type[i] = sensed_port; 353 } else { 354 dev->caps.possible_type[i] = dev->caps.port_type[i]; 355 } 356 357 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 358 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 359 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 360 i, 1 << dev->caps.log_num_macs); 361 } 362 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 363 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 364 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 365 i, 1 << dev->caps.log_num_vlans); 366 } 367 } 368 369 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 370 371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 372 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 374 (1 << dev->caps.log_num_macs) * 375 (1 << dev->caps.log_num_vlans) * 376 dev->caps.num_ports; 377 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 378 379 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 380 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 381 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 382 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 383 384 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 385 386 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 387 if (dev_cap->flags & 388 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 389 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 390 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 391 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 392 } 393 } 394 395 if ((dev->caps.flags & 396 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 397 mlx4_is_master(dev)) 398 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 399 400 return 0; 401 } 402 403 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 404 enum pci_bus_speed *speed, 405 enum pcie_link_width *width) 406 { 407 u32 lnkcap1, lnkcap2; 408 int err1, err2; 409 410 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 411 412 *speed = PCI_SPEED_UNKNOWN; 413 *width = PCIE_LNK_WIDTH_UNKNOWN; 414 415 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1); 416 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2); 417 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 418 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 419 *speed = PCIE_SPEED_8_0GT; 420 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 421 *speed = PCIE_SPEED_5_0GT; 422 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 423 *speed = PCIE_SPEED_2_5GT; 424 } 425 if (!err1) { 426 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 427 if (!lnkcap2) { /* pre-r3.0 */ 428 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 429 *speed = PCIE_SPEED_5_0GT; 430 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 431 *speed = PCIE_SPEED_2_5GT; 432 } 433 } 434 435 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 436 return err1 ? err1 : 437 err2 ? err2 : -EINVAL; 438 } 439 return 0; 440 } 441 442 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 443 { 444 enum pcie_link_width width, width_cap; 445 enum pci_bus_speed speed, speed_cap; 446 int err; 447 448 #define PCIE_SPEED_STR(speed) \ 449 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 450 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 451 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 452 "Unknown") 453 454 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 455 if (err) { 456 mlx4_warn(dev, 457 "Unable to determine PCIe device BW capabilities\n"); 458 return; 459 } 460 461 err = pcie_get_minimum_link(dev->pdev, &speed, &width); 462 if (err || speed == PCI_SPEED_UNKNOWN || 463 width == PCIE_LNK_WIDTH_UNKNOWN) { 464 mlx4_warn(dev, 465 "Unable to determine PCI device chain minimum BW\n"); 466 return; 467 } 468 469 if (width != width_cap || speed != speed_cap) 470 mlx4_warn(dev, 471 "PCIe BW is different than device's capability\n"); 472 473 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 474 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 475 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 476 width, width_cap); 477 return; 478 } 479 480 /*The function checks if there are live vf, return the num of them*/ 481 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 482 { 483 struct mlx4_priv *priv = mlx4_priv(dev); 484 struct mlx4_slave_state *s_state; 485 int i; 486 int ret = 0; 487 488 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 489 s_state = &priv->mfunc.master.slave_state[i]; 490 if (s_state->active && s_state->last_cmd != 491 MLX4_COMM_CMD_RESET) { 492 mlx4_warn(dev, "%s: slave: %d is still active\n", 493 __func__, i); 494 ret++; 495 } 496 } 497 return ret; 498 } 499 500 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 501 { 502 u32 qk = MLX4_RESERVED_QKEY_BASE; 503 504 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 505 qpn < dev->phys_caps.base_proxy_sqpn) 506 return -EINVAL; 507 508 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 509 /* tunnel qp */ 510 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 511 else 512 qk += qpn - dev->phys_caps.base_proxy_sqpn; 513 *qkey = qk; 514 return 0; 515 } 516 EXPORT_SYMBOL(mlx4_get_parav_qkey); 517 518 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 519 { 520 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 521 522 if (!mlx4_is_master(dev)) 523 return; 524 525 priv->virt2phys_pkey[slave][port - 1][i] = val; 526 } 527 EXPORT_SYMBOL(mlx4_sync_pkey_table); 528 529 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 530 { 531 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 532 533 if (!mlx4_is_master(dev)) 534 return; 535 536 priv->slave_node_guids[slave] = guid; 537 } 538 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 539 540 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 541 { 542 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 543 544 if (!mlx4_is_master(dev)) 545 return 0; 546 547 return priv->slave_node_guids[slave]; 548 } 549 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 550 551 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 552 { 553 struct mlx4_priv *priv = mlx4_priv(dev); 554 struct mlx4_slave_state *s_slave; 555 556 if (!mlx4_is_master(dev)) 557 return 0; 558 559 s_slave = &priv->mfunc.master.slave_state[slave]; 560 return !!s_slave->active; 561 } 562 EXPORT_SYMBOL(mlx4_is_slave_active); 563 564 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 565 struct mlx4_dev_cap *dev_cap, 566 struct mlx4_init_hca_param *hca_param) 567 { 568 dev->caps.steering_mode = hca_param->steering_mode; 569 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 570 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 571 dev->caps.fs_log_max_ucast_qp_range_size = 572 dev_cap->fs_log_max_ucast_qp_range_size; 573 } else 574 dev->caps.num_qp_per_mgm = 575 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 576 577 mlx4_dbg(dev, "Steering mode is: %s\n", 578 mlx4_steering_mode_str(dev->caps.steering_mode)); 579 } 580 581 static int mlx4_slave_cap(struct mlx4_dev *dev) 582 { 583 int err; 584 u32 page_size; 585 struct mlx4_dev_cap dev_cap; 586 struct mlx4_func_cap func_cap; 587 struct mlx4_init_hca_param hca_param; 588 int i; 589 590 memset(&hca_param, 0, sizeof(hca_param)); 591 err = mlx4_QUERY_HCA(dev, &hca_param); 592 if (err) { 593 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 594 return err; 595 } 596 597 /* fail if the hca has an unknown global capability 598 * at this time global_caps should be always zeroed 599 */ 600 if (hca_param.global_caps) { 601 mlx4_err(dev, "Unknown hca global capabilities\n"); 602 return -ENOSYS; 603 } 604 605 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 606 607 dev->caps.hca_core_clock = hca_param.hca_core_clock; 608 609 memset(&dev_cap, 0, sizeof(dev_cap)); 610 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 611 err = mlx4_dev_cap(dev, &dev_cap); 612 if (err) { 613 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 614 return err; 615 } 616 617 err = mlx4_QUERY_FW(dev); 618 if (err) 619 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 620 621 page_size = ~dev->caps.page_size_cap + 1; 622 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 623 if (page_size > PAGE_SIZE) { 624 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 625 page_size, PAGE_SIZE); 626 return -ENODEV; 627 } 628 629 /* slave gets uar page size from QUERY_HCA fw command */ 630 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 631 632 /* TODO: relax this assumption */ 633 if (dev->caps.uar_page_size != PAGE_SIZE) { 634 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 635 dev->caps.uar_page_size, PAGE_SIZE); 636 return -ENODEV; 637 } 638 639 memset(&func_cap, 0, sizeof(func_cap)); 640 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 641 if (err) { 642 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 643 err); 644 return err; 645 } 646 647 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 648 PF_CONTEXT_BEHAVIOUR_MASK) { 649 mlx4_err(dev, "Unknown pf context behaviour\n"); 650 return -ENOSYS; 651 } 652 653 dev->caps.num_ports = func_cap.num_ports; 654 dev->quotas.qp = func_cap.qp_quota; 655 dev->quotas.srq = func_cap.srq_quota; 656 dev->quotas.cq = func_cap.cq_quota; 657 dev->quotas.mpt = func_cap.mpt_quota; 658 dev->quotas.mtt = func_cap.mtt_quota; 659 dev->caps.num_qps = 1 << hca_param.log_num_qps; 660 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 661 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 662 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 663 dev->caps.num_eqs = func_cap.max_eq; 664 dev->caps.reserved_eqs = func_cap.reserved_eq; 665 dev->caps.num_pds = MLX4_NUM_PDS; 666 dev->caps.num_mgms = 0; 667 dev->caps.num_amgms = 0; 668 669 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 670 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 671 dev->caps.num_ports, MLX4_MAX_PORTS); 672 return -ENODEV; 673 } 674 675 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); 676 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 677 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 678 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 679 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 680 681 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 682 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || 683 !dev->caps.qp0_qkey) { 684 err = -ENOMEM; 685 goto err_mem; 686 } 687 688 for (i = 1; i <= dev->caps.num_ports; ++i) { 689 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); 690 if (err) { 691 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 692 i, err); 693 goto err_mem; 694 } 695 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; 696 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 697 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 698 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 699 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 700 dev->caps.port_mask[i] = dev->caps.port_type[i]; 701 dev->caps.phys_port_id[i] = func_cap.phys_port_id; 702 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 703 &dev->caps.gid_table_len[i], 704 &dev->caps.pkey_table_len[i])) 705 goto err_mem; 706 } 707 708 if (dev->caps.uar_page_size * (dev->caps.num_uars - 709 dev->caps.reserved_uars) > 710 pci_resource_len(dev->pdev, 2)) { 711 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 712 dev->caps.uar_page_size * dev->caps.num_uars, 713 (unsigned long long) pci_resource_len(dev->pdev, 2)); 714 goto err_mem; 715 } 716 717 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 718 dev->caps.eqe_size = 64; 719 dev->caps.eqe_factor = 1; 720 } else { 721 dev->caps.eqe_size = 32; 722 dev->caps.eqe_factor = 0; 723 } 724 725 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 726 dev->caps.cqe_size = 64; 727 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 728 } else { 729 dev->caps.cqe_size = 32; 730 } 731 732 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 733 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 734 735 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 736 737 return 0; 738 739 err_mem: 740 kfree(dev->caps.qp0_qkey); 741 kfree(dev->caps.qp0_tunnel); 742 kfree(dev->caps.qp0_proxy); 743 kfree(dev->caps.qp1_tunnel); 744 kfree(dev->caps.qp1_proxy); 745 dev->caps.qp0_qkey = NULL; 746 dev->caps.qp0_tunnel = NULL; 747 dev->caps.qp0_proxy = NULL; 748 dev->caps.qp1_tunnel = NULL; 749 dev->caps.qp1_proxy = NULL; 750 751 return err; 752 } 753 754 static void mlx4_request_modules(struct mlx4_dev *dev) 755 { 756 int port; 757 int has_ib_port = false; 758 int has_eth_port = false; 759 #define EN_DRV_NAME "mlx4_en" 760 #define IB_DRV_NAME "mlx4_ib" 761 762 for (port = 1; port <= dev->caps.num_ports; port++) { 763 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 764 has_ib_port = true; 765 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 766 has_eth_port = true; 767 } 768 769 if (has_eth_port) 770 request_module_nowait(EN_DRV_NAME); 771 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 772 request_module_nowait(IB_DRV_NAME); 773 } 774 775 /* 776 * Change the port configuration of the device. 777 * Every user of this function must hold the port mutex. 778 */ 779 int mlx4_change_port_types(struct mlx4_dev *dev, 780 enum mlx4_port_type *port_types) 781 { 782 int err = 0; 783 int change = 0; 784 int port; 785 786 for (port = 0; port < dev->caps.num_ports; port++) { 787 /* Change the port type only if the new type is different 788 * from the current, and not set to Auto */ 789 if (port_types[port] != dev->caps.port_type[port + 1]) 790 change = 1; 791 } 792 if (change) { 793 mlx4_unregister_device(dev); 794 for (port = 1; port <= dev->caps.num_ports; port++) { 795 mlx4_CLOSE_PORT(dev, port); 796 dev->caps.port_type[port] = port_types[port - 1]; 797 err = mlx4_SET_PORT(dev, port, -1); 798 if (err) { 799 mlx4_err(dev, "Failed to set port %d, aborting\n", 800 port); 801 goto out; 802 } 803 } 804 mlx4_set_port_mask(dev); 805 err = mlx4_register_device(dev); 806 if (err) { 807 mlx4_err(dev, "Failed to register device\n"); 808 goto out; 809 } 810 mlx4_request_modules(dev); 811 } 812 813 out: 814 return err; 815 } 816 817 static ssize_t show_port_type(struct device *dev, 818 struct device_attribute *attr, 819 char *buf) 820 { 821 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 822 port_attr); 823 struct mlx4_dev *mdev = info->dev; 824 char type[8]; 825 826 sprintf(type, "%s", 827 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 828 "ib" : "eth"); 829 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 830 sprintf(buf, "auto (%s)\n", type); 831 else 832 sprintf(buf, "%s\n", type); 833 834 return strlen(buf); 835 } 836 837 static ssize_t set_port_type(struct device *dev, 838 struct device_attribute *attr, 839 const char *buf, size_t count) 840 { 841 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 842 port_attr); 843 struct mlx4_dev *mdev = info->dev; 844 struct mlx4_priv *priv = mlx4_priv(mdev); 845 enum mlx4_port_type types[MLX4_MAX_PORTS]; 846 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 847 int i; 848 int err = 0; 849 850 if (!strcmp(buf, "ib\n")) 851 info->tmp_type = MLX4_PORT_TYPE_IB; 852 else if (!strcmp(buf, "eth\n")) 853 info->tmp_type = MLX4_PORT_TYPE_ETH; 854 else if (!strcmp(buf, "auto\n")) 855 info->tmp_type = MLX4_PORT_TYPE_AUTO; 856 else { 857 mlx4_err(mdev, "%s is not supported port type\n", buf); 858 return -EINVAL; 859 } 860 861 mlx4_stop_sense(mdev); 862 mutex_lock(&priv->port_mutex); 863 /* Possible type is always the one that was delivered */ 864 mdev->caps.possible_type[info->port] = info->tmp_type; 865 866 for (i = 0; i < mdev->caps.num_ports; i++) { 867 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 868 mdev->caps.possible_type[i+1]; 869 if (types[i] == MLX4_PORT_TYPE_AUTO) 870 types[i] = mdev->caps.port_type[i+1]; 871 } 872 873 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 874 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 875 for (i = 1; i <= mdev->caps.num_ports; i++) { 876 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 877 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 878 err = -EINVAL; 879 } 880 } 881 } 882 if (err) { 883 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 884 goto out; 885 } 886 887 mlx4_do_sense_ports(mdev, new_types, types); 888 889 err = mlx4_check_port_params(mdev, new_types); 890 if (err) 891 goto out; 892 893 /* We are about to apply the changes after the configuration 894 * was verified, no need to remember the temporary types 895 * any more */ 896 for (i = 0; i < mdev->caps.num_ports; i++) 897 priv->port[i + 1].tmp_type = 0; 898 899 err = mlx4_change_port_types(mdev, new_types); 900 901 out: 902 mlx4_start_sense(mdev); 903 mutex_unlock(&priv->port_mutex); 904 return err ? err : count; 905 } 906 907 enum ibta_mtu { 908 IB_MTU_256 = 1, 909 IB_MTU_512 = 2, 910 IB_MTU_1024 = 3, 911 IB_MTU_2048 = 4, 912 IB_MTU_4096 = 5 913 }; 914 915 static inline int int_to_ibta_mtu(int mtu) 916 { 917 switch (mtu) { 918 case 256: return IB_MTU_256; 919 case 512: return IB_MTU_512; 920 case 1024: return IB_MTU_1024; 921 case 2048: return IB_MTU_2048; 922 case 4096: return IB_MTU_4096; 923 default: return -1; 924 } 925 } 926 927 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 928 { 929 switch (mtu) { 930 case IB_MTU_256: return 256; 931 case IB_MTU_512: return 512; 932 case IB_MTU_1024: return 1024; 933 case IB_MTU_2048: return 2048; 934 case IB_MTU_4096: return 4096; 935 default: return -1; 936 } 937 } 938 939 static ssize_t show_port_ib_mtu(struct device *dev, 940 struct device_attribute *attr, 941 char *buf) 942 { 943 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 944 port_mtu_attr); 945 struct mlx4_dev *mdev = info->dev; 946 947 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 948 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 949 950 sprintf(buf, "%d\n", 951 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 952 return strlen(buf); 953 } 954 955 static ssize_t set_port_ib_mtu(struct device *dev, 956 struct device_attribute *attr, 957 const char *buf, size_t count) 958 { 959 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 960 port_mtu_attr); 961 struct mlx4_dev *mdev = info->dev; 962 struct mlx4_priv *priv = mlx4_priv(mdev); 963 int err, port, mtu, ibta_mtu = -1; 964 965 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 966 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 967 return -EINVAL; 968 } 969 970 err = kstrtoint(buf, 0, &mtu); 971 if (!err) 972 ibta_mtu = int_to_ibta_mtu(mtu); 973 974 if (err || ibta_mtu < 0) { 975 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 976 return -EINVAL; 977 } 978 979 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 980 981 mlx4_stop_sense(mdev); 982 mutex_lock(&priv->port_mutex); 983 mlx4_unregister_device(mdev); 984 for (port = 1; port <= mdev->caps.num_ports; port++) { 985 mlx4_CLOSE_PORT(mdev, port); 986 err = mlx4_SET_PORT(mdev, port, -1); 987 if (err) { 988 mlx4_err(mdev, "Failed to set port %d, aborting\n", 989 port); 990 goto err_set_port; 991 } 992 } 993 err = mlx4_register_device(mdev); 994 err_set_port: 995 mutex_unlock(&priv->port_mutex); 996 mlx4_start_sense(mdev); 997 return err ? err : count; 998 } 999 1000 static int mlx4_load_fw(struct mlx4_dev *dev) 1001 { 1002 struct mlx4_priv *priv = mlx4_priv(dev); 1003 int err; 1004 1005 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1006 GFP_HIGHUSER | __GFP_NOWARN, 0); 1007 if (!priv->fw.fw_icm) { 1008 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1009 return -ENOMEM; 1010 } 1011 1012 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1013 if (err) { 1014 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1015 goto err_free; 1016 } 1017 1018 err = mlx4_RUN_FW(dev); 1019 if (err) { 1020 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1021 goto err_unmap_fa; 1022 } 1023 1024 return 0; 1025 1026 err_unmap_fa: 1027 mlx4_UNMAP_FA(dev); 1028 1029 err_free: 1030 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1031 return err; 1032 } 1033 1034 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1035 int cmpt_entry_sz) 1036 { 1037 struct mlx4_priv *priv = mlx4_priv(dev); 1038 int err; 1039 int num_eqs; 1040 1041 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1042 cmpt_base + 1043 ((u64) (MLX4_CMPT_TYPE_QP * 1044 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1045 cmpt_entry_sz, dev->caps.num_qps, 1046 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1047 0, 0); 1048 if (err) 1049 goto err; 1050 1051 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1052 cmpt_base + 1053 ((u64) (MLX4_CMPT_TYPE_SRQ * 1054 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1055 cmpt_entry_sz, dev->caps.num_srqs, 1056 dev->caps.reserved_srqs, 0, 0); 1057 if (err) 1058 goto err_qp; 1059 1060 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1061 cmpt_base + 1062 ((u64) (MLX4_CMPT_TYPE_CQ * 1063 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1064 cmpt_entry_sz, dev->caps.num_cqs, 1065 dev->caps.reserved_cqs, 0, 0); 1066 if (err) 1067 goto err_srq; 1068 1069 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 1070 dev->caps.num_eqs; 1071 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1072 cmpt_base + 1073 ((u64) (MLX4_CMPT_TYPE_EQ * 1074 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1075 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1076 if (err) 1077 goto err_cq; 1078 1079 return 0; 1080 1081 err_cq: 1082 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1083 1084 err_srq: 1085 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1086 1087 err_qp: 1088 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1089 1090 err: 1091 return err; 1092 } 1093 1094 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1095 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1096 { 1097 struct mlx4_priv *priv = mlx4_priv(dev); 1098 u64 aux_pages; 1099 int num_eqs; 1100 int err; 1101 1102 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1103 if (err) { 1104 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1105 return err; 1106 } 1107 1108 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1109 (unsigned long long) icm_size >> 10, 1110 (unsigned long long) aux_pages << 2); 1111 1112 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1113 GFP_HIGHUSER | __GFP_NOWARN, 0); 1114 if (!priv->fw.aux_icm) { 1115 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1116 return -ENOMEM; 1117 } 1118 1119 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1120 if (err) { 1121 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1122 goto err_free_aux; 1123 } 1124 1125 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1126 if (err) { 1127 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1128 goto err_unmap_aux; 1129 } 1130 1131 1132 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 1133 dev->caps.num_eqs; 1134 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1135 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1136 num_eqs, num_eqs, 0, 0); 1137 if (err) { 1138 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1139 goto err_unmap_cmpt; 1140 } 1141 1142 /* 1143 * Reserved MTT entries must be aligned up to a cacheline 1144 * boundary, since the FW will write to them, while the driver 1145 * writes to all other MTT entries. (The variable 1146 * dev->caps.mtt_entry_sz below is really the MTT segment 1147 * size, not the raw entry size) 1148 */ 1149 dev->caps.reserved_mtts = 1150 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1151 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1152 1153 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1154 init_hca->mtt_base, 1155 dev->caps.mtt_entry_sz, 1156 dev->caps.num_mtts, 1157 dev->caps.reserved_mtts, 1, 0); 1158 if (err) { 1159 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1160 goto err_unmap_eq; 1161 } 1162 1163 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1164 init_hca->dmpt_base, 1165 dev_cap->dmpt_entry_sz, 1166 dev->caps.num_mpts, 1167 dev->caps.reserved_mrws, 1, 1); 1168 if (err) { 1169 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1170 goto err_unmap_mtt; 1171 } 1172 1173 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1174 init_hca->qpc_base, 1175 dev_cap->qpc_entry_sz, 1176 dev->caps.num_qps, 1177 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1178 0, 0); 1179 if (err) { 1180 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1181 goto err_unmap_dmpt; 1182 } 1183 1184 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1185 init_hca->auxc_base, 1186 dev_cap->aux_entry_sz, 1187 dev->caps.num_qps, 1188 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1189 0, 0); 1190 if (err) { 1191 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1192 goto err_unmap_qp; 1193 } 1194 1195 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1196 init_hca->altc_base, 1197 dev_cap->altc_entry_sz, 1198 dev->caps.num_qps, 1199 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1200 0, 0); 1201 if (err) { 1202 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1203 goto err_unmap_auxc; 1204 } 1205 1206 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1207 init_hca->rdmarc_base, 1208 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1209 dev->caps.num_qps, 1210 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1211 0, 0); 1212 if (err) { 1213 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1214 goto err_unmap_altc; 1215 } 1216 1217 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1218 init_hca->cqc_base, 1219 dev_cap->cqc_entry_sz, 1220 dev->caps.num_cqs, 1221 dev->caps.reserved_cqs, 0, 0); 1222 if (err) { 1223 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1224 goto err_unmap_rdmarc; 1225 } 1226 1227 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1228 init_hca->srqc_base, 1229 dev_cap->srq_entry_sz, 1230 dev->caps.num_srqs, 1231 dev->caps.reserved_srqs, 0, 0); 1232 if (err) { 1233 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1234 goto err_unmap_cq; 1235 } 1236 1237 /* 1238 * For flow steering device managed mode it is required to use 1239 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1240 * required, but for simplicity just map the whole multicast 1241 * group table now. The table isn't very big and it's a lot 1242 * easier than trying to track ref counts. 1243 */ 1244 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1245 init_hca->mc_base, 1246 mlx4_get_mgm_entry_size(dev), 1247 dev->caps.num_mgms + dev->caps.num_amgms, 1248 dev->caps.num_mgms + dev->caps.num_amgms, 1249 0, 0); 1250 if (err) { 1251 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1252 goto err_unmap_srq; 1253 } 1254 1255 return 0; 1256 1257 err_unmap_srq: 1258 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1259 1260 err_unmap_cq: 1261 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1262 1263 err_unmap_rdmarc: 1264 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1265 1266 err_unmap_altc: 1267 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1268 1269 err_unmap_auxc: 1270 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1271 1272 err_unmap_qp: 1273 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1274 1275 err_unmap_dmpt: 1276 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1277 1278 err_unmap_mtt: 1279 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1280 1281 err_unmap_eq: 1282 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1283 1284 err_unmap_cmpt: 1285 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1286 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1287 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1288 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1289 1290 err_unmap_aux: 1291 mlx4_UNMAP_ICM_AUX(dev); 1292 1293 err_free_aux: 1294 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1295 1296 return err; 1297 } 1298 1299 static void mlx4_free_icms(struct mlx4_dev *dev) 1300 { 1301 struct mlx4_priv *priv = mlx4_priv(dev); 1302 1303 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1304 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1305 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1306 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1307 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1308 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1309 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1310 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1311 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1312 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1313 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1314 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1315 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1316 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1317 1318 mlx4_UNMAP_ICM_AUX(dev); 1319 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1320 } 1321 1322 static void mlx4_slave_exit(struct mlx4_dev *dev) 1323 { 1324 struct mlx4_priv *priv = mlx4_priv(dev); 1325 1326 mutex_lock(&priv->cmd.slave_cmd_mutex); 1327 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1328 mlx4_warn(dev, "Failed to close slave function\n"); 1329 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1330 } 1331 1332 static int map_bf_area(struct mlx4_dev *dev) 1333 { 1334 struct mlx4_priv *priv = mlx4_priv(dev); 1335 resource_size_t bf_start; 1336 resource_size_t bf_len; 1337 int err = 0; 1338 1339 if (!dev->caps.bf_reg_size) 1340 return -ENXIO; 1341 1342 bf_start = pci_resource_start(dev->pdev, 2) + 1343 (dev->caps.num_uars << PAGE_SHIFT); 1344 bf_len = pci_resource_len(dev->pdev, 2) - 1345 (dev->caps.num_uars << PAGE_SHIFT); 1346 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1347 if (!priv->bf_mapping) 1348 err = -ENOMEM; 1349 1350 return err; 1351 } 1352 1353 static void unmap_bf_area(struct mlx4_dev *dev) 1354 { 1355 if (mlx4_priv(dev)->bf_mapping) 1356 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1357 } 1358 1359 cycle_t mlx4_read_clock(struct mlx4_dev *dev) 1360 { 1361 u32 clockhi, clocklo, clockhi1; 1362 cycle_t cycles; 1363 int i; 1364 struct mlx4_priv *priv = mlx4_priv(dev); 1365 1366 for (i = 0; i < 10; i++) { 1367 clockhi = swab32(readl(priv->clock_mapping)); 1368 clocklo = swab32(readl(priv->clock_mapping + 4)); 1369 clockhi1 = swab32(readl(priv->clock_mapping)); 1370 if (clockhi == clockhi1) 1371 break; 1372 } 1373 1374 cycles = (u64) clockhi << 32 | (u64) clocklo; 1375 1376 return cycles; 1377 } 1378 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1379 1380 1381 static int map_internal_clock(struct mlx4_dev *dev) 1382 { 1383 struct mlx4_priv *priv = mlx4_priv(dev); 1384 1385 priv->clock_mapping = 1386 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + 1387 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1388 1389 if (!priv->clock_mapping) 1390 return -ENOMEM; 1391 1392 return 0; 1393 } 1394 1395 static void unmap_internal_clock(struct mlx4_dev *dev) 1396 { 1397 struct mlx4_priv *priv = mlx4_priv(dev); 1398 1399 if (priv->clock_mapping) 1400 iounmap(priv->clock_mapping); 1401 } 1402 1403 static void mlx4_close_hca(struct mlx4_dev *dev) 1404 { 1405 unmap_internal_clock(dev); 1406 unmap_bf_area(dev); 1407 if (mlx4_is_slave(dev)) 1408 mlx4_slave_exit(dev); 1409 else { 1410 mlx4_CLOSE_HCA(dev, 0); 1411 mlx4_free_icms(dev); 1412 mlx4_UNMAP_FA(dev); 1413 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1414 } 1415 } 1416 1417 static int mlx4_init_slave(struct mlx4_dev *dev) 1418 { 1419 struct mlx4_priv *priv = mlx4_priv(dev); 1420 u64 dma = (u64) priv->mfunc.vhcr_dma; 1421 int ret_from_reset = 0; 1422 u32 slave_read; 1423 u32 cmd_channel_ver; 1424 1425 if (atomic_read(&pf_loading)) { 1426 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 1427 return -EPROBE_DEFER; 1428 } 1429 1430 mutex_lock(&priv->cmd.slave_cmd_mutex); 1431 priv->cmd.max_cmds = 1; 1432 mlx4_warn(dev, "Sending reset\n"); 1433 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1434 MLX4_COMM_TIME); 1435 /* if we are in the middle of flr the slave will try 1436 * NUM_OF_RESET_RETRIES times before leaving.*/ 1437 if (ret_from_reset) { 1438 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1439 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 1440 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1441 return -EPROBE_DEFER; 1442 } else 1443 goto err; 1444 } 1445 1446 /* check the driver version - the slave I/F revision 1447 * must match the master's */ 1448 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1449 cmd_channel_ver = mlx4_comm_get_version(); 1450 1451 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1452 MLX4_COMM_GET_IF_REV(slave_read)) { 1453 mlx4_err(dev, "slave driver version is not supported by the master\n"); 1454 goto err; 1455 } 1456 1457 mlx4_warn(dev, "Sending vhcr0\n"); 1458 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1459 MLX4_COMM_TIME)) 1460 goto err; 1461 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1462 MLX4_COMM_TIME)) 1463 goto err; 1464 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1465 MLX4_COMM_TIME)) 1466 goto err; 1467 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1468 goto err; 1469 1470 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1471 return 0; 1472 1473 err: 1474 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1475 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1476 return -EIO; 1477 } 1478 1479 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1480 { 1481 int i; 1482 1483 for (i = 1; i <= dev->caps.num_ports; i++) { 1484 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1485 dev->caps.gid_table_len[i] = 1486 mlx4_get_slave_num_gids(dev, 0, i); 1487 else 1488 dev->caps.gid_table_len[i] = 1; 1489 dev->caps.pkey_table_len[i] = 1490 dev->phys_caps.pkey_phys_table_len[i] - 1; 1491 } 1492 } 1493 1494 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1495 { 1496 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1497 1498 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1499 i++) { 1500 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1501 break; 1502 } 1503 1504 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1505 } 1506 1507 static void choose_steering_mode(struct mlx4_dev *dev, 1508 struct mlx4_dev_cap *dev_cap) 1509 { 1510 if (mlx4_log_num_mgm_entry_size == -1 && 1511 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1512 (!mlx4_is_mfunc(dev) || 1513 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) && 1514 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1515 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1516 dev->oper_log_mgm_entry_size = 1517 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1518 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1519 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1520 dev->caps.fs_log_max_ucast_qp_range_size = 1521 dev_cap->fs_log_max_ucast_qp_range_size; 1522 } else { 1523 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1524 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1525 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1526 else { 1527 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1528 1529 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1530 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1531 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 1532 } 1533 dev->oper_log_mgm_entry_size = 1534 mlx4_log_num_mgm_entry_size > 0 ? 1535 mlx4_log_num_mgm_entry_size : 1536 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1537 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1538 } 1539 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 1540 mlx4_steering_mode_str(dev->caps.steering_mode), 1541 dev->oper_log_mgm_entry_size, 1542 mlx4_log_num_mgm_entry_size); 1543 } 1544 1545 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 1546 struct mlx4_dev_cap *dev_cap) 1547 { 1548 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 1549 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 1550 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 1551 else 1552 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 1553 1554 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 1555 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 1556 } 1557 1558 static int mlx4_init_hca(struct mlx4_dev *dev) 1559 { 1560 struct mlx4_priv *priv = mlx4_priv(dev); 1561 struct mlx4_adapter adapter; 1562 struct mlx4_dev_cap dev_cap; 1563 struct mlx4_mod_stat_cfg mlx4_cfg; 1564 struct mlx4_profile profile; 1565 struct mlx4_init_hca_param init_hca; 1566 u64 icm_size; 1567 int err; 1568 1569 if (!mlx4_is_slave(dev)) { 1570 err = mlx4_QUERY_FW(dev); 1571 if (err) { 1572 if (err == -EACCES) 1573 mlx4_info(dev, "non-primary physical function, skipping\n"); 1574 else 1575 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 1576 return err; 1577 } 1578 1579 err = mlx4_load_fw(dev); 1580 if (err) { 1581 mlx4_err(dev, "Failed to start FW, aborting\n"); 1582 return err; 1583 } 1584 1585 mlx4_cfg.log_pg_sz_m = 1; 1586 mlx4_cfg.log_pg_sz = 0; 1587 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1588 if (err) 1589 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1590 1591 err = mlx4_dev_cap(dev, &dev_cap); 1592 if (err) { 1593 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 1594 goto err_stop_fw; 1595 } 1596 1597 choose_steering_mode(dev, &dev_cap); 1598 choose_tunnel_offload_mode(dev, &dev_cap); 1599 1600 err = mlx4_get_phys_port_id(dev); 1601 if (err) 1602 mlx4_err(dev, "Fail to get physical port id\n"); 1603 1604 if (mlx4_is_master(dev)) 1605 mlx4_parav_master_pf_caps(dev); 1606 1607 if (mlx4_low_memory_profile()) { 1608 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 1609 profile = low_mem_profile; 1610 } else { 1611 profile = default_profile; 1612 } 1613 if (dev->caps.steering_mode == 1614 MLX4_STEERING_MODE_DEVICE_MANAGED) 1615 profile.num_mcg = MLX4_FS_NUM_MCG; 1616 1617 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 1618 &init_hca); 1619 if ((long long) icm_size < 0) { 1620 err = icm_size; 1621 goto err_stop_fw; 1622 } 1623 1624 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 1625 1626 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 1627 init_hca.uar_page_sz = PAGE_SHIFT - 12; 1628 init_hca.mw_enabled = 0; 1629 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 1630 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 1631 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 1632 1633 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 1634 if (err) 1635 goto err_stop_fw; 1636 1637 err = mlx4_INIT_HCA(dev, &init_hca); 1638 if (err) { 1639 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 1640 goto err_free_icm; 1641 } 1642 /* 1643 * If TS is supported by FW 1644 * read HCA frequency by QUERY_HCA command 1645 */ 1646 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1647 memset(&init_hca, 0, sizeof(init_hca)); 1648 err = mlx4_QUERY_HCA(dev, &init_hca); 1649 if (err) { 1650 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 1651 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1652 } else { 1653 dev->caps.hca_core_clock = 1654 init_hca.hca_core_clock; 1655 } 1656 1657 /* In case we got HCA frequency 0 - disable timestamping 1658 * to avoid dividing by zero 1659 */ 1660 if (!dev->caps.hca_core_clock) { 1661 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1662 mlx4_err(dev, 1663 "HCA frequency is 0 - timestamping is not supported\n"); 1664 } else if (map_internal_clock(dev)) { 1665 /* 1666 * Map internal clock, 1667 * in case of failure disable timestamping 1668 */ 1669 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1670 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 1671 } 1672 } 1673 } else { 1674 err = mlx4_init_slave(dev); 1675 if (err) { 1676 if (err != -EPROBE_DEFER) 1677 mlx4_err(dev, "Failed to initialize slave\n"); 1678 return err; 1679 } 1680 1681 err = mlx4_slave_cap(dev); 1682 if (err) { 1683 mlx4_err(dev, "Failed to obtain slave caps\n"); 1684 goto err_close; 1685 } 1686 } 1687 1688 if (map_bf_area(dev)) 1689 mlx4_dbg(dev, "Failed to map blue flame area\n"); 1690 1691 /*Only the master set the ports, all the rest got it from it.*/ 1692 if (!mlx4_is_slave(dev)) 1693 mlx4_set_port_mask(dev); 1694 1695 err = mlx4_QUERY_ADAPTER(dev, &adapter); 1696 if (err) { 1697 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 1698 goto unmap_bf; 1699 } 1700 1701 priv->eq_table.inta_pin = adapter.inta_pin; 1702 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 1703 1704 return 0; 1705 1706 unmap_bf: 1707 unmap_internal_clock(dev); 1708 unmap_bf_area(dev); 1709 1710 if (mlx4_is_slave(dev)) { 1711 kfree(dev->caps.qp0_qkey); 1712 kfree(dev->caps.qp0_tunnel); 1713 kfree(dev->caps.qp0_proxy); 1714 kfree(dev->caps.qp1_tunnel); 1715 kfree(dev->caps.qp1_proxy); 1716 } 1717 1718 err_close: 1719 if (mlx4_is_slave(dev)) 1720 mlx4_slave_exit(dev); 1721 else 1722 mlx4_CLOSE_HCA(dev, 0); 1723 1724 err_free_icm: 1725 if (!mlx4_is_slave(dev)) 1726 mlx4_free_icms(dev); 1727 1728 err_stop_fw: 1729 if (!mlx4_is_slave(dev)) { 1730 mlx4_UNMAP_FA(dev); 1731 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1732 } 1733 return err; 1734 } 1735 1736 static int mlx4_init_counters_table(struct mlx4_dev *dev) 1737 { 1738 struct mlx4_priv *priv = mlx4_priv(dev); 1739 int nent; 1740 1741 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1742 return -ENOENT; 1743 1744 nent = dev->caps.max_counters; 1745 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 1746 } 1747 1748 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 1749 { 1750 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 1751 } 1752 1753 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1754 { 1755 struct mlx4_priv *priv = mlx4_priv(dev); 1756 1757 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1758 return -ENOENT; 1759 1760 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 1761 if (*idx == -1) 1762 return -ENOMEM; 1763 1764 return 0; 1765 } 1766 1767 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1768 { 1769 u64 out_param; 1770 int err; 1771 1772 if (mlx4_is_mfunc(dev)) { 1773 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 1774 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 1775 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1776 if (!err) 1777 *idx = get_param_l(&out_param); 1778 1779 return err; 1780 } 1781 return __mlx4_counter_alloc(dev, idx); 1782 } 1783 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 1784 1785 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1786 { 1787 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 1788 return; 1789 } 1790 1791 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1792 { 1793 u64 in_param = 0; 1794 1795 if (mlx4_is_mfunc(dev)) { 1796 set_param_l(&in_param, idx); 1797 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 1798 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 1799 MLX4_CMD_WRAPPED); 1800 return; 1801 } 1802 __mlx4_counter_free(dev, idx); 1803 } 1804 EXPORT_SYMBOL_GPL(mlx4_counter_free); 1805 1806 static int mlx4_setup_hca(struct mlx4_dev *dev) 1807 { 1808 struct mlx4_priv *priv = mlx4_priv(dev); 1809 int err; 1810 int port; 1811 __be32 ib_port_default_caps; 1812 1813 err = mlx4_init_uar_table(dev); 1814 if (err) { 1815 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 1816 return err; 1817 } 1818 1819 err = mlx4_uar_alloc(dev, &priv->driver_uar); 1820 if (err) { 1821 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 1822 goto err_uar_table_free; 1823 } 1824 1825 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 1826 if (!priv->kar) { 1827 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 1828 err = -ENOMEM; 1829 goto err_uar_free; 1830 } 1831 1832 err = mlx4_init_pd_table(dev); 1833 if (err) { 1834 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 1835 goto err_kar_unmap; 1836 } 1837 1838 err = mlx4_init_xrcd_table(dev); 1839 if (err) { 1840 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 1841 goto err_pd_table_free; 1842 } 1843 1844 err = mlx4_init_mr_table(dev); 1845 if (err) { 1846 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 1847 goto err_xrcd_table_free; 1848 } 1849 1850 if (!mlx4_is_slave(dev)) { 1851 err = mlx4_init_mcg_table(dev); 1852 if (err) { 1853 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 1854 goto err_mr_table_free; 1855 } 1856 err = mlx4_config_mad_demux(dev); 1857 if (err) { 1858 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 1859 goto err_mcg_table_free; 1860 } 1861 } 1862 1863 err = mlx4_init_eq_table(dev); 1864 if (err) { 1865 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 1866 goto err_mcg_table_free; 1867 } 1868 1869 err = mlx4_cmd_use_events(dev); 1870 if (err) { 1871 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 1872 goto err_eq_table_free; 1873 } 1874 1875 err = mlx4_NOP(dev); 1876 if (err) { 1877 if (dev->flags & MLX4_FLAG_MSI_X) { 1878 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 1879 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1880 mlx4_warn(dev, "Trying again without MSI-X\n"); 1881 } else { 1882 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 1883 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1884 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 1885 } 1886 1887 goto err_cmd_poll; 1888 } 1889 1890 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 1891 1892 err = mlx4_init_cq_table(dev); 1893 if (err) { 1894 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 1895 goto err_cmd_poll; 1896 } 1897 1898 err = mlx4_init_srq_table(dev); 1899 if (err) { 1900 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 1901 goto err_cq_table_free; 1902 } 1903 1904 err = mlx4_init_qp_table(dev); 1905 if (err) { 1906 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 1907 goto err_srq_table_free; 1908 } 1909 1910 err = mlx4_init_counters_table(dev); 1911 if (err && err != -ENOENT) { 1912 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 1913 goto err_qp_table_free; 1914 } 1915 1916 if (!mlx4_is_slave(dev)) { 1917 for (port = 1; port <= dev->caps.num_ports; port++) { 1918 ib_port_default_caps = 0; 1919 err = mlx4_get_port_ib_caps(dev, port, 1920 &ib_port_default_caps); 1921 if (err) 1922 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 1923 port, err); 1924 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 1925 1926 /* initialize per-slave default ib port capabilities */ 1927 if (mlx4_is_master(dev)) { 1928 int i; 1929 for (i = 0; i < dev->num_slaves; i++) { 1930 if (i == mlx4_master_func_num(dev)) 1931 continue; 1932 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 1933 ib_port_default_caps; 1934 } 1935 } 1936 1937 if (mlx4_is_mfunc(dev)) 1938 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 1939 else 1940 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 1941 1942 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 1943 dev->caps.pkey_table_len[port] : -1); 1944 if (err) { 1945 mlx4_err(dev, "Failed to set port %d, aborting\n", 1946 port); 1947 goto err_counters_table_free; 1948 } 1949 } 1950 } 1951 1952 return 0; 1953 1954 err_counters_table_free: 1955 mlx4_cleanup_counters_table(dev); 1956 1957 err_qp_table_free: 1958 mlx4_cleanup_qp_table(dev); 1959 1960 err_srq_table_free: 1961 mlx4_cleanup_srq_table(dev); 1962 1963 err_cq_table_free: 1964 mlx4_cleanup_cq_table(dev); 1965 1966 err_cmd_poll: 1967 mlx4_cmd_use_polling(dev); 1968 1969 err_eq_table_free: 1970 mlx4_cleanup_eq_table(dev); 1971 1972 err_mcg_table_free: 1973 if (!mlx4_is_slave(dev)) 1974 mlx4_cleanup_mcg_table(dev); 1975 1976 err_mr_table_free: 1977 mlx4_cleanup_mr_table(dev); 1978 1979 err_xrcd_table_free: 1980 mlx4_cleanup_xrcd_table(dev); 1981 1982 err_pd_table_free: 1983 mlx4_cleanup_pd_table(dev); 1984 1985 err_kar_unmap: 1986 iounmap(priv->kar); 1987 1988 err_uar_free: 1989 mlx4_uar_free(dev, &priv->driver_uar); 1990 1991 err_uar_table_free: 1992 mlx4_cleanup_uar_table(dev); 1993 return err; 1994 } 1995 1996 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 1997 { 1998 struct mlx4_priv *priv = mlx4_priv(dev); 1999 struct msix_entry *entries; 2000 int nreq = min_t(int, dev->caps.num_ports * 2001 min_t(int, num_online_cpus() + 1, 2002 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); 2003 int i; 2004 2005 if (msi_x) { 2006 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2007 nreq); 2008 2009 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2010 if (!entries) 2011 goto no_msi; 2012 2013 for (i = 0; i < nreq; ++i) 2014 entries[i].entry = i; 2015 2016 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq); 2017 2018 if (nreq < 0) { 2019 kfree(entries); 2020 goto no_msi; 2021 } else if (nreq < MSIX_LEGACY_SZ + 2022 dev->caps.num_ports * MIN_MSIX_P_PORT) { 2023 /*Working in legacy mode , all EQ's shared*/ 2024 dev->caps.comp_pool = 0; 2025 dev->caps.num_comp_vectors = nreq - 1; 2026 } else { 2027 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 2028 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 2029 } 2030 for (i = 0; i < nreq; ++i) 2031 priv->eq_table.eq[i].irq = entries[i].vector; 2032 2033 dev->flags |= MLX4_FLAG_MSI_X; 2034 2035 kfree(entries); 2036 return; 2037 } 2038 2039 no_msi: 2040 dev->caps.num_comp_vectors = 1; 2041 dev->caps.comp_pool = 0; 2042 2043 for (i = 0; i < 2; ++i) 2044 priv->eq_table.eq[i].irq = dev->pdev->irq; 2045 } 2046 2047 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2048 { 2049 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2050 int err = 0; 2051 2052 info->dev = dev; 2053 info->port = port; 2054 if (!mlx4_is_slave(dev)) { 2055 mlx4_init_mac_table(dev, &info->mac_table); 2056 mlx4_init_vlan_table(dev, &info->vlan_table); 2057 mlx4_init_roce_gid_table(dev, &info->gid_table); 2058 info->base_qpn = mlx4_get_base_qpn(dev, port); 2059 } 2060 2061 sprintf(info->dev_name, "mlx4_port%d", port); 2062 info->port_attr.attr.name = info->dev_name; 2063 if (mlx4_is_mfunc(dev)) 2064 info->port_attr.attr.mode = S_IRUGO; 2065 else { 2066 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2067 info->port_attr.store = set_port_type; 2068 } 2069 info->port_attr.show = show_port_type; 2070 sysfs_attr_init(&info->port_attr.attr); 2071 2072 err = device_create_file(&dev->pdev->dev, &info->port_attr); 2073 if (err) { 2074 mlx4_err(dev, "Failed to create file for port %d\n", port); 2075 info->port = -1; 2076 } 2077 2078 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2079 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2080 if (mlx4_is_mfunc(dev)) 2081 info->port_mtu_attr.attr.mode = S_IRUGO; 2082 else { 2083 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2084 info->port_mtu_attr.store = set_port_ib_mtu; 2085 } 2086 info->port_mtu_attr.show = show_port_ib_mtu; 2087 sysfs_attr_init(&info->port_mtu_attr.attr); 2088 2089 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 2090 if (err) { 2091 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2092 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2093 info->port = -1; 2094 } 2095 2096 return err; 2097 } 2098 2099 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 2100 { 2101 if (info->port < 0) 2102 return; 2103 2104 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2105 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 2106 } 2107 2108 static int mlx4_init_steering(struct mlx4_dev *dev) 2109 { 2110 struct mlx4_priv *priv = mlx4_priv(dev); 2111 int num_entries = dev->caps.num_ports; 2112 int i, j; 2113 2114 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 2115 if (!priv->steer) 2116 return -ENOMEM; 2117 2118 for (i = 0; i < num_entries; i++) 2119 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2120 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 2121 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 2122 } 2123 return 0; 2124 } 2125 2126 static void mlx4_clear_steering(struct mlx4_dev *dev) 2127 { 2128 struct mlx4_priv *priv = mlx4_priv(dev); 2129 struct mlx4_steer_index *entry, *tmp_entry; 2130 struct mlx4_promisc_qp *pqp, *tmp_pqp; 2131 int num_entries = dev->caps.num_ports; 2132 int i, j; 2133 2134 for (i = 0; i < num_entries; i++) { 2135 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2136 list_for_each_entry_safe(pqp, tmp_pqp, 2137 &priv->steer[i].promisc_qps[j], 2138 list) { 2139 list_del(&pqp->list); 2140 kfree(pqp); 2141 } 2142 list_for_each_entry_safe(entry, tmp_entry, 2143 &priv->steer[i].steer_entries[j], 2144 list) { 2145 list_del(&entry->list); 2146 list_for_each_entry_safe(pqp, tmp_pqp, 2147 &entry->duplicates, 2148 list) { 2149 list_del(&pqp->list); 2150 kfree(pqp); 2151 } 2152 kfree(entry); 2153 } 2154 } 2155 } 2156 kfree(priv->steer); 2157 } 2158 2159 static int extended_func_num(struct pci_dev *pdev) 2160 { 2161 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 2162 } 2163 2164 #define MLX4_OWNER_BASE 0x8069c 2165 #define MLX4_OWNER_SIZE 4 2166 2167 static int mlx4_get_ownership(struct mlx4_dev *dev) 2168 { 2169 void __iomem *owner; 2170 u32 ret; 2171 2172 if (pci_channel_offline(dev->pdev)) 2173 return -EIO; 2174 2175 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2176 MLX4_OWNER_SIZE); 2177 if (!owner) { 2178 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2179 return -ENOMEM; 2180 } 2181 2182 ret = readl(owner); 2183 iounmap(owner); 2184 return (int) !!ret; 2185 } 2186 2187 static void mlx4_free_ownership(struct mlx4_dev *dev) 2188 { 2189 void __iomem *owner; 2190 2191 if (pci_channel_offline(dev->pdev)) 2192 return; 2193 2194 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2195 MLX4_OWNER_SIZE); 2196 if (!owner) { 2197 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2198 return; 2199 } 2200 writel(0, owner); 2201 msleep(1000); 2202 iounmap(owner); 2203 } 2204 2205 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) 2206 { 2207 struct mlx4_priv *priv; 2208 struct mlx4_dev *dev; 2209 int err; 2210 int port; 2211 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 2212 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 2213 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 2214 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 2215 unsigned total_vfs = 0; 2216 int sriov_initialized = 0; 2217 unsigned int i; 2218 2219 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 2220 2221 err = pci_enable_device(pdev); 2222 if (err) { 2223 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 2224 return err; 2225 } 2226 2227 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 2228 * per port, we must limit the number of VFs to 63 (since their are 2229 * 128 MACs) 2230 */ 2231 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 2232 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 2233 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 2234 if (nvfs[i] < 0) { 2235 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 2236 return -EINVAL; 2237 } 2238 } 2239 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 2240 i++) { 2241 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 2242 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 2243 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 2244 return -EINVAL; 2245 } 2246 } 2247 if (total_vfs >= MLX4_MAX_NUM_VF) { 2248 dev_err(&pdev->dev, 2249 "Requested more VF's (%d) than allowed (%d)\n", 2250 total_vfs, MLX4_MAX_NUM_VF - 1); 2251 return -EINVAL; 2252 } 2253 2254 for (i = 0; i < MLX4_MAX_PORTS; i++) { 2255 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { 2256 dev_err(&pdev->dev, 2257 "Requested more VF's (%d) for port (%d) than allowed (%d)\n", 2258 nvfs[i] + nvfs[2], i + 1, 2259 MLX4_MAX_NUM_VF_P_PORT - 1); 2260 return -EINVAL; 2261 } 2262 } 2263 2264 2265 /* 2266 * Check for BARs. 2267 */ 2268 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 2269 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2270 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 2271 pci_dev_data, pci_resource_flags(pdev, 0)); 2272 err = -ENODEV; 2273 goto err_disable_pdev; 2274 } 2275 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 2276 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 2277 err = -ENODEV; 2278 goto err_disable_pdev; 2279 } 2280 2281 err = pci_request_regions(pdev, DRV_NAME); 2282 if (err) { 2283 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 2284 goto err_disable_pdev; 2285 } 2286 2287 pci_set_master(pdev); 2288 2289 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 2290 if (err) { 2291 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 2292 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2293 if (err) { 2294 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 2295 goto err_release_regions; 2296 } 2297 } 2298 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2299 if (err) { 2300 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 2301 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2302 if (err) { 2303 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 2304 goto err_release_regions; 2305 } 2306 } 2307 2308 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 2309 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 2310 2311 dev = pci_get_drvdata(pdev); 2312 priv = mlx4_priv(dev); 2313 dev->pdev = pdev; 2314 INIT_LIST_HEAD(&priv->ctx_list); 2315 spin_lock_init(&priv->ctx_lock); 2316 2317 mutex_init(&priv->port_mutex); 2318 2319 INIT_LIST_HEAD(&priv->pgdir_list); 2320 mutex_init(&priv->pgdir_mutex); 2321 2322 INIT_LIST_HEAD(&priv->bf_list); 2323 mutex_init(&priv->bf_mutex); 2324 2325 dev->rev_id = pdev->revision; 2326 dev->numa_node = dev_to_node(&pdev->dev); 2327 /* Detect if this device is a virtual function */ 2328 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2329 /* When acting as pf, we normally skip vfs unless explicitly 2330 * requested to probe them. */ 2331 if (total_vfs) { 2332 unsigned vfs_offset = 0; 2333 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 2334 vfs_offset + nvfs[i] < extended_func_num(pdev); 2335 vfs_offset += nvfs[i], i++) 2336 ; 2337 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 2338 err = -ENODEV; 2339 goto err_free_dev; 2340 } 2341 if ((extended_func_num(pdev) - vfs_offset) 2342 > prb_vf[i]) { 2343 mlx4_warn(dev, "Skipping virtual function:%d\n", 2344 extended_func_num(pdev)); 2345 err = -ENODEV; 2346 goto err_free_dev; 2347 } 2348 } 2349 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 2350 dev->flags |= MLX4_FLAG_SLAVE; 2351 } else { 2352 /* We reset the device and enable SRIOV only for physical 2353 * devices. Try to claim ownership on the device; 2354 * if already taken, skip -- do not allow multiple PFs */ 2355 err = mlx4_get_ownership(dev); 2356 if (err) { 2357 if (err < 0) 2358 goto err_free_dev; 2359 else { 2360 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 2361 err = -EINVAL; 2362 goto err_free_dev; 2363 } 2364 } 2365 2366 if (total_vfs) { 2367 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", 2368 total_vfs); 2369 dev->dev_vfs = kzalloc( 2370 total_vfs * sizeof(*dev->dev_vfs), 2371 GFP_KERNEL); 2372 if (NULL == dev->dev_vfs) { 2373 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 2374 err = 0; 2375 } else { 2376 atomic_inc(&pf_loading); 2377 err = pci_enable_sriov(pdev, total_vfs); 2378 if (err) { 2379 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 2380 err); 2381 atomic_dec(&pf_loading); 2382 err = 0; 2383 } else { 2384 mlx4_warn(dev, "Running in master mode\n"); 2385 dev->flags |= MLX4_FLAG_SRIOV | 2386 MLX4_FLAG_MASTER; 2387 dev->num_vfs = total_vfs; 2388 sriov_initialized = 1; 2389 } 2390 } 2391 } 2392 2393 atomic_set(&priv->opreq_count, 0); 2394 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 2395 2396 /* 2397 * Now reset the HCA before we touch the PCI capabilities or 2398 * attempt a firmware command, since a boot ROM may have left 2399 * the HCA in an undefined state. 2400 */ 2401 err = mlx4_reset(dev); 2402 if (err) { 2403 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 2404 goto err_rel_own; 2405 } 2406 } 2407 2408 slave_start: 2409 err = mlx4_cmd_init(dev); 2410 if (err) { 2411 mlx4_err(dev, "Failed to init command interface, aborting\n"); 2412 goto err_sriov; 2413 } 2414 2415 /* In slave functions, the communication channel must be initialized 2416 * before posting commands. Also, init num_slaves before calling 2417 * mlx4_init_hca */ 2418 if (mlx4_is_mfunc(dev)) { 2419 if (mlx4_is_master(dev)) 2420 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2421 else { 2422 dev->num_slaves = 0; 2423 err = mlx4_multi_func_init(dev); 2424 if (err) { 2425 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 2426 goto err_cmd; 2427 } 2428 } 2429 } 2430 2431 err = mlx4_init_hca(dev); 2432 if (err) { 2433 if (err == -EACCES) { 2434 /* Not primary Physical function 2435 * Running in slave mode */ 2436 mlx4_cmd_cleanup(dev); 2437 dev->flags |= MLX4_FLAG_SLAVE; 2438 dev->flags &= ~MLX4_FLAG_MASTER; 2439 goto slave_start; 2440 } else 2441 goto err_mfunc; 2442 } 2443 2444 /* check if the device is functioning at its maximum possible speed. 2445 * No return code for this call, just warn the user in case of PCI 2446 * express device capabilities are under-satisfied by the bus. 2447 */ 2448 if (!mlx4_is_slave(dev)) 2449 mlx4_check_pcie_caps(dev); 2450 2451 /* In master functions, the communication channel must be initialized 2452 * after obtaining its address from fw */ 2453 if (mlx4_is_master(dev)) { 2454 unsigned sum = 0; 2455 err = mlx4_multi_func_init(dev); 2456 if (err) { 2457 mlx4_err(dev, "Failed to init master mfunc interface, aborting\n"); 2458 goto err_close; 2459 } 2460 if (sriov_initialized) { 2461 int ib_ports = 0; 2462 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2463 ib_ports++; 2464 2465 if (ib_ports && 2466 (num_vfs_argc > 1 || probe_vfs_argc > 1)) { 2467 mlx4_err(dev, 2468 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); 2469 err = -EINVAL; 2470 goto err_master_mfunc; 2471 } 2472 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) { 2473 unsigned j; 2474 for (j = 0; j < nvfs[i]; ++sum, ++j) { 2475 dev->dev_vfs[sum].min_port = 2476 i < 2 ? i + 1 : 1; 2477 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 2478 dev->caps.num_ports; 2479 } 2480 } 2481 } 2482 } 2483 2484 err = mlx4_alloc_eq_table(dev); 2485 if (err) 2486 goto err_master_mfunc; 2487 2488 priv->msix_ctl.pool_bm = 0; 2489 mutex_init(&priv->msix_ctl.pool_lock); 2490 2491 mlx4_enable_msi_x(dev); 2492 if ((mlx4_is_mfunc(dev)) && 2493 !(dev->flags & MLX4_FLAG_MSI_X)) { 2494 err = -ENOSYS; 2495 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 2496 goto err_free_eq; 2497 } 2498 2499 if (!mlx4_is_slave(dev)) { 2500 err = mlx4_init_steering(dev); 2501 if (err) 2502 goto err_free_eq; 2503 } 2504 2505 err = mlx4_setup_hca(dev); 2506 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 2507 !mlx4_is_mfunc(dev)) { 2508 dev->flags &= ~MLX4_FLAG_MSI_X; 2509 dev->caps.num_comp_vectors = 1; 2510 dev->caps.comp_pool = 0; 2511 pci_disable_msix(pdev); 2512 err = mlx4_setup_hca(dev); 2513 } 2514 2515 if (err) 2516 goto err_steer; 2517 2518 mlx4_init_quotas(dev); 2519 2520 for (port = 1; port <= dev->caps.num_ports; port++) { 2521 err = mlx4_init_port_info(dev, port); 2522 if (err) 2523 goto err_port; 2524 } 2525 2526 err = mlx4_register_device(dev); 2527 if (err) 2528 goto err_port; 2529 2530 mlx4_request_modules(dev); 2531 2532 mlx4_sense_init(dev); 2533 mlx4_start_sense(dev); 2534 2535 priv->removed = 0; 2536 2537 if (mlx4_is_master(dev) && dev->num_vfs) 2538 atomic_dec(&pf_loading); 2539 2540 return 0; 2541 2542 err_port: 2543 for (--port; port >= 1; --port) 2544 mlx4_cleanup_port_info(&priv->port[port]); 2545 2546 mlx4_cleanup_counters_table(dev); 2547 mlx4_cleanup_qp_table(dev); 2548 mlx4_cleanup_srq_table(dev); 2549 mlx4_cleanup_cq_table(dev); 2550 mlx4_cmd_use_polling(dev); 2551 mlx4_cleanup_eq_table(dev); 2552 mlx4_cleanup_mcg_table(dev); 2553 mlx4_cleanup_mr_table(dev); 2554 mlx4_cleanup_xrcd_table(dev); 2555 mlx4_cleanup_pd_table(dev); 2556 mlx4_cleanup_uar_table(dev); 2557 2558 err_steer: 2559 if (!mlx4_is_slave(dev)) 2560 mlx4_clear_steering(dev); 2561 2562 err_free_eq: 2563 mlx4_free_eq_table(dev); 2564 2565 err_master_mfunc: 2566 if (mlx4_is_master(dev)) 2567 mlx4_multi_func_cleanup(dev); 2568 2569 if (mlx4_is_slave(dev)) { 2570 kfree(dev->caps.qp0_qkey); 2571 kfree(dev->caps.qp0_tunnel); 2572 kfree(dev->caps.qp0_proxy); 2573 kfree(dev->caps.qp1_tunnel); 2574 kfree(dev->caps.qp1_proxy); 2575 } 2576 2577 err_close: 2578 if (dev->flags & MLX4_FLAG_MSI_X) 2579 pci_disable_msix(pdev); 2580 2581 mlx4_close_hca(dev); 2582 2583 err_mfunc: 2584 if (mlx4_is_slave(dev)) 2585 mlx4_multi_func_cleanup(dev); 2586 2587 err_cmd: 2588 mlx4_cmd_cleanup(dev); 2589 2590 err_sriov: 2591 if (dev->flags & MLX4_FLAG_SRIOV) 2592 pci_disable_sriov(pdev); 2593 2594 err_rel_own: 2595 if (!mlx4_is_slave(dev)) 2596 mlx4_free_ownership(dev); 2597 2598 if (mlx4_is_master(dev) && dev->num_vfs) 2599 atomic_dec(&pf_loading); 2600 2601 kfree(priv->dev.dev_vfs); 2602 2603 err_free_dev: 2604 kfree(priv); 2605 2606 err_release_regions: 2607 pci_release_regions(pdev); 2608 2609 err_disable_pdev: 2610 pci_disable_device(pdev); 2611 pci_set_drvdata(pdev, NULL); 2612 return err; 2613 } 2614 2615 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 2616 { 2617 struct mlx4_priv *priv; 2618 struct mlx4_dev *dev; 2619 2620 printk_once(KERN_INFO "%s", mlx4_version); 2621 2622 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 2623 if (!priv) 2624 return -ENOMEM; 2625 2626 dev = &priv->dev; 2627 pci_set_drvdata(pdev, dev); 2628 priv->pci_dev_data = id->driver_data; 2629 2630 return __mlx4_init_one(pdev, id->driver_data); 2631 } 2632 2633 static void __mlx4_remove_one(struct pci_dev *pdev) 2634 { 2635 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2636 struct mlx4_priv *priv = mlx4_priv(dev); 2637 int pci_dev_data; 2638 int p; 2639 2640 if (priv->removed) 2641 return; 2642 2643 pci_dev_data = priv->pci_dev_data; 2644 2645 /* in SRIOV it is not allowed to unload the pf's 2646 * driver while there are alive vf's */ 2647 if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev)) 2648 pr_warn("Removing PF when there are assigned VF's !!!\n"); 2649 mlx4_stop_sense(dev); 2650 mlx4_unregister_device(dev); 2651 2652 for (p = 1; p <= dev->caps.num_ports; p++) { 2653 mlx4_cleanup_port_info(&priv->port[p]); 2654 mlx4_CLOSE_PORT(dev, p); 2655 } 2656 2657 if (mlx4_is_master(dev)) 2658 mlx4_free_resource_tracker(dev, 2659 RES_TR_FREE_SLAVES_ONLY); 2660 2661 mlx4_cleanup_counters_table(dev); 2662 mlx4_cleanup_qp_table(dev); 2663 mlx4_cleanup_srq_table(dev); 2664 mlx4_cleanup_cq_table(dev); 2665 mlx4_cmd_use_polling(dev); 2666 mlx4_cleanup_eq_table(dev); 2667 mlx4_cleanup_mcg_table(dev); 2668 mlx4_cleanup_mr_table(dev); 2669 mlx4_cleanup_xrcd_table(dev); 2670 mlx4_cleanup_pd_table(dev); 2671 2672 if (mlx4_is_master(dev)) 2673 mlx4_free_resource_tracker(dev, 2674 RES_TR_FREE_STRUCTS_ONLY); 2675 2676 iounmap(priv->kar); 2677 mlx4_uar_free(dev, &priv->driver_uar); 2678 mlx4_cleanup_uar_table(dev); 2679 if (!mlx4_is_slave(dev)) 2680 mlx4_clear_steering(dev); 2681 mlx4_free_eq_table(dev); 2682 if (mlx4_is_master(dev)) 2683 mlx4_multi_func_cleanup(dev); 2684 mlx4_close_hca(dev); 2685 if (mlx4_is_slave(dev)) 2686 mlx4_multi_func_cleanup(dev); 2687 mlx4_cmd_cleanup(dev); 2688 2689 if (dev->flags & MLX4_FLAG_MSI_X) 2690 pci_disable_msix(pdev); 2691 if (dev->flags & MLX4_FLAG_SRIOV) { 2692 mlx4_warn(dev, "Disabling SR-IOV\n"); 2693 pci_disable_sriov(pdev); 2694 dev->num_vfs = 0; 2695 } 2696 2697 if (!mlx4_is_slave(dev)) 2698 mlx4_free_ownership(dev); 2699 2700 kfree(dev->caps.qp0_qkey); 2701 kfree(dev->caps.qp0_tunnel); 2702 kfree(dev->caps.qp0_proxy); 2703 kfree(dev->caps.qp1_tunnel); 2704 kfree(dev->caps.qp1_proxy); 2705 kfree(dev->dev_vfs); 2706 2707 pci_release_regions(pdev); 2708 pci_disable_device(pdev); 2709 memset(priv, 0, sizeof(*priv)); 2710 priv->pci_dev_data = pci_dev_data; 2711 priv->removed = 1; 2712 } 2713 2714 static void mlx4_remove_one(struct pci_dev *pdev) 2715 { 2716 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2717 struct mlx4_priv *priv = mlx4_priv(dev); 2718 2719 __mlx4_remove_one(pdev); 2720 kfree(priv); 2721 pci_set_drvdata(pdev, NULL); 2722 } 2723 2724 int mlx4_restart_one(struct pci_dev *pdev) 2725 { 2726 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2727 struct mlx4_priv *priv = mlx4_priv(dev); 2728 int pci_dev_data; 2729 2730 pci_dev_data = priv->pci_dev_data; 2731 __mlx4_remove_one(pdev); 2732 return __mlx4_init_one(pdev, pci_dev_data); 2733 } 2734 2735 static const struct pci_device_id mlx4_pci_table[] = { 2736 /* MT25408 "Hermon" SDR */ 2737 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2738 /* MT25408 "Hermon" DDR */ 2739 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2740 /* MT25408 "Hermon" QDR */ 2741 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2742 /* MT25408 "Hermon" DDR PCIe gen2 */ 2743 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2744 /* MT25408 "Hermon" QDR PCIe gen2 */ 2745 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2746 /* MT25408 "Hermon" EN 10GigE */ 2747 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2748 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 2749 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2750 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 2751 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2752 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 2753 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2754 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 2755 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2756 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 2757 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2758 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 2759 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2760 /* MT25400 Family [ConnectX-2 Virtual Function] */ 2761 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 2762 /* MT27500 Family [ConnectX-3] */ 2763 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 2764 /* MT27500 Family [ConnectX-3 Virtual Function] */ 2765 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 2766 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 2767 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 2768 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 2769 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 2770 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 2771 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 2772 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 2773 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 2774 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 2775 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 2776 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 2777 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 2778 { 0, } 2779 }; 2780 2781 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 2782 2783 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 2784 pci_channel_state_t state) 2785 { 2786 __mlx4_remove_one(pdev); 2787 2788 return state == pci_channel_io_perm_failure ? 2789 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2790 } 2791 2792 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 2793 { 2794 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2795 struct mlx4_priv *priv = mlx4_priv(dev); 2796 int ret; 2797 2798 ret = __mlx4_init_one(pdev, priv->pci_dev_data); 2799 2800 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 2801 } 2802 2803 static const struct pci_error_handlers mlx4_err_handler = { 2804 .error_detected = mlx4_pci_err_detected, 2805 .slot_reset = mlx4_pci_slot_reset, 2806 }; 2807 2808 static struct pci_driver mlx4_driver = { 2809 .name = DRV_NAME, 2810 .id_table = mlx4_pci_table, 2811 .probe = mlx4_init_one, 2812 .shutdown = __mlx4_remove_one, 2813 .remove = mlx4_remove_one, 2814 .err_handler = &mlx4_err_handler, 2815 }; 2816 2817 static int __init mlx4_verify_params(void) 2818 { 2819 if ((log_num_mac < 0) || (log_num_mac > 7)) { 2820 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 2821 return -1; 2822 } 2823 2824 if (log_num_vlan != 0) 2825 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 2826 MLX4_LOG_NUM_VLANS); 2827 2828 if (use_prio != 0) 2829 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 2830 2831 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 2832 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 2833 log_mtts_per_seg); 2834 return -1; 2835 } 2836 2837 /* Check if module param for ports type has legal combination */ 2838 if (port_type_array[0] == false && port_type_array[1] == true) { 2839 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 2840 port_type_array[0] = true; 2841 } 2842 2843 if (mlx4_log_num_mgm_entry_size != -1 && 2844 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 2845 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { 2846 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n", 2847 mlx4_log_num_mgm_entry_size, 2848 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 2849 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 2850 return -1; 2851 } 2852 2853 return 0; 2854 } 2855 2856 static int __init mlx4_init(void) 2857 { 2858 int ret; 2859 2860 if (mlx4_verify_params()) 2861 return -EINVAL; 2862 2863 mlx4_catas_init(); 2864 2865 mlx4_wq = create_singlethread_workqueue("mlx4"); 2866 if (!mlx4_wq) 2867 return -ENOMEM; 2868 2869 ret = pci_register_driver(&mlx4_driver); 2870 if (ret < 0) 2871 destroy_workqueue(mlx4_wq); 2872 return ret < 0 ? ret : 0; 2873 } 2874 2875 static void __exit mlx4_cleanup(void) 2876 { 2877 pci_unregister_driver(&mlx4_driver); 2878 destroy_workqueue(mlx4_wq); 2879 } 2880 2881 module_init(mlx4_init); 2882 module_exit(mlx4_cleanup); 2883