1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/errno.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/slab.h> 43 #include <linux/io-mapping.h> 44 #include <linux/delay.h> 45 #include <linux/kmod.h> 46 #include <linux/etherdevice.h> 47 #include <net/devlink.h> 48 49 #include <uapi/rdma/mlx4-abi.h> 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/doorbell.h> 52 53 #include "mlx4.h" 54 #include "fw.h" 55 #include "icm.h" 56 57 MODULE_AUTHOR("Roland Dreier"); 58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 MODULE_VERSION(DRV_VERSION); 61 62 struct workqueue_struct *mlx4_wq; 63 64 #ifdef CONFIG_MLX4_DEBUG 65 66 int mlx4_debug_level; /* 0 by default */ 67 module_param_named(debug_level, mlx4_debug_level, int, 0644); 68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 69 70 #endif /* CONFIG_MLX4_DEBUG */ 71 72 #ifdef CONFIG_PCI_MSI 73 74 static int msi_x = 1; 75 module_param(msi_x, int, 0444); 76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 77 78 #else /* CONFIG_PCI_MSI */ 79 80 #define msi_x (0) 81 82 #endif /* CONFIG_PCI_MSI */ 83 84 static uint8_t num_vfs[3] = {0, 0, 0}; 85 static int num_vfs_argc; 86 module_param_array(num_vfs, byte, &num_vfs_argc, 0444); 87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 88 "num_vfs=port1,port2,port1+2"); 89 90 static uint8_t probe_vf[3] = {0, 0, 0}; 91 static int probe_vfs_argc; 92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 94 "probe_vf=port1,port2,port1+2"); 95 96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 97 module_param_named(log_num_mgm_entry_size, 98 mlx4_log_num_mgm_entry_size, int, 0444); 99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 100 " of qp per mcg, for example:" 101 " 10 gives 248.range: 7 <=" 102 " log_num_mgm_entry_size <= 12." 103 " To activate device managed" 104 " flow steering when available, set to -1"); 105 106 static bool enable_64b_cqe_eqe = true; 107 module_param(enable_64b_cqe_eqe, bool, 0444); 108 MODULE_PARM_DESC(enable_64b_cqe_eqe, 109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 110 111 static bool enable_4k_uar; 112 module_param(enable_4k_uar, bool, 0444); 113 MODULE_PARM_DESC(enable_4k_uar, 114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 115 116 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 118 MLX4_FUNC_CAP_DMFS_A0_STATIC) 119 120 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 121 122 static char mlx4_version[] = 123 DRV_NAME ": Mellanox ConnectX core driver v" 124 DRV_VERSION "\n"; 125 126 static const struct mlx4_profile default_profile = { 127 .num_qp = 1 << 18, 128 .num_srq = 1 << 16, 129 .rdmarc_per_qp = 1 << 4, 130 .num_cq = 1 << 16, 131 .num_mcg = 1 << 13, 132 .num_mpt = 1 << 19, 133 .num_mtt = 1 << 20, /* It is really num mtt segements */ 134 }; 135 136 static const struct mlx4_profile low_mem_profile = { 137 .num_qp = 1 << 17, 138 .num_srq = 1 << 6, 139 .rdmarc_per_qp = 1 << 4, 140 .num_cq = 1 << 8, 141 .num_mcg = 1 << 8, 142 .num_mpt = 1 << 9, 143 .num_mtt = 1 << 7, 144 }; 145 146 static int log_num_mac = 7; 147 module_param_named(log_num_mac, log_num_mac, int, 0444); 148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 149 150 static int log_num_vlan; 151 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 153 /* Log2 max number of VLANs per ETH port (0-7) */ 154 #define MLX4_LOG_NUM_VLANS 7 155 #define MLX4_MIN_LOG_NUM_VLANS 0 156 #define MLX4_MIN_LOG_NUM_MAC 1 157 158 static bool use_prio; 159 module_param_named(use_prio, use_prio, bool, 0444); 160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 161 162 int log_mtts_per_seg = ilog2(1); 163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 165 "(0-7) (default: 0)"); 166 167 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 168 static int arr_argc = 2; 169 module_param_array(port_type_array, int, &arr_argc, 0444); 170 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 171 "1 for IB, 2 for Ethernet"); 172 173 struct mlx4_port_config { 174 struct list_head list; 175 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 176 struct pci_dev *pdev; 177 }; 178 179 static atomic_t pf_loading = ATOMIC_INIT(0); 180 181 static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 182 struct devlink_param_gset_ctx *ctx) 183 { 184 ctx->val.vbool = !!mlx4_internal_err_reset; 185 return 0; 186 } 187 188 static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 189 struct devlink_param_gset_ctx *ctx) 190 { 191 mlx4_internal_err_reset = ctx->val.vbool; 192 return 0; 193 } 194 195 static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 196 struct devlink_param_gset_ctx *ctx) 197 { 198 struct mlx4_priv *priv = devlink_priv(devlink); 199 struct mlx4_dev *dev = &priv->dev; 200 201 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 202 return 0; 203 } 204 205 static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 206 struct devlink_param_gset_ctx *ctx) 207 { 208 struct mlx4_priv *priv = devlink_priv(devlink); 209 struct mlx4_dev *dev = &priv->dev; 210 211 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 212 return 0; 213 } 214 215 static int 216 mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 217 union devlink_param_value val, 218 struct netlink_ext_ack *extack) 219 { 220 u32 value = val.vu32; 221 222 if (value < 1 || value > 128) 223 return -ERANGE; 224 225 if (!is_power_of_2(value)) { 226 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 enum mlx4_devlink_param_id { 234 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 235 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 236 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 237 }; 238 239 static const struct devlink_param mlx4_devlink_params[] = { 240 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 241 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 242 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 243 mlx4_devlink_ierr_reset_get, 244 mlx4_devlink_ierr_reset_set, NULL), 245 DEVLINK_PARAM_GENERIC(MAX_MACS, 246 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 247 NULL, NULL, mlx4_devlink_max_macs_validate), 248 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 249 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 250 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 251 mlx4_devlink_crdump_snapshot_get, 252 mlx4_devlink_crdump_snapshot_set, NULL), 253 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 254 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 255 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 256 NULL, NULL, NULL), 257 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 258 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 259 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 260 NULL, NULL, NULL), 261 }; 262 263 static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 264 { 265 union devlink_param_value value; 266 267 value.vbool = !!mlx4_internal_err_reset; 268 devlink_param_driverinit_value_set(devlink, 269 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 270 value); 271 272 value.vu32 = 1UL << log_num_mac; 273 devlink_param_driverinit_value_set(devlink, 274 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 275 value); 276 277 value.vbool = enable_64b_cqe_eqe; 278 devlink_param_driverinit_value_set(devlink, 279 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 280 value); 281 282 value.vbool = enable_4k_uar; 283 devlink_param_driverinit_value_set(devlink, 284 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 285 value); 286 287 value.vbool = false; 288 devlink_param_driverinit_value_set(devlink, 289 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 290 value); 291 } 292 293 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 294 struct mlx4_dev_cap *dev_cap) 295 { 296 /* The reserved_uars is calculated by system page size unit. 297 * Therefore, adjustment is added when the uar page size is less 298 * than the system page size 299 */ 300 dev->caps.reserved_uars = 301 max_t(int, 302 mlx4_get_num_reserved_uar(dev), 303 dev_cap->reserved_uars / 304 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 305 } 306 307 int mlx4_check_port_params(struct mlx4_dev *dev, 308 enum mlx4_port_type *port_type) 309 { 310 int i; 311 312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 313 for (i = 0; i < dev->caps.num_ports - 1; i++) { 314 if (port_type[i] != port_type[i + 1]) { 315 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 316 return -EOPNOTSUPP; 317 } 318 } 319 } 320 321 for (i = 0; i < dev->caps.num_ports; i++) { 322 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 323 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 324 i + 1); 325 return -EOPNOTSUPP; 326 } 327 } 328 return 0; 329 } 330 331 static void mlx4_set_port_mask(struct mlx4_dev *dev) 332 { 333 int i; 334 335 for (i = 1; i <= dev->caps.num_ports; ++i) 336 dev->caps.port_mask[i] = dev->caps.port_type[i]; 337 } 338 339 enum { 340 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 341 }; 342 343 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 344 { 345 int err = 0; 346 struct mlx4_func func; 347 348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 349 err = mlx4_QUERY_FUNC(dev, &func, 0); 350 if (err) { 351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 352 return err; 353 } 354 dev_cap->max_eqs = func.max_eq; 355 dev_cap->reserved_eqs = func.rsvd_eqs; 356 dev_cap->reserved_uars = func.rsvd_uars; 357 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 358 } 359 return err; 360 } 361 362 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 363 { 364 struct mlx4_caps *dev_cap = &dev->caps; 365 366 /* FW not supporting or cancelled by user */ 367 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 368 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 369 return; 370 371 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 372 * When FW has NCSI it may decide not to report 64B CQE/EQEs 373 */ 374 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 375 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 376 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 377 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 378 return; 379 } 380 381 if (cache_line_size() == 128 || cache_line_size() == 256) { 382 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 383 /* Changing the real data inside CQE size to 32B */ 384 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 385 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 386 387 if (mlx4_is_master(dev)) 388 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 389 } else { 390 if (cache_line_size() != 32 && cache_line_size() != 64) 391 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 392 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 393 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 394 } 395 } 396 397 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 398 struct mlx4_port_cap *port_cap) 399 { 400 dev->caps.vl_cap[port] = port_cap->max_vl; 401 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 402 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 403 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 404 /* set gid and pkey table operating lengths by default 405 * to non-sriov values 406 */ 407 dev->caps.gid_table_len[port] = port_cap->max_gids; 408 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 409 dev->caps.port_width_cap[port] = port_cap->max_port_width; 410 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 411 dev->caps.max_tc_eth = port_cap->max_tc_eth; 412 dev->caps.def_mac[port] = port_cap->def_mac; 413 dev->caps.supported_type[port] = port_cap->supported_port_types; 414 dev->caps.suggested_type[port] = port_cap->suggested_type; 415 dev->caps.default_sense[port] = port_cap->default_sense; 416 dev->caps.trans_type[port] = port_cap->trans_type; 417 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 418 dev->caps.wavelength[port] = port_cap->wavelength; 419 dev->caps.trans_code[port] = port_cap->trans_code; 420 421 return 0; 422 } 423 424 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 425 struct mlx4_port_cap *port_cap) 426 { 427 int err = 0; 428 429 err = mlx4_QUERY_PORT(dev, port, port_cap); 430 431 if (err) 432 mlx4_err(dev, "QUERY_PORT command failed.\n"); 433 434 return err; 435 } 436 437 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 438 { 439 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 440 return; 441 442 if (mlx4_is_mfunc(dev)) { 443 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 444 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 445 return; 446 } 447 448 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 449 mlx4_dbg(dev, 450 "Keep FCS is not supported - Disabling Ignore FCS"); 451 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 452 return; 453 } 454 } 455 456 #define MLX4_A0_STEERING_TABLE_SIZE 256 457 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 458 { 459 int err; 460 int i; 461 462 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 463 if (err) { 464 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 465 return err; 466 } 467 mlx4_dev_cap_dump(dev, dev_cap); 468 469 if (dev_cap->min_page_sz > PAGE_SIZE) { 470 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 471 dev_cap->min_page_sz, PAGE_SIZE); 472 return -ENODEV; 473 } 474 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 475 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 476 dev_cap->num_ports, MLX4_MAX_PORTS); 477 return -ENODEV; 478 } 479 480 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 481 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 482 dev_cap->uar_size, 483 (unsigned long long) 484 pci_resource_len(dev->persist->pdev, 2)); 485 return -ENODEV; 486 } 487 488 dev->caps.num_ports = dev_cap->num_ports; 489 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 490 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 491 dev->caps.num_sys_eqs : 492 MLX4_MAX_EQ_NUM; 493 for (i = 1; i <= dev->caps.num_ports; ++i) { 494 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 495 if (err) { 496 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 497 return err; 498 } 499 } 500 501 dev->caps.uar_page_size = PAGE_SIZE; 502 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 503 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 504 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 505 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 506 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 507 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 508 dev->caps.max_wqes = dev_cap->max_qp_sz; 509 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 510 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 511 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 512 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 513 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 514 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 515 /* 516 * Subtract 1 from the limit because we need to allocate a 517 * spare CQE so the HCA HW can tell the difference between an 518 * empty CQ and a full CQ. 519 */ 520 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 521 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 522 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 523 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 524 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 525 526 dev->caps.reserved_pds = dev_cap->reserved_pds; 527 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 528 dev_cap->reserved_xrcds : 0; 529 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 530 dev_cap->max_xrcds : 0; 531 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 532 533 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 534 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 535 dev->caps.flags = dev_cap->flags; 536 dev->caps.flags2 = dev_cap->flags2; 537 dev->caps.bmme_flags = dev_cap->bmme_flags; 538 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 539 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 540 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 541 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 542 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 543 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 544 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 545 546 /* Save uar page shift */ 547 if (!mlx4_is_slave(dev)) { 548 /* Virtual PCI function needs to determine UAR page size from 549 * firmware. Only master PCI function can set the uar page size 550 */ 551 if (enable_4k_uar || !dev->persist->num_vfs) 552 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 553 else 554 dev->uar_page_shift = PAGE_SHIFT; 555 556 mlx4_set_num_reserved_uars(dev, dev_cap); 557 } 558 559 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 560 struct mlx4_init_hca_param hca_param; 561 562 memset(&hca_param, 0, sizeof(hca_param)); 563 err = mlx4_QUERY_HCA(dev, &hca_param); 564 /* Turn off PHV_EN flag in case phv_check_en is set. 565 * phv_check_en is a HW check that parse the packet and verify 566 * phv bit was reported correctly in the wqe. To allow QinQ 567 * PHV_EN flag should be set and phv_check_en must be cleared 568 * otherwise QinQ packets will be drop by the HW. 569 */ 570 if (err || hca_param.phv_check_en) 571 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 572 } 573 574 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 575 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 576 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 577 /* Don't do sense port on multifunction devices (for now at least) */ 578 if (mlx4_is_mfunc(dev)) 579 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 580 581 if (mlx4_low_memory_profile()) { 582 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 583 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 584 } else { 585 dev->caps.log_num_macs = log_num_mac; 586 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 587 } 588 589 for (i = 1; i <= dev->caps.num_ports; ++i) { 590 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 591 if (dev->caps.supported_type[i]) { 592 /* if only ETH is supported - assign ETH */ 593 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 594 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 595 /* if only IB is supported, assign IB */ 596 else if (dev->caps.supported_type[i] == 597 MLX4_PORT_TYPE_IB) 598 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 599 else { 600 /* if IB and ETH are supported, we set the port 601 * type according to user selection of port type; 602 * if user selected none, take the FW hint */ 603 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 604 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 605 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 606 else 607 dev->caps.port_type[i] = port_type_array[i - 1]; 608 } 609 } 610 /* 611 * Link sensing is allowed on the port if 3 conditions are true: 612 * 1. Both protocols are supported on the port. 613 * 2. Different types are supported on the port 614 * 3. FW declared that it supports link sensing 615 */ 616 mlx4_priv(dev)->sense.sense_allowed[i] = 617 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 618 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 619 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 620 621 /* 622 * If "default_sense" bit is set, we move the port to "AUTO" mode 623 * and perform sense_port FW command to try and set the correct 624 * port type from beginning 625 */ 626 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 627 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 628 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 629 mlx4_SENSE_PORT(dev, i, &sensed_port); 630 if (sensed_port != MLX4_PORT_TYPE_NONE) 631 dev->caps.port_type[i] = sensed_port; 632 } else { 633 dev->caps.possible_type[i] = dev->caps.port_type[i]; 634 } 635 636 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 637 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 638 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 639 i, 1 << dev->caps.log_num_macs); 640 } 641 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 642 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 643 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 644 i, 1 << dev->caps.log_num_vlans); 645 } 646 } 647 648 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 649 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 650 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 651 mlx4_warn(dev, 652 "Granular QoS per VF not supported with IB/Eth configuration\n"); 653 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 654 } 655 656 dev->caps.max_counters = dev_cap->max_counters; 657 658 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 660 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 661 (1 << dev->caps.log_num_macs) * 662 (1 << dev->caps.log_num_vlans) * 663 dev->caps.num_ports; 664 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 665 666 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 667 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 668 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 669 else 670 dev->caps.dmfs_high_rate_qpn_base = 671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 672 673 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 674 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 675 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 677 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 678 } else { 679 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 680 dev->caps.dmfs_high_rate_qpn_base = 681 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 682 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 683 } 684 685 dev->caps.rl_caps = dev_cap->rl_caps; 686 687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 688 dev->caps.dmfs_high_rate_qpn_range; 689 690 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 691 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 694 695 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 696 697 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 698 if (dev_cap->flags & 699 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 700 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 702 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 703 } 704 705 if (dev_cap->flags2 & 706 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 707 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 708 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 709 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 710 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 711 } 712 } 713 714 if ((dev->caps.flags & 715 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 716 mlx4_is_master(dev)) 717 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 718 719 if (!mlx4_is_slave(dev)) { 720 mlx4_enable_cqe_eqe_stride(dev); 721 dev->caps.alloc_res_qp_mask = 722 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 723 MLX4_RESERVE_A0_QP; 724 725 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 726 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 727 mlx4_warn(dev, "Old device ETS support detected\n"); 728 mlx4_warn(dev, "Consider upgrading device FW.\n"); 729 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 730 } 731 732 } else { 733 dev->caps.alloc_res_qp_mask = 0; 734 } 735 736 mlx4_enable_ignore_fcs(dev); 737 738 return 0; 739 } 740 741 /*The function checks if there are live vf, return the num of them*/ 742 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 743 { 744 struct mlx4_priv *priv = mlx4_priv(dev); 745 struct mlx4_slave_state *s_state; 746 int i; 747 int ret = 0; 748 749 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 750 s_state = &priv->mfunc.master.slave_state[i]; 751 if (s_state->active && s_state->last_cmd != 752 MLX4_COMM_CMD_RESET) { 753 mlx4_warn(dev, "%s: slave: %d is still active\n", 754 __func__, i); 755 ret++; 756 } 757 } 758 return ret; 759 } 760 761 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 762 { 763 u32 qk = MLX4_RESERVED_QKEY_BASE; 764 765 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 766 qpn < dev->phys_caps.base_proxy_sqpn) 767 return -EINVAL; 768 769 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 770 /* tunnel qp */ 771 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 772 else 773 qk += qpn - dev->phys_caps.base_proxy_sqpn; 774 *qkey = qk; 775 return 0; 776 } 777 EXPORT_SYMBOL(mlx4_get_parav_qkey); 778 779 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 780 { 781 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 782 783 if (!mlx4_is_master(dev)) 784 return; 785 786 priv->virt2phys_pkey[slave][port - 1][i] = val; 787 } 788 EXPORT_SYMBOL(mlx4_sync_pkey_table); 789 790 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 791 { 792 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 793 794 if (!mlx4_is_master(dev)) 795 return; 796 797 priv->slave_node_guids[slave] = guid; 798 } 799 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 800 801 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 802 { 803 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 804 805 if (!mlx4_is_master(dev)) 806 return 0; 807 808 return priv->slave_node_guids[slave]; 809 } 810 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 811 812 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 813 { 814 struct mlx4_priv *priv = mlx4_priv(dev); 815 struct mlx4_slave_state *s_slave; 816 817 if (!mlx4_is_master(dev)) 818 return 0; 819 820 s_slave = &priv->mfunc.master.slave_state[slave]; 821 return !!s_slave->active; 822 } 823 EXPORT_SYMBOL(mlx4_is_slave_active); 824 825 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 826 struct _rule_hw *eth_header) 827 { 828 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 829 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 830 struct mlx4_net_trans_rule_hw_eth *eth = 831 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 832 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 833 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 834 next_rule->rsvd == 0; 835 836 if (last_rule) 837 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 838 } 839 } 840 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 841 842 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 843 struct mlx4_dev_cap *dev_cap, 844 struct mlx4_init_hca_param *hca_param) 845 { 846 dev->caps.steering_mode = hca_param->steering_mode; 847 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 848 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 849 dev->caps.fs_log_max_ucast_qp_range_size = 850 dev_cap->fs_log_max_ucast_qp_range_size; 851 } else 852 dev->caps.num_qp_per_mgm = 853 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 854 855 mlx4_dbg(dev, "Steering mode is: %s\n", 856 mlx4_steering_mode_str(dev->caps.steering_mode)); 857 } 858 859 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 860 { 861 kfree(dev->caps.spec_qps); 862 dev->caps.spec_qps = NULL; 863 } 864 865 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 866 { 867 struct mlx4_func_cap *func_cap = NULL; 868 struct mlx4_caps *caps = &dev->caps; 869 int i, err = 0; 870 871 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 872 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 873 874 if (!func_cap || !caps->spec_qps) { 875 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 876 err = -ENOMEM; 877 goto err_mem; 878 } 879 880 for (i = 1; i <= caps->num_ports; ++i) { 881 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 882 if (err) { 883 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 884 i, err); 885 goto err_mem; 886 } 887 caps->spec_qps[i - 1] = func_cap->spec_qps; 888 caps->port_mask[i] = caps->port_type[i]; 889 caps->phys_port_id[i] = func_cap->phys_port_id; 890 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 891 &caps->gid_table_len[i], 892 &caps->pkey_table_len[i]); 893 if (err) { 894 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 895 i, err); 896 goto err_mem; 897 } 898 } 899 900 err_mem: 901 if (err) 902 mlx4_slave_destroy_special_qp_cap(dev); 903 kfree(func_cap); 904 return err; 905 } 906 907 static int mlx4_slave_cap(struct mlx4_dev *dev) 908 { 909 int err; 910 u32 page_size; 911 struct mlx4_dev_cap *dev_cap = NULL; 912 struct mlx4_func_cap *func_cap = NULL; 913 struct mlx4_init_hca_param *hca_param = NULL; 914 915 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 916 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 917 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 918 if (!hca_param || !func_cap || !dev_cap) { 919 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 920 err = -ENOMEM; 921 goto free_mem; 922 } 923 924 err = mlx4_QUERY_HCA(dev, hca_param); 925 if (err) { 926 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 927 goto free_mem; 928 } 929 930 /* fail if the hca has an unknown global capability 931 * at this time global_caps should be always zeroed 932 */ 933 if (hca_param->global_caps) { 934 mlx4_err(dev, "Unknown hca global capabilities\n"); 935 err = -EINVAL; 936 goto free_mem; 937 } 938 939 dev->caps.hca_core_clock = hca_param->hca_core_clock; 940 941 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 942 err = mlx4_dev_cap(dev, dev_cap); 943 if (err) { 944 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 945 goto free_mem; 946 } 947 948 err = mlx4_QUERY_FW(dev); 949 if (err) 950 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 951 952 page_size = ~dev->caps.page_size_cap + 1; 953 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 954 if (page_size > PAGE_SIZE) { 955 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 956 page_size, PAGE_SIZE); 957 err = -ENODEV; 958 goto free_mem; 959 } 960 961 /* Set uar_page_shift for VF */ 962 dev->uar_page_shift = hca_param->uar_page_sz + 12; 963 964 /* Make sure the master uar page size is valid */ 965 if (dev->uar_page_shift > PAGE_SHIFT) { 966 mlx4_err(dev, 967 "Invalid configuration: uar page size is larger than system page size\n"); 968 err = -ENODEV; 969 goto free_mem; 970 } 971 972 /* Set reserved_uars based on the uar_page_shift */ 973 mlx4_set_num_reserved_uars(dev, dev_cap); 974 975 /* Although uar page size in FW differs from system page size, 976 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 977 * still works with assumption that uar page size == system page size 978 */ 979 dev->caps.uar_page_size = PAGE_SIZE; 980 981 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 982 if (err) { 983 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 984 err); 985 goto free_mem; 986 } 987 988 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 989 PF_CONTEXT_BEHAVIOUR_MASK) { 990 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 991 func_cap->pf_context_behaviour, 992 PF_CONTEXT_BEHAVIOUR_MASK); 993 err = -EINVAL; 994 goto free_mem; 995 } 996 997 dev->caps.num_ports = func_cap->num_ports; 998 dev->quotas.qp = func_cap->qp_quota; 999 dev->quotas.srq = func_cap->srq_quota; 1000 dev->quotas.cq = func_cap->cq_quota; 1001 dev->quotas.mpt = func_cap->mpt_quota; 1002 dev->quotas.mtt = func_cap->mtt_quota; 1003 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1004 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1005 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1006 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1007 dev->caps.num_eqs = func_cap->max_eq; 1008 dev->caps.reserved_eqs = func_cap->reserved_eq; 1009 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1010 dev->caps.num_pds = MLX4_NUM_PDS; 1011 dev->caps.num_mgms = 0; 1012 dev->caps.num_amgms = 0; 1013 1014 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1015 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1016 dev->caps.num_ports, MLX4_MAX_PORTS); 1017 err = -ENODEV; 1018 goto free_mem; 1019 } 1020 1021 mlx4_replace_zero_macs(dev); 1022 1023 err = mlx4_slave_special_qp_cap(dev); 1024 if (err) { 1025 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1026 goto free_mem; 1027 } 1028 1029 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1030 dev->caps.reserved_uars) > 1031 pci_resource_len(dev->persist->pdev, 1032 2)) { 1033 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1034 dev->caps.uar_page_size * dev->caps.num_uars, 1035 (unsigned long long) 1036 pci_resource_len(dev->persist->pdev, 2)); 1037 err = -ENOMEM; 1038 goto err_mem; 1039 } 1040 1041 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1042 dev->caps.eqe_size = 64; 1043 dev->caps.eqe_factor = 1; 1044 } else { 1045 dev->caps.eqe_size = 32; 1046 dev->caps.eqe_factor = 0; 1047 } 1048 1049 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1050 dev->caps.cqe_size = 64; 1051 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1052 } else { 1053 dev->caps.cqe_size = 32; 1054 } 1055 1056 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1057 dev->caps.eqe_size = hca_param->eqe_size; 1058 dev->caps.eqe_factor = 0; 1059 } 1060 1061 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1062 dev->caps.cqe_size = hca_param->cqe_size; 1063 /* User still need to know when CQE > 32B */ 1064 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1065 } 1066 1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1068 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1069 1070 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1071 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1072 1073 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1074 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1075 hca_param->rss_ip_frags ? "on" : "off"); 1076 1077 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1078 dev->caps.bf_reg_size) 1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1080 1081 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1082 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1083 1084 err_mem: 1085 if (err) 1086 mlx4_slave_destroy_special_qp_cap(dev); 1087 free_mem: 1088 kfree(hca_param); 1089 kfree(func_cap); 1090 kfree(dev_cap); 1091 return err; 1092 } 1093 1094 static void mlx4_request_modules(struct mlx4_dev *dev) 1095 { 1096 int port; 1097 int has_ib_port = false; 1098 int has_eth_port = false; 1099 #define EN_DRV_NAME "mlx4_en" 1100 #define IB_DRV_NAME "mlx4_ib" 1101 1102 for (port = 1; port <= dev->caps.num_ports; port++) { 1103 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1104 has_ib_port = true; 1105 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1106 has_eth_port = true; 1107 } 1108 1109 if (has_eth_port) 1110 request_module_nowait(EN_DRV_NAME); 1111 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1112 request_module_nowait(IB_DRV_NAME); 1113 } 1114 1115 /* 1116 * Change the port configuration of the device. 1117 * Every user of this function must hold the port mutex. 1118 */ 1119 int mlx4_change_port_types(struct mlx4_dev *dev, 1120 enum mlx4_port_type *port_types) 1121 { 1122 int err = 0; 1123 int change = 0; 1124 int port; 1125 1126 for (port = 0; port < dev->caps.num_ports; port++) { 1127 /* Change the port type only if the new type is different 1128 * from the current, and not set to Auto */ 1129 if (port_types[port] != dev->caps.port_type[port + 1]) 1130 change = 1; 1131 } 1132 if (change) { 1133 mlx4_unregister_device(dev); 1134 for (port = 1; port <= dev->caps.num_ports; port++) { 1135 mlx4_CLOSE_PORT(dev, port); 1136 dev->caps.port_type[port] = port_types[port - 1]; 1137 err = mlx4_SET_PORT(dev, port, -1); 1138 if (err) { 1139 mlx4_err(dev, "Failed to set port %d, aborting\n", 1140 port); 1141 goto out; 1142 } 1143 } 1144 mlx4_set_port_mask(dev); 1145 err = mlx4_register_device(dev); 1146 if (err) { 1147 mlx4_err(dev, "Failed to register device\n"); 1148 goto out; 1149 } 1150 mlx4_request_modules(dev); 1151 } 1152 1153 out: 1154 return err; 1155 } 1156 1157 static ssize_t show_port_type(struct device *dev, 1158 struct device_attribute *attr, 1159 char *buf) 1160 { 1161 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1162 port_attr); 1163 struct mlx4_dev *mdev = info->dev; 1164 char type[8]; 1165 1166 sprintf(type, "%s", 1167 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1168 "ib" : "eth"); 1169 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1170 sprintf(buf, "auto (%s)\n", type); 1171 else 1172 sprintf(buf, "%s\n", type); 1173 1174 return strlen(buf); 1175 } 1176 1177 static int __set_port_type(struct mlx4_port_info *info, 1178 enum mlx4_port_type port_type) 1179 { 1180 struct mlx4_dev *mdev = info->dev; 1181 struct mlx4_priv *priv = mlx4_priv(mdev); 1182 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1183 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1184 int i; 1185 int err = 0; 1186 1187 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1188 mlx4_err(mdev, 1189 "Requested port type for port %d is not supported on this HCA\n", 1190 info->port); 1191 return -EOPNOTSUPP; 1192 } 1193 1194 mlx4_stop_sense(mdev); 1195 mutex_lock(&priv->port_mutex); 1196 info->tmp_type = port_type; 1197 1198 /* Possible type is always the one that was delivered */ 1199 mdev->caps.possible_type[info->port] = info->tmp_type; 1200 1201 for (i = 0; i < mdev->caps.num_ports; i++) { 1202 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1203 mdev->caps.possible_type[i+1]; 1204 if (types[i] == MLX4_PORT_TYPE_AUTO) 1205 types[i] = mdev->caps.port_type[i+1]; 1206 } 1207 1208 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1209 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1210 for (i = 1; i <= mdev->caps.num_ports; i++) { 1211 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1212 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1213 err = -EOPNOTSUPP; 1214 } 1215 } 1216 } 1217 if (err) { 1218 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1219 goto out; 1220 } 1221 1222 mlx4_do_sense_ports(mdev, new_types, types); 1223 1224 err = mlx4_check_port_params(mdev, new_types); 1225 if (err) 1226 goto out; 1227 1228 /* We are about to apply the changes after the configuration 1229 * was verified, no need to remember the temporary types 1230 * any more */ 1231 for (i = 0; i < mdev->caps.num_ports; i++) 1232 priv->port[i + 1].tmp_type = 0; 1233 1234 err = mlx4_change_port_types(mdev, new_types); 1235 1236 out: 1237 mlx4_start_sense(mdev); 1238 mutex_unlock(&priv->port_mutex); 1239 1240 return err; 1241 } 1242 1243 static ssize_t set_port_type(struct device *dev, 1244 struct device_attribute *attr, 1245 const char *buf, size_t count) 1246 { 1247 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1248 port_attr); 1249 struct mlx4_dev *mdev = info->dev; 1250 enum mlx4_port_type port_type; 1251 static DEFINE_MUTEX(set_port_type_mutex); 1252 int err; 1253 1254 mutex_lock(&set_port_type_mutex); 1255 1256 if (!strcmp(buf, "ib\n")) { 1257 port_type = MLX4_PORT_TYPE_IB; 1258 } else if (!strcmp(buf, "eth\n")) { 1259 port_type = MLX4_PORT_TYPE_ETH; 1260 } else if (!strcmp(buf, "auto\n")) { 1261 port_type = MLX4_PORT_TYPE_AUTO; 1262 } else { 1263 mlx4_err(mdev, "%s is not supported port type\n", buf); 1264 err = -EINVAL; 1265 goto err_out; 1266 } 1267 1268 err = __set_port_type(info, port_type); 1269 1270 err_out: 1271 mutex_unlock(&set_port_type_mutex); 1272 1273 return err ? err : count; 1274 } 1275 1276 enum ibta_mtu { 1277 IB_MTU_256 = 1, 1278 IB_MTU_512 = 2, 1279 IB_MTU_1024 = 3, 1280 IB_MTU_2048 = 4, 1281 IB_MTU_4096 = 5 1282 }; 1283 1284 static inline int int_to_ibta_mtu(int mtu) 1285 { 1286 switch (mtu) { 1287 case 256: return IB_MTU_256; 1288 case 512: return IB_MTU_512; 1289 case 1024: return IB_MTU_1024; 1290 case 2048: return IB_MTU_2048; 1291 case 4096: return IB_MTU_4096; 1292 default: return -1; 1293 } 1294 } 1295 1296 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1297 { 1298 switch (mtu) { 1299 case IB_MTU_256: return 256; 1300 case IB_MTU_512: return 512; 1301 case IB_MTU_1024: return 1024; 1302 case IB_MTU_2048: return 2048; 1303 case IB_MTU_4096: return 4096; 1304 default: return -1; 1305 } 1306 } 1307 1308 static ssize_t show_port_ib_mtu(struct device *dev, 1309 struct device_attribute *attr, 1310 char *buf) 1311 { 1312 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1313 port_mtu_attr); 1314 struct mlx4_dev *mdev = info->dev; 1315 1316 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1317 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1318 1319 sprintf(buf, "%d\n", 1320 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1321 return strlen(buf); 1322 } 1323 1324 static ssize_t set_port_ib_mtu(struct device *dev, 1325 struct device_attribute *attr, 1326 const char *buf, size_t count) 1327 { 1328 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1329 port_mtu_attr); 1330 struct mlx4_dev *mdev = info->dev; 1331 struct mlx4_priv *priv = mlx4_priv(mdev); 1332 int err, port, mtu, ibta_mtu = -1; 1333 1334 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1335 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1336 return -EINVAL; 1337 } 1338 1339 err = kstrtoint(buf, 0, &mtu); 1340 if (!err) 1341 ibta_mtu = int_to_ibta_mtu(mtu); 1342 1343 if (err || ibta_mtu < 0) { 1344 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1345 return -EINVAL; 1346 } 1347 1348 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1349 1350 mlx4_stop_sense(mdev); 1351 mutex_lock(&priv->port_mutex); 1352 mlx4_unregister_device(mdev); 1353 for (port = 1; port <= mdev->caps.num_ports; port++) { 1354 mlx4_CLOSE_PORT(mdev, port); 1355 err = mlx4_SET_PORT(mdev, port, -1); 1356 if (err) { 1357 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1358 port); 1359 goto err_set_port; 1360 } 1361 } 1362 err = mlx4_register_device(mdev); 1363 err_set_port: 1364 mutex_unlock(&priv->port_mutex); 1365 mlx4_start_sense(mdev); 1366 return err ? err : count; 1367 } 1368 1369 /* bond for multi-function device */ 1370 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1371 static int mlx4_mf_bond(struct mlx4_dev *dev) 1372 { 1373 int err = 0; 1374 int nvfs; 1375 struct mlx4_slaves_pport slaves_port1; 1376 struct mlx4_slaves_pport slaves_port2; 1377 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1378 1379 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1380 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1381 bitmap_and(slaves_port_1_2, 1382 slaves_port1.slaves, slaves_port2.slaves, 1383 dev->persist->num_vfs + 1); 1384 1385 /* only single port vfs are allowed */ 1386 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1387 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1388 return -EINVAL; 1389 } 1390 1391 /* number of virtual functions is number of total functions minus one 1392 * physical function for each port. 1393 */ 1394 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1395 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1396 1397 /* limit on maximum allowed VFs */ 1398 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1399 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1400 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1401 return -EINVAL; 1402 } 1403 1404 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1405 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1406 return -EINVAL; 1407 } 1408 1409 err = mlx4_bond_mac_table(dev); 1410 if (err) 1411 return err; 1412 err = mlx4_bond_vlan_table(dev); 1413 if (err) 1414 goto err1; 1415 err = mlx4_bond_fs_rules(dev); 1416 if (err) 1417 goto err2; 1418 1419 return 0; 1420 err2: 1421 (void)mlx4_unbond_vlan_table(dev); 1422 err1: 1423 (void)mlx4_unbond_mac_table(dev); 1424 return err; 1425 } 1426 1427 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1428 { 1429 int ret, ret1; 1430 1431 ret = mlx4_unbond_fs_rules(dev); 1432 if (ret) 1433 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1434 ret1 = mlx4_unbond_mac_table(dev); 1435 if (ret1) { 1436 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1437 ret = ret1; 1438 } 1439 ret1 = mlx4_unbond_vlan_table(dev); 1440 if (ret1) { 1441 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1442 ret = ret1; 1443 } 1444 return ret; 1445 } 1446 1447 int mlx4_bond(struct mlx4_dev *dev) 1448 { 1449 int ret = 0; 1450 struct mlx4_priv *priv = mlx4_priv(dev); 1451 1452 mutex_lock(&priv->bond_mutex); 1453 1454 if (!mlx4_is_bonded(dev)) { 1455 ret = mlx4_do_bond(dev, true); 1456 if (ret) 1457 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1458 if (!ret && mlx4_is_master(dev)) { 1459 ret = mlx4_mf_bond(dev); 1460 if (ret) { 1461 mlx4_err(dev, "bond for multifunction failed\n"); 1462 mlx4_do_bond(dev, false); 1463 } 1464 } 1465 } 1466 1467 mutex_unlock(&priv->bond_mutex); 1468 if (!ret) 1469 mlx4_dbg(dev, "Device is bonded\n"); 1470 1471 return ret; 1472 } 1473 EXPORT_SYMBOL_GPL(mlx4_bond); 1474 1475 int mlx4_unbond(struct mlx4_dev *dev) 1476 { 1477 int ret = 0; 1478 struct mlx4_priv *priv = mlx4_priv(dev); 1479 1480 mutex_lock(&priv->bond_mutex); 1481 1482 if (mlx4_is_bonded(dev)) { 1483 int ret2 = 0; 1484 1485 ret = mlx4_do_bond(dev, false); 1486 if (ret) 1487 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1488 if (mlx4_is_master(dev)) 1489 ret2 = mlx4_mf_unbond(dev); 1490 if (ret2) { 1491 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1492 ret = ret2; 1493 } 1494 } 1495 1496 mutex_unlock(&priv->bond_mutex); 1497 if (!ret) 1498 mlx4_dbg(dev, "Device is unbonded\n"); 1499 1500 return ret; 1501 } 1502 EXPORT_SYMBOL_GPL(mlx4_unbond); 1503 1504 1505 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1506 { 1507 u8 port1 = v2p->port1; 1508 u8 port2 = v2p->port2; 1509 struct mlx4_priv *priv = mlx4_priv(dev); 1510 int err; 1511 1512 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1513 return -EOPNOTSUPP; 1514 1515 mutex_lock(&priv->bond_mutex); 1516 1517 /* zero means keep current mapping for this port */ 1518 if (port1 == 0) 1519 port1 = priv->v2p.port1; 1520 if (port2 == 0) 1521 port2 = priv->v2p.port2; 1522 1523 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1524 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1525 (port1 == 2 && port2 == 1)) { 1526 /* besides boundary checks cross mapping makes 1527 * no sense and therefore not allowed */ 1528 err = -EINVAL; 1529 } else if ((port1 == priv->v2p.port1) && 1530 (port2 == priv->v2p.port2)) { 1531 err = 0; 1532 } else { 1533 err = mlx4_virt2phy_port_map(dev, port1, port2); 1534 if (!err) { 1535 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1536 port1, port2); 1537 priv->v2p.port1 = port1; 1538 priv->v2p.port2 = port2; 1539 } else { 1540 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1541 } 1542 } 1543 1544 mutex_unlock(&priv->bond_mutex); 1545 return err; 1546 } 1547 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1548 1549 static int mlx4_load_fw(struct mlx4_dev *dev) 1550 { 1551 struct mlx4_priv *priv = mlx4_priv(dev); 1552 int err; 1553 1554 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1555 GFP_HIGHUSER | __GFP_NOWARN, 0); 1556 if (!priv->fw.fw_icm) { 1557 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1558 return -ENOMEM; 1559 } 1560 1561 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1562 if (err) { 1563 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1564 goto err_free; 1565 } 1566 1567 err = mlx4_RUN_FW(dev); 1568 if (err) { 1569 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1570 goto err_unmap_fa; 1571 } 1572 1573 return 0; 1574 1575 err_unmap_fa: 1576 mlx4_UNMAP_FA(dev); 1577 1578 err_free: 1579 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1580 return err; 1581 } 1582 1583 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1584 int cmpt_entry_sz) 1585 { 1586 struct mlx4_priv *priv = mlx4_priv(dev); 1587 int err; 1588 int num_eqs; 1589 1590 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1591 cmpt_base + 1592 ((u64) (MLX4_CMPT_TYPE_QP * 1593 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1594 cmpt_entry_sz, dev->caps.num_qps, 1595 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1596 0, 0); 1597 if (err) 1598 goto err; 1599 1600 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1601 cmpt_base + 1602 ((u64) (MLX4_CMPT_TYPE_SRQ * 1603 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1604 cmpt_entry_sz, dev->caps.num_srqs, 1605 dev->caps.reserved_srqs, 0, 0); 1606 if (err) 1607 goto err_qp; 1608 1609 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1610 cmpt_base + 1611 ((u64) (MLX4_CMPT_TYPE_CQ * 1612 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1613 cmpt_entry_sz, dev->caps.num_cqs, 1614 dev->caps.reserved_cqs, 0, 0); 1615 if (err) 1616 goto err_srq; 1617 1618 num_eqs = dev->phys_caps.num_phys_eqs; 1619 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1620 cmpt_base + 1621 ((u64) (MLX4_CMPT_TYPE_EQ * 1622 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1623 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1624 if (err) 1625 goto err_cq; 1626 1627 return 0; 1628 1629 err_cq: 1630 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1631 1632 err_srq: 1633 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1634 1635 err_qp: 1636 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1637 1638 err: 1639 return err; 1640 } 1641 1642 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1643 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1644 { 1645 struct mlx4_priv *priv = mlx4_priv(dev); 1646 u64 aux_pages; 1647 int num_eqs; 1648 int err; 1649 1650 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1651 if (err) { 1652 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1653 return err; 1654 } 1655 1656 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1657 (unsigned long long) icm_size >> 10, 1658 (unsigned long long) aux_pages << 2); 1659 1660 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1661 GFP_HIGHUSER | __GFP_NOWARN, 0); 1662 if (!priv->fw.aux_icm) { 1663 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1664 return -ENOMEM; 1665 } 1666 1667 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1668 if (err) { 1669 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1670 goto err_free_aux; 1671 } 1672 1673 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1674 if (err) { 1675 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1676 goto err_unmap_aux; 1677 } 1678 1679 1680 num_eqs = dev->phys_caps.num_phys_eqs; 1681 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1682 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1683 num_eqs, num_eqs, 0, 0); 1684 if (err) { 1685 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1686 goto err_unmap_cmpt; 1687 } 1688 1689 /* 1690 * Reserved MTT entries must be aligned up to a cacheline 1691 * boundary, since the FW will write to them, while the driver 1692 * writes to all other MTT entries. (The variable 1693 * dev->caps.mtt_entry_sz below is really the MTT segment 1694 * size, not the raw entry size) 1695 */ 1696 dev->caps.reserved_mtts = 1697 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1698 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1699 1700 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1701 init_hca->mtt_base, 1702 dev->caps.mtt_entry_sz, 1703 dev->caps.num_mtts, 1704 dev->caps.reserved_mtts, 1, 0); 1705 if (err) { 1706 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1707 goto err_unmap_eq; 1708 } 1709 1710 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1711 init_hca->dmpt_base, 1712 dev_cap->dmpt_entry_sz, 1713 dev->caps.num_mpts, 1714 dev->caps.reserved_mrws, 1, 1); 1715 if (err) { 1716 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1717 goto err_unmap_mtt; 1718 } 1719 1720 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1721 init_hca->qpc_base, 1722 dev_cap->qpc_entry_sz, 1723 dev->caps.num_qps, 1724 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1725 0, 0); 1726 if (err) { 1727 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1728 goto err_unmap_dmpt; 1729 } 1730 1731 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1732 init_hca->auxc_base, 1733 dev_cap->aux_entry_sz, 1734 dev->caps.num_qps, 1735 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1736 0, 0); 1737 if (err) { 1738 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1739 goto err_unmap_qp; 1740 } 1741 1742 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1743 init_hca->altc_base, 1744 dev_cap->altc_entry_sz, 1745 dev->caps.num_qps, 1746 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1747 0, 0); 1748 if (err) { 1749 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1750 goto err_unmap_auxc; 1751 } 1752 1753 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1754 init_hca->rdmarc_base, 1755 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1756 dev->caps.num_qps, 1757 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1758 0, 0); 1759 if (err) { 1760 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1761 goto err_unmap_altc; 1762 } 1763 1764 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1765 init_hca->cqc_base, 1766 dev_cap->cqc_entry_sz, 1767 dev->caps.num_cqs, 1768 dev->caps.reserved_cqs, 0, 0); 1769 if (err) { 1770 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1771 goto err_unmap_rdmarc; 1772 } 1773 1774 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1775 init_hca->srqc_base, 1776 dev_cap->srq_entry_sz, 1777 dev->caps.num_srqs, 1778 dev->caps.reserved_srqs, 0, 0); 1779 if (err) { 1780 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1781 goto err_unmap_cq; 1782 } 1783 1784 /* 1785 * For flow steering device managed mode it is required to use 1786 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1787 * required, but for simplicity just map the whole multicast 1788 * group table now. The table isn't very big and it's a lot 1789 * easier than trying to track ref counts. 1790 */ 1791 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1792 init_hca->mc_base, 1793 mlx4_get_mgm_entry_size(dev), 1794 dev->caps.num_mgms + dev->caps.num_amgms, 1795 dev->caps.num_mgms + dev->caps.num_amgms, 1796 0, 0); 1797 if (err) { 1798 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1799 goto err_unmap_srq; 1800 } 1801 1802 return 0; 1803 1804 err_unmap_srq: 1805 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1806 1807 err_unmap_cq: 1808 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1809 1810 err_unmap_rdmarc: 1811 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1812 1813 err_unmap_altc: 1814 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1815 1816 err_unmap_auxc: 1817 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1818 1819 err_unmap_qp: 1820 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1821 1822 err_unmap_dmpt: 1823 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1824 1825 err_unmap_mtt: 1826 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1827 1828 err_unmap_eq: 1829 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1830 1831 err_unmap_cmpt: 1832 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1833 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1834 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1836 1837 err_unmap_aux: 1838 mlx4_UNMAP_ICM_AUX(dev); 1839 1840 err_free_aux: 1841 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1842 1843 return err; 1844 } 1845 1846 static void mlx4_free_icms(struct mlx4_dev *dev) 1847 { 1848 struct mlx4_priv *priv = mlx4_priv(dev); 1849 1850 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1851 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1852 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1853 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1854 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1855 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1856 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1857 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1858 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1859 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1860 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1861 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1862 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1863 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1864 1865 mlx4_UNMAP_ICM_AUX(dev); 1866 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1867 } 1868 1869 static void mlx4_slave_exit(struct mlx4_dev *dev) 1870 { 1871 struct mlx4_priv *priv = mlx4_priv(dev); 1872 1873 mutex_lock(&priv->cmd.slave_cmd_mutex); 1874 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1875 MLX4_COMM_TIME)) 1876 mlx4_warn(dev, "Failed to close slave function\n"); 1877 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1878 } 1879 1880 static int map_bf_area(struct mlx4_dev *dev) 1881 { 1882 struct mlx4_priv *priv = mlx4_priv(dev); 1883 resource_size_t bf_start; 1884 resource_size_t bf_len; 1885 int err = 0; 1886 1887 if (!dev->caps.bf_reg_size) 1888 return -ENXIO; 1889 1890 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1891 (dev->caps.num_uars << PAGE_SHIFT); 1892 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1893 (dev->caps.num_uars << PAGE_SHIFT); 1894 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1895 if (!priv->bf_mapping) 1896 err = -ENOMEM; 1897 1898 return err; 1899 } 1900 1901 static void unmap_bf_area(struct mlx4_dev *dev) 1902 { 1903 if (mlx4_priv(dev)->bf_mapping) 1904 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1905 } 1906 1907 u64 mlx4_read_clock(struct mlx4_dev *dev) 1908 { 1909 u32 clockhi, clocklo, clockhi1; 1910 u64 cycles; 1911 int i; 1912 struct mlx4_priv *priv = mlx4_priv(dev); 1913 1914 for (i = 0; i < 10; i++) { 1915 clockhi = swab32(readl(priv->clock_mapping)); 1916 clocklo = swab32(readl(priv->clock_mapping + 4)); 1917 clockhi1 = swab32(readl(priv->clock_mapping)); 1918 if (clockhi == clockhi1) 1919 break; 1920 } 1921 1922 cycles = (u64) clockhi << 32 | (u64) clocklo; 1923 1924 return cycles; 1925 } 1926 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1927 1928 1929 static int map_internal_clock(struct mlx4_dev *dev) 1930 { 1931 struct mlx4_priv *priv = mlx4_priv(dev); 1932 1933 priv->clock_mapping = 1934 ioremap(pci_resource_start(dev->persist->pdev, 1935 priv->fw.clock_bar) + 1936 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1937 1938 if (!priv->clock_mapping) 1939 return -ENOMEM; 1940 1941 return 0; 1942 } 1943 1944 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1945 struct mlx4_clock_params *params) 1946 { 1947 struct mlx4_priv *priv = mlx4_priv(dev); 1948 1949 if (mlx4_is_slave(dev)) 1950 return -EOPNOTSUPP; 1951 1952 if (!params) 1953 return -EINVAL; 1954 1955 params->bar = priv->fw.clock_bar; 1956 params->offset = priv->fw.clock_offset; 1957 params->size = MLX4_CLOCK_SIZE; 1958 1959 return 0; 1960 } 1961 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1962 1963 static void unmap_internal_clock(struct mlx4_dev *dev) 1964 { 1965 struct mlx4_priv *priv = mlx4_priv(dev); 1966 1967 if (priv->clock_mapping) 1968 iounmap(priv->clock_mapping); 1969 } 1970 1971 static void mlx4_close_hca(struct mlx4_dev *dev) 1972 { 1973 unmap_internal_clock(dev); 1974 unmap_bf_area(dev); 1975 if (mlx4_is_slave(dev)) 1976 mlx4_slave_exit(dev); 1977 else { 1978 mlx4_CLOSE_HCA(dev, 0); 1979 mlx4_free_icms(dev); 1980 } 1981 } 1982 1983 static void mlx4_close_fw(struct mlx4_dev *dev) 1984 { 1985 if (!mlx4_is_slave(dev)) { 1986 mlx4_UNMAP_FA(dev); 1987 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1988 } 1989 } 1990 1991 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1992 { 1993 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1994 1995 u32 comm_flags; 1996 u32 offline_bit; 1997 unsigned long end; 1998 struct mlx4_priv *priv = mlx4_priv(dev); 1999 2000 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2001 while (time_before(jiffies, end)) { 2002 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2003 MLX4_COMM_CHAN_FLAGS)); 2004 offline_bit = (comm_flags & 2005 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2006 if (!offline_bit) 2007 return 0; 2008 2009 /* If device removal has been requested, 2010 * do not continue retrying. 2011 */ 2012 if (dev->persist->interface_state & 2013 MLX4_INTERFACE_STATE_NOWAIT) 2014 break; 2015 2016 /* There are cases as part of AER/Reset flow that PF needs 2017 * around 100 msec to load. We therefore sleep for 100 msec 2018 * to allow other tasks to make use of that CPU during this 2019 * time interval. 2020 */ 2021 msleep(100); 2022 } 2023 mlx4_err(dev, "Communication channel is offline.\n"); 2024 return -EIO; 2025 } 2026 2027 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2028 { 2029 #define COMM_CHAN_RST_OFFSET 0x1e 2030 2031 struct mlx4_priv *priv = mlx4_priv(dev); 2032 u32 comm_rst; 2033 u32 comm_caps; 2034 2035 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2036 MLX4_COMM_CHAN_CAPS)); 2037 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2038 2039 if (comm_rst) 2040 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2041 } 2042 2043 static int mlx4_init_slave(struct mlx4_dev *dev) 2044 { 2045 struct mlx4_priv *priv = mlx4_priv(dev); 2046 u64 dma = (u64) priv->mfunc.vhcr_dma; 2047 int ret_from_reset = 0; 2048 u32 slave_read; 2049 u32 cmd_channel_ver; 2050 2051 if (atomic_read(&pf_loading)) { 2052 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2053 return -EPROBE_DEFER; 2054 } 2055 2056 mutex_lock(&priv->cmd.slave_cmd_mutex); 2057 priv->cmd.max_cmds = 1; 2058 if (mlx4_comm_check_offline(dev)) { 2059 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2060 goto err_offline; 2061 } 2062 2063 mlx4_reset_vf_support(dev); 2064 mlx4_warn(dev, "Sending reset\n"); 2065 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2066 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2067 /* if we are in the middle of flr the slave will try 2068 * NUM_OF_RESET_RETRIES times before leaving.*/ 2069 if (ret_from_reset) { 2070 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2071 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2072 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2073 return -EPROBE_DEFER; 2074 } else 2075 goto err; 2076 } 2077 2078 /* check the driver version - the slave I/F revision 2079 * must match the master's */ 2080 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2081 cmd_channel_ver = mlx4_comm_get_version(); 2082 2083 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2084 MLX4_COMM_GET_IF_REV(slave_read)) { 2085 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2086 goto err; 2087 } 2088 2089 mlx4_warn(dev, "Sending vhcr0\n"); 2090 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2091 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2092 goto err; 2093 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2094 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2095 goto err; 2096 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2097 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2098 goto err; 2099 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2100 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2101 goto err; 2102 2103 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2104 return 0; 2105 2106 err: 2107 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2108 err_offline: 2109 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2110 return -EIO; 2111 } 2112 2113 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2114 { 2115 int i; 2116 2117 for (i = 1; i <= dev->caps.num_ports; i++) { 2118 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2119 dev->caps.gid_table_len[i] = 2120 mlx4_get_slave_num_gids(dev, 0, i); 2121 else 2122 dev->caps.gid_table_len[i] = 1; 2123 dev->caps.pkey_table_len[i] = 2124 dev->phys_caps.pkey_phys_table_len[i] - 1; 2125 } 2126 } 2127 2128 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2129 { 2130 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2131 2132 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2133 i++) { 2134 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2135 break; 2136 } 2137 2138 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2139 } 2140 2141 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2142 { 2143 switch (dmfs_high_steer_mode) { 2144 case MLX4_STEERING_DMFS_A0_DEFAULT: 2145 return "default performance"; 2146 2147 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2148 return "dynamic hybrid mode"; 2149 2150 case MLX4_STEERING_DMFS_A0_STATIC: 2151 return "performance optimized for limited rule configuration (static)"; 2152 2153 case MLX4_STEERING_DMFS_A0_DISABLE: 2154 return "disabled performance optimized steering"; 2155 2156 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2157 return "performance optimized steering not supported"; 2158 2159 default: 2160 return "Unrecognized mode"; 2161 } 2162 } 2163 2164 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2165 2166 static void choose_steering_mode(struct mlx4_dev *dev, 2167 struct mlx4_dev_cap *dev_cap) 2168 { 2169 if (mlx4_log_num_mgm_entry_size <= 0) { 2170 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2171 if (dev->caps.dmfs_high_steer_mode == 2172 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2173 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2174 else 2175 dev->caps.dmfs_high_steer_mode = 2176 MLX4_STEERING_DMFS_A0_STATIC; 2177 } 2178 } 2179 2180 if (mlx4_log_num_mgm_entry_size <= 0 && 2181 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2182 (!mlx4_is_mfunc(dev) || 2183 (dev_cap->fs_max_num_qp_per_entry >= 2184 (dev->persist->num_vfs + 1))) && 2185 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2186 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2187 dev->oper_log_mgm_entry_size = 2188 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2189 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2190 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2191 dev->caps.fs_log_max_ucast_qp_range_size = 2192 dev_cap->fs_log_max_ucast_qp_range_size; 2193 } else { 2194 if (dev->caps.dmfs_high_steer_mode != 2195 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2196 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2197 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2198 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2199 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2200 else { 2201 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2202 2203 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2204 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2205 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2206 } 2207 dev->oper_log_mgm_entry_size = 2208 mlx4_log_num_mgm_entry_size > 0 ? 2209 mlx4_log_num_mgm_entry_size : 2210 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2211 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2212 } 2213 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2214 mlx4_steering_mode_str(dev->caps.steering_mode), 2215 dev->oper_log_mgm_entry_size, 2216 mlx4_log_num_mgm_entry_size); 2217 } 2218 2219 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2220 struct mlx4_dev_cap *dev_cap) 2221 { 2222 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2223 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2224 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2225 else 2226 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2227 2228 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2229 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2230 } 2231 2232 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2233 { 2234 int i; 2235 struct mlx4_port_cap port_cap; 2236 2237 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2238 return -EINVAL; 2239 2240 for (i = 1; i <= dev->caps.num_ports; i++) { 2241 if (mlx4_dev_port(dev, i, &port_cap)) { 2242 mlx4_err(dev, 2243 "QUERY_DEV_CAP command failed, can't verify DMFS high rate steering.\n"); 2244 } else if ((dev->caps.dmfs_high_steer_mode != 2245 MLX4_STEERING_DMFS_A0_DEFAULT) && 2246 (port_cap.dmfs_optimized_state == 2247 !!(dev->caps.dmfs_high_steer_mode == 2248 MLX4_STEERING_DMFS_A0_DISABLE))) { 2249 mlx4_err(dev, 2250 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2251 dmfs_high_rate_steering_mode_str( 2252 dev->caps.dmfs_high_steer_mode), 2253 (port_cap.dmfs_optimized_state ? 2254 "enabled" : "disabled")); 2255 } 2256 } 2257 2258 return 0; 2259 } 2260 2261 static int mlx4_init_fw(struct mlx4_dev *dev) 2262 { 2263 struct mlx4_mod_stat_cfg mlx4_cfg; 2264 int err = 0; 2265 2266 if (!mlx4_is_slave(dev)) { 2267 err = mlx4_QUERY_FW(dev); 2268 if (err) { 2269 if (err == -EACCES) 2270 mlx4_info(dev, "non-primary physical function, skipping\n"); 2271 else 2272 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2273 return err; 2274 } 2275 2276 err = mlx4_load_fw(dev); 2277 if (err) { 2278 mlx4_err(dev, "Failed to start FW, aborting\n"); 2279 return err; 2280 } 2281 2282 mlx4_cfg.log_pg_sz_m = 1; 2283 mlx4_cfg.log_pg_sz = 0; 2284 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2285 if (err) 2286 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2287 } 2288 2289 return err; 2290 } 2291 2292 static int mlx4_init_hca(struct mlx4_dev *dev) 2293 { 2294 struct mlx4_priv *priv = mlx4_priv(dev); 2295 struct mlx4_init_hca_param *init_hca = NULL; 2296 struct mlx4_dev_cap *dev_cap = NULL; 2297 struct mlx4_adapter adapter; 2298 struct mlx4_profile profile; 2299 u64 icm_size; 2300 struct mlx4_config_dev_params params; 2301 int err; 2302 2303 if (!mlx4_is_slave(dev)) { 2304 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2305 init_hca = kzalloc(sizeof(*init_hca), GFP_KERNEL); 2306 2307 if (!dev_cap || !init_hca) { 2308 err = -ENOMEM; 2309 goto out_free; 2310 } 2311 2312 err = mlx4_dev_cap(dev, dev_cap); 2313 if (err) { 2314 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2315 goto out_free; 2316 } 2317 2318 choose_steering_mode(dev, dev_cap); 2319 choose_tunnel_offload_mode(dev, dev_cap); 2320 2321 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2322 mlx4_is_master(dev)) 2323 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2324 2325 err = mlx4_get_phys_port_id(dev); 2326 if (err) 2327 mlx4_err(dev, "Fail to get physical port id\n"); 2328 2329 if (mlx4_is_master(dev)) 2330 mlx4_parav_master_pf_caps(dev); 2331 2332 if (mlx4_low_memory_profile()) { 2333 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2334 profile = low_mem_profile; 2335 } else { 2336 profile = default_profile; 2337 } 2338 if (dev->caps.steering_mode == 2339 MLX4_STEERING_MODE_DEVICE_MANAGED) 2340 profile.num_mcg = MLX4_FS_NUM_MCG; 2341 2342 icm_size = mlx4_make_profile(dev, &profile, dev_cap, 2343 init_hca); 2344 if ((long long) icm_size < 0) { 2345 err = icm_size; 2346 goto out_free; 2347 } 2348 2349 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2350 2351 if (enable_4k_uar || !dev->persist->num_vfs) { 2352 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) + 2353 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2354 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2355 } else { 2356 init_hca->log_uar_sz = ilog2(dev->caps.num_uars); 2357 init_hca->uar_page_sz = PAGE_SHIFT - 12; 2358 } 2359 2360 init_hca->mw_enabled = 0; 2361 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2362 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2363 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2364 2365 err = mlx4_init_icm(dev, dev_cap, init_hca, icm_size); 2366 if (err) 2367 goto out_free; 2368 2369 err = mlx4_INIT_HCA(dev, init_hca); 2370 if (err) { 2371 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2372 goto err_free_icm; 2373 } 2374 2375 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2376 err = mlx4_query_func(dev, dev_cap); 2377 if (err < 0) { 2378 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2379 goto err_close; 2380 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2381 dev->caps.num_eqs = dev_cap->max_eqs; 2382 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 2383 dev->caps.reserved_uars = dev_cap->reserved_uars; 2384 } 2385 } 2386 2387 /* 2388 * If TS is supported by FW 2389 * read HCA frequency by QUERY_HCA command 2390 */ 2391 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2392 err = mlx4_QUERY_HCA(dev, init_hca); 2393 if (err) { 2394 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2395 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2396 } else { 2397 dev->caps.hca_core_clock = 2398 init_hca->hca_core_clock; 2399 } 2400 2401 /* In case we got HCA frequency 0 - disable timestamping 2402 * to avoid dividing by zero 2403 */ 2404 if (!dev->caps.hca_core_clock) { 2405 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2406 mlx4_err(dev, 2407 "HCA frequency is 0 - timestamping is not supported\n"); 2408 } else if (map_internal_clock(dev)) { 2409 /* 2410 * Map internal clock, 2411 * in case of failure disable timestamping 2412 */ 2413 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2414 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2415 } 2416 } 2417 2418 if (dev->caps.dmfs_high_steer_mode != 2419 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2420 if (mlx4_validate_optimized_steering(dev)) 2421 mlx4_warn(dev, "Optimized steering validation failed\n"); 2422 2423 if (dev->caps.dmfs_high_steer_mode == 2424 MLX4_STEERING_DMFS_A0_DISABLE) { 2425 dev->caps.dmfs_high_rate_qpn_base = 2426 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2427 dev->caps.dmfs_high_rate_qpn_range = 2428 MLX4_A0_STEERING_TABLE_SIZE; 2429 } 2430 2431 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2432 dmfs_high_rate_steering_mode_str( 2433 dev->caps.dmfs_high_steer_mode)); 2434 } 2435 } else { 2436 err = mlx4_init_slave(dev); 2437 if (err) { 2438 if (err != -EPROBE_DEFER) 2439 mlx4_err(dev, "Failed to initialize slave\n"); 2440 return err; 2441 } 2442 2443 err = mlx4_slave_cap(dev); 2444 if (err) { 2445 mlx4_err(dev, "Failed to obtain slave caps\n"); 2446 goto err_close; 2447 } 2448 } 2449 2450 if (map_bf_area(dev)) 2451 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2452 2453 /*Only the master set the ports, all the rest got it from it.*/ 2454 if (!mlx4_is_slave(dev)) 2455 mlx4_set_port_mask(dev); 2456 2457 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2458 if (err) { 2459 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2460 goto unmap_bf; 2461 } 2462 2463 /* Query CONFIG_DEV parameters */ 2464 err = mlx4_config_dev_retrieval(dev, ¶ms); 2465 if (err && err != -EOPNOTSUPP) { 2466 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2467 } else if (!err) { 2468 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2469 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2470 } 2471 priv->eq_table.inta_pin = adapter.inta_pin; 2472 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2473 2474 err = 0; 2475 goto out_free; 2476 2477 unmap_bf: 2478 unmap_internal_clock(dev); 2479 unmap_bf_area(dev); 2480 2481 if (mlx4_is_slave(dev)) 2482 mlx4_slave_destroy_special_qp_cap(dev); 2483 2484 err_close: 2485 if (mlx4_is_slave(dev)) 2486 mlx4_slave_exit(dev); 2487 else 2488 mlx4_CLOSE_HCA(dev, 0); 2489 2490 err_free_icm: 2491 if (!mlx4_is_slave(dev)) 2492 mlx4_free_icms(dev); 2493 2494 out_free: 2495 kfree(dev_cap); 2496 kfree(init_hca); 2497 2498 return err; 2499 } 2500 2501 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2502 { 2503 struct mlx4_priv *priv = mlx4_priv(dev); 2504 int nent_pow2; 2505 2506 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2507 return -ENOENT; 2508 2509 if (!dev->caps.max_counters) 2510 return -ENOSPC; 2511 2512 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2513 /* reserve last counter index for sink counter */ 2514 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2515 nent_pow2 - 1, 0, 2516 nent_pow2 - dev->caps.max_counters + 1); 2517 } 2518 2519 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2520 { 2521 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2522 return; 2523 2524 if (!dev->caps.max_counters) 2525 return; 2526 2527 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2528 } 2529 2530 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2531 { 2532 struct mlx4_priv *priv = mlx4_priv(dev); 2533 int port; 2534 2535 for (port = 0; port < dev->caps.num_ports; port++) 2536 if (priv->def_counter[port] != -1) 2537 mlx4_counter_free(dev, priv->def_counter[port]); 2538 } 2539 2540 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2541 { 2542 struct mlx4_priv *priv = mlx4_priv(dev); 2543 int port, err = 0; 2544 u32 idx; 2545 2546 for (port = 0; port < dev->caps.num_ports; port++) 2547 priv->def_counter[port] = -1; 2548 2549 for (port = 0; port < dev->caps.num_ports; port++) { 2550 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2551 2552 if (!err || err == -ENOSPC) { 2553 priv->def_counter[port] = idx; 2554 } else if (err == -ENOENT) { 2555 err = 0; 2556 continue; 2557 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2558 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2559 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2560 MLX4_SINK_COUNTER_INDEX(dev)); 2561 err = 0; 2562 } else { 2563 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2564 __func__, port + 1, err); 2565 mlx4_cleanup_default_counters(dev); 2566 return err; 2567 } 2568 2569 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2570 __func__, priv->def_counter[port], port + 1); 2571 } 2572 2573 return err; 2574 } 2575 2576 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2577 { 2578 struct mlx4_priv *priv = mlx4_priv(dev); 2579 2580 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2581 return -ENOENT; 2582 2583 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2584 if (*idx == -1) { 2585 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2586 return -ENOSPC; 2587 } 2588 2589 return 0; 2590 } 2591 2592 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2593 { 2594 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2595 u64 out_param; 2596 int err; 2597 2598 if (mlx4_is_mfunc(dev)) { 2599 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2600 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2601 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2602 if (!err) 2603 *idx = get_param_l(&out_param); 2604 2605 return err; 2606 } 2607 return __mlx4_counter_alloc(dev, idx); 2608 } 2609 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2610 2611 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2612 u8 counter_index) 2613 { 2614 struct mlx4_cmd_mailbox *if_stat_mailbox; 2615 int err; 2616 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2617 2618 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2619 if (IS_ERR(if_stat_mailbox)) 2620 return PTR_ERR(if_stat_mailbox); 2621 2622 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2623 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2624 MLX4_CMD_NATIVE); 2625 2626 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2627 return err; 2628 } 2629 2630 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2631 { 2632 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2633 return; 2634 2635 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2636 return; 2637 2638 __mlx4_clear_if_stat(dev, idx); 2639 2640 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2641 return; 2642 } 2643 2644 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2645 { 2646 u64 in_param = 0; 2647 2648 if (mlx4_is_mfunc(dev)) { 2649 set_param_l(&in_param, idx); 2650 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2651 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2652 MLX4_CMD_WRAPPED); 2653 return; 2654 } 2655 __mlx4_counter_free(dev, idx); 2656 } 2657 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2658 2659 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2660 { 2661 struct mlx4_priv *priv = mlx4_priv(dev); 2662 2663 return priv->def_counter[port - 1]; 2664 } 2665 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2666 2667 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2668 { 2669 struct mlx4_priv *priv = mlx4_priv(dev); 2670 2671 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2672 } 2673 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2674 2675 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2676 { 2677 struct mlx4_priv *priv = mlx4_priv(dev); 2678 2679 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2680 } 2681 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2682 2683 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2684 { 2685 struct mlx4_priv *priv = mlx4_priv(dev); 2686 __be64 guid; 2687 2688 /* hw GUID */ 2689 if (entry == 0) 2690 return; 2691 2692 get_random_bytes((char *)&guid, sizeof(guid)); 2693 guid &= ~(cpu_to_be64(1ULL << 56)); 2694 guid |= cpu_to_be64(1ULL << 57); 2695 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2696 } 2697 2698 static int mlx4_setup_hca(struct mlx4_dev *dev) 2699 { 2700 struct mlx4_priv *priv = mlx4_priv(dev); 2701 int err; 2702 int port; 2703 __be32 ib_port_default_caps; 2704 2705 err = mlx4_init_uar_table(dev); 2706 if (err) { 2707 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2708 return err; 2709 } 2710 2711 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2712 if (err) { 2713 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2714 goto err_uar_table_free; 2715 } 2716 2717 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2718 if (!priv->kar) { 2719 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2720 err = -ENOMEM; 2721 goto err_uar_free; 2722 } 2723 2724 err = mlx4_init_pd_table(dev); 2725 if (err) { 2726 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2727 goto err_kar_unmap; 2728 } 2729 2730 err = mlx4_init_xrcd_table(dev); 2731 if (err) { 2732 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2733 goto err_pd_table_free; 2734 } 2735 2736 err = mlx4_init_mr_table(dev); 2737 if (err) { 2738 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2739 goto err_xrcd_table_free; 2740 } 2741 2742 if (!mlx4_is_slave(dev)) { 2743 err = mlx4_init_mcg_table(dev); 2744 if (err) { 2745 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2746 goto err_mr_table_free; 2747 } 2748 err = mlx4_config_mad_demux(dev); 2749 if (err) { 2750 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2751 goto err_mcg_table_free; 2752 } 2753 } 2754 2755 err = mlx4_init_eq_table(dev); 2756 if (err) { 2757 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2758 goto err_mcg_table_free; 2759 } 2760 2761 err = mlx4_cmd_use_events(dev); 2762 if (err) { 2763 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2764 goto err_eq_table_free; 2765 } 2766 2767 err = mlx4_NOP(dev); 2768 if (err) { 2769 if (dev->flags & MLX4_FLAG_MSI_X) { 2770 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2771 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2772 mlx4_warn(dev, "Trying again without MSI-X\n"); 2773 } else { 2774 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2775 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2776 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2777 } 2778 2779 goto err_cmd_poll; 2780 } 2781 2782 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2783 2784 err = mlx4_init_cq_table(dev); 2785 if (err) { 2786 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2787 goto err_cmd_poll; 2788 } 2789 2790 err = mlx4_init_srq_table(dev); 2791 if (err) { 2792 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2793 goto err_cq_table_free; 2794 } 2795 2796 err = mlx4_init_qp_table(dev); 2797 if (err) { 2798 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2799 goto err_srq_table_free; 2800 } 2801 2802 if (!mlx4_is_slave(dev)) { 2803 err = mlx4_init_counters_table(dev); 2804 if (err && err != -ENOENT) { 2805 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2806 goto err_qp_table_free; 2807 } 2808 } 2809 2810 err = mlx4_allocate_default_counters(dev); 2811 if (err) { 2812 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2813 goto err_counters_table_free; 2814 } 2815 2816 if (!mlx4_is_slave(dev)) { 2817 for (port = 1; port <= dev->caps.num_ports; port++) { 2818 ib_port_default_caps = 0; 2819 err = mlx4_get_port_ib_caps(dev, port, 2820 &ib_port_default_caps); 2821 if (err) 2822 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2823 port, err); 2824 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2825 2826 /* initialize per-slave default ib port capabilities */ 2827 if (mlx4_is_master(dev)) { 2828 int i; 2829 for (i = 0; i < dev->num_slaves; i++) { 2830 if (i == mlx4_master_func_num(dev)) 2831 continue; 2832 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2833 ib_port_default_caps; 2834 } 2835 } 2836 2837 if (mlx4_is_mfunc(dev)) 2838 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2839 else 2840 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2841 2842 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2843 dev->caps.pkey_table_len[port] : -1); 2844 if (err) { 2845 mlx4_err(dev, "Failed to set port %d, aborting\n", 2846 port); 2847 goto err_default_countes_free; 2848 } 2849 } 2850 } 2851 2852 return 0; 2853 2854 err_default_countes_free: 2855 mlx4_cleanup_default_counters(dev); 2856 2857 err_counters_table_free: 2858 if (!mlx4_is_slave(dev)) 2859 mlx4_cleanup_counters_table(dev); 2860 2861 err_qp_table_free: 2862 mlx4_cleanup_qp_table(dev); 2863 2864 err_srq_table_free: 2865 mlx4_cleanup_srq_table(dev); 2866 2867 err_cq_table_free: 2868 mlx4_cleanup_cq_table(dev); 2869 2870 err_cmd_poll: 2871 mlx4_cmd_use_polling(dev); 2872 2873 err_eq_table_free: 2874 mlx4_cleanup_eq_table(dev); 2875 2876 err_mcg_table_free: 2877 if (!mlx4_is_slave(dev)) 2878 mlx4_cleanup_mcg_table(dev); 2879 2880 err_mr_table_free: 2881 mlx4_cleanup_mr_table(dev); 2882 2883 err_xrcd_table_free: 2884 mlx4_cleanup_xrcd_table(dev); 2885 2886 err_pd_table_free: 2887 mlx4_cleanup_pd_table(dev); 2888 2889 err_kar_unmap: 2890 iounmap(priv->kar); 2891 2892 err_uar_free: 2893 mlx4_uar_free(dev, &priv->driver_uar); 2894 2895 err_uar_table_free: 2896 mlx4_cleanup_uar_table(dev); 2897 return err; 2898 } 2899 2900 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2901 { 2902 int requested_cpu = 0; 2903 struct mlx4_priv *priv = mlx4_priv(dev); 2904 struct mlx4_eq *eq; 2905 int off = 0; 2906 int i; 2907 2908 if (eqn > dev->caps.num_comp_vectors) 2909 return -EINVAL; 2910 2911 for (i = 1; i < port; i++) 2912 off += mlx4_get_eqs_per_port(dev, i); 2913 2914 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2915 2916 /* Meaning EQs are shared, and this call comes from the second port */ 2917 if (requested_cpu < 0) 2918 return 0; 2919 2920 eq = &priv->eq_table.eq[eqn]; 2921 2922 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2923 return -ENOMEM; 2924 2925 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2926 2927 return 0; 2928 } 2929 2930 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2931 { 2932 struct mlx4_priv *priv = mlx4_priv(dev); 2933 struct msix_entry *entries; 2934 int i; 2935 int port = 0; 2936 2937 if (msi_x) { 2938 int nreq = min3(dev->caps.num_ports * 2939 (int)num_online_cpus() + 1, 2940 dev->caps.num_eqs - dev->caps.reserved_eqs, 2941 MAX_MSIX); 2942 2943 if (msi_x > 1) 2944 nreq = min_t(int, nreq, msi_x); 2945 2946 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2947 if (!entries) 2948 goto no_msi; 2949 2950 for (i = 0; i < nreq; ++i) 2951 entries[i].entry = i; 2952 2953 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2954 nreq); 2955 2956 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2957 kfree(entries); 2958 goto no_msi; 2959 } 2960 /* 1 is reserved for events (asyncrounous EQ) */ 2961 dev->caps.num_comp_vectors = nreq - 1; 2962 2963 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2964 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2965 dev->caps.num_ports); 2966 2967 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2968 if (i == MLX4_EQ_ASYNC) 2969 continue; 2970 2971 priv->eq_table.eq[i].irq = 2972 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2973 2974 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2975 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2976 dev->caps.num_ports); 2977 /* We don't set affinity hint when there 2978 * aren't enough EQs 2979 */ 2980 } else { 2981 set_bit(port, 2982 priv->eq_table.eq[i].actv_ports.ports); 2983 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2984 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2985 i); 2986 } 2987 /* We divide the Eqs evenly between the two ports. 2988 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2989 * refers to the number of Eqs per port 2990 * (i.e eqs_per_port). Theoretically, we would like to 2991 * write something like (i + 1) % eqs_per_port == 0. 2992 * However, since there's an asynchronous Eq, we have 2993 * to skip over it by comparing this condition to 2994 * !!((i + 1) > MLX4_EQ_ASYNC). 2995 */ 2996 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2997 ((i + 1) % 2998 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 2999 !!((i + 1) > MLX4_EQ_ASYNC)) 3000 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 3001 * everything is shared anyway. 3002 */ 3003 port++; 3004 } 3005 3006 dev->flags |= MLX4_FLAG_MSI_X; 3007 3008 kfree(entries); 3009 return; 3010 } 3011 3012 no_msi: 3013 dev->caps.num_comp_vectors = 1; 3014 3015 BUG_ON(MLX4_EQ_ASYNC >= 2); 3016 for (i = 0; i < 2; ++i) { 3017 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3018 if (i != MLX4_EQ_ASYNC) { 3019 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3020 dev->caps.num_ports); 3021 } 3022 } 3023 } 3024 3025 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3026 { 3027 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3028 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3029 int err; 3030 3031 err = devlink_port_register(devlink, &info->devlink_port, port); 3032 if (err) 3033 return err; 3034 3035 info->dev = dev; 3036 info->port = port; 3037 if (!mlx4_is_slave(dev)) { 3038 mlx4_init_mac_table(dev, &info->mac_table); 3039 mlx4_init_vlan_table(dev, &info->vlan_table); 3040 mlx4_init_roce_gid_table(dev, &info->gid_table); 3041 info->base_qpn = mlx4_get_base_qpn(dev, port); 3042 } 3043 3044 sprintf(info->dev_name, "mlx4_port%d", port); 3045 info->port_attr.attr.name = info->dev_name; 3046 if (mlx4_is_mfunc(dev)) { 3047 info->port_attr.attr.mode = 0444; 3048 } else { 3049 info->port_attr.attr.mode = 0644; 3050 info->port_attr.store = set_port_type; 3051 } 3052 info->port_attr.show = show_port_type; 3053 sysfs_attr_init(&info->port_attr.attr); 3054 3055 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3056 if (err) { 3057 mlx4_err(dev, "Failed to create file for port %d\n", port); 3058 devlink_port_unregister(&info->devlink_port); 3059 info->port = -1; 3060 return err; 3061 } 3062 3063 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3064 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3065 if (mlx4_is_mfunc(dev)) { 3066 info->port_mtu_attr.attr.mode = 0444; 3067 } else { 3068 info->port_mtu_attr.attr.mode = 0644; 3069 info->port_mtu_attr.store = set_port_ib_mtu; 3070 } 3071 info->port_mtu_attr.show = show_port_ib_mtu; 3072 sysfs_attr_init(&info->port_mtu_attr.attr); 3073 3074 err = device_create_file(&dev->persist->pdev->dev, 3075 &info->port_mtu_attr); 3076 if (err) { 3077 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3078 device_remove_file(&info->dev->persist->pdev->dev, 3079 &info->port_attr); 3080 devlink_port_unregister(&info->devlink_port); 3081 info->port = -1; 3082 return err; 3083 } 3084 3085 return 0; 3086 } 3087 3088 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3089 { 3090 if (info->port < 0) 3091 return; 3092 3093 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3094 device_remove_file(&info->dev->persist->pdev->dev, 3095 &info->port_mtu_attr); 3096 devlink_port_unregister(&info->devlink_port); 3097 3098 #ifdef CONFIG_RFS_ACCEL 3099 free_irq_cpu_rmap(info->rmap); 3100 info->rmap = NULL; 3101 #endif 3102 } 3103 3104 static int mlx4_init_steering(struct mlx4_dev *dev) 3105 { 3106 struct mlx4_priv *priv = mlx4_priv(dev); 3107 int num_entries = dev->caps.num_ports; 3108 int i, j; 3109 3110 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3111 GFP_KERNEL); 3112 if (!priv->steer) 3113 return -ENOMEM; 3114 3115 for (i = 0; i < num_entries; i++) 3116 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3117 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3118 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3119 } 3120 return 0; 3121 } 3122 3123 static void mlx4_clear_steering(struct mlx4_dev *dev) 3124 { 3125 struct mlx4_priv *priv = mlx4_priv(dev); 3126 struct mlx4_steer_index *entry, *tmp_entry; 3127 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3128 int num_entries = dev->caps.num_ports; 3129 int i, j; 3130 3131 for (i = 0; i < num_entries; i++) { 3132 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3133 list_for_each_entry_safe(pqp, tmp_pqp, 3134 &priv->steer[i].promisc_qps[j], 3135 list) { 3136 list_del(&pqp->list); 3137 kfree(pqp); 3138 } 3139 list_for_each_entry_safe(entry, tmp_entry, 3140 &priv->steer[i].steer_entries[j], 3141 list) { 3142 list_del(&entry->list); 3143 list_for_each_entry_safe(pqp, tmp_pqp, 3144 &entry->duplicates, 3145 list) { 3146 list_del(&pqp->list); 3147 kfree(pqp); 3148 } 3149 kfree(entry); 3150 } 3151 } 3152 } 3153 kfree(priv->steer); 3154 } 3155 3156 static int extended_func_num(struct pci_dev *pdev) 3157 { 3158 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3159 } 3160 3161 #define MLX4_OWNER_BASE 0x8069c 3162 #define MLX4_OWNER_SIZE 4 3163 3164 static int mlx4_get_ownership(struct mlx4_dev *dev) 3165 { 3166 void __iomem *owner; 3167 u32 ret; 3168 3169 if (pci_channel_offline(dev->persist->pdev)) 3170 return -EIO; 3171 3172 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3173 MLX4_OWNER_BASE, 3174 MLX4_OWNER_SIZE); 3175 if (!owner) { 3176 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3177 return -ENOMEM; 3178 } 3179 3180 ret = readl(owner); 3181 iounmap(owner); 3182 return (int) !!ret; 3183 } 3184 3185 static void mlx4_free_ownership(struct mlx4_dev *dev) 3186 { 3187 void __iomem *owner; 3188 3189 if (pci_channel_offline(dev->persist->pdev)) 3190 return; 3191 3192 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3193 MLX4_OWNER_BASE, 3194 MLX4_OWNER_SIZE); 3195 if (!owner) { 3196 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3197 return; 3198 } 3199 writel(0, owner); 3200 msleep(1000); 3201 iounmap(owner); 3202 } 3203 3204 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3205 !!((flags) & MLX4_FLAG_MASTER)) 3206 3207 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3208 u8 total_vfs, int existing_vfs, int reset_flow) 3209 { 3210 u64 dev_flags = dev->flags; 3211 int err = 0; 3212 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3213 MLX4_MAX_NUM_VF); 3214 3215 if (reset_flow) { 3216 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3217 GFP_KERNEL); 3218 if (!dev->dev_vfs) 3219 goto free_mem; 3220 return dev_flags; 3221 } 3222 3223 atomic_inc(&pf_loading); 3224 if (dev->flags & MLX4_FLAG_SRIOV) { 3225 if (existing_vfs != total_vfs) { 3226 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3227 existing_vfs, total_vfs); 3228 total_vfs = existing_vfs; 3229 } 3230 } 3231 3232 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3233 if (NULL == dev->dev_vfs) { 3234 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3235 goto disable_sriov; 3236 } 3237 3238 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3239 if (total_vfs > fw_enabled_sriov_vfs) { 3240 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3241 total_vfs, fw_enabled_sriov_vfs); 3242 err = -ENOMEM; 3243 goto disable_sriov; 3244 } 3245 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3246 err = pci_enable_sriov(pdev, total_vfs); 3247 } 3248 if (err) { 3249 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3250 err); 3251 goto disable_sriov; 3252 } else { 3253 mlx4_warn(dev, "Running in master mode\n"); 3254 dev_flags |= MLX4_FLAG_SRIOV | 3255 MLX4_FLAG_MASTER; 3256 dev_flags &= ~MLX4_FLAG_SLAVE; 3257 dev->persist->num_vfs = total_vfs; 3258 } 3259 return dev_flags; 3260 3261 disable_sriov: 3262 atomic_dec(&pf_loading); 3263 free_mem: 3264 dev->persist->num_vfs = 0; 3265 kfree(dev->dev_vfs); 3266 dev->dev_vfs = NULL; 3267 return dev_flags & ~MLX4_FLAG_MASTER; 3268 } 3269 3270 enum { 3271 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3272 }; 3273 3274 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3275 int *nvfs) 3276 { 3277 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3278 /* Checking for 64 VFs as a limitation of CX2 */ 3279 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3280 requested_vfs >= 64) { 3281 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3282 requested_vfs); 3283 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3284 } 3285 return 0; 3286 } 3287 3288 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3289 { 3290 struct pci_dev *pdev = dev->persist->pdev; 3291 int err = 0; 3292 3293 mutex_lock(&dev->persist->pci_status_mutex); 3294 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3295 err = pci_enable_device(pdev); 3296 if (!err) 3297 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3298 } 3299 mutex_unlock(&dev->persist->pci_status_mutex); 3300 3301 return err; 3302 } 3303 3304 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3305 { 3306 struct pci_dev *pdev = dev->persist->pdev; 3307 3308 mutex_lock(&dev->persist->pci_status_mutex); 3309 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3310 pci_disable_device(pdev); 3311 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3312 } 3313 mutex_unlock(&dev->persist->pci_status_mutex); 3314 } 3315 3316 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3317 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3318 int reset_flow) 3319 { 3320 struct mlx4_dev *dev; 3321 unsigned sum = 0; 3322 int err; 3323 int port; 3324 int i; 3325 struct mlx4_dev_cap *dev_cap = NULL; 3326 int existing_vfs = 0; 3327 3328 dev = &priv->dev; 3329 3330 INIT_LIST_HEAD(&priv->ctx_list); 3331 spin_lock_init(&priv->ctx_lock); 3332 3333 mutex_init(&priv->port_mutex); 3334 mutex_init(&priv->bond_mutex); 3335 3336 INIT_LIST_HEAD(&priv->pgdir_list); 3337 mutex_init(&priv->pgdir_mutex); 3338 spin_lock_init(&priv->cmd.context_lock); 3339 3340 INIT_LIST_HEAD(&priv->bf_list); 3341 mutex_init(&priv->bf_mutex); 3342 3343 dev->rev_id = pdev->revision; 3344 dev->numa_node = dev_to_node(&pdev->dev); 3345 3346 /* Detect if this device is a virtual function */ 3347 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3348 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3349 dev->flags |= MLX4_FLAG_SLAVE; 3350 } else { 3351 /* We reset the device and enable SRIOV only for physical 3352 * devices. Try to claim ownership on the device; 3353 * if already taken, skip -- do not allow multiple PFs */ 3354 err = mlx4_get_ownership(dev); 3355 if (err) { 3356 if (err < 0) 3357 return err; 3358 else { 3359 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3360 return -EINVAL; 3361 } 3362 } 3363 3364 atomic_set(&priv->opreq_count, 0); 3365 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3366 3367 /* 3368 * Now reset the HCA before we touch the PCI capabilities or 3369 * attempt a firmware command, since a boot ROM may have left 3370 * the HCA in an undefined state. 3371 */ 3372 err = mlx4_reset(dev); 3373 if (err) { 3374 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3375 goto err_sriov; 3376 } 3377 3378 if (total_vfs) { 3379 dev->flags = MLX4_FLAG_MASTER; 3380 existing_vfs = pci_num_vf(pdev); 3381 if (existing_vfs) 3382 dev->flags |= MLX4_FLAG_SRIOV; 3383 dev->persist->num_vfs = total_vfs; 3384 } 3385 } 3386 3387 /* on load remove any previous indication of internal error, 3388 * device is up. 3389 */ 3390 dev->persist->state = MLX4_DEVICE_STATE_UP; 3391 3392 slave_start: 3393 err = mlx4_cmd_init(dev); 3394 if (err) { 3395 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3396 goto err_sriov; 3397 } 3398 3399 /* In slave functions, the communication channel must be initialized 3400 * before posting commands. Also, init num_slaves before calling 3401 * mlx4_init_hca */ 3402 if (mlx4_is_mfunc(dev)) { 3403 if (mlx4_is_master(dev)) { 3404 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3405 3406 } else { 3407 dev->num_slaves = 0; 3408 err = mlx4_multi_func_init(dev); 3409 if (err) { 3410 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3411 goto err_cmd; 3412 } 3413 } 3414 } 3415 3416 err = mlx4_init_fw(dev); 3417 if (err) { 3418 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3419 goto err_mfunc; 3420 } 3421 3422 if (mlx4_is_master(dev)) { 3423 /* when we hit the goto slave_start below, dev_cap already initialized */ 3424 if (!dev_cap) { 3425 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3426 3427 if (!dev_cap) { 3428 err = -ENOMEM; 3429 goto err_fw; 3430 } 3431 3432 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3433 if (err) { 3434 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3435 goto err_fw; 3436 } 3437 3438 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3439 goto err_fw; 3440 3441 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3442 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3443 total_vfs, 3444 existing_vfs, 3445 reset_flow); 3446 3447 mlx4_close_fw(dev); 3448 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3449 dev->flags = dev_flags; 3450 if (!SRIOV_VALID_STATE(dev->flags)) { 3451 mlx4_err(dev, "Invalid SRIOV state\n"); 3452 goto err_sriov; 3453 } 3454 err = mlx4_reset(dev); 3455 if (err) { 3456 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3457 goto err_sriov; 3458 } 3459 goto slave_start; 3460 } 3461 } else { 3462 /* Legacy mode FW requires SRIOV to be enabled before 3463 * doing QUERY_DEV_CAP, since max_eq's value is different if 3464 * SRIOV is enabled. 3465 */ 3466 memset(dev_cap, 0, sizeof(*dev_cap)); 3467 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3468 if (err) { 3469 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3470 goto err_fw; 3471 } 3472 3473 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3474 goto err_fw; 3475 } 3476 } 3477 3478 err = mlx4_init_hca(dev); 3479 if (err) { 3480 if (err == -EACCES) { 3481 /* Not primary Physical function 3482 * Running in slave mode */ 3483 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3484 /* We're not a PF */ 3485 if (dev->flags & MLX4_FLAG_SRIOV) { 3486 if (!existing_vfs) 3487 pci_disable_sriov(pdev); 3488 if (mlx4_is_master(dev) && !reset_flow) 3489 atomic_dec(&pf_loading); 3490 dev->flags &= ~MLX4_FLAG_SRIOV; 3491 } 3492 if (!mlx4_is_slave(dev)) 3493 mlx4_free_ownership(dev); 3494 dev->flags |= MLX4_FLAG_SLAVE; 3495 dev->flags &= ~MLX4_FLAG_MASTER; 3496 goto slave_start; 3497 } else 3498 goto err_fw; 3499 } 3500 3501 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3502 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3503 existing_vfs, reset_flow); 3504 3505 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3506 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3507 dev->flags = dev_flags; 3508 err = mlx4_cmd_init(dev); 3509 if (err) { 3510 /* Only VHCR is cleaned up, so could still 3511 * send FW commands 3512 */ 3513 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3514 goto err_close; 3515 } 3516 } else { 3517 dev->flags = dev_flags; 3518 } 3519 3520 if (!SRIOV_VALID_STATE(dev->flags)) { 3521 mlx4_err(dev, "Invalid SRIOV state\n"); 3522 goto err_close; 3523 } 3524 } 3525 3526 /* check if the device is functioning at its maximum possible speed. 3527 * No return code for this call, just warn the user in case of PCI 3528 * express device capabilities are under-satisfied by the bus. 3529 */ 3530 if (!mlx4_is_slave(dev)) 3531 pcie_print_link_status(dev->persist->pdev); 3532 3533 /* In master functions, the communication channel must be initialized 3534 * after obtaining its address from fw */ 3535 if (mlx4_is_master(dev)) { 3536 if (dev->caps.num_ports < 2 && 3537 num_vfs_argc > 1) { 3538 err = -EINVAL; 3539 mlx4_err(dev, 3540 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3541 dev->caps.num_ports); 3542 goto err_close; 3543 } 3544 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3545 3546 for (i = 0; 3547 i < sizeof(dev->persist->nvfs)/ 3548 sizeof(dev->persist->nvfs[0]); i++) { 3549 unsigned j; 3550 3551 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3552 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3553 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3554 dev->caps.num_ports; 3555 } 3556 } 3557 3558 /* In master functions, the communication channel 3559 * must be initialized after obtaining its address from fw 3560 */ 3561 err = mlx4_multi_func_init(dev); 3562 if (err) { 3563 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3564 goto err_close; 3565 } 3566 } 3567 3568 err = mlx4_alloc_eq_table(dev); 3569 if (err) 3570 goto err_master_mfunc; 3571 3572 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3573 mutex_init(&priv->msix_ctl.pool_lock); 3574 3575 mlx4_enable_msi_x(dev); 3576 if ((mlx4_is_mfunc(dev)) && 3577 !(dev->flags & MLX4_FLAG_MSI_X)) { 3578 err = -EOPNOTSUPP; 3579 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3580 goto err_free_eq; 3581 } 3582 3583 if (!mlx4_is_slave(dev)) { 3584 err = mlx4_init_steering(dev); 3585 if (err) 3586 goto err_disable_msix; 3587 } 3588 3589 mlx4_init_quotas(dev); 3590 3591 err = mlx4_setup_hca(dev); 3592 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3593 !mlx4_is_mfunc(dev)) { 3594 dev->flags &= ~MLX4_FLAG_MSI_X; 3595 dev->caps.num_comp_vectors = 1; 3596 pci_disable_msix(pdev); 3597 err = mlx4_setup_hca(dev); 3598 } 3599 3600 if (err) 3601 goto err_steer; 3602 3603 /* When PF resources are ready arm its comm channel to enable 3604 * getting commands 3605 */ 3606 if (mlx4_is_master(dev)) { 3607 err = mlx4_ARM_COMM_CHANNEL(dev); 3608 if (err) { 3609 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3610 err); 3611 goto err_steer; 3612 } 3613 } 3614 3615 for (port = 1; port <= dev->caps.num_ports; port++) { 3616 err = mlx4_init_port_info(dev, port); 3617 if (err) 3618 goto err_port; 3619 } 3620 3621 priv->v2p.port1 = 1; 3622 priv->v2p.port2 = 2; 3623 3624 err = mlx4_register_device(dev); 3625 if (err) 3626 goto err_port; 3627 3628 mlx4_request_modules(dev); 3629 3630 mlx4_sense_init(dev); 3631 mlx4_start_sense(dev); 3632 3633 priv->removed = 0; 3634 3635 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3636 atomic_dec(&pf_loading); 3637 3638 kfree(dev_cap); 3639 return 0; 3640 3641 err_port: 3642 for (--port; port >= 1; --port) 3643 mlx4_cleanup_port_info(&priv->port[port]); 3644 3645 mlx4_cleanup_default_counters(dev); 3646 if (!mlx4_is_slave(dev)) 3647 mlx4_cleanup_counters_table(dev); 3648 mlx4_cleanup_qp_table(dev); 3649 mlx4_cleanup_srq_table(dev); 3650 mlx4_cleanup_cq_table(dev); 3651 mlx4_cmd_use_polling(dev); 3652 mlx4_cleanup_eq_table(dev); 3653 mlx4_cleanup_mcg_table(dev); 3654 mlx4_cleanup_mr_table(dev); 3655 mlx4_cleanup_xrcd_table(dev); 3656 mlx4_cleanup_pd_table(dev); 3657 mlx4_cleanup_uar_table(dev); 3658 3659 err_steer: 3660 if (!mlx4_is_slave(dev)) 3661 mlx4_clear_steering(dev); 3662 3663 err_disable_msix: 3664 if (dev->flags & MLX4_FLAG_MSI_X) 3665 pci_disable_msix(pdev); 3666 3667 err_free_eq: 3668 mlx4_free_eq_table(dev); 3669 3670 err_master_mfunc: 3671 if (mlx4_is_master(dev)) { 3672 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3673 mlx4_multi_func_cleanup(dev); 3674 } 3675 3676 if (mlx4_is_slave(dev)) 3677 mlx4_slave_destroy_special_qp_cap(dev); 3678 3679 err_close: 3680 mlx4_close_hca(dev); 3681 3682 err_fw: 3683 mlx4_close_fw(dev); 3684 3685 err_mfunc: 3686 if (mlx4_is_slave(dev)) 3687 mlx4_multi_func_cleanup(dev); 3688 3689 err_cmd: 3690 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3691 3692 err_sriov: 3693 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3694 pci_disable_sriov(pdev); 3695 dev->flags &= ~MLX4_FLAG_SRIOV; 3696 } 3697 3698 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3699 atomic_dec(&pf_loading); 3700 3701 kfree(priv->dev.dev_vfs); 3702 3703 if (!mlx4_is_slave(dev)) 3704 mlx4_free_ownership(dev); 3705 3706 kfree(dev_cap); 3707 return err; 3708 } 3709 3710 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3711 struct mlx4_priv *priv) 3712 { 3713 int err; 3714 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3715 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3716 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3717 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3718 unsigned total_vfs = 0; 3719 unsigned int i; 3720 3721 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3722 3723 err = mlx4_pci_enable_device(&priv->dev); 3724 if (err) { 3725 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3726 return err; 3727 } 3728 3729 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3730 * per port, we must limit the number of VFs to 63 (since their are 3731 * 128 MACs) 3732 */ 3733 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3734 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3735 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3736 if (nvfs[i] < 0) { 3737 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3738 err = -EINVAL; 3739 goto err_disable_pdev; 3740 } 3741 } 3742 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3743 i++) { 3744 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3745 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3746 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3747 err = -EINVAL; 3748 goto err_disable_pdev; 3749 } 3750 } 3751 if (total_vfs > MLX4_MAX_NUM_VF) { 3752 dev_err(&pdev->dev, 3753 "Requested more VF's (%d) than allowed by hw (%d)\n", 3754 total_vfs, MLX4_MAX_NUM_VF); 3755 err = -EINVAL; 3756 goto err_disable_pdev; 3757 } 3758 3759 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3760 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3761 dev_err(&pdev->dev, 3762 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3763 nvfs[i] + nvfs[2], i + 1, 3764 MLX4_MAX_NUM_VF_P_PORT); 3765 err = -EINVAL; 3766 goto err_disable_pdev; 3767 } 3768 } 3769 3770 /* Check for BARs. */ 3771 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3772 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3773 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3774 pci_dev_data, pci_resource_flags(pdev, 0)); 3775 err = -ENODEV; 3776 goto err_disable_pdev; 3777 } 3778 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3779 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3780 err = -ENODEV; 3781 goto err_disable_pdev; 3782 } 3783 3784 err = pci_request_regions(pdev, DRV_NAME); 3785 if (err) { 3786 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3787 goto err_disable_pdev; 3788 } 3789 3790 pci_set_master(pdev); 3791 3792 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3793 if (err) { 3794 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3795 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3796 if (err) { 3797 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3798 goto err_release_regions; 3799 } 3800 } 3801 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3802 if (err) { 3803 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3804 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3805 if (err) { 3806 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3807 goto err_release_regions; 3808 } 3809 } 3810 3811 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3812 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3813 /* Detect if this device is a virtual function */ 3814 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3815 /* When acting as pf, we normally skip vfs unless explicitly 3816 * requested to probe them. 3817 */ 3818 if (total_vfs) { 3819 unsigned vfs_offset = 0; 3820 3821 for (i = 0; i < ARRAY_SIZE(nvfs) && 3822 vfs_offset + nvfs[i] < extended_func_num(pdev); 3823 vfs_offset += nvfs[i], i++) 3824 ; 3825 if (i == ARRAY_SIZE(nvfs)) { 3826 err = -ENODEV; 3827 goto err_release_regions; 3828 } 3829 if ((extended_func_num(pdev) - vfs_offset) 3830 > prb_vf[i]) { 3831 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3832 extended_func_num(pdev)); 3833 err = -ENODEV; 3834 goto err_release_regions; 3835 } 3836 } 3837 } 3838 3839 err = mlx4_crdump_init(&priv->dev); 3840 if (err) 3841 goto err_release_regions; 3842 3843 err = mlx4_catas_init(&priv->dev); 3844 if (err) 3845 goto err_crdump; 3846 3847 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3848 if (err) 3849 goto err_catas; 3850 3851 return 0; 3852 3853 err_catas: 3854 mlx4_catas_end(&priv->dev); 3855 3856 err_crdump: 3857 mlx4_crdump_end(&priv->dev); 3858 3859 err_release_regions: 3860 pci_release_regions(pdev); 3861 3862 err_disable_pdev: 3863 mlx4_pci_disable_device(&priv->dev); 3864 return err; 3865 } 3866 3867 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3868 enum devlink_port_type port_type) 3869 { 3870 struct mlx4_port_info *info = container_of(devlink_port, 3871 struct mlx4_port_info, 3872 devlink_port); 3873 enum mlx4_port_type mlx4_port_type; 3874 3875 switch (port_type) { 3876 case DEVLINK_PORT_TYPE_AUTO: 3877 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3878 break; 3879 case DEVLINK_PORT_TYPE_ETH: 3880 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3881 break; 3882 case DEVLINK_PORT_TYPE_IB: 3883 mlx4_port_type = MLX4_PORT_TYPE_IB; 3884 break; 3885 default: 3886 return -EOPNOTSUPP; 3887 } 3888 3889 return __set_port_type(info, mlx4_port_type); 3890 } 3891 3892 static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3893 { 3894 struct mlx4_priv *priv = devlink_priv(devlink); 3895 struct mlx4_dev *dev = &priv->dev; 3896 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3897 union devlink_param_value saved_value; 3898 int err; 3899 3900 err = devlink_param_driverinit_value_get(devlink, 3901 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3902 &saved_value); 3903 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3904 mlx4_internal_err_reset = saved_value.vbool; 3905 /* Notify on value changed on runtime configuration mode */ 3906 devlink_param_value_changed(devlink, 3907 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3908 } 3909 err = devlink_param_driverinit_value_get(devlink, 3910 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3911 &saved_value); 3912 if (!err) 3913 log_num_mac = order_base_2(saved_value.vu32); 3914 err = devlink_param_driverinit_value_get(devlink, 3915 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3916 &saved_value); 3917 if (!err) 3918 enable_64b_cqe_eqe = saved_value.vbool; 3919 err = devlink_param_driverinit_value_get(devlink, 3920 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3921 &saved_value); 3922 if (!err) 3923 enable_4k_uar = saved_value.vbool; 3924 err = devlink_param_driverinit_value_get(devlink, 3925 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3926 &saved_value); 3927 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3928 crdump->snapshot_enable = saved_value.vbool; 3929 devlink_param_value_changed(devlink, 3930 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3931 } 3932 } 3933 3934 static void mlx4_restart_one_down(struct pci_dev *pdev); 3935 static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 3936 struct devlink *devlink); 3937 3938 static int mlx4_devlink_reload_down(struct devlink *devlink, 3939 struct netlink_ext_ack *extack) 3940 { 3941 struct mlx4_priv *priv = devlink_priv(devlink); 3942 struct mlx4_dev *dev = &priv->dev; 3943 struct mlx4_dev_persistent *persist = dev->persist; 3944 3945 if (persist->num_vfs) 3946 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 3947 mlx4_restart_one_down(persist->pdev); 3948 return 0; 3949 } 3950 3951 static int mlx4_devlink_reload_up(struct devlink *devlink, 3952 struct netlink_ext_ack *extack) 3953 { 3954 struct mlx4_priv *priv = devlink_priv(devlink); 3955 struct mlx4_dev *dev = &priv->dev; 3956 struct mlx4_dev_persistent *persist = dev->persist; 3957 int err; 3958 3959 err = mlx4_restart_one_up(persist->pdev, true, devlink); 3960 if (err) 3961 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n", 3962 err); 3963 3964 return err; 3965 } 3966 3967 static const struct devlink_ops mlx4_devlink_ops = { 3968 .port_type_set = mlx4_devlink_port_type_set, 3969 .reload_down = mlx4_devlink_reload_down, 3970 .reload_up = mlx4_devlink_reload_up, 3971 }; 3972 3973 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3974 { 3975 struct devlink *devlink; 3976 struct mlx4_priv *priv; 3977 struct mlx4_dev *dev; 3978 int ret; 3979 3980 printk_once(KERN_INFO "%s", mlx4_version); 3981 3982 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3983 if (!devlink) 3984 return -ENOMEM; 3985 priv = devlink_priv(devlink); 3986 3987 dev = &priv->dev; 3988 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3989 if (!dev->persist) { 3990 ret = -ENOMEM; 3991 goto err_devlink_free; 3992 } 3993 dev->persist->pdev = pdev; 3994 dev->persist->dev = dev; 3995 pci_set_drvdata(pdev, dev->persist); 3996 priv->pci_dev_data = id->driver_data; 3997 mutex_init(&dev->persist->device_state_mutex); 3998 mutex_init(&dev->persist->interface_state_mutex); 3999 mutex_init(&dev->persist->pci_status_mutex); 4000 4001 ret = devlink_register(devlink, &pdev->dev); 4002 if (ret) 4003 goto err_persist_free; 4004 ret = devlink_params_register(devlink, mlx4_devlink_params, 4005 ARRAY_SIZE(mlx4_devlink_params)); 4006 if (ret) 4007 goto err_devlink_unregister; 4008 mlx4_devlink_set_params_init_values(devlink); 4009 ret = __mlx4_init_one(pdev, id->driver_data, priv); 4010 if (ret) 4011 goto err_params_unregister; 4012 4013 devlink_params_publish(devlink); 4014 pci_save_state(pdev); 4015 return 0; 4016 4017 err_params_unregister: 4018 devlink_params_unregister(devlink, mlx4_devlink_params, 4019 ARRAY_SIZE(mlx4_devlink_params)); 4020 err_devlink_unregister: 4021 devlink_unregister(devlink); 4022 err_persist_free: 4023 kfree(dev->persist); 4024 err_devlink_free: 4025 devlink_free(devlink); 4026 return ret; 4027 } 4028 4029 static void mlx4_clean_dev(struct mlx4_dev *dev) 4030 { 4031 struct mlx4_dev_persistent *persist = dev->persist; 4032 struct mlx4_priv *priv = mlx4_priv(dev); 4033 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4034 4035 memset(priv, 0, sizeof(*priv)); 4036 priv->dev.persist = persist; 4037 priv->dev.flags = flags; 4038 } 4039 4040 static void mlx4_unload_one(struct pci_dev *pdev) 4041 { 4042 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4043 struct mlx4_dev *dev = persist->dev; 4044 struct mlx4_priv *priv = mlx4_priv(dev); 4045 int pci_dev_data; 4046 int p, i; 4047 4048 if (priv->removed) 4049 return; 4050 4051 /* saving current ports type for further use */ 4052 for (i = 0; i < dev->caps.num_ports; i++) { 4053 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4054 dev->persist->curr_port_poss_type[i] = dev->caps. 4055 possible_type[i + 1]; 4056 } 4057 4058 pci_dev_data = priv->pci_dev_data; 4059 4060 mlx4_stop_sense(dev); 4061 mlx4_unregister_device(dev); 4062 4063 for (p = 1; p <= dev->caps.num_ports; p++) { 4064 mlx4_cleanup_port_info(&priv->port[p]); 4065 mlx4_CLOSE_PORT(dev, p); 4066 } 4067 4068 if (mlx4_is_master(dev)) 4069 mlx4_free_resource_tracker(dev, 4070 RES_TR_FREE_SLAVES_ONLY); 4071 4072 mlx4_cleanup_default_counters(dev); 4073 if (!mlx4_is_slave(dev)) 4074 mlx4_cleanup_counters_table(dev); 4075 mlx4_cleanup_qp_table(dev); 4076 mlx4_cleanup_srq_table(dev); 4077 mlx4_cleanup_cq_table(dev); 4078 mlx4_cmd_use_polling(dev); 4079 mlx4_cleanup_eq_table(dev); 4080 mlx4_cleanup_mcg_table(dev); 4081 mlx4_cleanup_mr_table(dev); 4082 mlx4_cleanup_xrcd_table(dev); 4083 mlx4_cleanup_pd_table(dev); 4084 4085 if (mlx4_is_master(dev)) 4086 mlx4_free_resource_tracker(dev, 4087 RES_TR_FREE_STRUCTS_ONLY); 4088 4089 iounmap(priv->kar); 4090 mlx4_uar_free(dev, &priv->driver_uar); 4091 mlx4_cleanup_uar_table(dev); 4092 if (!mlx4_is_slave(dev)) 4093 mlx4_clear_steering(dev); 4094 mlx4_free_eq_table(dev); 4095 if (mlx4_is_master(dev)) 4096 mlx4_multi_func_cleanup(dev); 4097 mlx4_close_hca(dev); 4098 mlx4_close_fw(dev); 4099 if (mlx4_is_slave(dev)) 4100 mlx4_multi_func_cleanup(dev); 4101 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4102 4103 if (dev->flags & MLX4_FLAG_MSI_X) 4104 pci_disable_msix(pdev); 4105 4106 if (!mlx4_is_slave(dev)) 4107 mlx4_free_ownership(dev); 4108 4109 mlx4_slave_destroy_special_qp_cap(dev); 4110 kfree(dev->dev_vfs); 4111 4112 mlx4_clean_dev(dev); 4113 priv->pci_dev_data = pci_dev_data; 4114 priv->removed = 1; 4115 } 4116 4117 static void mlx4_remove_one(struct pci_dev *pdev) 4118 { 4119 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4120 struct mlx4_dev *dev = persist->dev; 4121 struct mlx4_priv *priv = mlx4_priv(dev); 4122 struct devlink *devlink = priv_to_devlink(priv); 4123 int active_vfs = 0; 4124 4125 if (mlx4_is_slave(dev)) 4126 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4127 4128 mutex_lock(&persist->interface_state_mutex); 4129 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4130 mutex_unlock(&persist->interface_state_mutex); 4131 4132 /* Disabling SR-IOV is not allowed while there are active vf's */ 4133 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4134 active_vfs = mlx4_how_many_lives_vf(dev); 4135 if (active_vfs) { 4136 pr_warn("Removing PF when there are active VF's !!\n"); 4137 pr_warn("Will not disable SR-IOV.\n"); 4138 } 4139 } 4140 4141 /* device marked to be under deletion running now without the lock 4142 * letting other tasks to be terminated 4143 */ 4144 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4145 mlx4_unload_one(pdev); 4146 else 4147 mlx4_info(dev, "%s: interface is down\n", __func__); 4148 mlx4_catas_end(dev); 4149 mlx4_crdump_end(dev); 4150 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4151 mlx4_warn(dev, "Disabling SR-IOV\n"); 4152 pci_disable_sriov(pdev); 4153 } 4154 4155 pci_release_regions(pdev); 4156 mlx4_pci_disable_device(dev); 4157 devlink_params_unregister(devlink, mlx4_devlink_params, 4158 ARRAY_SIZE(mlx4_devlink_params)); 4159 devlink_unregister(devlink); 4160 kfree(dev->persist); 4161 devlink_free(devlink); 4162 } 4163 4164 static int restore_current_port_types(struct mlx4_dev *dev, 4165 enum mlx4_port_type *types, 4166 enum mlx4_port_type *poss_types) 4167 { 4168 struct mlx4_priv *priv = mlx4_priv(dev); 4169 int err, i; 4170 4171 mlx4_stop_sense(dev); 4172 4173 mutex_lock(&priv->port_mutex); 4174 for (i = 0; i < dev->caps.num_ports; i++) 4175 dev->caps.possible_type[i + 1] = poss_types[i]; 4176 err = mlx4_change_port_types(dev, types); 4177 mlx4_start_sense(dev); 4178 mutex_unlock(&priv->port_mutex); 4179 4180 return err; 4181 } 4182 4183 static void mlx4_restart_one_down(struct pci_dev *pdev) 4184 { 4185 mlx4_unload_one(pdev); 4186 } 4187 4188 static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 4189 struct devlink *devlink) 4190 { 4191 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4192 struct mlx4_dev *dev = persist->dev; 4193 struct mlx4_priv *priv = mlx4_priv(dev); 4194 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4195 int pci_dev_data, err, total_vfs; 4196 4197 pci_dev_data = priv->pci_dev_data; 4198 total_vfs = dev->persist->num_vfs; 4199 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4200 4201 if (reload) 4202 mlx4_devlink_param_load_driverinit_values(devlink); 4203 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4204 if (err) { 4205 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4206 __func__, pci_name(pdev), err); 4207 return err; 4208 } 4209 4210 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4211 dev->persist->curr_port_poss_type); 4212 if (err) 4213 mlx4_err(dev, "could not restore original port types (%d)\n", 4214 err); 4215 4216 return err; 4217 } 4218 4219 int mlx4_restart_one(struct pci_dev *pdev) 4220 { 4221 mlx4_restart_one_down(pdev); 4222 return mlx4_restart_one_up(pdev, false, NULL); 4223 } 4224 4225 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4226 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4227 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4228 4229 static const struct pci_device_id mlx4_pci_table[] = { 4230 #ifdef CONFIG_MLX4_CORE_GEN2 4231 /* MT25408 "Hermon" */ 4232 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4233 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4234 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4235 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4236 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4237 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4238 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4239 /* MT25458 ConnectX EN 10GBASE-T */ 4240 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4241 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4242 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4243 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4244 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4245 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4246 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4247 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4248 /* MT25400 Family [ConnectX-2] */ 4249 MLX_VF(0x1002), /* Virtual Function */ 4250 #endif /* CONFIG_MLX4_CORE_GEN2 */ 4251 /* MT27500 Family [ConnectX-3] */ 4252 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4253 MLX_VF(0x1004), /* Virtual Function */ 4254 MLX_GN(0x1005), /* MT27510 Family */ 4255 MLX_GN(0x1006), /* MT27511 Family */ 4256 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4257 MLX_GN(0x1008), /* MT27521 Family */ 4258 MLX_GN(0x1009), /* MT27530 Family */ 4259 MLX_GN(0x100a), /* MT27531 Family */ 4260 MLX_GN(0x100b), /* MT27540 Family */ 4261 MLX_GN(0x100c), /* MT27541 Family */ 4262 MLX_GN(0x100d), /* MT27550 Family */ 4263 MLX_GN(0x100e), /* MT27551 Family */ 4264 MLX_GN(0x100f), /* MT27560 Family */ 4265 MLX_GN(0x1010), /* MT27561 Family */ 4266 4267 /* 4268 * See the mellanox_check_broken_intx_masking() quirk when 4269 * adding devices 4270 */ 4271 4272 { 0, } 4273 }; 4274 4275 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4276 4277 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4278 pci_channel_state_t state) 4279 { 4280 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4281 4282 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4283 mlx4_enter_error_state(persist); 4284 4285 mutex_lock(&persist->interface_state_mutex); 4286 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4287 mlx4_unload_one(pdev); 4288 4289 mutex_unlock(&persist->interface_state_mutex); 4290 if (state == pci_channel_io_perm_failure) 4291 return PCI_ERS_RESULT_DISCONNECT; 4292 4293 mlx4_pci_disable_device(persist->dev); 4294 return PCI_ERS_RESULT_NEED_RESET; 4295 } 4296 4297 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4298 { 4299 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4300 struct mlx4_dev *dev = persist->dev; 4301 int err; 4302 4303 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4304 err = mlx4_pci_enable_device(dev); 4305 if (err) { 4306 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4307 return PCI_ERS_RESULT_DISCONNECT; 4308 } 4309 4310 pci_set_master(pdev); 4311 pci_restore_state(pdev); 4312 pci_save_state(pdev); 4313 return PCI_ERS_RESULT_RECOVERED; 4314 } 4315 4316 static void mlx4_pci_resume(struct pci_dev *pdev) 4317 { 4318 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4319 struct mlx4_dev *dev = persist->dev; 4320 struct mlx4_priv *priv = mlx4_priv(dev); 4321 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4322 int total_vfs; 4323 int err; 4324 4325 mlx4_err(dev, "%s was called\n", __func__); 4326 total_vfs = dev->persist->num_vfs; 4327 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4328 4329 mutex_lock(&persist->interface_state_mutex); 4330 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4331 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4332 priv, 1); 4333 if (err) { 4334 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4335 __func__, err); 4336 goto end; 4337 } 4338 4339 err = restore_current_port_types(dev, dev->persist-> 4340 curr_port_type, dev->persist-> 4341 curr_port_poss_type); 4342 if (err) 4343 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4344 } 4345 end: 4346 mutex_unlock(&persist->interface_state_mutex); 4347 4348 } 4349 4350 static void mlx4_shutdown(struct pci_dev *pdev) 4351 { 4352 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4353 4354 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4355 mutex_lock(&persist->interface_state_mutex); 4356 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4357 mlx4_unload_one(pdev); 4358 mutex_unlock(&persist->interface_state_mutex); 4359 } 4360 4361 static const struct pci_error_handlers mlx4_err_handler = { 4362 .error_detected = mlx4_pci_err_detected, 4363 .slot_reset = mlx4_pci_slot_reset, 4364 .resume = mlx4_pci_resume, 4365 }; 4366 4367 static int mlx4_suspend(struct pci_dev *pdev, pm_message_t state) 4368 { 4369 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4370 struct mlx4_dev *dev = persist->dev; 4371 4372 mlx4_err(dev, "suspend was called\n"); 4373 mutex_lock(&persist->interface_state_mutex); 4374 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4375 mlx4_unload_one(pdev); 4376 mutex_unlock(&persist->interface_state_mutex); 4377 4378 return 0; 4379 } 4380 4381 static int mlx4_resume(struct pci_dev *pdev) 4382 { 4383 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4384 struct mlx4_dev *dev = persist->dev; 4385 struct mlx4_priv *priv = mlx4_priv(dev); 4386 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4387 int total_vfs; 4388 int ret = 0; 4389 4390 mlx4_err(dev, "resume was called\n"); 4391 total_vfs = dev->persist->num_vfs; 4392 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4393 4394 mutex_lock(&persist->interface_state_mutex); 4395 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4396 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4397 nvfs, priv, 1); 4398 if (!ret) { 4399 ret = restore_current_port_types(dev, 4400 dev->persist->curr_port_type, 4401 dev->persist->curr_port_poss_type); 4402 if (ret) 4403 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4404 } 4405 } 4406 mutex_unlock(&persist->interface_state_mutex); 4407 4408 return ret; 4409 } 4410 4411 static struct pci_driver mlx4_driver = { 4412 .name = DRV_NAME, 4413 .id_table = mlx4_pci_table, 4414 .probe = mlx4_init_one, 4415 .shutdown = mlx4_shutdown, 4416 .remove = mlx4_remove_one, 4417 .suspend = mlx4_suspend, 4418 .resume = mlx4_resume, 4419 .err_handler = &mlx4_err_handler, 4420 }; 4421 4422 static int __init mlx4_verify_params(void) 4423 { 4424 if (msi_x < 0) { 4425 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4426 return -1; 4427 } 4428 4429 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4430 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4431 return -1; 4432 } 4433 4434 if (log_num_vlan != 0) 4435 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4436 MLX4_LOG_NUM_VLANS); 4437 4438 if (use_prio != 0) 4439 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4440 4441 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 4442 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4443 log_mtts_per_seg); 4444 return -1; 4445 } 4446 4447 /* Check if module param for ports type has legal combination */ 4448 if (port_type_array[0] == false && port_type_array[1] == true) { 4449 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4450 port_type_array[0] = true; 4451 } 4452 4453 if (mlx4_log_num_mgm_entry_size < -7 || 4454 (mlx4_log_num_mgm_entry_size > 0 && 4455 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4456 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4457 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4458 mlx4_log_num_mgm_entry_size, 4459 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4460 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4461 return -1; 4462 } 4463 4464 return 0; 4465 } 4466 4467 static int __init mlx4_init(void) 4468 { 4469 int ret; 4470 4471 if (mlx4_verify_params()) 4472 return -EINVAL; 4473 4474 4475 mlx4_wq = create_singlethread_workqueue("mlx4"); 4476 if (!mlx4_wq) 4477 return -ENOMEM; 4478 4479 ret = pci_register_driver(&mlx4_driver); 4480 if (ret < 0) 4481 destroy_workqueue(mlx4_wq); 4482 return ret < 0 ? ret : 0; 4483 } 4484 4485 static void __exit mlx4_cleanup(void) 4486 { 4487 pci_unregister_driver(&mlx4_driver); 4488 destroy_workqueue(mlx4_wq); 4489 } 4490 4491 module_init(mlx4_init); 4492 module_exit(mlx4_cleanup); 4493