1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/netdevice.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static int num_vfs; 81 module_param(num_vfs, int, 0444); 82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0"); 83 84 static int probe_vf; 85 module_param(probe_vf, int, 0644); 86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); 87 88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 89 module_param_named(log_num_mgm_entry_size, 90 mlx4_log_num_mgm_entry_size, int, 0444); 91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 92 " of qp per mcg, for example:" 93 " 10 gives 248.range: 7 <=" 94 " log_num_mgm_entry_size <= 12." 95 " To activate device managed" 96 " flow steering when available, set to -1"); 97 98 static bool enable_64b_cqe_eqe; 99 module_param(enable_64b_cqe_eqe, bool, 0444); 100 MODULE_PARM_DESC(enable_64b_cqe_eqe, 101 "Enable 64 byte CQEs/EQEs when the FW supports this"); 102 103 #define HCA_GLOBAL_CAP_MASK 0 104 105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE 106 107 static char mlx4_version[] = 108 DRV_NAME ": Mellanox ConnectX core driver v" 109 DRV_VERSION " (" DRV_RELDATE ")\n"; 110 111 static struct mlx4_profile default_profile = { 112 .num_qp = 1 << 18, 113 .num_srq = 1 << 16, 114 .rdmarc_per_qp = 1 << 4, 115 .num_cq = 1 << 16, 116 .num_mcg = 1 << 13, 117 .num_mpt = 1 << 19, 118 .num_mtt = 1 << 20, /* It is really num mtt segements */ 119 }; 120 121 static int log_num_mac = 7; 122 module_param_named(log_num_mac, log_num_mac, int, 0444); 123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 124 125 static int log_num_vlan; 126 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 128 /* Log2 max number of VLANs per ETH port (0-7) */ 129 #define MLX4_LOG_NUM_VLANS 7 130 131 static bool use_prio; 132 module_param_named(use_prio, use_prio, bool, 0444); 133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " 134 "(0/1, default 0)"); 135 136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 139 140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 141 static int arr_argc = 2; 142 module_param_array(port_type_array, int, &arr_argc, 0444); 143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 144 "1 for IB, 2 for Ethernet"); 145 146 struct mlx4_port_config { 147 struct list_head list; 148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 149 struct pci_dev *pdev; 150 }; 151 152 int mlx4_check_port_params(struct mlx4_dev *dev, 153 enum mlx4_port_type *port_type) 154 { 155 int i; 156 157 for (i = 0; i < dev->caps.num_ports - 1; i++) { 158 if (port_type[i] != port_type[i + 1]) { 159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 160 mlx4_err(dev, "Only same port types supported " 161 "on this HCA, aborting.\n"); 162 return -EINVAL; 163 } 164 } 165 } 166 167 for (i = 0; i < dev->caps.num_ports; i++) { 168 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 169 mlx4_err(dev, "Requested port type for port %d is not " 170 "supported on this HCA\n", i + 1); 171 return -EINVAL; 172 } 173 } 174 return 0; 175 } 176 177 static void mlx4_set_port_mask(struct mlx4_dev *dev) 178 { 179 int i; 180 181 for (i = 1; i <= dev->caps.num_ports; ++i) 182 dev->caps.port_mask[i] = dev->caps.port_type[i]; 183 } 184 185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 186 { 187 int err; 188 int i; 189 190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 191 if (err) { 192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 193 return err; 194 } 195 196 if (dev_cap->min_page_sz > PAGE_SIZE) { 197 mlx4_err(dev, "HCA minimum page size of %d bigger than " 198 "kernel PAGE_SIZE of %ld, aborting.\n", 199 dev_cap->min_page_sz, PAGE_SIZE); 200 return -ENODEV; 201 } 202 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 203 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 204 "aborting.\n", 205 dev_cap->num_ports, MLX4_MAX_PORTS); 206 return -ENODEV; 207 } 208 209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " 211 "PCI resource 2 size of 0x%llx, aborting.\n", 212 dev_cap->uar_size, 213 (unsigned long long) pci_resource_len(dev->pdev, 2)); 214 return -ENODEV; 215 } 216 217 dev->caps.num_ports = dev_cap->num_ports; 218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; 219 for (i = 1; i <= dev->caps.num_ports; ++i) { 220 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 224 /* set gid and pkey table operating lengths by default 225 * to non-sriov values */ 226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 230 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 233 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 234 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 236 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 237 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 238 } 239 240 dev->caps.uar_page_size = PAGE_SIZE; 241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 243 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 245 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 246 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 247 dev->caps.max_wqes = dev_cap->max_qp_sz; 248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 251 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 254 /* 255 * Subtract 1 from the limit because we need to allocate a 256 * spare CQE so the HCA HW can tell the difference between an 257 * empty CQ and a full CQ. 258 */ 259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 260 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 261 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 262 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 263 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 264 265 /* The first 128 UARs are used for EQ doorbells */ 266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 267 dev->caps.reserved_pds = dev_cap->reserved_pds; 268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 269 dev_cap->reserved_xrcds : 0; 270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 271 dev_cap->max_xrcds : 0; 272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 273 274 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 276 dev->caps.flags = dev_cap->flags; 277 dev->caps.flags2 = dev_cap->flags2; 278 dev->caps.bmme_flags = dev_cap->bmme_flags; 279 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 280 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 281 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 283 284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 287 /* Don't do sense port on multifunction devices (for now at least) */ 288 if (mlx4_is_mfunc(dev)) 289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 290 291 dev->caps.log_num_macs = log_num_mac; 292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 293 dev->caps.log_num_prios = use_prio ? 3 : 0; 294 295 for (i = 1; i <= dev->caps.num_ports; ++i) { 296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 297 if (dev->caps.supported_type[i]) { 298 /* if only ETH is supported - assign ETH */ 299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 301 /* if only IB is supported, assign IB */ 302 else if (dev->caps.supported_type[i] == 303 MLX4_PORT_TYPE_IB) 304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 305 else { 306 /* if IB and ETH are supported, we set the port 307 * type according to user selection of port type; 308 * if user selected none, take the FW hint */ 309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 312 else 313 dev->caps.port_type[i] = port_type_array[i - 1]; 314 } 315 } 316 /* 317 * Link sensing is allowed on the port if 3 conditions are true: 318 * 1. Both protocols are supported on the port. 319 * 2. Different types are supported on the port 320 * 3. FW declared that it supports link sensing 321 */ 322 mlx4_priv(dev)->sense.sense_allowed[i] = 323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 326 327 /* 328 * If "default_sense" bit is set, we move the port to "AUTO" mode 329 * and perform sense_port FW command to try and set the correct 330 * port type from beginning 331 */ 332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 335 mlx4_SENSE_PORT(dev, i, &sensed_port); 336 if (sensed_port != MLX4_PORT_TYPE_NONE) 337 dev->caps.port_type[i] = sensed_port; 338 } else { 339 dev->caps.possible_type[i] = dev->caps.port_type[i]; 340 } 341 342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 343 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 344 mlx4_warn(dev, "Requested number of MACs is too much " 345 "for port %d, reducing to %d.\n", 346 i, 1 << dev->caps.log_num_macs); 347 } 348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 350 mlx4_warn(dev, "Requested number of VLANs is too much " 351 "for port %d, reducing to %d.\n", 352 i, 1 << dev->caps.log_num_vlans); 353 } 354 } 355 356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 357 358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 361 (1 << dev->caps.log_num_macs) * 362 (1 << dev->caps.log_num_vlans) * 363 (1 << dev->caps.log_num_prios) * 364 dev->caps.num_ports; 365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 366 367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 371 372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 373 374 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 375 if (dev_cap->flags & 376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 380 } 381 } 382 383 if ((dev->caps.flags & 384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 385 mlx4_is_master(dev)) 386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 387 388 return 0; 389 } 390 /*The function checks if there are live vf, return the num of them*/ 391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 392 { 393 struct mlx4_priv *priv = mlx4_priv(dev); 394 struct mlx4_slave_state *s_state; 395 int i; 396 int ret = 0; 397 398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 399 s_state = &priv->mfunc.master.slave_state[i]; 400 if (s_state->active && s_state->last_cmd != 401 MLX4_COMM_CMD_RESET) { 402 mlx4_warn(dev, "%s: slave: %d is still active\n", 403 __func__, i); 404 ret++; 405 } 406 } 407 return ret; 408 } 409 410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 411 { 412 u32 qk = MLX4_RESERVED_QKEY_BASE; 413 414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 415 qpn < dev->phys_caps.base_proxy_sqpn) 416 return -EINVAL; 417 418 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 419 /* tunnel qp */ 420 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 421 else 422 qk += qpn - dev->phys_caps.base_proxy_sqpn; 423 *qkey = qk; 424 return 0; 425 } 426 EXPORT_SYMBOL(mlx4_get_parav_qkey); 427 428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 429 { 430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 431 432 if (!mlx4_is_master(dev)) 433 return; 434 435 priv->virt2phys_pkey[slave][port - 1][i] = val; 436 } 437 EXPORT_SYMBOL(mlx4_sync_pkey_table); 438 439 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 440 { 441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 442 443 if (!mlx4_is_master(dev)) 444 return; 445 446 priv->slave_node_guids[slave] = guid; 447 } 448 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 449 450 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 451 { 452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 453 454 if (!mlx4_is_master(dev)) 455 return 0; 456 457 return priv->slave_node_guids[slave]; 458 } 459 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 460 461 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 462 { 463 struct mlx4_priv *priv = mlx4_priv(dev); 464 struct mlx4_slave_state *s_slave; 465 466 if (!mlx4_is_master(dev)) 467 return 0; 468 469 s_slave = &priv->mfunc.master.slave_state[slave]; 470 return !!s_slave->active; 471 } 472 EXPORT_SYMBOL(mlx4_is_slave_active); 473 474 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 475 struct mlx4_dev_cap *dev_cap, 476 struct mlx4_init_hca_param *hca_param) 477 { 478 dev->caps.steering_mode = hca_param->steering_mode; 479 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 480 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 481 dev->caps.fs_log_max_ucast_qp_range_size = 482 dev_cap->fs_log_max_ucast_qp_range_size; 483 } else 484 dev->caps.num_qp_per_mgm = 485 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 486 487 mlx4_dbg(dev, "Steering mode is: %s\n", 488 mlx4_steering_mode_str(dev->caps.steering_mode)); 489 } 490 491 static int mlx4_slave_cap(struct mlx4_dev *dev) 492 { 493 int err; 494 u32 page_size; 495 struct mlx4_dev_cap dev_cap; 496 struct mlx4_func_cap func_cap; 497 struct mlx4_init_hca_param hca_param; 498 int i; 499 500 memset(&hca_param, 0, sizeof(hca_param)); 501 err = mlx4_QUERY_HCA(dev, &hca_param); 502 if (err) { 503 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); 504 return err; 505 } 506 507 /*fail if the hca has an unknown capability */ 508 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != 509 HCA_GLOBAL_CAP_MASK) { 510 mlx4_err(dev, "Unknown hca global capabilities\n"); 511 return -ENOSYS; 512 } 513 514 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 515 516 dev->caps.hca_core_clock = hca_param.hca_core_clock; 517 518 memset(&dev_cap, 0, sizeof(dev_cap)); 519 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 520 err = mlx4_dev_cap(dev, &dev_cap); 521 if (err) { 522 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 523 return err; 524 } 525 526 err = mlx4_QUERY_FW(dev); 527 if (err) 528 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n"); 529 530 page_size = ~dev->caps.page_size_cap + 1; 531 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 532 if (page_size > PAGE_SIZE) { 533 mlx4_err(dev, "HCA minimum page size of %d bigger than " 534 "kernel PAGE_SIZE of %ld, aborting.\n", 535 page_size, PAGE_SIZE); 536 return -ENODEV; 537 } 538 539 /* slave gets uar page size from QUERY_HCA fw command */ 540 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 541 542 /* TODO: relax this assumption */ 543 if (dev->caps.uar_page_size != PAGE_SIZE) { 544 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 545 dev->caps.uar_page_size, PAGE_SIZE); 546 return -ENODEV; 547 } 548 549 memset(&func_cap, 0, sizeof(func_cap)); 550 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 551 if (err) { 552 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n", 553 err); 554 return err; 555 } 556 557 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 558 PF_CONTEXT_BEHAVIOUR_MASK) { 559 mlx4_err(dev, "Unknown pf context behaviour\n"); 560 return -ENOSYS; 561 } 562 563 dev->caps.num_ports = func_cap.num_ports; 564 dev->caps.num_qps = func_cap.qp_quota; 565 dev->caps.num_srqs = func_cap.srq_quota; 566 dev->caps.num_cqs = func_cap.cq_quota; 567 dev->caps.num_eqs = func_cap.max_eq; 568 dev->caps.reserved_eqs = func_cap.reserved_eq; 569 dev->caps.num_mpts = func_cap.mpt_quota; 570 dev->caps.num_mtts = func_cap.mtt_quota; 571 dev->caps.num_pds = MLX4_NUM_PDS; 572 dev->caps.num_mgms = 0; 573 dev->caps.num_amgms = 0; 574 575 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 576 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 577 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); 578 return -ENODEV; 579 } 580 581 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 582 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 583 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 584 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 585 586 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 587 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { 588 err = -ENOMEM; 589 goto err_mem; 590 } 591 592 for (i = 1; i <= dev->caps.num_ports; ++i) { 593 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); 594 if (err) { 595 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for" 596 " port %d, aborting (%d).\n", i, err); 597 goto err_mem; 598 } 599 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 600 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 601 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 602 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 603 dev->caps.port_mask[i] = dev->caps.port_type[i]; 604 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 605 &dev->caps.gid_table_len[i], 606 &dev->caps.pkey_table_len[i])) 607 goto err_mem; 608 } 609 610 if (dev->caps.uar_page_size * (dev->caps.num_uars - 611 dev->caps.reserved_uars) > 612 pci_resource_len(dev->pdev, 2)) { 613 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " 614 "PCI resource 2 size of 0x%llx, aborting.\n", 615 dev->caps.uar_page_size * dev->caps.num_uars, 616 (unsigned long long) pci_resource_len(dev->pdev, 2)); 617 goto err_mem; 618 } 619 620 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 621 dev->caps.eqe_size = 64; 622 dev->caps.eqe_factor = 1; 623 } else { 624 dev->caps.eqe_size = 32; 625 dev->caps.eqe_factor = 0; 626 } 627 628 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 629 dev->caps.cqe_size = 64; 630 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 631 } else { 632 dev->caps.cqe_size = 32; 633 } 634 635 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 636 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n"); 637 638 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 639 640 return 0; 641 642 err_mem: 643 kfree(dev->caps.qp0_tunnel); 644 kfree(dev->caps.qp0_proxy); 645 kfree(dev->caps.qp1_tunnel); 646 kfree(dev->caps.qp1_proxy); 647 dev->caps.qp0_tunnel = dev->caps.qp0_proxy = 648 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; 649 650 return err; 651 } 652 653 /* 654 * Change the port configuration of the device. 655 * Every user of this function must hold the port mutex. 656 */ 657 int mlx4_change_port_types(struct mlx4_dev *dev, 658 enum mlx4_port_type *port_types) 659 { 660 int err = 0; 661 int change = 0; 662 int port; 663 664 for (port = 0; port < dev->caps.num_ports; port++) { 665 /* Change the port type only if the new type is different 666 * from the current, and not set to Auto */ 667 if (port_types[port] != dev->caps.port_type[port + 1]) 668 change = 1; 669 } 670 if (change) { 671 mlx4_unregister_device(dev); 672 for (port = 1; port <= dev->caps.num_ports; port++) { 673 mlx4_CLOSE_PORT(dev, port); 674 dev->caps.port_type[port] = port_types[port - 1]; 675 err = mlx4_SET_PORT(dev, port, -1); 676 if (err) { 677 mlx4_err(dev, "Failed to set port %d, " 678 "aborting\n", port); 679 goto out; 680 } 681 } 682 mlx4_set_port_mask(dev); 683 err = mlx4_register_device(dev); 684 } 685 686 out: 687 return err; 688 } 689 690 static ssize_t show_port_type(struct device *dev, 691 struct device_attribute *attr, 692 char *buf) 693 { 694 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 695 port_attr); 696 struct mlx4_dev *mdev = info->dev; 697 char type[8]; 698 699 sprintf(type, "%s", 700 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 701 "ib" : "eth"); 702 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 703 sprintf(buf, "auto (%s)\n", type); 704 else 705 sprintf(buf, "%s\n", type); 706 707 return strlen(buf); 708 } 709 710 static ssize_t set_port_type(struct device *dev, 711 struct device_attribute *attr, 712 const char *buf, size_t count) 713 { 714 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 715 port_attr); 716 struct mlx4_dev *mdev = info->dev; 717 struct mlx4_priv *priv = mlx4_priv(mdev); 718 enum mlx4_port_type types[MLX4_MAX_PORTS]; 719 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 720 int i; 721 int err = 0; 722 723 if (!strcmp(buf, "ib\n")) 724 info->tmp_type = MLX4_PORT_TYPE_IB; 725 else if (!strcmp(buf, "eth\n")) 726 info->tmp_type = MLX4_PORT_TYPE_ETH; 727 else if (!strcmp(buf, "auto\n")) 728 info->tmp_type = MLX4_PORT_TYPE_AUTO; 729 else { 730 mlx4_err(mdev, "%s is not supported port type\n", buf); 731 return -EINVAL; 732 } 733 734 mlx4_stop_sense(mdev); 735 mutex_lock(&priv->port_mutex); 736 /* Possible type is always the one that was delivered */ 737 mdev->caps.possible_type[info->port] = info->tmp_type; 738 739 for (i = 0; i < mdev->caps.num_ports; i++) { 740 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 741 mdev->caps.possible_type[i+1]; 742 if (types[i] == MLX4_PORT_TYPE_AUTO) 743 types[i] = mdev->caps.port_type[i+1]; 744 } 745 746 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 747 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 748 for (i = 1; i <= mdev->caps.num_ports; i++) { 749 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 750 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 751 err = -EINVAL; 752 } 753 } 754 } 755 if (err) { 756 mlx4_err(mdev, "Auto sensing is not supported on this HCA. " 757 "Set only 'eth' or 'ib' for both ports " 758 "(should be the same)\n"); 759 goto out; 760 } 761 762 mlx4_do_sense_ports(mdev, new_types, types); 763 764 err = mlx4_check_port_params(mdev, new_types); 765 if (err) 766 goto out; 767 768 /* We are about to apply the changes after the configuration 769 * was verified, no need to remember the temporary types 770 * any more */ 771 for (i = 0; i < mdev->caps.num_ports; i++) 772 priv->port[i + 1].tmp_type = 0; 773 774 err = mlx4_change_port_types(mdev, new_types); 775 776 out: 777 mlx4_start_sense(mdev); 778 mutex_unlock(&priv->port_mutex); 779 return err ? err : count; 780 } 781 782 enum ibta_mtu { 783 IB_MTU_256 = 1, 784 IB_MTU_512 = 2, 785 IB_MTU_1024 = 3, 786 IB_MTU_2048 = 4, 787 IB_MTU_4096 = 5 788 }; 789 790 static inline int int_to_ibta_mtu(int mtu) 791 { 792 switch (mtu) { 793 case 256: return IB_MTU_256; 794 case 512: return IB_MTU_512; 795 case 1024: return IB_MTU_1024; 796 case 2048: return IB_MTU_2048; 797 case 4096: return IB_MTU_4096; 798 default: return -1; 799 } 800 } 801 802 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 803 { 804 switch (mtu) { 805 case IB_MTU_256: return 256; 806 case IB_MTU_512: return 512; 807 case IB_MTU_1024: return 1024; 808 case IB_MTU_2048: return 2048; 809 case IB_MTU_4096: return 4096; 810 default: return -1; 811 } 812 } 813 814 static ssize_t show_port_ib_mtu(struct device *dev, 815 struct device_attribute *attr, 816 char *buf) 817 { 818 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 819 port_mtu_attr); 820 struct mlx4_dev *mdev = info->dev; 821 822 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 823 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 824 825 sprintf(buf, "%d\n", 826 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 827 return strlen(buf); 828 } 829 830 static ssize_t set_port_ib_mtu(struct device *dev, 831 struct device_attribute *attr, 832 const char *buf, size_t count) 833 { 834 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 835 port_mtu_attr); 836 struct mlx4_dev *mdev = info->dev; 837 struct mlx4_priv *priv = mlx4_priv(mdev); 838 int err, port, mtu, ibta_mtu = -1; 839 840 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 841 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 842 return -EINVAL; 843 } 844 845 err = kstrtoint(buf, 0, &mtu); 846 if (!err) 847 ibta_mtu = int_to_ibta_mtu(mtu); 848 849 if (err || ibta_mtu < 0) { 850 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 851 return -EINVAL; 852 } 853 854 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 855 856 mlx4_stop_sense(mdev); 857 mutex_lock(&priv->port_mutex); 858 mlx4_unregister_device(mdev); 859 for (port = 1; port <= mdev->caps.num_ports; port++) { 860 mlx4_CLOSE_PORT(mdev, port); 861 err = mlx4_SET_PORT(mdev, port, -1); 862 if (err) { 863 mlx4_err(mdev, "Failed to set port %d, " 864 "aborting\n", port); 865 goto err_set_port; 866 } 867 } 868 err = mlx4_register_device(mdev); 869 err_set_port: 870 mutex_unlock(&priv->port_mutex); 871 mlx4_start_sense(mdev); 872 return err ? err : count; 873 } 874 875 static int mlx4_load_fw(struct mlx4_dev *dev) 876 { 877 struct mlx4_priv *priv = mlx4_priv(dev); 878 int err; 879 880 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 881 GFP_HIGHUSER | __GFP_NOWARN, 0); 882 if (!priv->fw.fw_icm) { 883 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); 884 return -ENOMEM; 885 } 886 887 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 888 if (err) { 889 mlx4_err(dev, "MAP_FA command failed, aborting.\n"); 890 goto err_free; 891 } 892 893 err = mlx4_RUN_FW(dev); 894 if (err) { 895 mlx4_err(dev, "RUN_FW command failed, aborting.\n"); 896 goto err_unmap_fa; 897 } 898 899 return 0; 900 901 err_unmap_fa: 902 mlx4_UNMAP_FA(dev); 903 904 err_free: 905 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 906 return err; 907 } 908 909 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 910 int cmpt_entry_sz) 911 { 912 struct mlx4_priv *priv = mlx4_priv(dev); 913 int err; 914 int num_eqs; 915 916 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 917 cmpt_base + 918 ((u64) (MLX4_CMPT_TYPE_QP * 919 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 920 cmpt_entry_sz, dev->caps.num_qps, 921 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 922 0, 0); 923 if (err) 924 goto err; 925 926 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 927 cmpt_base + 928 ((u64) (MLX4_CMPT_TYPE_SRQ * 929 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 930 cmpt_entry_sz, dev->caps.num_srqs, 931 dev->caps.reserved_srqs, 0, 0); 932 if (err) 933 goto err_qp; 934 935 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 936 cmpt_base + 937 ((u64) (MLX4_CMPT_TYPE_CQ * 938 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 939 cmpt_entry_sz, dev->caps.num_cqs, 940 dev->caps.reserved_cqs, 0, 0); 941 if (err) 942 goto err_srq; 943 944 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 945 dev->caps.num_eqs; 946 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 947 cmpt_base + 948 ((u64) (MLX4_CMPT_TYPE_EQ * 949 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 950 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 951 if (err) 952 goto err_cq; 953 954 return 0; 955 956 err_cq: 957 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 958 959 err_srq: 960 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 961 962 err_qp: 963 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 964 965 err: 966 return err; 967 } 968 969 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 970 struct mlx4_init_hca_param *init_hca, u64 icm_size) 971 { 972 struct mlx4_priv *priv = mlx4_priv(dev); 973 u64 aux_pages; 974 int num_eqs; 975 int err; 976 977 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 978 if (err) { 979 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); 980 return err; 981 } 982 983 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", 984 (unsigned long long) icm_size >> 10, 985 (unsigned long long) aux_pages << 2); 986 987 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 988 GFP_HIGHUSER | __GFP_NOWARN, 0); 989 if (!priv->fw.aux_icm) { 990 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); 991 return -ENOMEM; 992 } 993 994 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 995 if (err) { 996 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); 997 goto err_free_aux; 998 } 999 1000 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1001 if (err) { 1002 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); 1003 goto err_unmap_aux; 1004 } 1005 1006 1007 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 1008 dev->caps.num_eqs; 1009 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1010 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1011 num_eqs, num_eqs, 0, 0); 1012 if (err) { 1013 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); 1014 goto err_unmap_cmpt; 1015 } 1016 1017 /* 1018 * Reserved MTT entries must be aligned up to a cacheline 1019 * boundary, since the FW will write to them, while the driver 1020 * writes to all other MTT entries. (The variable 1021 * dev->caps.mtt_entry_sz below is really the MTT segment 1022 * size, not the raw entry size) 1023 */ 1024 dev->caps.reserved_mtts = 1025 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1026 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1027 1028 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1029 init_hca->mtt_base, 1030 dev->caps.mtt_entry_sz, 1031 dev->caps.num_mtts, 1032 dev->caps.reserved_mtts, 1, 0); 1033 if (err) { 1034 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); 1035 goto err_unmap_eq; 1036 } 1037 1038 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1039 init_hca->dmpt_base, 1040 dev_cap->dmpt_entry_sz, 1041 dev->caps.num_mpts, 1042 dev->caps.reserved_mrws, 1, 1); 1043 if (err) { 1044 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); 1045 goto err_unmap_mtt; 1046 } 1047 1048 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1049 init_hca->qpc_base, 1050 dev_cap->qpc_entry_sz, 1051 dev->caps.num_qps, 1052 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1053 0, 0); 1054 if (err) { 1055 mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); 1056 goto err_unmap_dmpt; 1057 } 1058 1059 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1060 init_hca->auxc_base, 1061 dev_cap->aux_entry_sz, 1062 dev->caps.num_qps, 1063 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1064 0, 0); 1065 if (err) { 1066 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); 1067 goto err_unmap_qp; 1068 } 1069 1070 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1071 init_hca->altc_base, 1072 dev_cap->altc_entry_sz, 1073 dev->caps.num_qps, 1074 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1075 0, 0); 1076 if (err) { 1077 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); 1078 goto err_unmap_auxc; 1079 } 1080 1081 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1082 init_hca->rdmarc_base, 1083 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1084 dev->caps.num_qps, 1085 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1086 0, 0); 1087 if (err) { 1088 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1089 goto err_unmap_altc; 1090 } 1091 1092 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1093 init_hca->cqc_base, 1094 dev_cap->cqc_entry_sz, 1095 dev->caps.num_cqs, 1096 dev->caps.reserved_cqs, 0, 0); 1097 if (err) { 1098 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); 1099 goto err_unmap_rdmarc; 1100 } 1101 1102 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1103 init_hca->srqc_base, 1104 dev_cap->srq_entry_sz, 1105 dev->caps.num_srqs, 1106 dev->caps.reserved_srqs, 0, 0); 1107 if (err) { 1108 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); 1109 goto err_unmap_cq; 1110 } 1111 1112 /* 1113 * For flow steering device managed mode it is required to use 1114 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1115 * required, but for simplicity just map the whole multicast 1116 * group table now. The table isn't very big and it's a lot 1117 * easier than trying to track ref counts. 1118 */ 1119 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1120 init_hca->mc_base, 1121 mlx4_get_mgm_entry_size(dev), 1122 dev->caps.num_mgms + dev->caps.num_amgms, 1123 dev->caps.num_mgms + dev->caps.num_amgms, 1124 0, 0); 1125 if (err) { 1126 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); 1127 goto err_unmap_srq; 1128 } 1129 1130 return 0; 1131 1132 err_unmap_srq: 1133 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1134 1135 err_unmap_cq: 1136 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1137 1138 err_unmap_rdmarc: 1139 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1140 1141 err_unmap_altc: 1142 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1143 1144 err_unmap_auxc: 1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1146 1147 err_unmap_qp: 1148 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1149 1150 err_unmap_dmpt: 1151 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1152 1153 err_unmap_mtt: 1154 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1155 1156 err_unmap_eq: 1157 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1158 1159 err_unmap_cmpt: 1160 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1161 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1162 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1163 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1164 1165 err_unmap_aux: 1166 mlx4_UNMAP_ICM_AUX(dev); 1167 1168 err_free_aux: 1169 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1170 1171 return err; 1172 } 1173 1174 static void mlx4_free_icms(struct mlx4_dev *dev) 1175 { 1176 struct mlx4_priv *priv = mlx4_priv(dev); 1177 1178 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1179 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1180 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1182 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1183 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1184 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1185 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1186 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1187 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1188 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1189 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1190 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1191 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1192 1193 mlx4_UNMAP_ICM_AUX(dev); 1194 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1195 } 1196 1197 static void mlx4_slave_exit(struct mlx4_dev *dev) 1198 { 1199 struct mlx4_priv *priv = mlx4_priv(dev); 1200 1201 mutex_lock(&priv->cmd.slave_cmd_mutex); 1202 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1203 mlx4_warn(dev, "Failed to close slave function.\n"); 1204 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1205 } 1206 1207 static int map_bf_area(struct mlx4_dev *dev) 1208 { 1209 struct mlx4_priv *priv = mlx4_priv(dev); 1210 resource_size_t bf_start; 1211 resource_size_t bf_len; 1212 int err = 0; 1213 1214 if (!dev->caps.bf_reg_size) 1215 return -ENXIO; 1216 1217 bf_start = pci_resource_start(dev->pdev, 2) + 1218 (dev->caps.num_uars << PAGE_SHIFT); 1219 bf_len = pci_resource_len(dev->pdev, 2) - 1220 (dev->caps.num_uars << PAGE_SHIFT); 1221 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1222 if (!priv->bf_mapping) 1223 err = -ENOMEM; 1224 1225 return err; 1226 } 1227 1228 static void unmap_bf_area(struct mlx4_dev *dev) 1229 { 1230 if (mlx4_priv(dev)->bf_mapping) 1231 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1232 } 1233 1234 cycle_t mlx4_read_clock(struct mlx4_dev *dev) 1235 { 1236 u32 clockhi, clocklo, clockhi1; 1237 cycle_t cycles; 1238 int i; 1239 struct mlx4_priv *priv = mlx4_priv(dev); 1240 1241 for (i = 0; i < 10; i++) { 1242 clockhi = swab32(readl(priv->clock_mapping)); 1243 clocklo = swab32(readl(priv->clock_mapping + 4)); 1244 clockhi1 = swab32(readl(priv->clock_mapping)); 1245 if (clockhi == clockhi1) 1246 break; 1247 } 1248 1249 cycles = (u64) clockhi << 32 | (u64) clocklo; 1250 1251 return cycles; 1252 } 1253 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1254 1255 1256 static int map_internal_clock(struct mlx4_dev *dev) 1257 { 1258 struct mlx4_priv *priv = mlx4_priv(dev); 1259 1260 priv->clock_mapping = 1261 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + 1262 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1263 1264 if (!priv->clock_mapping) 1265 return -ENOMEM; 1266 1267 return 0; 1268 } 1269 1270 static void unmap_internal_clock(struct mlx4_dev *dev) 1271 { 1272 struct mlx4_priv *priv = mlx4_priv(dev); 1273 1274 if (priv->clock_mapping) 1275 iounmap(priv->clock_mapping); 1276 } 1277 1278 static void mlx4_close_hca(struct mlx4_dev *dev) 1279 { 1280 unmap_internal_clock(dev); 1281 unmap_bf_area(dev); 1282 if (mlx4_is_slave(dev)) 1283 mlx4_slave_exit(dev); 1284 else { 1285 mlx4_CLOSE_HCA(dev, 0); 1286 mlx4_free_icms(dev); 1287 mlx4_UNMAP_FA(dev); 1288 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1289 } 1290 } 1291 1292 static int mlx4_init_slave(struct mlx4_dev *dev) 1293 { 1294 struct mlx4_priv *priv = mlx4_priv(dev); 1295 u64 dma = (u64) priv->mfunc.vhcr_dma; 1296 int ret_from_reset = 0; 1297 u32 slave_read; 1298 u32 cmd_channel_ver; 1299 1300 mutex_lock(&priv->cmd.slave_cmd_mutex); 1301 priv->cmd.max_cmds = 1; 1302 mlx4_warn(dev, "Sending reset\n"); 1303 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1304 MLX4_COMM_TIME); 1305 /* if we are in the middle of flr the slave will try 1306 * NUM_OF_RESET_RETRIES times before leaving.*/ 1307 if (ret_from_reset) { 1308 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1309 mlx4_warn(dev, "slave is currently in the " 1310 "middle of FLR. Deferring probe.\n"); 1311 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1312 return -EPROBE_DEFER; 1313 } else 1314 goto err; 1315 } 1316 1317 /* check the driver version - the slave I/F revision 1318 * must match the master's */ 1319 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1320 cmd_channel_ver = mlx4_comm_get_version(); 1321 1322 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1323 MLX4_COMM_GET_IF_REV(slave_read)) { 1324 mlx4_err(dev, "slave driver version is not supported" 1325 " by the master\n"); 1326 goto err; 1327 } 1328 1329 mlx4_warn(dev, "Sending vhcr0\n"); 1330 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1331 MLX4_COMM_TIME)) 1332 goto err; 1333 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1334 MLX4_COMM_TIME)) 1335 goto err; 1336 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1337 MLX4_COMM_TIME)) 1338 goto err; 1339 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1340 goto err; 1341 1342 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1343 return 0; 1344 1345 err: 1346 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1347 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1348 return -EIO; 1349 } 1350 1351 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1352 { 1353 int i; 1354 1355 for (i = 1; i <= dev->caps.num_ports; i++) { 1356 dev->caps.gid_table_len[i] = 1; 1357 dev->caps.pkey_table_len[i] = 1358 dev->phys_caps.pkey_phys_table_len[i] - 1; 1359 } 1360 } 1361 1362 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1363 { 1364 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1365 1366 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1367 i++) { 1368 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1369 break; 1370 } 1371 1372 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1373 } 1374 1375 static void choose_steering_mode(struct mlx4_dev *dev, 1376 struct mlx4_dev_cap *dev_cap) 1377 { 1378 if (mlx4_log_num_mgm_entry_size == -1 && 1379 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1380 (!mlx4_is_mfunc(dev) || 1381 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) && 1382 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1383 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1384 dev->oper_log_mgm_entry_size = 1385 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1386 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1387 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1388 dev->caps.fs_log_max_ucast_qp_range_size = 1389 dev_cap->fs_log_max_ucast_qp_range_size; 1390 } else { 1391 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1392 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1393 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1394 else { 1395 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1396 1397 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1398 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1399 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags " 1400 "set to use B0 steering. Falling back to A0 steering mode.\n"); 1401 } 1402 dev->oper_log_mgm_entry_size = 1403 mlx4_log_num_mgm_entry_size > 0 ? 1404 mlx4_log_num_mgm_entry_size : 1405 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1406 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1407 } 1408 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, " 1409 "modparam log_num_mgm_entry_size = %d\n", 1410 mlx4_steering_mode_str(dev->caps.steering_mode), 1411 dev->oper_log_mgm_entry_size, 1412 mlx4_log_num_mgm_entry_size); 1413 } 1414 1415 static int mlx4_init_hca(struct mlx4_dev *dev) 1416 { 1417 struct mlx4_priv *priv = mlx4_priv(dev); 1418 struct mlx4_adapter adapter; 1419 struct mlx4_dev_cap dev_cap; 1420 struct mlx4_mod_stat_cfg mlx4_cfg; 1421 struct mlx4_profile profile; 1422 struct mlx4_init_hca_param init_hca; 1423 u64 icm_size; 1424 int err; 1425 1426 if (!mlx4_is_slave(dev)) { 1427 err = mlx4_QUERY_FW(dev); 1428 if (err) { 1429 if (err == -EACCES) 1430 mlx4_info(dev, "non-primary physical function, skipping.\n"); 1431 else 1432 mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); 1433 return err; 1434 } 1435 1436 err = mlx4_load_fw(dev); 1437 if (err) { 1438 mlx4_err(dev, "Failed to start FW, aborting.\n"); 1439 return err; 1440 } 1441 1442 mlx4_cfg.log_pg_sz_m = 1; 1443 mlx4_cfg.log_pg_sz = 0; 1444 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1445 if (err) 1446 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1447 1448 err = mlx4_dev_cap(dev, &dev_cap); 1449 if (err) { 1450 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 1451 goto err_stop_fw; 1452 } 1453 1454 choose_steering_mode(dev, &dev_cap); 1455 1456 if (mlx4_is_master(dev)) 1457 mlx4_parav_master_pf_caps(dev); 1458 1459 profile = default_profile; 1460 if (dev->caps.steering_mode == 1461 MLX4_STEERING_MODE_DEVICE_MANAGED) 1462 profile.num_mcg = MLX4_FS_NUM_MCG; 1463 1464 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 1465 &init_hca); 1466 if ((long long) icm_size < 0) { 1467 err = icm_size; 1468 goto err_stop_fw; 1469 } 1470 1471 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 1472 1473 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 1474 init_hca.uar_page_sz = PAGE_SHIFT - 12; 1475 init_hca.mw_enabled = 0; 1476 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 1477 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 1478 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 1479 1480 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 1481 if (err) 1482 goto err_stop_fw; 1483 1484 err = mlx4_INIT_HCA(dev, &init_hca); 1485 if (err) { 1486 mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); 1487 goto err_free_icm; 1488 } 1489 /* 1490 * If TS is supported by FW 1491 * read HCA frequency by QUERY_HCA command 1492 */ 1493 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1494 memset(&init_hca, 0, sizeof(init_hca)); 1495 err = mlx4_QUERY_HCA(dev, &init_hca); 1496 if (err) { 1497 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n"); 1498 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1499 } else { 1500 dev->caps.hca_core_clock = 1501 init_hca.hca_core_clock; 1502 } 1503 1504 /* In case we got HCA frequency 0 - disable timestamping 1505 * to avoid dividing by zero 1506 */ 1507 if (!dev->caps.hca_core_clock) { 1508 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1509 mlx4_err(dev, 1510 "HCA frequency is 0. Timestamping is not supported."); 1511 } else if (map_internal_clock(dev)) { 1512 /* 1513 * Map internal clock, 1514 * in case of failure disable timestamping 1515 */ 1516 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1517 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n"); 1518 } 1519 } 1520 } else { 1521 err = mlx4_init_slave(dev); 1522 if (err) { 1523 if (err != -EPROBE_DEFER) 1524 mlx4_err(dev, "Failed to initialize slave\n"); 1525 return err; 1526 } 1527 1528 err = mlx4_slave_cap(dev); 1529 if (err) { 1530 mlx4_err(dev, "Failed to obtain slave caps\n"); 1531 goto err_close; 1532 } 1533 } 1534 1535 if (map_bf_area(dev)) 1536 mlx4_dbg(dev, "Failed to map blue flame area\n"); 1537 1538 /*Only the master set the ports, all the rest got it from it.*/ 1539 if (!mlx4_is_slave(dev)) 1540 mlx4_set_port_mask(dev); 1541 1542 err = mlx4_QUERY_ADAPTER(dev, &adapter); 1543 if (err) { 1544 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); 1545 goto unmap_bf; 1546 } 1547 1548 priv->eq_table.inta_pin = adapter.inta_pin; 1549 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 1550 1551 return 0; 1552 1553 unmap_bf: 1554 unmap_internal_clock(dev); 1555 unmap_bf_area(dev); 1556 1557 err_close: 1558 if (mlx4_is_slave(dev)) 1559 mlx4_slave_exit(dev); 1560 else 1561 mlx4_CLOSE_HCA(dev, 0); 1562 1563 err_free_icm: 1564 if (!mlx4_is_slave(dev)) 1565 mlx4_free_icms(dev); 1566 1567 err_stop_fw: 1568 if (!mlx4_is_slave(dev)) { 1569 mlx4_UNMAP_FA(dev); 1570 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1571 } 1572 return err; 1573 } 1574 1575 static int mlx4_init_counters_table(struct mlx4_dev *dev) 1576 { 1577 struct mlx4_priv *priv = mlx4_priv(dev); 1578 int nent; 1579 1580 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1581 return -ENOENT; 1582 1583 nent = dev->caps.max_counters; 1584 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 1585 } 1586 1587 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 1588 { 1589 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 1590 } 1591 1592 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1593 { 1594 struct mlx4_priv *priv = mlx4_priv(dev); 1595 1596 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 1597 return -ENOENT; 1598 1599 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 1600 if (*idx == -1) 1601 return -ENOMEM; 1602 1603 return 0; 1604 } 1605 1606 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 1607 { 1608 u64 out_param; 1609 int err; 1610 1611 if (mlx4_is_mfunc(dev)) { 1612 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 1613 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 1614 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1615 if (!err) 1616 *idx = get_param_l(&out_param); 1617 1618 return err; 1619 } 1620 return __mlx4_counter_alloc(dev, idx); 1621 } 1622 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 1623 1624 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1625 { 1626 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx); 1627 return; 1628 } 1629 1630 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 1631 { 1632 u64 in_param = 0; 1633 1634 if (mlx4_is_mfunc(dev)) { 1635 set_param_l(&in_param, idx); 1636 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 1637 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 1638 MLX4_CMD_WRAPPED); 1639 return; 1640 } 1641 __mlx4_counter_free(dev, idx); 1642 } 1643 EXPORT_SYMBOL_GPL(mlx4_counter_free); 1644 1645 static int mlx4_setup_hca(struct mlx4_dev *dev) 1646 { 1647 struct mlx4_priv *priv = mlx4_priv(dev); 1648 int err; 1649 int port; 1650 __be32 ib_port_default_caps; 1651 1652 err = mlx4_init_uar_table(dev); 1653 if (err) { 1654 mlx4_err(dev, "Failed to initialize " 1655 "user access region table, aborting.\n"); 1656 return err; 1657 } 1658 1659 err = mlx4_uar_alloc(dev, &priv->driver_uar); 1660 if (err) { 1661 mlx4_err(dev, "Failed to allocate driver access region, " 1662 "aborting.\n"); 1663 goto err_uar_table_free; 1664 } 1665 1666 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 1667 if (!priv->kar) { 1668 mlx4_err(dev, "Couldn't map kernel access region, " 1669 "aborting.\n"); 1670 err = -ENOMEM; 1671 goto err_uar_free; 1672 } 1673 1674 err = mlx4_init_pd_table(dev); 1675 if (err) { 1676 mlx4_err(dev, "Failed to initialize " 1677 "protection domain table, aborting.\n"); 1678 goto err_kar_unmap; 1679 } 1680 1681 err = mlx4_init_xrcd_table(dev); 1682 if (err) { 1683 mlx4_err(dev, "Failed to initialize " 1684 "reliable connection domain table, aborting.\n"); 1685 goto err_pd_table_free; 1686 } 1687 1688 err = mlx4_init_mr_table(dev); 1689 if (err) { 1690 mlx4_err(dev, "Failed to initialize " 1691 "memory region table, aborting.\n"); 1692 goto err_xrcd_table_free; 1693 } 1694 1695 if (!mlx4_is_slave(dev)) { 1696 err = mlx4_init_mcg_table(dev); 1697 if (err) { 1698 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n"); 1699 goto err_mr_table_free; 1700 } 1701 } 1702 1703 err = mlx4_init_eq_table(dev); 1704 if (err) { 1705 mlx4_err(dev, "Failed to initialize " 1706 "event queue table, aborting.\n"); 1707 goto err_mcg_table_free; 1708 } 1709 1710 err = mlx4_cmd_use_events(dev); 1711 if (err) { 1712 mlx4_err(dev, "Failed to switch to event-driven " 1713 "firmware commands, aborting.\n"); 1714 goto err_eq_table_free; 1715 } 1716 1717 err = mlx4_NOP(dev); 1718 if (err) { 1719 if (dev->flags & MLX4_FLAG_MSI_X) { 1720 mlx4_warn(dev, "NOP command failed to generate MSI-X " 1721 "interrupt IRQ %d).\n", 1722 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1723 mlx4_warn(dev, "Trying again without MSI-X.\n"); 1724 } else { 1725 mlx4_err(dev, "NOP command failed to generate interrupt " 1726 "(IRQ %d), aborting.\n", 1727 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 1728 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 1729 } 1730 1731 goto err_cmd_poll; 1732 } 1733 1734 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 1735 1736 err = mlx4_init_cq_table(dev); 1737 if (err) { 1738 mlx4_err(dev, "Failed to initialize " 1739 "completion queue table, aborting.\n"); 1740 goto err_cmd_poll; 1741 } 1742 1743 err = mlx4_init_srq_table(dev); 1744 if (err) { 1745 mlx4_err(dev, "Failed to initialize " 1746 "shared receive queue table, aborting.\n"); 1747 goto err_cq_table_free; 1748 } 1749 1750 err = mlx4_init_qp_table(dev); 1751 if (err) { 1752 mlx4_err(dev, "Failed to initialize " 1753 "queue pair table, aborting.\n"); 1754 goto err_srq_table_free; 1755 } 1756 1757 err = mlx4_init_counters_table(dev); 1758 if (err && err != -ENOENT) { 1759 mlx4_err(dev, "Failed to initialize counters table, aborting.\n"); 1760 goto err_qp_table_free; 1761 } 1762 1763 if (!mlx4_is_slave(dev)) { 1764 for (port = 1; port <= dev->caps.num_ports; port++) { 1765 ib_port_default_caps = 0; 1766 err = mlx4_get_port_ib_caps(dev, port, 1767 &ib_port_default_caps); 1768 if (err) 1769 mlx4_warn(dev, "failed to get port %d default " 1770 "ib capabilities (%d). Continuing " 1771 "with caps = 0\n", port, err); 1772 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 1773 1774 /* initialize per-slave default ib port capabilities */ 1775 if (mlx4_is_master(dev)) { 1776 int i; 1777 for (i = 0; i < dev->num_slaves; i++) { 1778 if (i == mlx4_master_func_num(dev)) 1779 continue; 1780 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 1781 ib_port_default_caps; 1782 } 1783 } 1784 1785 if (mlx4_is_mfunc(dev)) 1786 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 1787 else 1788 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 1789 1790 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 1791 dev->caps.pkey_table_len[port] : -1); 1792 if (err) { 1793 mlx4_err(dev, "Failed to set port %d, aborting\n", 1794 port); 1795 goto err_counters_table_free; 1796 } 1797 } 1798 } 1799 1800 return 0; 1801 1802 err_counters_table_free: 1803 mlx4_cleanup_counters_table(dev); 1804 1805 err_qp_table_free: 1806 mlx4_cleanup_qp_table(dev); 1807 1808 err_srq_table_free: 1809 mlx4_cleanup_srq_table(dev); 1810 1811 err_cq_table_free: 1812 mlx4_cleanup_cq_table(dev); 1813 1814 err_cmd_poll: 1815 mlx4_cmd_use_polling(dev); 1816 1817 err_eq_table_free: 1818 mlx4_cleanup_eq_table(dev); 1819 1820 err_mcg_table_free: 1821 if (!mlx4_is_slave(dev)) 1822 mlx4_cleanup_mcg_table(dev); 1823 1824 err_mr_table_free: 1825 mlx4_cleanup_mr_table(dev); 1826 1827 err_xrcd_table_free: 1828 mlx4_cleanup_xrcd_table(dev); 1829 1830 err_pd_table_free: 1831 mlx4_cleanup_pd_table(dev); 1832 1833 err_kar_unmap: 1834 iounmap(priv->kar); 1835 1836 err_uar_free: 1837 mlx4_uar_free(dev, &priv->driver_uar); 1838 1839 err_uar_table_free: 1840 mlx4_cleanup_uar_table(dev); 1841 return err; 1842 } 1843 1844 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 1845 { 1846 struct mlx4_priv *priv = mlx4_priv(dev); 1847 struct msix_entry *entries; 1848 int nreq = min_t(int, dev->caps.num_ports * 1849 min_t(int, netif_get_num_default_rss_queues() + 1, 1850 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); 1851 int err; 1852 int i; 1853 1854 if (msi_x) { 1855 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 1856 nreq); 1857 1858 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 1859 if (!entries) 1860 goto no_msi; 1861 1862 for (i = 0; i < nreq; ++i) 1863 entries[i].entry = i; 1864 1865 retry: 1866 err = pci_enable_msix(dev->pdev, entries, nreq); 1867 if (err) { 1868 /* Try again if at least 2 vectors are available */ 1869 if (err > 1) { 1870 mlx4_info(dev, "Requested %d vectors, " 1871 "but only %d MSI-X vectors available, " 1872 "trying again\n", nreq, err); 1873 nreq = err; 1874 goto retry; 1875 } 1876 kfree(entries); 1877 goto no_msi; 1878 } 1879 1880 if (nreq < 1881 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { 1882 /*Working in legacy mode , all EQ's shared*/ 1883 dev->caps.comp_pool = 0; 1884 dev->caps.num_comp_vectors = nreq - 1; 1885 } else { 1886 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 1887 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 1888 } 1889 for (i = 0; i < nreq; ++i) 1890 priv->eq_table.eq[i].irq = entries[i].vector; 1891 1892 dev->flags |= MLX4_FLAG_MSI_X; 1893 1894 kfree(entries); 1895 return; 1896 } 1897 1898 no_msi: 1899 dev->caps.num_comp_vectors = 1; 1900 dev->caps.comp_pool = 0; 1901 1902 for (i = 0; i < 2; ++i) 1903 priv->eq_table.eq[i].irq = dev->pdev->irq; 1904 } 1905 1906 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 1907 { 1908 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 1909 int err = 0; 1910 1911 info->dev = dev; 1912 info->port = port; 1913 if (!mlx4_is_slave(dev)) { 1914 mlx4_init_mac_table(dev, &info->mac_table); 1915 mlx4_init_vlan_table(dev, &info->vlan_table); 1916 info->base_qpn = mlx4_get_base_qpn(dev, port); 1917 } 1918 1919 sprintf(info->dev_name, "mlx4_port%d", port); 1920 info->port_attr.attr.name = info->dev_name; 1921 if (mlx4_is_mfunc(dev)) 1922 info->port_attr.attr.mode = S_IRUGO; 1923 else { 1924 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 1925 info->port_attr.store = set_port_type; 1926 } 1927 info->port_attr.show = show_port_type; 1928 sysfs_attr_init(&info->port_attr.attr); 1929 1930 err = device_create_file(&dev->pdev->dev, &info->port_attr); 1931 if (err) { 1932 mlx4_err(dev, "Failed to create file for port %d\n", port); 1933 info->port = -1; 1934 } 1935 1936 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 1937 info->port_mtu_attr.attr.name = info->dev_mtu_name; 1938 if (mlx4_is_mfunc(dev)) 1939 info->port_mtu_attr.attr.mode = S_IRUGO; 1940 else { 1941 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 1942 info->port_mtu_attr.store = set_port_ib_mtu; 1943 } 1944 info->port_mtu_attr.show = show_port_ib_mtu; 1945 sysfs_attr_init(&info->port_mtu_attr.attr); 1946 1947 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 1948 if (err) { 1949 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 1950 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1951 info->port = -1; 1952 } 1953 1954 return err; 1955 } 1956 1957 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 1958 { 1959 if (info->port < 0) 1960 return; 1961 1962 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 1963 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 1964 } 1965 1966 static int mlx4_init_steering(struct mlx4_dev *dev) 1967 { 1968 struct mlx4_priv *priv = mlx4_priv(dev); 1969 int num_entries = dev->caps.num_ports; 1970 int i, j; 1971 1972 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 1973 if (!priv->steer) 1974 return -ENOMEM; 1975 1976 for (i = 0; i < num_entries; i++) 1977 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1978 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 1979 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 1980 } 1981 return 0; 1982 } 1983 1984 static void mlx4_clear_steering(struct mlx4_dev *dev) 1985 { 1986 struct mlx4_priv *priv = mlx4_priv(dev); 1987 struct mlx4_steer_index *entry, *tmp_entry; 1988 struct mlx4_promisc_qp *pqp, *tmp_pqp; 1989 int num_entries = dev->caps.num_ports; 1990 int i, j; 1991 1992 for (i = 0; i < num_entries; i++) { 1993 for (j = 0; j < MLX4_NUM_STEERS; j++) { 1994 list_for_each_entry_safe(pqp, tmp_pqp, 1995 &priv->steer[i].promisc_qps[j], 1996 list) { 1997 list_del(&pqp->list); 1998 kfree(pqp); 1999 } 2000 list_for_each_entry_safe(entry, tmp_entry, 2001 &priv->steer[i].steer_entries[j], 2002 list) { 2003 list_del(&entry->list); 2004 list_for_each_entry_safe(pqp, tmp_pqp, 2005 &entry->duplicates, 2006 list) { 2007 list_del(&pqp->list); 2008 kfree(pqp); 2009 } 2010 kfree(entry); 2011 } 2012 } 2013 } 2014 kfree(priv->steer); 2015 } 2016 2017 static int extended_func_num(struct pci_dev *pdev) 2018 { 2019 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 2020 } 2021 2022 #define MLX4_OWNER_BASE 0x8069c 2023 #define MLX4_OWNER_SIZE 4 2024 2025 static int mlx4_get_ownership(struct mlx4_dev *dev) 2026 { 2027 void __iomem *owner; 2028 u32 ret; 2029 2030 if (pci_channel_offline(dev->pdev)) 2031 return -EIO; 2032 2033 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2034 MLX4_OWNER_SIZE); 2035 if (!owner) { 2036 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2037 return -ENOMEM; 2038 } 2039 2040 ret = readl(owner); 2041 iounmap(owner); 2042 return (int) !!ret; 2043 } 2044 2045 static void mlx4_free_ownership(struct mlx4_dev *dev) 2046 { 2047 void __iomem *owner; 2048 2049 if (pci_channel_offline(dev->pdev)) 2050 return; 2051 2052 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2053 MLX4_OWNER_SIZE); 2054 if (!owner) { 2055 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2056 return; 2057 } 2058 writel(0, owner); 2059 msleep(1000); 2060 iounmap(owner); 2061 } 2062 2063 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) 2064 { 2065 struct mlx4_priv *priv; 2066 struct mlx4_dev *dev; 2067 int err; 2068 int port; 2069 2070 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 2071 2072 err = pci_enable_device(pdev); 2073 if (err) { 2074 dev_err(&pdev->dev, "Cannot enable PCI device, " 2075 "aborting.\n"); 2076 return err; 2077 } 2078 if (num_vfs > MLX4_MAX_NUM_VF) { 2079 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n", 2080 num_vfs, MLX4_MAX_NUM_VF); 2081 return -EINVAL; 2082 } 2083 2084 if (num_vfs < 0) { 2085 pr_err("num_vfs module parameter cannot be negative\n"); 2086 return -EINVAL; 2087 } 2088 /* 2089 * Check for BARs. 2090 */ 2091 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 2092 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2093 dev_err(&pdev->dev, "Missing DCS, aborting." 2094 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 2095 pci_dev_data, pci_resource_flags(pdev, 0)); 2096 err = -ENODEV; 2097 goto err_disable_pdev; 2098 } 2099 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 2100 dev_err(&pdev->dev, "Missing UAR, aborting.\n"); 2101 err = -ENODEV; 2102 goto err_disable_pdev; 2103 } 2104 2105 err = pci_request_regions(pdev, DRV_NAME); 2106 if (err) { 2107 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 2108 goto err_disable_pdev; 2109 } 2110 2111 pci_set_master(pdev); 2112 2113 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 2114 if (err) { 2115 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); 2116 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2117 if (err) { 2118 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); 2119 goto err_release_regions; 2120 } 2121 } 2122 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2123 if (err) { 2124 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " 2125 "consistent PCI DMA mask.\n"); 2126 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2127 if (err) { 2128 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " 2129 "aborting.\n"); 2130 goto err_release_regions; 2131 } 2132 } 2133 2134 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 2135 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 2136 2137 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 2138 if (!priv) { 2139 err = -ENOMEM; 2140 goto err_release_regions; 2141 } 2142 2143 dev = &priv->dev; 2144 dev->pdev = pdev; 2145 INIT_LIST_HEAD(&priv->ctx_list); 2146 spin_lock_init(&priv->ctx_lock); 2147 2148 mutex_init(&priv->port_mutex); 2149 2150 INIT_LIST_HEAD(&priv->pgdir_list); 2151 mutex_init(&priv->pgdir_mutex); 2152 2153 INIT_LIST_HEAD(&priv->bf_list); 2154 mutex_init(&priv->bf_mutex); 2155 2156 dev->rev_id = pdev->revision; 2157 /* Detect if this device is a virtual function */ 2158 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2159 /* When acting as pf, we normally skip vfs unless explicitly 2160 * requested to probe them. */ 2161 if (num_vfs && extended_func_num(pdev) > probe_vf) { 2162 mlx4_warn(dev, "Skipping virtual function:%d\n", 2163 extended_func_num(pdev)); 2164 err = -ENODEV; 2165 goto err_free_dev; 2166 } 2167 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 2168 dev->flags |= MLX4_FLAG_SLAVE; 2169 } else { 2170 /* We reset the device and enable SRIOV only for physical 2171 * devices. Try to claim ownership on the device; 2172 * if already taken, skip -- do not allow multiple PFs */ 2173 err = mlx4_get_ownership(dev); 2174 if (err) { 2175 if (err < 0) 2176 goto err_free_dev; 2177 else { 2178 mlx4_warn(dev, "Multiple PFs not yet supported." 2179 " Skipping PF.\n"); 2180 err = -EINVAL; 2181 goto err_free_dev; 2182 } 2183 } 2184 2185 if (num_vfs) { 2186 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs); 2187 err = pci_enable_sriov(pdev, num_vfs); 2188 if (err) { 2189 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n", 2190 err); 2191 err = 0; 2192 } else { 2193 mlx4_warn(dev, "Running in master mode\n"); 2194 dev->flags |= MLX4_FLAG_SRIOV | 2195 MLX4_FLAG_MASTER; 2196 dev->num_vfs = num_vfs; 2197 } 2198 } 2199 2200 atomic_set(&priv->opreq_count, 0); 2201 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 2202 2203 /* 2204 * Now reset the HCA before we touch the PCI capabilities or 2205 * attempt a firmware command, since a boot ROM may have left 2206 * the HCA in an undefined state. 2207 */ 2208 err = mlx4_reset(dev); 2209 if (err) { 2210 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 2211 goto err_rel_own; 2212 } 2213 } 2214 2215 slave_start: 2216 err = mlx4_cmd_init(dev); 2217 if (err) { 2218 mlx4_err(dev, "Failed to init command interface, aborting.\n"); 2219 goto err_sriov; 2220 } 2221 2222 /* In slave functions, the communication channel must be initialized 2223 * before posting commands. Also, init num_slaves before calling 2224 * mlx4_init_hca */ 2225 if (mlx4_is_mfunc(dev)) { 2226 if (mlx4_is_master(dev)) 2227 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2228 else { 2229 dev->num_slaves = 0; 2230 err = mlx4_multi_func_init(dev); 2231 if (err) { 2232 mlx4_err(dev, "Failed to init slave mfunc" 2233 " interface, aborting.\n"); 2234 goto err_cmd; 2235 } 2236 } 2237 } 2238 2239 err = mlx4_init_hca(dev); 2240 if (err) { 2241 if (err == -EACCES) { 2242 /* Not primary Physical function 2243 * Running in slave mode */ 2244 mlx4_cmd_cleanup(dev); 2245 dev->flags |= MLX4_FLAG_SLAVE; 2246 dev->flags &= ~MLX4_FLAG_MASTER; 2247 goto slave_start; 2248 } else 2249 goto err_mfunc; 2250 } 2251 2252 /* In master functions, the communication channel must be initialized 2253 * after obtaining its address from fw */ 2254 if (mlx4_is_master(dev)) { 2255 err = mlx4_multi_func_init(dev); 2256 if (err) { 2257 mlx4_err(dev, "Failed to init master mfunc" 2258 "interface, aborting.\n"); 2259 goto err_close; 2260 } 2261 } 2262 2263 err = mlx4_alloc_eq_table(dev); 2264 if (err) 2265 goto err_master_mfunc; 2266 2267 priv->msix_ctl.pool_bm = 0; 2268 mutex_init(&priv->msix_ctl.pool_lock); 2269 2270 mlx4_enable_msi_x(dev); 2271 if ((mlx4_is_mfunc(dev)) && 2272 !(dev->flags & MLX4_FLAG_MSI_X)) { 2273 err = -ENOSYS; 2274 mlx4_err(dev, "INTx is not supported in multi-function mode." 2275 " aborting.\n"); 2276 goto err_free_eq; 2277 } 2278 2279 if (!mlx4_is_slave(dev)) { 2280 err = mlx4_init_steering(dev); 2281 if (err) 2282 goto err_free_eq; 2283 } 2284 2285 err = mlx4_setup_hca(dev); 2286 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 2287 !mlx4_is_mfunc(dev)) { 2288 dev->flags &= ~MLX4_FLAG_MSI_X; 2289 dev->caps.num_comp_vectors = 1; 2290 dev->caps.comp_pool = 0; 2291 pci_disable_msix(pdev); 2292 err = mlx4_setup_hca(dev); 2293 } 2294 2295 if (err) 2296 goto err_steer; 2297 2298 for (port = 1; port <= dev->caps.num_ports; port++) { 2299 err = mlx4_init_port_info(dev, port); 2300 if (err) 2301 goto err_port; 2302 } 2303 2304 err = mlx4_register_device(dev); 2305 if (err) 2306 goto err_port; 2307 2308 mlx4_sense_init(dev); 2309 mlx4_start_sense(dev); 2310 2311 priv->pci_dev_data = pci_dev_data; 2312 pci_set_drvdata(pdev, dev); 2313 2314 return 0; 2315 2316 err_port: 2317 for (--port; port >= 1; --port) 2318 mlx4_cleanup_port_info(&priv->port[port]); 2319 2320 mlx4_cleanup_counters_table(dev); 2321 mlx4_cleanup_qp_table(dev); 2322 mlx4_cleanup_srq_table(dev); 2323 mlx4_cleanup_cq_table(dev); 2324 mlx4_cmd_use_polling(dev); 2325 mlx4_cleanup_eq_table(dev); 2326 mlx4_cleanup_mcg_table(dev); 2327 mlx4_cleanup_mr_table(dev); 2328 mlx4_cleanup_xrcd_table(dev); 2329 mlx4_cleanup_pd_table(dev); 2330 mlx4_cleanup_uar_table(dev); 2331 2332 err_steer: 2333 if (!mlx4_is_slave(dev)) 2334 mlx4_clear_steering(dev); 2335 2336 err_free_eq: 2337 mlx4_free_eq_table(dev); 2338 2339 err_master_mfunc: 2340 if (mlx4_is_master(dev)) 2341 mlx4_multi_func_cleanup(dev); 2342 2343 err_close: 2344 if (dev->flags & MLX4_FLAG_MSI_X) 2345 pci_disable_msix(pdev); 2346 2347 mlx4_close_hca(dev); 2348 2349 err_mfunc: 2350 if (mlx4_is_slave(dev)) 2351 mlx4_multi_func_cleanup(dev); 2352 2353 err_cmd: 2354 mlx4_cmd_cleanup(dev); 2355 2356 err_sriov: 2357 if (dev->flags & MLX4_FLAG_SRIOV) 2358 pci_disable_sriov(pdev); 2359 2360 err_rel_own: 2361 if (!mlx4_is_slave(dev)) 2362 mlx4_free_ownership(dev); 2363 2364 err_free_dev: 2365 kfree(priv); 2366 2367 err_release_regions: 2368 pci_release_regions(pdev); 2369 2370 err_disable_pdev: 2371 pci_disable_device(pdev); 2372 pci_set_drvdata(pdev, NULL); 2373 return err; 2374 } 2375 2376 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 2377 { 2378 printk_once(KERN_INFO "%s", mlx4_version); 2379 2380 return __mlx4_init_one(pdev, id->driver_data); 2381 } 2382 2383 static void mlx4_remove_one(struct pci_dev *pdev) 2384 { 2385 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2386 struct mlx4_priv *priv = mlx4_priv(dev); 2387 int p; 2388 2389 if (dev) { 2390 /* in SRIOV it is not allowed to unload the pf's 2391 * driver while there are alive vf's */ 2392 if (mlx4_is_master(dev)) { 2393 if (mlx4_how_many_lives_vf(dev)) 2394 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); 2395 } 2396 mlx4_stop_sense(dev); 2397 mlx4_unregister_device(dev); 2398 2399 for (p = 1; p <= dev->caps.num_ports; p++) { 2400 mlx4_cleanup_port_info(&priv->port[p]); 2401 mlx4_CLOSE_PORT(dev, p); 2402 } 2403 2404 if (mlx4_is_master(dev)) 2405 mlx4_free_resource_tracker(dev, 2406 RES_TR_FREE_SLAVES_ONLY); 2407 2408 mlx4_cleanup_counters_table(dev); 2409 mlx4_cleanup_qp_table(dev); 2410 mlx4_cleanup_srq_table(dev); 2411 mlx4_cleanup_cq_table(dev); 2412 mlx4_cmd_use_polling(dev); 2413 mlx4_cleanup_eq_table(dev); 2414 mlx4_cleanup_mcg_table(dev); 2415 mlx4_cleanup_mr_table(dev); 2416 mlx4_cleanup_xrcd_table(dev); 2417 mlx4_cleanup_pd_table(dev); 2418 2419 if (mlx4_is_master(dev)) 2420 mlx4_free_resource_tracker(dev, 2421 RES_TR_FREE_STRUCTS_ONLY); 2422 2423 iounmap(priv->kar); 2424 mlx4_uar_free(dev, &priv->driver_uar); 2425 mlx4_cleanup_uar_table(dev); 2426 if (!mlx4_is_slave(dev)) 2427 mlx4_clear_steering(dev); 2428 mlx4_free_eq_table(dev); 2429 if (mlx4_is_master(dev)) 2430 mlx4_multi_func_cleanup(dev); 2431 mlx4_close_hca(dev); 2432 if (mlx4_is_slave(dev)) 2433 mlx4_multi_func_cleanup(dev); 2434 mlx4_cmd_cleanup(dev); 2435 2436 if (dev->flags & MLX4_FLAG_MSI_X) 2437 pci_disable_msix(pdev); 2438 if (dev->flags & MLX4_FLAG_SRIOV) { 2439 mlx4_warn(dev, "Disabling SR-IOV\n"); 2440 pci_disable_sriov(pdev); 2441 } 2442 2443 if (!mlx4_is_slave(dev)) 2444 mlx4_free_ownership(dev); 2445 2446 kfree(dev->caps.qp0_tunnel); 2447 kfree(dev->caps.qp0_proxy); 2448 kfree(dev->caps.qp1_tunnel); 2449 kfree(dev->caps.qp1_proxy); 2450 2451 kfree(priv); 2452 pci_release_regions(pdev); 2453 pci_disable_device(pdev); 2454 pci_set_drvdata(pdev, NULL); 2455 } 2456 } 2457 2458 int mlx4_restart_one(struct pci_dev *pdev) 2459 { 2460 struct mlx4_dev *dev = pci_get_drvdata(pdev); 2461 struct mlx4_priv *priv = mlx4_priv(dev); 2462 int pci_dev_data; 2463 2464 pci_dev_data = priv->pci_dev_data; 2465 mlx4_remove_one(pdev); 2466 return __mlx4_init_one(pdev, pci_dev_data); 2467 } 2468 2469 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { 2470 /* MT25408 "Hermon" SDR */ 2471 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2472 /* MT25408 "Hermon" DDR */ 2473 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2474 /* MT25408 "Hermon" QDR */ 2475 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2476 /* MT25408 "Hermon" DDR PCIe gen2 */ 2477 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2478 /* MT25408 "Hermon" QDR PCIe gen2 */ 2479 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2480 /* MT25408 "Hermon" EN 10GigE */ 2481 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2482 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 2483 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2484 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 2485 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2486 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 2487 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2488 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 2489 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2490 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 2491 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2492 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 2493 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 2494 /* MT25400 Family [ConnectX-2 Virtual Function] */ 2495 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 2496 /* MT27500 Family [ConnectX-3] */ 2497 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 2498 /* MT27500 Family [ConnectX-3 Virtual Function] */ 2499 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 2500 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 2501 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 2502 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 2503 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 2504 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 2505 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 2506 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 2507 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 2508 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 2509 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 2510 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 2511 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 2512 { 0, } 2513 }; 2514 2515 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 2516 2517 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 2518 pci_channel_state_t state) 2519 { 2520 mlx4_remove_one(pdev); 2521 2522 return state == pci_channel_io_perm_failure ? 2523 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2524 } 2525 2526 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 2527 { 2528 int ret = __mlx4_init_one(pdev, 0); 2529 2530 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 2531 } 2532 2533 static const struct pci_error_handlers mlx4_err_handler = { 2534 .error_detected = mlx4_pci_err_detected, 2535 .slot_reset = mlx4_pci_slot_reset, 2536 }; 2537 2538 static struct pci_driver mlx4_driver = { 2539 .name = DRV_NAME, 2540 .id_table = mlx4_pci_table, 2541 .probe = mlx4_init_one, 2542 .remove = mlx4_remove_one, 2543 .err_handler = &mlx4_err_handler, 2544 }; 2545 2546 static int __init mlx4_verify_params(void) 2547 { 2548 if ((log_num_mac < 0) || (log_num_mac > 7)) { 2549 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); 2550 return -1; 2551 } 2552 2553 if (log_num_vlan != 0) 2554 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 2555 MLX4_LOG_NUM_VLANS); 2556 2557 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 2558 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); 2559 return -1; 2560 } 2561 2562 /* Check if module param for ports type has legal combination */ 2563 if (port_type_array[0] == false && port_type_array[1] == true) { 2564 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 2565 port_type_array[0] = true; 2566 } 2567 2568 if (mlx4_log_num_mgm_entry_size != -1 && 2569 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 2570 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { 2571 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not " 2572 "in legal range (-1 or %d..%d)\n", 2573 mlx4_log_num_mgm_entry_size, 2574 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 2575 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 2576 return -1; 2577 } 2578 2579 return 0; 2580 } 2581 2582 static int __init mlx4_init(void) 2583 { 2584 int ret; 2585 2586 if (mlx4_verify_params()) 2587 return -EINVAL; 2588 2589 mlx4_catas_init(); 2590 2591 mlx4_wq = create_singlethread_workqueue("mlx4"); 2592 if (!mlx4_wq) 2593 return -ENOMEM; 2594 2595 ret = pci_register_driver(&mlx4_driver); 2596 return ret < 0 ? ret : 0; 2597 } 2598 2599 static void __exit mlx4_cleanup(void) 2600 { 2601 pci_unregister_driver(&mlx4_driver); 2602 destroy_workqueue(mlx4_wq); 2603 } 2604 2605 module_init(mlx4_init); 2606 module_exit(mlx4_cleanup); 2607