1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/errno.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/slab.h> 43 #include <linux/io-mapping.h> 44 #include <linux/delay.h> 45 #include <linux/kmod.h> 46 #include <linux/etherdevice.h> 47 #include <net/devlink.h> 48 49 #include <uapi/rdma/mlx4-abi.h> 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/doorbell.h> 52 53 #include "mlx4.h" 54 #include "fw.h" 55 #include "icm.h" 56 57 MODULE_AUTHOR("Roland Dreier"); 58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 MODULE_VERSION(DRV_VERSION); 61 62 struct workqueue_struct *mlx4_wq; 63 64 #ifdef CONFIG_MLX4_DEBUG 65 66 int mlx4_debug_level = 0; 67 module_param_named(debug_level, mlx4_debug_level, int, 0644); 68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 69 70 #endif /* CONFIG_MLX4_DEBUG */ 71 72 #ifdef CONFIG_PCI_MSI 73 74 static int msi_x = 1; 75 module_param(msi_x, int, 0444); 76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 77 78 #else /* CONFIG_PCI_MSI */ 79 80 #define msi_x (0) 81 82 #endif /* CONFIG_PCI_MSI */ 83 84 static uint8_t num_vfs[3] = {0, 0, 0}; 85 static int num_vfs_argc; 86 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 88 "num_vfs=port1,port2,port1+2"); 89 90 static uint8_t probe_vf[3] = {0, 0, 0}; 91 static int probe_vfs_argc; 92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 94 "probe_vf=port1,port2,port1+2"); 95 96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 97 module_param_named(log_num_mgm_entry_size, 98 mlx4_log_num_mgm_entry_size, int, 0444); 99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 100 " of qp per mcg, for example:" 101 " 10 gives 248.range: 7 <=" 102 " log_num_mgm_entry_size <= 12." 103 " To activate device managed" 104 " flow steering when available, set to -1"); 105 106 static bool enable_64b_cqe_eqe = true; 107 module_param(enable_64b_cqe_eqe, bool, 0444); 108 MODULE_PARM_DESC(enable_64b_cqe_eqe, 109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 110 111 static bool enable_4k_uar; 112 module_param(enable_4k_uar, bool, 0444); 113 MODULE_PARM_DESC(enable_4k_uar, 114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 115 116 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 118 MLX4_FUNC_CAP_DMFS_A0_STATIC) 119 120 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 121 122 static char mlx4_version[] = 123 DRV_NAME ": Mellanox ConnectX core driver v" 124 DRV_VERSION "\n"; 125 126 static const struct mlx4_profile default_profile = { 127 .num_qp = 1 << 18, 128 .num_srq = 1 << 16, 129 .rdmarc_per_qp = 1 << 4, 130 .num_cq = 1 << 16, 131 .num_mcg = 1 << 13, 132 .num_mpt = 1 << 19, 133 .num_mtt = 1 << 20, /* It is really num mtt segements */ 134 }; 135 136 static const struct mlx4_profile low_mem_profile = { 137 .num_qp = 1 << 17, 138 .num_srq = 1 << 6, 139 .rdmarc_per_qp = 1 << 4, 140 .num_cq = 1 << 8, 141 .num_mcg = 1 << 8, 142 .num_mpt = 1 << 9, 143 .num_mtt = 1 << 7, 144 }; 145 146 static int log_num_mac = 7; 147 module_param_named(log_num_mac, log_num_mac, int, 0444); 148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 149 150 static int log_num_vlan; 151 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 153 /* Log2 max number of VLANs per ETH port (0-7) */ 154 #define MLX4_LOG_NUM_VLANS 7 155 #define MLX4_MIN_LOG_NUM_VLANS 0 156 #define MLX4_MIN_LOG_NUM_MAC 1 157 158 static bool use_prio; 159 module_param_named(use_prio, use_prio, bool, 0444); 160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 161 162 int log_mtts_per_seg = ilog2(1); 163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 165 "(0-7) (default: 0)"); 166 167 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 168 static int arr_argc = 2; 169 module_param_array(port_type_array, int, &arr_argc, 0444); 170 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 171 "1 for IB, 2 for Ethernet"); 172 173 struct mlx4_port_config { 174 struct list_head list; 175 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 176 struct pci_dev *pdev; 177 }; 178 179 static atomic_t pf_loading = ATOMIC_INIT(0); 180 181 static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 182 struct devlink_param_gset_ctx *ctx) 183 { 184 ctx->val.vbool = !!mlx4_internal_err_reset; 185 return 0; 186 } 187 188 static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 189 struct devlink_param_gset_ctx *ctx) 190 { 191 mlx4_internal_err_reset = ctx->val.vbool; 192 return 0; 193 } 194 195 static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 196 struct devlink_param_gset_ctx *ctx) 197 { 198 struct mlx4_priv *priv = devlink_priv(devlink); 199 struct mlx4_dev *dev = &priv->dev; 200 201 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 202 return 0; 203 } 204 205 static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 206 struct devlink_param_gset_ctx *ctx) 207 { 208 struct mlx4_priv *priv = devlink_priv(devlink); 209 struct mlx4_dev *dev = &priv->dev; 210 211 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 212 return 0; 213 } 214 215 static int 216 mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 217 union devlink_param_value val, 218 struct netlink_ext_ack *extack) 219 { 220 u32 value = val.vu32; 221 222 if (value < 1 || value > 128) 223 return -ERANGE; 224 225 if (!is_power_of_2(value)) { 226 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 enum mlx4_devlink_param_id { 234 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 235 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 236 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 237 }; 238 239 static const struct devlink_param mlx4_devlink_params[] = { 240 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 241 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 242 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 243 mlx4_devlink_ierr_reset_get, 244 mlx4_devlink_ierr_reset_set, NULL), 245 DEVLINK_PARAM_GENERIC(MAX_MACS, 246 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 247 NULL, NULL, mlx4_devlink_max_macs_validate), 248 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 249 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 250 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 251 mlx4_devlink_crdump_snapshot_get, 252 mlx4_devlink_crdump_snapshot_set, NULL), 253 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 254 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 255 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 256 NULL, NULL, NULL), 257 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 258 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 259 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 260 NULL, NULL, NULL), 261 }; 262 263 static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 264 { 265 union devlink_param_value value; 266 267 value.vbool = !!mlx4_internal_err_reset; 268 devlink_param_driverinit_value_set(devlink, 269 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 270 value); 271 272 value.vu32 = 1UL << log_num_mac; 273 devlink_param_driverinit_value_set(devlink, 274 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 275 value); 276 277 value.vbool = enable_64b_cqe_eqe; 278 devlink_param_driverinit_value_set(devlink, 279 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 280 value); 281 282 value.vbool = enable_4k_uar; 283 devlink_param_driverinit_value_set(devlink, 284 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 285 value); 286 287 value.vbool = false; 288 devlink_param_driverinit_value_set(devlink, 289 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 290 value); 291 } 292 293 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 294 struct mlx4_dev_cap *dev_cap) 295 { 296 /* The reserved_uars is calculated by system page size unit. 297 * Therefore, adjustment is added when the uar page size is less 298 * than the system page size 299 */ 300 dev->caps.reserved_uars = 301 max_t(int, 302 mlx4_get_num_reserved_uar(dev), 303 dev_cap->reserved_uars / 304 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 305 } 306 307 int mlx4_check_port_params(struct mlx4_dev *dev, 308 enum mlx4_port_type *port_type) 309 { 310 int i; 311 312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 313 for (i = 0; i < dev->caps.num_ports - 1; i++) { 314 if (port_type[i] != port_type[i + 1]) { 315 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 316 return -EINVAL; 317 } 318 } 319 } 320 321 for (i = 0; i < dev->caps.num_ports; i++) { 322 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 323 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 324 i + 1); 325 return -EINVAL; 326 } 327 } 328 return 0; 329 } 330 331 static void mlx4_set_port_mask(struct mlx4_dev *dev) 332 { 333 int i; 334 335 for (i = 1; i <= dev->caps.num_ports; ++i) 336 dev->caps.port_mask[i] = dev->caps.port_type[i]; 337 } 338 339 enum { 340 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 341 }; 342 343 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 344 { 345 int err = 0; 346 struct mlx4_func func; 347 348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 349 err = mlx4_QUERY_FUNC(dev, &func, 0); 350 if (err) { 351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 352 return err; 353 } 354 dev_cap->max_eqs = func.max_eq; 355 dev_cap->reserved_eqs = func.rsvd_eqs; 356 dev_cap->reserved_uars = func.rsvd_uars; 357 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 358 } 359 return err; 360 } 361 362 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 363 { 364 struct mlx4_caps *dev_cap = &dev->caps; 365 366 /* FW not supporting or cancelled by user */ 367 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 368 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 369 return; 370 371 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 372 * When FW has NCSI it may decide not to report 64B CQE/EQEs 373 */ 374 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 375 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 376 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 377 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 378 return; 379 } 380 381 if (cache_line_size() == 128 || cache_line_size() == 256) { 382 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 383 /* Changing the real data inside CQE size to 32B */ 384 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 385 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 386 387 if (mlx4_is_master(dev)) 388 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 389 } else { 390 if (cache_line_size() != 32 && cache_line_size() != 64) 391 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 392 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 393 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 394 } 395 } 396 397 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 398 struct mlx4_port_cap *port_cap) 399 { 400 dev->caps.vl_cap[port] = port_cap->max_vl; 401 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 402 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 403 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 404 /* set gid and pkey table operating lengths by default 405 * to non-sriov values 406 */ 407 dev->caps.gid_table_len[port] = port_cap->max_gids; 408 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 409 dev->caps.port_width_cap[port] = port_cap->max_port_width; 410 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 411 dev->caps.max_tc_eth = port_cap->max_tc_eth; 412 dev->caps.def_mac[port] = port_cap->def_mac; 413 dev->caps.supported_type[port] = port_cap->supported_port_types; 414 dev->caps.suggested_type[port] = port_cap->suggested_type; 415 dev->caps.default_sense[port] = port_cap->default_sense; 416 dev->caps.trans_type[port] = port_cap->trans_type; 417 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 418 dev->caps.wavelength[port] = port_cap->wavelength; 419 dev->caps.trans_code[port] = port_cap->trans_code; 420 421 return 0; 422 } 423 424 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 425 struct mlx4_port_cap *port_cap) 426 { 427 int err = 0; 428 429 err = mlx4_QUERY_PORT(dev, port, port_cap); 430 431 if (err) 432 mlx4_err(dev, "QUERY_PORT command failed.\n"); 433 434 return err; 435 } 436 437 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 438 { 439 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 440 return; 441 442 if (mlx4_is_mfunc(dev)) { 443 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 444 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 445 return; 446 } 447 448 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 449 mlx4_dbg(dev, 450 "Keep FCS is not supported - Disabling Ignore FCS"); 451 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 452 return; 453 } 454 } 455 456 #define MLX4_A0_STEERING_TABLE_SIZE 256 457 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 458 { 459 int err; 460 int i; 461 462 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 463 if (err) { 464 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 465 return err; 466 } 467 mlx4_dev_cap_dump(dev, dev_cap); 468 469 if (dev_cap->min_page_sz > PAGE_SIZE) { 470 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 471 dev_cap->min_page_sz, PAGE_SIZE); 472 return -ENODEV; 473 } 474 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 475 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 476 dev_cap->num_ports, MLX4_MAX_PORTS); 477 return -ENODEV; 478 } 479 480 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 481 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 482 dev_cap->uar_size, 483 (unsigned long long) 484 pci_resource_len(dev->persist->pdev, 2)); 485 return -ENODEV; 486 } 487 488 dev->caps.num_ports = dev_cap->num_ports; 489 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 490 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 491 dev->caps.num_sys_eqs : 492 MLX4_MAX_EQ_NUM; 493 for (i = 1; i <= dev->caps.num_ports; ++i) { 494 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 495 if (err) { 496 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 497 return err; 498 } 499 } 500 501 dev->caps.uar_page_size = PAGE_SIZE; 502 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 503 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 504 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 505 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 506 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 507 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 508 dev->caps.max_wqes = dev_cap->max_qp_sz; 509 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 510 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 511 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 512 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 513 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 514 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 515 /* 516 * Subtract 1 from the limit because we need to allocate a 517 * spare CQE so the HCA HW can tell the difference between an 518 * empty CQ and a full CQ. 519 */ 520 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 521 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 522 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 523 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 524 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 525 526 dev->caps.reserved_pds = dev_cap->reserved_pds; 527 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 528 dev_cap->reserved_xrcds : 0; 529 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 530 dev_cap->max_xrcds : 0; 531 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 532 533 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 534 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 535 dev->caps.flags = dev_cap->flags; 536 dev->caps.flags2 = dev_cap->flags2; 537 dev->caps.bmme_flags = dev_cap->bmme_flags; 538 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 539 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 540 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 541 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 542 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 543 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 544 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 545 546 /* Save uar page shift */ 547 if (!mlx4_is_slave(dev)) { 548 /* Virtual PCI function needs to determine UAR page size from 549 * firmware. Only master PCI function can set the uar page size 550 */ 551 if (enable_4k_uar || !dev->persist->num_vfs) 552 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 553 else 554 dev->uar_page_shift = PAGE_SHIFT; 555 556 mlx4_set_num_reserved_uars(dev, dev_cap); 557 } 558 559 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 560 struct mlx4_init_hca_param hca_param; 561 562 memset(&hca_param, 0, sizeof(hca_param)); 563 err = mlx4_QUERY_HCA(dev, &hca_param); 564 /* Turn off PHV_EN flag in case phv_check_en is set. 565 * phv_check_en is a HW check that parse the packet and verify 566 * phv bit was reported correctly in the wqe. To allow QinQ 567 * PHV_EN flag should be set and phv_check_en must be cleared 568 * otherwise QinQ packets will be drop by the HW. 569 */ 570 if (err || hca_param.phv_check_en) 571 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 572 } 573 574 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 575 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 576 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 577 /* Don't do sense port on multifunction devices (for now at least) */ 578 if (mlx4_is_mfunc(dev)) 579 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 580 581 if (mlx4_low_memory_profile()) { 582 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 583 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 584 } else { 585 dev->caps.log_num_macs = log_num_mac; 586 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 587 } 588 589 for (i = 1; i <= dev->caps.num_ports; ++i) { 590 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 591 if (dev->caps.supported_type[i]) { 592 /* if only ETH is supported - assign ETH */ 593 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 594 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 595 /* if only IB is supported, assign IB */ 596 else if (dev->caps.supported_type[i] == 597 MLX4_PORT_TYPE_IB) 598 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 599 else { 600 /* if IB and ETH are supported, we set the port 601 * type according to user selection of port type; 602 * if user selected none, take the FW hint */ 603 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 604 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 605 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 606 else 607 dev->caps.port_type[i] = port_type_array[i - 1]; 608 } 609 } 610 /* 611 * Link sensing is allowed on the port if 3 conditions are true: 612 * 1. Both protocols are supported on the port. 613 * 2. Different types are supported on the port 614 * 3. FW declared that it supports link sensing 615 */ 616 mlx4_priv(dev)->sense.sense_allowed[i] = 617 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 618 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 619 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 620 621 /* 622 * If "default_sense" bit is set, we move the port to "AUTO" mode 623 * and perform sense_port FW command to try and set the correct 624 * port type from beginning 625 */ 626 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 627 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 628 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 629 mlx4_SENSE_PORT(dev, i, &sensed_port); 630 if (sensed_port != MLX4_PORT_TYPE_NONE) 631 dev->caps.port_type[i] = sensed_port; 632 } else { 633 dev->caps.possible_type[i] = dev->caps.port_type[i]; 634 } 635 636 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 637 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 638 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 639 i, 1 << dev->caps.log_num_macs); 640 } 641 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 642 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 643 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 644 i, 1 << dev->caps.log_num_vlans); 645 } 646 } 647 648 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 649 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 650 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 651 mlx4_warn(dev, 652 "Granular QoS per VF not supported with IB/Eth configuration\n"); 653 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 654 } 655 656 dev->caps.max_counters = dev_cap->max_counters; 657 658 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 660 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 661 (1 << dev->caps.log_num_macs) * 662 (1 << dev->caps.log_num_vlans) * 663 dev->caps.num_ports; 664 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 665 666 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 667 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 668 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 669 else 670 dev->caps.dmfs_high_rate_qpn_base = 671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 672 673 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 674 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 675 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 677 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 678 } else { 679 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 680 dev->caps.dmfs_high_rate_qpn_base = 681 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 682 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 683 } 684 685 dev->caps.rl_caps = dev_cap->rl_caps; 686 687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 688 dev->caps.dmfs_high_rate_qpn_range; 689 690 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 691 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 694 695 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 696 697 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 698 if (dev_cap->flags & 699 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 700 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 702 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 703 } 704 705 if (dev_cap->flags2 & 706 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 707 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 708 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 709 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 710 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 711 } 712 } 713 714 if ((dev->caps.flags & 715 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 716 mlx4_is_master(dev)) 717 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 718 719 if (!mlx4_is_slave(dev)) { 720 mlx4_enable_cqe_eqe_stride(dev); 721 dev->caps.alloc_res_qp_mask = 722 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 723 MLX4_RESERVE_A0_QP; 724 725 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 726 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 727 mlx4_warn(dev, "Old device ETS support detected\n"); 728 mlx4_warn(dev, "Consider upgrading device FW.\n"); 729 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 730 } 731 732 } else { 733 dev->caps.alloc_res_qp_mask = 0; 734 } 735 736 mlx4_enable_ignore_fcs(dev); 737 738 return 0; 739 } 740 741 /*The function checks if there are live vf, return the num of them*/ 742 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 743 { 744 struct mlx4_priv *priv = mlx4_priv(dev); 745 struct mlx4_slave_state *s_state; 746 int i; 747 int ret = 0; 748 749 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 750 s_state = &priv->mfunc.master.slave_state[i]; 751 if (s_state->active && s_state->last_cmd != 752 MLX4_COMM_CMD_RESET) { 753 mlx4_warn(dev, "%s: slave: %d is still active\n", 754 __func__, i); 755 ret++; 756 } 757 } 758 return ret; 759 } 760 761 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 762 { 763 u32 qk = MLX4_RESERVED_QKEY_BASE; 764 765 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 766 qpn < dev->phys_caps.base_proxy_sqpn) 767 return -EINVAL; 768 769 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 770 /* tunnel qp */ 771 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 772 else 773 qk += qpn - dev->phys_caps.base_proxy_sqpn; 774 *qkey = qk; 775 return 0; 776 } 777 EXPORT_SYMBOL(mlx4_get_parav_qkey); 778 779 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 780 { 781 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 782 783 if (!mlx4_is_master(dev)) 784 return; 785 786 priv->virt2phys_pkey[slave][port - 1][i] = val; 787 } 788 EXPORT_SYMBOL(mlx4_sync_pkey_table); 789 790 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 791 { 792 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 793 794 if (!mlx4_is_master(dev)) 795 return; 796 797 priv->slave_node_guids[slave] = guid; 798 } 799 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 800 801 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 802 { 803 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 804 805 if (!mlx4_is_master(dev)) 806 return 0; 807 808 return priv->slave_node_guids[slave]; 809 } 810 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 811 812 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 813 { 814 struct mlx4_priv *priv = mlx4_priv(dev); 815 struct mlx4_slave_state *s_slave; 816 817 if (!mlx4_is_master(dev)) 818 return 0; 819 820 s_slave = &priv->mfunc.master.slave_state[slave]; 821 return !!s_slave->active; 822 } 823 EXPORT_SYMBOL(mlx4_is_slave_active); 824 825 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 826 struct _rule_hw *eth_header) 827 { 828 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 829 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 830 struct mlx4_net_trans_rule_hw_eth *eth = 831 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 832 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 833 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 834 next_rule->rsvd == 0; 835 836 if (last_rule) 837 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 838 } 839 } 840 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 841 842 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 843 struct mlx4_dev_cap *dev_cap, 844 struct mlx4_init_hca_param *hca_param) 845 { 846 dev->caps.steering_mode = hca_param->steering_mode; 847 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 848 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 849 dev->caps.fs_log_max_ucast_qp_range_size = 850 dev_cap->fs_log_max_ucast_qp_range_size; 851 } else 852 dev->caps.num_qp_per_mgm = 853 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 854 855 mlx4_dbg(dev, "Steering mode is: %s\n", 856 mlx4_steering_mode_str(dev->caps.steering_mode)); 857 } 858 859 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 860 { 861 kfree(dev->caps.spec_qps); 862 dev->caps.spec_qps = NULL; 863 } 864 865 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 866 { 867 struct mlx4_func_cap *func_cap = NULL; 868 struct mlx4_caps *caps = &dev->caps; 869 int i, err = 0; 870 871 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 872 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 873 874 if (!func_cap || !caps->spec_qps) { 875 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 876 err = -ENOMEM; 877 goto err_mem; 878 } 879 880 for (i = 1; i <= caps->num_ports; ++i) { 881 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 882 if (err) { 883 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 884 i, err); 885 goto err_mem; 886 } 887 caps->spec_qps[i - 1] = func_cap->spec_qps; 888 caps->port_mask[i] = caps->port_type[i]; 889 caps->phys_port_id[i] = func_cap->phys_port_id; 890 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 891 &caps->gid_table_len[i], 892 &caps->pkey_table_len[i]); 893 if (err) { 894 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 895 i, err); 896 goto err_mem; 897 } 898 } 899 900 err_mem: 901 if (err) 902 mlx4_slave_destroy_special_qp_cap(dev); 903 kfree(func_cap); 904 return err; 905 } 906 907 static int mlx4_slave_cap(struct mlx4_dev *dev) 908 { 909 int err; 910 u32 page_size; 911 struct mlx4_dev_cap *dev_cap = NULL; 912 struct mlx4_func_cap *func_cap = NULL; 913 struct mlx4_init_hca_param *hca_param = NULL; 914 915 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 916 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 917 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 918 if (!hca_param || !func_cap || !dev_cap) { 919 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 920 err = -ENOMEM; 921 goto free_mem; 922 } 923 924 err = mlx4_QUERY_HCA(dev, hca_param); 925 if (err) { 926 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 927 goto free_mem; 928 } 929 930 /* fail if the hca has an unknown global capability 931 * at this time global_caps should be always zeroed 932 */ 933 if (hca_param->global_caps) { 934 mlx4_err(dev, "Unknown hca global capabilities\n"); 935 err = -EINVAL; 936 goto free_mem; 937 } 938 939 dev->caps.hca_core_clock = hca_param->hca_core_clock; 940 941 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 942 err = mlx4_dev_cap(dev, dev_cap); 943 if (err) { 944 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 945 goto free_mem; 946 } 947 948 err = mlx4_QUERY_FW(dev); 949 if (err) 950 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 951 952 page_size = ~dev->caps.page_size_cap + 1; 953 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 954 if (page_size > PAGE_SIZE) { 955 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 956 page_size, PAGE_SIZE); 957 err = -ENODEV; 958 goto free_mem; 959 } 960 961 /* Set uar_page_shift for VF */ 962 dev->uar_page_shift = hca_param->uar_page_sz + 12; 963 964 /* Make sure the master uar page size is valid */ 965 if (dev->uar_page_shift > PAGE_SHIFT) { 966 mlx4_err(dev, 967 "Invalid configuration: uar page size is larger than system page size\n"); 968 err = -ENODEV; 969 goto free_mem; 970 } 971 972 /* Set reserved_uars based on the uar_page_shift */ 973 mlx4_set_num_reserved_uars(dev, dev_cap); 974 975 /* Although uar page size in FW differs from system page size, 976 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 977 * still works with assumption that uar page size == system page size 978 */ 979 dev->caps.uar_page_size = PAGE_SIZE; 980 981 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 982 if (err) { 983 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 984 err); 985 goto free_mem; 986 } 987 988 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 989 PF_CONTEXT_BEHAVIOUR_MASK) { 990 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 991 func_cap->pf_context_behaviour, 992 PF_CONTEXT_BEHAVIOUR_MASK); 993 err = -EINVAL; 994 goto free_mem; 995 } 996 997 dev->caps.num_ports = func_cap->num_ports; 998 dev->quotas.qp = func_cap->qp_quota; 999 dev->quotas.srq = func_cap->srq_quota; 1000 dev->quotas.cq = func_cap->cq_quota; 1001 dev->quotas.mpt = func_cap->mpt_quota; 1002 dev->quotas.mtt = func_cap->mtt_quota; 1003 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1004 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1005 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1006 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1007 dev->caps.num_eqs = func_cap->max_eq; 1008 dev->caps.reserved_eqs = func_cap->reserved_eq; 1009 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1010 dev->caps.num_pds = MLX4_NUM_PDS; 1011 dev->caps.num_mgms = 0; 1012 dev->caps.num_amgms = 0; 1013 1014 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1015 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1016 dev->caps.num_ports, MLX4_MAX_PORTS); 1017 err = -ENODEV; 1018 goto free_mem; 1019 } 1020 1021 mlx4_replace_zero_macs(dev); 1022 1023 err = mlx4_slave_special_qp_cap(dev); 1024 if (err) { 1025 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1026 goto free_mem; 1027 } 1028 1029 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1030 dev->caps.reserved_uars) > 1031 pci_resource_len(dev->persist->pdev, 1032 2)) { 1033 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1034 dev->caps.uar_page_size * dev->caps.num_uars, 1035 (unsigned long long) 1036 pci_resource_len(dev->persist->pdev, 2)); 1037 err = -ENOMEM; 1038 goto err_mem; 1039 } 1040 1041 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1042 dev->caps.eqe_size = 64; 1043 dev->caps.eqe_factor = 1; 1044 } else { 1045 dev->caps.eqe_size = 32; 1046 dev->caps.eqe_factor = 0; 1047 } 1048 1049 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1050 dev->caps.cqe_size = 64; 1051 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1052 } else { 1053 dev->caps.cqe_size = 32; 1054 } 1055 1056 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1057 dev->caps.eqe_size = hca_param->eqe_size; 1058 dev->caps.eqe_factor = 0; 1059 } 1060 1061 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1062 dev->caps.cqe_size = hca_param->cqe_size; 1063 /* User still need to know when CQE > 32B */ 1064 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1065 } 1066 1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1068 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1069 1070 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1071 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1072 1073 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1074 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1075 hca_param->rss_ip_frags ? "on" : "off"); 1076 1077 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1078 dev->caps.bf_reg_size) 1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1080 1081 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1082 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1083 1084 err_mem: 1085 if (err) 1086 mlx4_slave_destroy_special_qp_cap(dev); 1087 free_mem: 1088 kfree(hca_param); 1089 kfree(func_cap); 1090 kfree(dev_cap); 1091 return err; 1092 } 1093 1094 static void mlx4_request_modules(struct mlx4_dev *dev) 1095 { 1096 int port; 1097 int has_ib_port = false; 1098 int has_eth_port = false; 1099 #define EN_DRV_NAME "mlx4_en" 1100 #define IB_DRV_NAME "mlx4_ib" 1101 1102 for (port = 1; port <= dev->caps.num_ports; port++) { 1103 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1104 has_ib_port = true; 1105 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1106 has_eth_port = true; 1107 } 1108 1109 if (has_eth_port) 1110 request_module_nowait(EN_DRV_NAME); 1111 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1112 request_module_nowait(IB_DRV_NAME); 1113 } 1114 1115 /* 1116 * Change the port configuration of the device. 1117 * Every user of this function must hold the port mutex. 1118 */ 1119 int mlx4_change_port_types(struct mlx4_dev *dev, 1120 enum mlx4_port_type *port_types) 1121 { 1122 int err = 0; 1123 int change = 0; 1124 int port; 1125 1126 for (port = 0; port < dev->caps.num_ports; port++) { 1127 /* Change the port type only if the new type is different 1128 * from the current, and not set to Auto */ 1129 if (port_types[port] != dev->caps.port_type[port + 1]) 1130 change = 1; 1131 } 1132 if (change) { 1133 mlx4_unregister_device(dev); 1134 for (port = 1; port <= dev->caps.num_ports; port++) { 1135 mlx4_CLOSE_PORT(dev, port); 1136 dev->caps.port_type[port] = port_types[port - 1]; 1137 err = mlx4_SET_PORT(dev, port, -1); 1138 if (err) { 1139 mlx4_err(dev, "Failed to set port %d, aborting\n", 1140 port); 1141 goto out; 1142 } 1143 } 1144 mlx4_set_port_mask(dev); 1145 err = mlx4_register_device(dev); 1146 if (err) { 1147 mlx4_err(dev, "Failed to register device\n"); 1148 goto out; 1149 } 1150 mlx4_request_modules(dev); 1151 } 1152 1153 out: 1154 return err; 1155 } 1156 1157 static ssize_t show_port_type(struct device *dev, 1158 struct device_attribute *attr, 1159 char *buf) 1160 { 1161 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1162 port_attr); 1163 struct mlx4_dev *mdev = info->dev; 1164 char type[8]; 1165 1166 sprintf(type, "%s", 1167 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1168 "ib" : "eth"); 1169 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1170 sprintf(buf, "auto (%s)\n", type); 1171 else 1172 sprintf(buf, "%s\n", type); 1173 1174 return strlen(buf); 1175 } 1176 1177 static int __set_port_type(struct mlx4_port_info *info, 1178 enum mlx4_port_type port_type) 1179 { 1180 struct mlx4_dev *mdev = info->dev; 1181 struct mlx4_priv *priv = mlx4_priv(mdev); 1182 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1183 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1184 int i; 1185 int err = 0; 1186 1187 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1188 mlx4_err(mdev, 1189 "Requested port type for port %d is not supported on this HCA\n", 1190 info->port); 1191 err = -EINVAL; 1192 goto err_sup; 1193 } 1194 1195 mlx4_stop_sense(mdev); 1196 mutex_lock(&priv->port_mutex); 1197 info->tmp_type = port_type; 1198 1199 /* Possible type is always the one that was delivered */ 1200 mdev->caps.possible_type[info->port] = info->tmp_type; 1201 1202 for (i = 0; i < mdev->caps.num_ports; i++) { 1203 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1204 mdev->caps.possible_type[i+1]; 1205 if (types[i] == MLX4_PORT_TYPE_AUTO) 1206 types[i] = mdev->caps.port_type[i+1]; 1207 } 1208 1209 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1210 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1211 for (i = 1; i <= mdev->caps.num_ports; i++) { 1212 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1213 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1214 err = -EINVAL; 1215 } 1216 } 1217 } 1218 if (err) { 1219 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1220 goto out; 1221 } 1222 1223 mlx4_do_sense_ports(mdev, new_types, types); 1224 1225 err = mlx4_check_port_params(mdev, new_types); 1226 if (err) 1227 goto out; 1228 1229 /* We are about to apply the changes after the configuration 1230 * was verified, no need to remember the temporary types 1231 * any more */ 1232 for (i = 0; i < mdev->caps.num_ports; i++) 1233 priv->port[i + 1].tmp_type = 0; 1234 1235 err = mlx4_change_port_types(mdev, new_types); 1236 1237 out: 1238 mlx4_start_sense(mdev); 1239 mutex_unlock(&priv->port_mutex); 1240 err_sup: 1241 return err; 1242 } 1243 1244 static ssize_t set_port_type(struct device *dev, 1245 struct device_attribute *attr, 1246 const char *buf, size_t count) 1247 { 1248 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1249 port_attr); 1250 struct mlx4_dev *mdev = info->dev; 1251 enum mlx4_port_type port_type; 1252 static DEFINE_MUTEX(set_port_type_mutex); 1253 int err; 1254 1255 mutex_lock(&set_port_type_mutex); 1256 1257 if (!strcmp(buf, "ib\n")) { 1258 port_type = MLX4_PORT_TYPE_IB; 1259 } else if (!strcmp(buf, "eth\n")) { 1260 port_type = MLX4_PORT_TYPE_ETH; 1261 } else if (!strcmp(buf, "auto\n")) { 1262 port_type = MLX4_PORT_TYPE_AUTO; 1263 } else { 1264 mlx4_err(mdev, "%s is not supported port type\n", buf); 1265 err = -EINVAL; 1266 goto err_out; 1267 } 1268 1269 err = __set_port_type(info, port_type); 1270 1271 err_out: 1272 mutex_unlock(&set_port_type_mutex); 1273 1274 return err ? err : count; 1275 } 1276 1277 enum ibta_mtu { 1278 IB_MTU_256 = 1, 1279 IB_MTU_512 = 2, 1280 IB_MTU_1024 = 3, 1281 IB_MTU_2048 = 4, 1282 IB_MTU_4096 = 5 1283 }; 1284 1285 static inline int int_to_ibta_mtu(int mtu) 1286 { 1287 switch (mtu) { 1288 case 256: return IB_MTU_256; 1289 case 512: return IB_MTU_512; 1290 case 1024: return IB_MTU_1024; 1291 case 2048: return IB_MTU_2048; 1292 case 4096: return IB_MTU_4096; 1293 default: return -1; 1294 } 1295 } 1296 1297 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1298 { 1299 switch (mtu) { 1300 case IB_MTU_256: return 256; 1301 case IB_MTU_512: return 512; 1302 case IB_MTU_1024: return 1024; 1303 case IB_MTU_2048: return 2048; 1304 case IB_MTU_4096: return 4096; 1305 default: return -1; 1306 } 1307 } 1308 1309 static ssize_t show_port_ib_mtu(struct device *dev, 1310 struct device_attribute *attr, 1311 char *buf) 1312 { 1313 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1314 port_mtu_attr); 1315 struct mlx4_dev *mdev = info->dev; 1316 1317 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1318 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1319 1320 sprintf(buf, "%d\n", 1321 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1322 return strlen(buf); 1323 } 1324 1325 static ssize_t set_port_ib_mtu(struct device *dev, 1326 struct device_attribute *attr, 1327 const char *buf, size_t count) 1328 { 1329 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1330 port_mtu_attr); 1331 struct mlx4_dev *mdev = info->dev; 1332 struct mlx4_priv *priv = mlx4_priv(mdev); 1333 int err, port, mtu, ibta_mtu = -1; 1334 1335 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1336 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1337 return -EINVAL; 1338 } 1339 1340 err = kstrtoint(buf, 0, &mtu); 1341 if (!err) 1342 ibta_mtu = int_to_ibta_mtu(mtu); 1343 1344 if (err || ibta_mtu < 0) { 1345 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1346 return -EINVAL; 1347 } 1348 1349 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1350 1351 mlx4_stop_sense(mdev); 1352 mutex_lock(&priv->port_mutex); 1353 mlx4_unregister_device(mdev); 1354 for (port = 1; port <= mdev->caps.num_ports; port++) { 1355 mlx4_CLOSE_PORT(mdev, port); 1356 err = mlx4_SET_PORT(mdev, port, -1); 1357 if (err) { 1358 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1359 port); 1360 goto err_set_port; 1361 } 1362 } 1363 err = mlx4_register_device(mdev); 1364 err_set_port: 1365 mutex_unlock(&priv->port_mutex); 1366 mlx4_start_sense(mdev); 1367 return err ? err : count; 1368 } 1369 1370 /* bond for multi-function device */ 1371 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1372 static int mlx4_mf_bond(struct mlx4_dev *dev) 1373 { 1374 int err = 0; 1375 int nvfs; 1376 struct mlx4_slaves_pport slaves_port1; 1377 struct mlx4_slaves_pport slaves_port2; 1378 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1379 1380 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1381 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1382 bitmap_and(slaves_port_1_2, 1383 slaves_port1.slaves, slaves_port2.slaves, 1384 dev->persist->num_vfs + 1); 1385 1386 /* only single port vfs are allowed */ 1387 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1388 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1389 return -EINVAL; 1390 } 1391 1392 /* number of virtual functions is number of total functions minus one 1393 * physical function for each port. 1394 */ 1395 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1396 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1397 1398 /* limit on maximum allowed VFs */ 1399 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1400 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1401 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1402 return -EINVAL; 1403 } 1404 1405 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1406 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1407 return -EINVAL; 1408 } 1409 1410 err = mlx4_bond_mac_table(dev); 1411 if (err) 1412 return err; 1413 err = mlx4_bond_vlan_table(dev); 1414 if (err) 1415 goto err1; 1416 err = mlx4_bond_fs_rules(dev); 1417 if (err) 1418 goto err2; 1419 1420 return 0; 1421 err2: 1422 (void)mlx4_unbond_vlan_table(dev); 1423 err1: 1424 (void)mlx4_unbond_mac_table(dev); 1425 return err; 1426 } 1427 1428 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1429 { 1430 int ret, ret1; 1431 1432 ret = mlx4_unbond_fs_rules(dev); 1433 if (ret) 1434 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1435 ret1 = mlx4_unbond_mac_table(dev); 1436 if (ret1) { 1437 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1438 ret = ret1; 1439 } 1440 ret1 = mlx4_unbond_vlan_table(dev); 1441 if (ret1) { 1442 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1443 ret = ret1; 1444 } 1445 return ret; 1446 } 1447 1448 int mlx4_bond(struct mlx4_dev *dev) 1449 { 1450 int ret = 0; 1451 struct mlx4_priv *priv = mlx4_priv(dev); 1452 1453 mutex_lock(&priv->bond_mutex); 1454 1455 if (!mlx4_is_bonded(dev)) { 1456 ret = mlx4_do_bond(dev, true); 1457 if (ret) 1458 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1459 if (!ret && mlx4_is_master(dev)) { 1460 ret = mlx4_mf_bond(dev); 1461 if (ret) { 1462 mlx4_err(dev, "bond for multifunction failed\n"); 1463 mlx4_do_bond(dev, false); 1464 } 1465 } 1466 } 1467 1468 mutex_unlock(&priv->bond_mutex); 1469 if (!ret) 1470 mlx4_dbg(dev, "Device is bonded\n"); 1471 1472 return ret; 1473 } 1474 EXPORT_SYMBOL_GPL(mlx4_bond); 1475 1476 int mlx4_unbond(struct mlx4_dev *dev) 1477 { 1478 int ret = 0; 1479 struct mlx4_priv *priv = mlx4_priv(dev); 1480 1481 mutex_lock(&priv->bond_mutex); 1482 1483 if (mlx4_is_bonded(dev)) { 1484 int ret2 = 0; 1485 1486 ret = mlx4_do_bond(dev, false); 1487 if (ret) 1488 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1489 if (mlx4_is_master(dev)) 1490 ret2 = mlx4_mf_unbond(dev); 1491 if (ret2) { 1492 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1493 ret = ret2; 1494 } 1495 } 1496 1497 mutex_unlock(&priv->bond_mutex); 1498 if (!ret) 1499 mlx4_dbg(dev, "Device is unbonded\n"); 1500 1501 return ret; 1502 } 1503 EXPORT_SYMBOL_GPL(mlx4_unbond); 1504 1505 1506 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1507 { 1508 u8 port1 = v2p->port1; 1509 u8 port2 = v2p->port2; 1510 struct mlx4_priv *priv = mlx4_priv(dev); 1511 int err; 1512 1513 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1514 return -EOPNOTSUPP; 1515 1516 mutex_lock(&priv->bond_mutex); 1517 1518 /* zero means keep current mapping for this port */ 1519 if (port1 == 0) 1520 port1 = priv->v2p.port1; 1521 if (port2 == 0) 1522 port2 = priv->v2p.port2; 1523 1524 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1525 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1526 (port1 == 2 && port2 == 1)) { 1527 /* besides boundary checks cross mapping makes 1528 * no sense and therefore not allowed */ 1529 err = -EINVAL; 1530 } else if ((port1 == priv->v2p.port1) && 1531 (port2 == priv->v2p.port2)) { 1532 err = 0; 1533 } else { 1534 err = mlx4_virt2phy_port_map(dev, port1, port2); 1535 if (!err) { 1536 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1537 port1, port2); 1538 priv->v2p.port1 = port1; 1539 priv->v2p.port2 = port2; 1540 } else { 1541 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1542 } 1543 } 1544 1545 mutex_unlock(&priv->bond_mutex); 1546 return err; 1547 } 1548 EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1549 1550 static int mlx4_load_fw(struct mlx4_dev *dev) 1551 { 1552 struct mlx4_priv *priv = mlx4_priv(dev); 1553 int err; 1554 1555 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1556 GFP_HIGHUSER | __GFP_NOWARN, 0); 1557 if (!priv->fw.fw_icm) { 1558 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1559 return -ENOMEM; 1560 } 1561 1562 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1563 if (err) { 1564 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1565 goto err_free; 1566 } 1567 1568 err = mlx4_RUN_FW(dev); 1569 if (err) { 1570 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1571 goto err_unmap_fa; 1572 } 1573 1574 return 0; 1575 1576 err_unmap_fa: 1577 mlx4_UNMAP_FA(dev); 1578 1579 err_free: 1580 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1581 return err; 1582 } 1583 1584 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1585 int cmpt_entry_sz) 1586 { 1587 struct mlx4_priv *priv = mlx4_priv(dev); 1588 int err; 1589 int num_eqs; 1590 1591 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1592 cmpt_base + 1593 ((u64) (MLX4_CMPT_TYPE_QP * 1594 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1595 cmpt_entry_sz, dev->caps.num_qps, 1596 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1597 0, 0); 1598 if (err) 1599 goto err; 1600 1601 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1602 cmpt_base + 1603 ((u64) (MLX4_CMPT_TYPE_SRQ * 1604 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1605 cmpt_entry_sz, dev->caps.num_srqs, 1606 dev->caps.reserved_srqs, 0, 0); 1607 if (err) 1608 goto err_qp; 1609 1610 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1611 cmpt_base + 1612 ((u64) (MLX4_CMPT_TYPE_CQ * 1613 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1614 cmpt_entry_sz, dev->caps.num_cqs, 1615 dev->caps.reserved_cqs, 0, 0); 1616 if (err) 1617 goto err_srq; 1618 1619 num_eqs = dev->phys_caps.num_phys_eqs; 1620 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1621 cmpt_base + 1622 ((u64) (MLX4_CMPT_TYPE_EQ * 1623 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1624 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1625 if (err) 1626 goto err_cq; 1627 1628 return 0; 1629 1630 err_cq: 1631 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1632 1633 err_srq: 1634 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1635 1636 err_qp: 1637 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1638 1639 err: 1640 return err; 1641 } 1642 1643 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1644 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1645 { 1646 struct mlx4_priv *priv = mlx4_priv(dev); 1647 u64 aux_pages; 1648 int num_eqs; 1649 int err; 1650 1651 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1652 if (err) { 1653 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1654 return err; 1655 } 1656 1657 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1658 (unsigned long long) icm_size >> 10, 1659 (unsigned long long) aux_pages << 2); 1660 1661 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1662 GFP_HIGHUSER | __GFP_NOWARN, 0); 1663 if (!priv->fw.aux_icm) { 1664 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1665 return -ENOMEM; 1666 } 1667 1668 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1669 if (err) { 1670 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1671 goto err_free_aux; 1672 } 1673 1674 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1675 if (err) { 1676 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1677 goto err_unmap_aux; 1678 } 1679 1680 1681 num_eqs = dev->phys_caps.num_phys_eqs; 1682 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1683 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1684 num_eqs, num_eqs, 0, 0); 1685 if (err) { 1686 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1687 goto err_unmap_cmpt; 1688 } 1689 1690 /* 1691 * Reserved MTT entries must be aligned up to a cacheline 1692 * boundary, since the FW will write to them, while the driver 1693 * writes to all other MTT entries. (The variable 1694 * dev->caps.mtt_entry_sz below is really the MTT segment 1695 * size, not the raw entry size) 1696 */ 1697 dev->caps.reserved_mtts = 1698 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1699 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1700 1701 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1702 init_hca->mtt_base, 1703 dev->caps.mtt_entry_sz, 1704 dev->caps.num_mtts, 1705 dev->caps.reserved_mtts, 1, 0); 1706 if (err) { 1707 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1708 goto err_unmap_eq; 1709 } 1710 1711 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1712 init_hca->dmpt_base, 1713 dev_cap->dmpt_entry_sz, 1714 dev->caps.num_mpts, 1715 dev->caps.reserved_mrws, 1, 1); 1716 if (err) { 1717 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1718 goto err_unmap_mtt; 1719 } 1720 1721 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1722 init_hca->qpc_base, 1723 dev_cap->qpc_entry_sz, 1724 dev->caps.num_qps, 1725 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1726 0, 0); 1727 if (err) { 1728 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1729 goto err_unmap_dmpt; 1730 } 1731 1732 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1733 init_hca->auxc_base, 1734 dev_cap->aux_entry_sz, 1735 dev->caps.num_qps, 1736 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1737 0, 0); 1738 if (err) { 1739 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1740 goto err_unmap_qp; 1741 } 1742 1743 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1744 init_hca->altc_base, 1745 dev_cap->altc_entry_sz, 1746 dev->caps.num_qps, 1747 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1748 0, 0); 1749 if (err) { 1750 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1751 goto err_unmap_auxc; 1752 } 1753 1754 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1755 init_hca->rdmarc_base, 1756 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1757 dev->caps.num_qps, 1758 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1759 0, 0); 1760 if (err) { 1761 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1762 goto err_unmap_altc; 1763 } 1764 1765 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1766 init_hca->cqc_base, 1767 dev_cap->cqc_entry_sz, 1768 dev->caps.num_cqs, 1769 dev->caps.reserved_cqs, 0, 0); 1770 if (err) { 1771 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1772 goto err_unmap_rdmarc; 1773 } 1774 1775 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1776 init_hca->srqc_base, 1777 dev_cap->srq_entry_sz, 1778 dev->caps.num_srqs, 1779 dev->caps.reserved_srqs, 0, 0); 1780 if (err) { 1781 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1782 goto err_unmap_cq; 1783 } 1784 1785 /* 1786 * For flow steering device managed mode it is required to use 1787 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1788 * required, but for simplicity just map the whole multicast 1789 * group table now. The table isn't very big and it's a lot 1790 * easier than trying to track ref counts. 1791 */ 1792 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1793 init_hca->mc_base, 1794 mlx4_get_mgm_entry_size(dev), 1795 dev->caps.num_mgms + dev->caps.num_amgms, 1796 dev->caps.num_mgms + dev->caps.num_amgms, 1797 0, 0); 1798 if (err) { 1799 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1800 goto err_unmap_srq; 1801 } 1802 1803 return 0; 1804 1805 err_unmap_srq: 1806 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1807 1808 err_unmap_cq: 1809 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1810 1811 err_unmap_rdmarc: 1812 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1813 1814 err_unmap_altc: 1815 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1816 1817 err_unmap_auxc: 1818 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1819 1820 err_unmap_qp: 1821 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1822 1823 err_unmap_dmpt: 1824 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1825 1826 err_unmap_mtt: 1827 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1828 1829 err_unmap_eq: 1830 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1831 1832 err_unmap_cmpt: 1833 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1834 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1835 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1836 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1837 1838 err_unmap_aux: 1839 mlx4_UNMAP_ICM_AUX(dev); 1840 1841 err_free_aux: 1842 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1843 1844 return err; 1845 } 1846 1847 static void mlx4_free_icms(struct mlx4_dev *dev) 1848 { 1849 struct mlx4_priv *priv = mlx4_priv(dev); 1850 1851 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1852 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1853 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1854 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1855 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1856 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1857 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1858 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1859 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1860 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1861 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1862 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1863 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1864 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1865 1866 mlx4_UNMAP_ICM_AUX(dev); 1867 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1868 } 1869 1870 static void mlx4_slave_exit(struct mlx4_dev *dev) 1871 { 1872 struct mlx4_priv *priv = mlx4_priv(dev); 1873 1874 mutex_lock(&priv->cmd.slave_cmd_mutex); 1875 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1876 MLX4_COMM_TIME)) 1877 mlx4_warn(dev, "Failed to close slave function\n"); 1878 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1879 } 1880 1881 static int map_bf_area(struct mlx4_dev *dev) 1882 { 1883 struct mlx4_priv *priv = mlx4_priv(dev); 1884 resource_size_t bf_start; 1885 resource_size_t bf_len; 1886 int err = 0; 1887 1888 if (!dev->caps.bf_reg_size) 1889 return -ENXIO; 1890 1891 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1892 (dev->caps.num_uars << PAGE_SHIFT); 1893 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1894 (dev->caps.num_uars << PAGE_SHIFT); 1895 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1896 if (!priv->bf_mapping) 1897 err = -ENOMEM; 1898 1899 return err; 1900 } 1901 1902 static void unmap_bf_area(struct mlx4_dev *dev) 1903 { 1904 if (mlx4_priv(dev)->bf_mapping) 1905 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1906 } 1907 1908 u64 mlx4_read_clock(struct mlx4_dev *dev) 1909 { 1910 u32 clockhi, clocklo, clockhi1; 1911 u64 cycles; 1912 int i; 1913 struct mlx4_priv *priv = mlx4_priv(dev); 1914 1915 for (i = 0; i < 10; i++) { 1916 clockhi = swab32(readl(priv->clock_mapping)); 1917 clocklo = swab32(readl(priv->clock_mapping + 4)); 1918 clockhi1 = swab32(readl(priv->clock_mapping)); 1919 if (clockhi == clockhi1) 1920 break; 1921 } 1922 1923 cycles = (u64) clockhi << 32 | (u64) clocklo; 1924 1925 return cycles; 1926 } 1927 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1928 1929 1930 static int map_internal_clock(struct mlx4_dev *dev) 1931 { 1932 struct mlx4_priv *priv = mlx4_priv(dev); 1933 1934 priv->clock_mapping = 1935 ioremap(pci_resource_start(dev->persist->pdev, 1936 priv->fw.clock_bar) + 1937 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1938 1939 if (!priv->clock_mapping) 1940 return -ENOMEM; 1941 1942 return 0; 1943 } 1944 1945 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1946 struct mlx4_clock_params *params) 1947 { 1948 struct mlx4_priv *priv = mlx4_priv(dev); 1949 1950 if (mlx4_is_slave(dev)) 1951 return -EOPNOTSUPP; 1952 1953 if (!params) 1954 return -EINVAL; 1955 1956 params->bar = priv->fw.clock_bar; 1957 params->offset = priv->fw.clock_offset; 1958 params->size = MLX4_CLOCK_SIZE; 1959 1960 return 0; 1961 } 1962 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1963 1964 static void unmap_internal_clock(struct mlx4_dev *dev) 1965 { 1966 struct mlx4_priv *priv = mlx4_priv(dev); 1967 1968 if (priv->clock_mapping) 1969 iounmap(priv->clock_mapping); 1970 } 1971 1972 static void mlx4_close_hca(struct mlx4_dev *dev) 1973 { 1974 unmap_internal_clock(dev); 1975 unmap_bf_area(dev); 1976 if (mlx4_is_slave(dev)) 1977 mlx4_slave_exit(dev); 1978 else { 1979 mlx4_CLOSE_HCA(dev, 0); 1980 mlx4_free_icms(dev); 1981 } 1982 } 1983 1984 static void mlx4_close_fw(struct mlx4_dev *dev) 1985 { 1986 if (!mlx4_is_slave(dev)) { 1987 mlx4_UNMAP_FA(dev); 1988 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1989 } 1990 } 1991 1992 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1993 { 1994 #define COMM_CHAN_OFFLINE_OFFSET 0x09 1995 1996 u32 comm_flags; 1997 u32 offline_bit; 1998 unsigned long end; 1999 struct mlx4_priv *priv = mlx4_priv(dev); 2000 2001 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2002 while (time_before(jiffies, end)) { 2003 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2004 MLX4_COMM_CHAN_FLAGS)); 2005 offline_bit = (comm_flags & 2006 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2007 if (!offline_bit) 2008 return 0; 2009 2010 /* If device removal has been requested, 2011 * do not continue retrying. 2012 */ 2013 if (dev->persist->interface_state & 2014 MLX4_INTERFACE_STATE_NOWAIT) 2015 break; 2016 2017 /* There are cases as part of AER/Reset flow that PF needs 2018 * around 100 msec to load. We therefore sleep for 100 msec 2019 * to allow other tasks to make use of that CPU during this 2020 * time interval. 2021 */ 2022 msleep(100); 2023 } 2024 mlx4_err(dev, "Communication channel is offline.\n"); 2025 return -EIO; 2026 } 2027 2028 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2029 { 2030 #define COMM_CHAN_RST_OFFSET 0x1e 2031 2032 struct mlx4_priv *priv = mlx4_priv(dev); 2033 u32 comm_rst; 2034 u32 comm_caps; 2035 2036 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2037 MLX4_COMM_CHAN_CAPS)); 2038 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2039 2040 if (comm_rst) 2041 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2042 } 2043 2044 static int mlx4_init_slave(struct mlx4_dev *dev) 2045 { 2046 struct mlx4_priv *priv = mlx4_priv(dev); 2047 u64 dma = (u64) priv->mfunc.vhcr_dma; 2048 int ret_from_reset = 0; 2049 u32 slave_read; 2050 u32 cmd_channel_ver; 2051 2052 if (atomic_read(&pf_loading)) { 2053 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2054 return -EPROBE_DEFER; 2055 } 2056 2057 mutex_lock(&priv->cmd.slave_cmd_mutex); 2058 priv->cmd.max_cmds = 1; 2059 if (mlx4_comm_check_offline(dev)) { 2060 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2061 goto err_offline; 2062 } 2063 2064 mlx4_reset_vf_support(dev); 2065 mlx4_warn(dev, "Sending reset\n"); 2066 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2067 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2068 /* if we are in the middle of flr the slave will try 2069 * NUM_OF_RESET_RETRIES times before leaving.*/ 2070 if (ret_from_reset) { 2071 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2072 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2073 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2074 return -EPROBE_DEFER; 2075 } else 2076 goto err; 2077 } 2078 2079 /* check the driver version - the slave I/F revision 2080 * must match the master's */ 2081 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2082 cmd_channel_ver = mlx4_comm_get_version(); 2083 2084 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2085 MLX4_COMM_GET_IF_REV(slave_read)) { 2086 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2087 goto err; 2088 } 2089 2090 mlx4_warn(dev, "Sending vhcr0\n"); 2091 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2092 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2093 goto err; 2094 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2095 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2096 goto err; 2097 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2098 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2099 goto err; 2100 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2101 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2102 goto err; 2103 2104 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2105 return 0; 2106 2107 err: 2108 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2109 err_offline: 2110 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2111 return -EIO; 2112 } 2113 2114 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2115 { 2116 int i; 2117 2118 for (i = 1; i <= dev->caps.num_ports; i++) { 2119 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2120 dev->caps.gid_table_len[i] = 2121 mlx4_get_slave_num_gids(dev, 0, i); 2122 else 2123 dev->caps.gid_table_len[i] = 1; 2124 dev->caps.pkey_table_len[i] = 2125 dev->phys_caps.pkey_phys_table_len[i] - 1; 2126 } 2127 } 2128 2129 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2130 { 2131 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2132 2133 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2134 i++) { 2135 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2136 break; 2137 } 2138 2139 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2140 } 2141 2142 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2143 { 2144 switch (dmfs_high_steer_mode) { 2145 case MLX4_STEERING_DMFS_A0_DEFAULT: 2146 return "default performance"; 2147 2148 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2149 return "dynamic hybrid mode"; 2150 2151 case MLX4_STEERING_DMFS_A0_STATIC: 2152 return "performance optimized for limited rule configuration (static)"; 2153 2154 case MLX4_STEERING_DMFS_A0_DISABLE: 2155 return "disabled performance optimized steering"; 2156 2157 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2158 return "performance optimized steering not supported"; 2159 2160 default: 2161 return "Unrecognized mode"; 2162 } 2163 } 2164 2165 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2166 2167 static void choose_steering_mode(struct mlx4_dev *dev, 2168 struct mlx4_dev_cap *dev_cap) 2169 { 2170 if (mlx4_log_num_mgm_entry_size <= 0) { 2171 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2172 if (dev->caps.dmfs_high_steer_mode == 2173 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2174 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2175 else 2176 dev->caps.dmfs_high_steer_mode = 2177 MLX4_STEERING_DMFS_A0_STATIC; 2178 } 2179 } 2180 2181 if (mlx4_log_num_mgm_entry_size <= 0 && 2182 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2183 (!mlx4_is_mfunc(dev) || 2184 (dev_cap->fs_max_num_qp_per_entry >= 2185 (dev->persist->num_vfs + 1))) && 2186 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2187 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2188 dev->oper_log_mgm_entry_size = 2189 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2190 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2191 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2192 dev->caps.fs_log_max_ucast_qp_range_size = 2193 dev_cap->fs_log_max_ucast_qp_range_size; 2194 } else { 2195 if (dev->caps.dmfs_high_steer_mode != 2196 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2197 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2198 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2199 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2200 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2201 else { 2202 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2203 2204 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2205 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2206 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2207 } 2208 dev->oper_log_mgm_entry_size = 2209 mlx4_log_num_mgm_entry_size > 0 ? 2210 mlx4_log_num_mgm_entry_size : 2211 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2212 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2213 } 2214 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2215 mlx4_steering_mode_str(dev->caps.steering_mode), 2216 dev->oper_log_mgm_entry_size, 2217 mlx4_log_num_mgm_entry_size); 2218 } 2219 2220 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2221 struct mlx4_dev_cap *dev_cap) 2222 { 2223 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2224 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2225 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2226 else 2227 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2228 2229 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2230 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2231 } 2232 2233 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2234 { 2235 int i; 2236 struct mlx4_port_cap port_cap; 2237 2238 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2239 return -EINVAL; 2240 2241 for (i = 1; i <= dev->caps.num_ports; i++) { 2242 if (mlx4_dev_port(dev, i, &port_cap)) { 2243 mlx4_err(dev, 2244 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 2245 } else if ((dev->caps.dmfs_high_steer_mode != 2246 MLX4_STEERING_DMFS_A0_DEFAULT) && 2247 (port_cap.dmfs_optimized_state == 2248 !!(dev->caps.dmfs_high_steer_mode == 2249 MLX4_STEERING_DMFS_A0_DISABLE))) { 2250 mlx4_err(dev, 2251 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2252 dmfs_high_rate_steering_mode_str( 2253 dev->caps.dmfs_high_steer_mode), 2254 (port_cap.dmfs_optimized_state ? 2255 "enabled" : "disabled")); 2256 } 2257 } 2258 2259 return 0; 2260 } 2261 2262 static int mlx4_init_fw(struct mlx4_dev *dev) 2263 { 2264 struct mlx4_mod_stat_cfg mlx4_cfg; 2265 int err = 0; 2266 2267 if (!mlx4_is_slave(dev)) { 2268 err = mlx4_QUERY_FW(dev); 2269 if (err) { 2270 if (err == -EACCES) 2271 mlx4_info(dev, "non-primary physical function, skipping\n"); 2272 else 2273 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2274 return err; 2275 } 2276 2277 err = mlx4_load_fw(dev); 2278 if (err) { 2279 mlx4_err(dev, "Failed to start FW, aborting\n"); 2280 return err; 2281 } 2282 2283 mlx4_cfg.log_pg_sz_m = 1; 2284 mlx4_cfg.log_pg_sz = 0; 2285 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2286 if (err) 2287 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2288 } 2289 2290 return err; 2291 } 2292 2293 static int mlx4_init_hca(struct mlx4_dev *dev) 2294 { 2295 struct mlx4_priv *priv = mlx4_priv(dev); 2296 struct mlx4_adapter adapter; 2297 struct mlx4_dev_cap dev_cap; 2298 struct mlx4_profile profile; 2299 struct mlx4_init_hca_param init_hca; 2300 u64 icm_size; 2301 struct mlx4_config_dev_params params; 2302 int err; 2303 2304 if (!mlx4_is_slave(dev)) { 2305 err = mlx4_dev_cap(dev, &dev_cap); 2306 if (err) { 2307 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2308 return err; 2309 } 2310 2311 choose_steering_mode(dev, &dev_cap); 2312 choose_tunnel_offload_mode(dev, &dev_cap); 2313 2314 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2315 mlx4_is_master(dev)) 2316 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2317 2318 err = mlx4_get_phys_port_id(dev); 2319 if (err) 2320 mlx4_err(dev, "Fail to get physical port id\n"); 2321 2322 if (mlx4_is_master(dev)) 2323 mlx4_parav_master_pf_caps(dev); 2324 2325 if (mlx4_low_memory_profile()) { 2326 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2327 profile = low_mem_profile; 2328 } else { 2329 profile = default_profile; 2330 } 2331 if (dev->caps.steering_mode == 2332 MLX4_STEERING_MODE_DEVICE_MANAGED) 2333 profile.num_mcg = MLX4_FS_NUM_MCG; 2334 2335 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 2336 &init_hca); 2337 if ((long long) icm_size < 0) { 2338 err = icm_size; 2339 return err; 2340 } 2341 2342 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2343 2344 if (enable_4k_uar || !dev->persist->num_vfs) { 2345 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) + 2346 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2347 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2348 } else { 2349 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2350 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2351 } 2352 2353 init_hca.mw_enabled = 0; 2354 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2355 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2356 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2357 2358 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 2359 if (err) 2360 return err; 2361 2362 err = mlx4_INIT_HCA(dev, &init_hca); 2363 if (err) { 2364 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2365 goto err_free_icm; 2366 } 2367 2368 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2369 err = mlx4_query_func(dev, &dev_cap); 2370 if (err < 0) { 2371 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2372 goto err_close; 2373 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2374 dev->caps.num_eqs = dev_cap.max_eqs; 2375 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 2376 dev->caps.reserved_uars = dev_cap.reserved_uars; 2377 } 2378 } 2379 2380 /* 2381 * If TS is supported by FW 2382 * read HCA frequency by QUERY_HCA command 2383 */ 2384 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2385 memset(&init_hca, 0, sizeof(init_hca)); 2386 err = mlx4_QUERY_HCA(dev, &init_hca); 2387 if (err) { 2388 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2389 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2390 } else { 2391 dev->caps.hca_core_clock = 2392 init_hca.hca_core_clock; 2393 } 2394 2395 /* In case we got HCA frequency 0 - disable timestamping 2396 * to avoid dividing by zero 2397 */ 2398 if (!dev->caps.hca_core_clock) { 2399 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2400 mlx4_err(dev, 2401 "HCA frequency is 0 - timestamping is not supported\n"); 2402 } else if (map_internal_clock(dev)) { 2403 /* 2404 * Map internal clock, 2405 * in case of failure disable timestamping 2406 */ 2407 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2408 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2409 } 2410 } 2411 2412 if (dev->caps.dmfs_high_steer_mode != 2413 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2414 if (mlx4_validate_optimized_steering(dev)) 2415 mlx4_warn(dev, "Optimized steering validation failed\n"); 2416 2417 if (dev->caps.dmfs_high_steer_mode == 2418 MLX4_STEERING_DMFS_A0_DISABLE) { 2419 dev->caps.dmfs_high_rate_qpn_base = 2420 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2421 dev->caps.dmfs_high_rate_qpn_range = 2422 MLX4_A0_STEERING_TABLE_SIZE; 2423 } 2424 2425 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2426 dmfs_high_rate_steering_mode_str( 2427 dev->caps.dmfs_high_steer_mode)); 2428 } 2429 } else { 2430 err = mlx4_init_slave(dev); 2431 if (err) { 2432 if (err != -EPROBE_DEFER) 2433 mlx4_err(dev, "Failed to initialize slave\n"); 2434 return err; 2435 } 2436 2437 err = mlx4_slave_cap(dev); 2438 if (err) { 2439 mlx4_err(dev, "Failed to obtain slave caps\n"); 2440 goto err_close; 2441 } 2442 } 2443 2444 if (map_bf_area(dev)) 2445 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2446 2447 /*Only the master set the ports, all the rest got it from it.*/ 2448 if (!mlx4_is_slave(dev)) 2449 mlx4_set_port_mask(dev); 2450 2451 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2452 if (err) { 2453 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2454 goto unmap_bf; 2455 } 2456 2457 /* Query CONFIG_DEV parameters */ 2458 err = mlx4_config_dev_retrieval(dev, ¶ms); 2459 if (err && err != -EOPNOTSUPP) { 2460 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2461 } else if (!err) { 2462 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2463 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2464 } 2465 priv->eq_table.inta_pin = adapter.inta_pin; 2466 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2467 2468 return 0; 2469 2470 unmap_bf: 2471 unmap_internal_clock(dev); 2472 unmap_bf_area(dev); 2473 2474 if (mlx4_is_slave(dev)) 2475 mlx4_slave_destroy_special_qp_cap(dev); 2476 2477 err_close: 2478 if (mlx4_is_slave(dev)) 2479 mlx4_slave_exit(dev); 2480 else 2481 mlx4_CLOSE_HCA(dev, 0); 2482 2483 err_free_icm: 2484 if (!mlx4_is_slave(dev)) 2485 mlx4_free_icms(dev); 2486 2487 return err; 2488 } 2489 2490 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2491 { 2492 struct mlx4_priv *priv = mlx4_priv(dev); 2493 int nent_pow2; 2494 2495 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2496 return -ENOENT; 2497 2498 if (!dev->caps.max_counters) 2499 return -ENOSPC; 2500 2501 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2502 /* reserve last counter index for sink counter */ 2503 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2504 nent_pow2 - 1, 0, 2505 nent_pow2 - dev->caps.max_counters + 1); 2506 } 2507 2508 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2509 { 2510 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2511 return; 2512 2513 if (!dev->caps.max_counters) 2514 return; 2515 2516 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2517 } 2518 2519 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2520 { 2521 struct mlx4_priv *priv = mlx4_priv(dev); 2522 int port; 2523 2524 for (port = 0; port < dev->caps.num_ports; port++) 2525 if (priv->def_counter[port] != -1) 2526 mlx4_counter_free(dev, priv->def_counter[port]); 2527 } 2528 2529 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2530 { 2531 struct mlx4_priv *priv = mlx4_priv(dev); 2532 int port, err = 0; 2533 u32 idx; 2534 2535 for (port = 0; port < dev->caps.num_ports; port++) 2536 priv->def_counter[port] = -1; 2537 2538 for (port = 0; port < dev->caps.num_ports; port++) { 2539 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2540 2541 if (!err || err == -ENOSPC) { 2542 priv->def_counter[port] = idx; 2543 } else if (err == -ENOENT) { 2544 err = 0; 2545 continue; 2546 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2547 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2548 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2549 MLX4_SINK_COUNTER_INDEX(dev)); 2550 err = 0; 2551 } else { 2552 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2553 __func__, port + 1, err); 2554 mlx4_cleanup_default_counters(dev); 2555 return err; 2556 } 2557 2558 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2559 __func__, priv->def_counter[port], port + 1); 2560 } 2561 2562 return err; 2563 } 2564 2565 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2566 { 2567 struct mlx4_priv *priv = mlx4_priv(dev); 2568 2569 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2570 return -ENOENT; 2571 2572 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2573 if (*idx == -1) { 2574 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2575 return -ENOSPC; 2576 } 2577 2578 return 0; 2579 } 2580 2581 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2582 { 2583 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2584 u64 out_param; 2585 int err; 2586 2587 if (mlx4_is_mfunc(dev)) { 2588 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2589 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2590 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2591 if (!err) 2592 *idx = get_param_l(&out_param); 2593 2594 return err; 2595 } 2596 return __mlx4_counter_alloc(dev, idx); 2597 } 2598 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2599 2600 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2601 u8 counter_index) 2602 { 2603 struct mlx4_cmd_mailbox *if_stat_mailbox; 2604 int err; 2605 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2606 2607 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2608 if (IS_ERR(if_stat_mailbox)) 2609 return PTR_ERR(if_stat_mailbox); 2610 2611 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2612 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2613 MLX4_CMD_NATIVE); 2614 2615 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2616 return err; 2617 } 2618 2619 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2620 { 2621 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2622 return; 2623 2624 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2625 return; 2626 2627 __mlx4_clear_if_stat(dev, idx); 2628 2629 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2630 return; 2631 } 2632 2633 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2634 { 2635 u64 in_param = 0; 2636 2637 if (mlx4_is_mfunc(dev)) { 2638 set_param_l(&in_param, idx); 2639 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2640 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2641 MLX4_CMD_WRAPPED); 2642 return; 2643 } 2644 __mlx4_counter_free(dev, idx); 2645 } 2646 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2647 2648 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2649 { 2650 struct mlx4_priv *priv = mlx4_priv(dev); 2651 2652 return priv->def_counter[port - 1]; 2653 } 2654 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2655 2656 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2657 { 2658 struct mlx4_priv *priv = mlx4_priv(dev); 2659 2660 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2661 } 2662 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2663 2664 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2665 { 2666 struct mlx4_priv *priv = mlx4_priv(dev); 2667 2668 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2669 } 2670 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2671 2672 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2673 { 2674 struct mlx4_priv *priv = mlx4_priv(dev); 2675 __be64 guid; 2676 2677 /* hw GUID */ 2678 if (entry == 0) 2679 return; 2680 2681 get_random_bytes((char *)&guid, sizeof(guid)); 2682 guid &= ~(cpu_to_be64(1ULL << 56)); 2683 guid |= cpu_to_be64(1ULL << 57); 2684 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2685 } 2686 2687 static int mlx4_setup_hca(struct mlx4_dev *dev) 2688 { 2689 struct mlx4_priv *priv = mlx4_priv(dev); 2690 int err; 2691 int port; 2692 __be32 ib_port_default_caps; 2693 2694 err = mlx4_init_uar_table(dev); 2695 if (err) { 2696 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2697 return err; 2698 } 2699 2700 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2701 if (err) { 2702 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2703 goto err_uar_table_free; 2704 } 2705 2706 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2707 if (!priv->kar) { 2708 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2709 err = -ENOMEM; 2710 goto err_uar_free; 2711 } 2712 2713 err = mlx4_init_pd_table(dev); 2714 if (err) { 2715 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2716 goto err_kar_unmap; 2717 } 2718 2719 err = mlx4_init_xrcd_table(dev); 2720 if (err) { 2721 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2722 goto err_pd_table_free; 2723 } 2724 2725 err = mlx4_init_mr_table(dev); 2726 if (err) { 2727 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2728 goto err_xrcd_table_free; 2729 } 2730 2731 if (!mlx4_is_slave(dev)) { 2732 err = mlx4_init_mcg_table(dev); 2733 if (err) { 2734 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2735 goto err_mr_table_free; 2736 } 2737 err = mlx4_config_mad_demux(dev); 2738 if (err) { 2739 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2740 goto err_mcg_table_free; 2741 } 2742 } 2743 2744 err = mlx4_init_eq_table(dev); 2745 if (err) { 2746 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2747 goto err_mcg_table_free; 2748 } 2749 2750 err = mlx4_cmd_use_events(dev); 2751 if (err) { 2752 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2753 goto err_eq_table_free; 2754 } 2755 2756 err = mlx4_NOP(dev); 2757 if (err) { 2758 if (dev->flags & MLX4_FLAG_MSI_X) { 2759 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2760 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2761 mlx4_warn(dev, "Trying again without MSI-X\n"); 2762 } else { 2763 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2764 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2765 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2766 } 2767 2768 goto err_cmd_poll; 2769 } 2770 2771 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2772 2773 err = mlx4_init_cq_table(dev); 2774 if (err) { 2775 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2776 goto err_cmd_poll; 2777 } 2778 2779 err = mlx4_init_srq_table(dev); 2780 if (err) { 2781 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2782 goto err_cq_table_free; 2783 } 2784 2785 err = mlx4_init_qp_table(dev); 2786 if (err) { 2787 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2788 goto err_srq_table_free; 2789 } 2790 2791 if (!mlx4_is_slave(dev)) { 2792 err = mlx4_init_counters_table(dev); 2793 if (err && err != -ENOENT) { 2794 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2795 goto err_qp_table_free; 2796 } 2797 } 2798 2799 err = mlx4_allocate_default_counters(dev); 2800 if (err) { 2801 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2802 goto err_counters_table_free; 2803 } 2804 2805 if (!mlx4_is_slave(dev)) { 2806 for (port = 1; port <= dev->caps.num_ports; port++) { 2807 ib_port_default_caps = 0; 2808 err = mlx4_get_port_ib_caps(dev, port, 2809 &ib_port_default_caps); 2810 if (err) 2811 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2812 port, err); 2813 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2814 2815 /* initialize per-slave default ib port capabilities */ 2816 if (mlx4_is_master(dev)) { 2817 int i; 2818 for (i = 0; i < dev->num_slaves; i++) { 2819 if (i == mlx4_master_func_num(dev)) 2820 continue; 2821 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2822 ib_port_default_caps; 2823 } 2824 } 2825 2826 if (mlx4_is_mfunc(dev)) 2827 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2828 else 2829 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2830 2831 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2832 dev->caps.pkey_table_len[port] : -1); 2833 if (err) { 2834 mlx4_err(dev, "Failed to set port %d, aborting\n", 2835 port); 2836 goto err_default_countes_free; 2837 } 2838 } 2839 } 2840 2841 return 0; 2842 2843 err_default_countes_free: 2844 mlx4_cleanup_default_counters(dev); 2845 2846 err_counters_table_free: 2847 if (!mlx4_is_slave(dev)) 2848 mlx4_cleanup_counters_table(dev); 2849 2850 err_qp_table_free: 2851 mlx4_cleanup_qp_table(dev); 2852 2853 err_srq_table_free: 2854 mlx4_cleanup_srq_table(dev); 2855 2856 err_cq_table_free: 2857 mlx4_cleanup_cq_table(dev); 2858 2859 err_cmd_poll: 2860 mlx4_cmd_use_polling(dev); 2861 2862 err_eq_table_free: 2863 mlx4_cleanup_eq_table(dev); 2864 2865 err_mcg_table_free: 2866 if (!mlx4_is_slave(dev)) 2867 mlx4_cleanup_mcg_table(dev); 2868 2869 err_mr_table_free: 2870 mlx4_cleanup_mr_table(dev); 2871 2872 err_xrcd_table_free: 2873 mlx4_cleanup_xrcd_table(dev); 2874 2875 err_pd_table_free: 2876 mlx4_cleanup_pd_table(dev); 2877 2878 err_kar_unmap: 2879 iounmap(priv->kar); 2880 2881 err_uar_free: 2882 mlx4_uar_free(dev, &priv->driver_uar); 2883 2884 err_uar_table_free: 2885 mlx4_cleanup_uar_table(dev); 2886 return err; 2887 } 2888 2889 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2890 { 2891 int requested_cpu = 0; 2892 struct mlx4_priv *priv = mlx4_priv(dev); 2893 struct mlx4_eq *eq; 2894 int off = 0; 2895 int i; 2896 2897 if (eqn > dev->caps.num_comp_vectors) 2898 return -EINVAL; 2899 2900 for (i = 1; i < port; i++) 2901 off += mlx4_get_eqs_per_port(dev, i); 2902 2903 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2904 2905 /* Meaning EQs are shared, and this call comes from the second port */ 2906 if (requested_cpu < 0) 2907 return 0; 2908 2909 eq = &priv->eq_table.eq[eqn]; 2910 2911 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2912 return -ENOMEM; 2913 2914 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2915 2916 return 0; 2917 } 2918 2919 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2920 { 2921 struct mlx4_priv *priv = mlx4_priv(dev); 2922 struct msix_entry *entries; 2923 int i; 2924 int port = 0; 2925 2926 if (msi_x) { 2927 int nreq = min3(dev->caps.num_ports * 2928 (int)num_online_cpus() + 1, 2929 dev->caps.num_eqs - dev->caps.reserved_eqs, 2930 MAX_MSIX); 2931 2932 if (msi_x > 1) 2933 nreq = min_t(int, nreq, msi_x); 2934 2935 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2936 if (!entries) 2937 goto no_msi; 2938 2939 for (i = 0; i < nreq; ++i) 2940 entries[i].entry = i; 2941 2942 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2943 nreq); 2944 2945 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2946 kfree(entries); 2947 goto no_msi; 2948 } 2949 /* 1 is reserved for events (asyncrounous EQ) */ 2950 dev->caps.num_comp_vectors = nreq - 1; 2951 2952 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2953 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2954 dev->caps.num_ports); 2955 2956 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2957 if (i == MLX4_EQ_ASYNC) 2958 continue; 2959 2960 priv->eq_table.eq[i].irq = 2961 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2962 2963 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2964 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2965 dev->caps.num_ports); 2966 /* We don't set affinity hint when there 2967 * aren't enough EQs 2968 */ 2969 } else { 2970 set_bit(port, 2971 priv->eq_table.eq[i].actv_ports.ports); 2972 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2973 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2974 i); 2975 } 2976 /* We divide the Eqs evenly between the two ports. 2977 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2978 * refers to the number of Eqs per port 2979 * (i.e eqs_per_port). Theoretically, we would like to 2980 * write something like (i + 1) % eqs_per_port == 0. 2981 * However, since there's an asynchronous Eq, we have 2982 * to skip over it by comparing this condition to 2983 * !!((i + 1) > MLX4_EQ_ASYNC). 2984 */ 2985 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 2986 ((i + 1) % 2987 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 2988 !!((i + 1) > MLX4_EQ_ASYNC)) 2989 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 2990 * everything is shared anyway. 2991 */ 2992 port++; 2993 } 2994 2995 dev->flags |= MLX4_FLAG_MSI_X; 2996 2997 kfree(entries); 2998 return; 2999 } 3000 3001 no_msi: 3002 dev->caps.num_comp_vectors = 1; 3003 3004 BUG_ON(MLX4_EQ_ASYNC >= 2); 3005 for (i = 0; i < 2; ++i) { 3006 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3007 if (i != MLX4_EQ_ASYNC) { 3008 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3009 dev->caps.num_ports); 3010 } 3011 } 3012 } 3013 3014 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3015 { 3016 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3017 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3018 int err; 3019 3020 err = devlink_port_register(devlink, &info->devlink_port, port); 3021 if (err) 3022 return err; 3023 3024 info->dev = dev; 3025 info->port = port; 3026 if (!mlx4_is_slave(dev)) { 3027 mlx4_init_mac_table(dev, &info->mac_table); 3028 mlx4_init_vlan_table(dev, &info->vlan_table); 3029 mlx4_init_roce_gid_table(dev, &info->gid_table); 3030 info->base_qpn = mlx4_get_base_qpn(dev, port); 3031 } 3032 3033 sprintf(info->dev_name, "mlx4_port%d", port); 3034 info->port_attr.attr.name = info->dev_name; 3035 if (mlx4_is_mfunc(dev)) { 3036 info->port_attr.attr.mode = 0444; 3037 } else { 3038 info->port_attr.attr.mode = 0644; 3039 info->port_attr.store = set_port_type; 3040 } 3041 info->port_attr.show = show_port_type; 3042 sysfs_attr_init(&info->port_attr.attr); 3043 3044 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3045 if (err) { 3046 mlx4_err(dev, "Failed to create file for port %d\n", port); 3047 devlink_port_unregister(&info->devlink_port); 3048 info->port = -1; 3049 return err; 3050 } 3051 3052 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3053 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3054 if (mlx4_is_mfunc(dev)) { 3055 info->port_mtu_attr.attr.mode = 0444; 3056 } else { 3057 info->port_mtu_attr.attr.mode = 0644; 3058 info->port_mtu_attr.store = set_port_ib_mtu; 3059 } 3060 info->port_mtu_attr.show = show_port_ib_mtu; 3061 sysfs_attr_init(&info->port_mtu_attr.attr); 3062 3063 err = device_create_file(&dev->persist->pdev->dev, 3064 &info->port_mtu_attr); 3065 if (err) { 3066 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3067 device_remove_file(&info->dev->persist->pdev->dev, 3068 &info->port_attr); 3069 devlink_port_unregister(&info->devlink_port); 3070 info->port = -1; 3071 return err; 3072 } 3073 3074 return 0; 3075 } 3076 3077 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3078 { 3079 if (info->port < 0) 3080 return; 3081 3082 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3083 device_remove_file(&info->dev->persist->pdev->dev, 3084 &info->port_mtu_attr); 3085 devlink_port_unregister(&info->devlink_port); 3086 3087 #ifdef CONFIG_RFS_ACCEL 3088 free_irq_cpu_rmap(info->rmap); 3089 info->rmap = NULL; 3090 #endif 3091 } 3092 3093 static int mlx4_init_steering(struct mlx4_dev *dev) 3094 { 3095 struct mlx4_priv *priv = mlx4_priv(dev); 3096 int num_entries = dev->caps.num_ports; 3097 int i, j; 3098 3099 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3100 GFP_KERNEL); 3101 if (!priv->steer) 3102 return -ENOMEM; 3103 3104 for (i = 0; i < num_entries; i++) 3105 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3106 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3107 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3108 } 3109 return 0; 3110 } 3111 3112 static void mlx4_clear_steering(struct mlx4_dev *dev) 3113 { 3114 struct mlx4_priv *priv = mlx4_priv(dev); 3115 struct mlx4_steer_index *entry, *tmp_entry; 3116 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3117 int num_entries = dev->caps.num_ports; 3118 int i, j; 3119 3120 for (i = 0; i < num_entries; i++) { 3121 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3122 list_for_each_entry_safe(pqp, tmp_pqp, 3123 &priv->steer[i].promisc_qps[j], 3124 list) { 3125 list_del(&pqp->list); 3126 kfree(pqp); 3127 } 3128 list_for_each_entry_safe(entry, tmp_entry, 3129 &priv->steer[i].steer_entries[j], 3130 list) { 3131 list_del(&entry->list); 3132 list_for_each_entry_safe(pqp, tmp_pqp, 3133 &entry->duplicates, 3134 list) { 3135 list_del(&pqp->list); 3136 kfree(pqp); 3137 } 3138 kfree(entry); 3139 } 3140 } 3141 } 3142 kfree(priv->steer); 3143 } 3144 3145 static int extended_func_num(struct pci_dev *pdev) 3146 { 3147 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3148 } 3149 3150 #define MLX4_OWNER_BASE 0x8069c 3151 #define MLX4_OWNER_SIZE 4 3152 3153 static int mlx4_get_ownership(struct mlx4_dev *dev) 3154 { 3155 void __iomem *owner; 3156 u32 ret; 3157 3158 if (pci_channel_offline(dev->persist->pdev)) 3159 return -EIO; 3160 3161 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3162 MLX4_OWNER_BASE, 3163 MLX4_OWNER_SIZE); 3164 if (!owner) { 3165 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3166 return -ENOMEM; 3167 } 3168 3169 ret = readl(owner); 3170 iounmap(owner); 3171 return (int) !!ret; 3172 } 3173 3174 static void mlx4_free_ownership(struct mlx4_dev *dev) 3175 { 3176 void __iomem *owner; 3177 3178 if (pci_channel_offline(dev->persist->pdev)) 3179 return; 3180 3181 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3182 MLX4_OWNER_BASE, 3183 MLX4_OWNER_SIZE); 3184 if (!owner) { 3185 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3186 return; 3187 } 3188 writel(0, owner); 3189 msleep(1000); 3190 iounmap(owner); 3191 } 3192 3193 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3194 !!((flags) & MLX4_FLAG_MASTER)) 3195 3196 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3197 u8 total_vfs, int existing_vfs, int reset_flow) 3198 { 3199 u64 dev_flags = dev->flags; 3200 int err = 0; 3201 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3202 MLX4_MAX_NUM_VF); 3203 3204 if (reset_flow) { 3205 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3206 GFP_KERNEL); 3207 if (!dev->dev_vfs) 3208 goto free_mem; 3209 return dev_flags; 3210 } 3211 3212 atomic_inc(&pf_loading); 3213 if (dev->flags & MLX4_FLAG_SRIOV) { 3214 if (existing_vfs != total_vfs) { 3215 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3216 existing_vfs, total_vfs); 3217 total_vfs = existing_vfs; 3218 } 3219 } 3220 3221 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3222 if (NULL == dev->dev_vfs) { 3223 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3224 goto disable_sriov; 3225 } 3226 3227 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3228 if (total_vfs > fw_enabled_sriov_vfs) { 3229 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3230 total_vfs, fw_enabled_sriov_vfs); 3231 err = -ENOMEM; 3232 goto disable_sriov; 3233 } 3234 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3235 err = pci_enable_sriov(pdev, total_vfs); 3236 } 3237 if (err) { 3238 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3239 err); 3240 goto disable_sriov; 3241 } else { 3242 mlx4_warn(dev, "Running in master mode\n"); 3243 dev_flags |= MLX4_FLAG_SRIOV | 3244 MLX4_FLAG_MASTER; 3245 dev_flags &= ~MLX4_FLAG_SLAVE; 3246 dev->persist->num_vfs = total_vfs; 3247 } 3248 return dev_flags; 3249 3250 disable_sriov: 3251 atomic_dec(&pf_loading); 3252 free_mem: 3253 dev->persist->num_vfs = 0; 3254 kfree(dev->dev_vfs); 3255 dev->dev_vfs = NULL; 3256 return dev_flags & ~MLX4_FLAG_MASTER; 3257 } 3258 3259 enum { 3260 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3261 }; 3262 3263 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3264 int *nvfs) 3265 { 3266 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3267 /* Checking for 64 VFs as a limitation of CX2 */ 3268 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3269 requested_vfs >= 64) { 3270 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3271 requested_vfs); 3272 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3273 } 3274 return 0; 3275 } 3276 3277 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3278 { 3279 struct pci_dev *pdev = dev->persist->pdev; 3280 int err = 0; 3281 3282 mutex_lock(&dev->persist->pci_status_mutex); 3283 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3284 err = pci_enable_device(pdev); 3285 if (!err) 3286 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3287 } 3288 mutex_unlock(&dev->persist->pci_status_mutex); 3289 3290 return err; 3291 } 3292 3293 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3294 { 3295 struct pci_dev *pdev = dev->persist->pdev; 3296 3297 mutex_lock(&dev->persist->pci_status_mutex); 3298 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3299 pci_disable_device(pdev); 3300 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3301 } 3302 mutex_unlock(&dev->persist->pci_status_mutex); 3303 } 3304 3305 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3306 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3307 int reset_flow) 3308 { 3309 struct mlx4_dev *dev; 3310 unsigned sum = 0; 3311 int err; 3312 int port; 3313 int i; 3314 struct mlx4_dev_cap *dev_cap = NULL; 3315 int existing_vfs = 0; 3316 3317 dev = &priv->dev; 3318 3319 INIT_LIST_HEAD(&priv->ctx_list); 3320 spin_lock_init(&priv->ctx_lock); 3321 3322 mutex_init(&priv->port_mutex); 3323 mutex_init(&priv->bond_mutex); 3324 3325 INIT_LIST_HEAD(&priv->pgdir_list); 3326 mutex_init(&priv->pgdir_mutex); 3327 spin_lock_init(&priv->cmd.context_lock); 3328 3329 INIT_LIST_HEAD(&priv->bf_list); 3330 mutex_init(&priv->bf_mutex); 3331 3332 dev->rev_id = pdev->revision; 3333 dev->numa_node = dev_to_node(&pdev->dev); 3334 3335 /* Detect if this device is a virtual function */ 3336 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3337 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3338 dev->flags |= MLX4_FLAG_SLAVE; 3339 } else { 3340 /* We reset the device and enable SRIOV only for physical 3341 * devices. Try to claim ownership on the device; 3342 * if already taken, skip -- do not allow multiple PFs */ 3343 err = mlx4_get_ownership(dev); 3344 if (err) { 3345 if (err < 0) 3346 return err; 3347 else { 3348 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3349 return -EINVAL; 3350 } 3351 } 3352 3353 atomic_set(&priv->opreq_count, 0); 3354 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3355 3356 /* 3357 * Now reset the HCA before we touch the PCI capabilities or 3358 * attempt a firmware command, since a boot ROM may have left 3359 * the HCA in an undefined state. 3360 */ 3361 err = mlx4_reset(dev); 3362 if (err) { 3363 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3364 goto err_sriov; 3365 } 3366 3367 if (total_vfs) { 3368 dev->flags = MLX4_FLAG_MASTER; 3369 existing_vfs = pci_num_vf(pdev); 3370 if (existing_vfs) 3371 dev->flags |= MLX4_FLAG_SRIOV; 3372 dev->persist->num_vfs = total_vfs; 3373 } 3374 } 3375 3376 /* on load remove any previous indication of internal error, 3377 * device is up. 3378 */ 3379 dev->persist->state = MLX4_DEVICE_STATE_UP; 3380 3381 slave_start: 3382 err = mlx4_cmd_init(dev); 3383 if (err) { 3384 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3385 goto err_sriov; 3386 } 3387 3388 /* In slave functions, the communication channel must be initialized 3389 * before posting commands. Also, init num_slaves before calling 3390 * mlx4_init_hca */ 3391 if (mlx4_is_mfunc(dev)) { 3392 if (mlx4_is_master(dev)) { 3393 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3394 3395 } else { 3396 dev->num_slaves = 0; 3397 err = mlx4_multi_func_init(dev); 3398 if (err) { 3399 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3400 goto err_cmd; 3401 } 3402 } 3403 } 3404 3405 err = mlx4_init_fw(dev); 3406 if (err) { 3407 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3408 goto err_mfunc; 3409 } 3410 3411 if (mlx4_is_master(dev)) { 3412 /* when we hit the goto slave_start below, dev_cap already initialized */ 3413 if (!dev_cap) { 3414 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3415 3416 if (!dev_cap) { 3417 err = -ENOMEM; 3418 goto err_fw; 3419 } 3420 3421 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3422 if (err) { 3423 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3424 goto err_fw; 3425 } 3426 3427 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3428 goto err_fw; 3429 3430 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3431 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3432 total_vfs, 3433 existing_vfs, 3434 reset_flow); 3435 3436 mlx4_close_fw(dev); 3437 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3438 dev->flags = dev_flags; 3439 if (!SRIOV_VALID_STATE(dev->flags)) { 3440 mlx4_err(dev, "Invalid SRIOV state\n"); 3441 goto err_sriov; 3442 } 3443 err = mlx4_reset(dev); 3444 if (err) { 3445 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3446 goto err_sriov; 3447 } 3448 goto slave_start; 3449 } 3450 } else { 3451 /* Legacy mode FW requires SRIOV to be enabled before 3452 * doing QUERY_DEV_CAP, since max_eq's value is different if 3453 * SRIOV is enabled. 3454 */ 3455 memset(dev_cap, 0, sizeof(*dev_cap)); 3456 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3457 if (err) { 3458 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3459 goto err_fw; 3460 } 3461 3462 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3463 goto err_fw; 3464 } 3465 } 3466 3467 err = mlx4_init_hca(dev); 3468 if (err) { 3469 if (err == -EACCES) { 3470 /* Not primary Physical function 3471 * Running in slave mode */ 3472 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3473 /* We're not a PF */ 3474 if (dev->flags & MLX4_FLAG_SRIOV) { 3475 if (!existing_vfs) 3476 pci_disable_sriov(pdev); 3477 if (mlx4_is_master(dev) && !reset_flow) 3478 atomic_dec(&pf_loading); 3479 dev->flags &= ~MLX4_FLAG_SRIOV; 3480 } 3481 if (!mlx4_is_slave(dev)) 3482 mlx4_free_ownership(dev); 3483 dev->flags |= MLX4_FLAG_SLAVE; 3484 dev->flags &= ~MLX4_FLAG_MASTER; 3485 goto slave_start; 3486 } else 3487 goto err_fw; 3488 } 3489 3490 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3491 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3492 existing_vfs, reset_flow); 3493 3494 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3495 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3496 dev->flags = dev_flags; 3497 err = mlx4_cmd_init(dev); 3498 if (err) { 3499 /* Only VHCR is cleaned up, so could still 3500 * send FW commands 3501 */ 3502 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3503 goto err_close; 3504 } 3505 } else { 3506 dev->flags = dev_flags; 3507 } 3508 3509 if (!SRIOV_VALID_STATE(dev->flags)) { 3510 mlx4_err(dev, "Invalid SRIOV state\n"); 3511 goto err_close; 3512 } 3513 } 3514 3515 /* check if the device is functioning at its maximum possible speed. 3516 * No return code for this call, just warn the user in case of PCI 3517 * express device capabilities are under-satisfied by the bus. 3518 */ 3519 if (!mlx4_is_slave(dev)) 3520 pcie_print_link_status(dev->persist->pdev); 3521 3522 /* In master functions, the communication channel must be initialized 3523 * after obtaining its address from fw */ 3524 if (mlx4_is_master(dev)) { 3525 if (dev->caps.num_ports < 2 && 3526 num_vfs_argc > 1) { 3527 err = -EINVAL; 3528 mlx4_err(dev, 3529 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3530 dev->caps.num_ports); 3531 goto err_close; 3532 } 3533 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3534 3535 for (i = 0; 3536 i < sizeof(dev->persist->nvfs)/ 3537 sizeof(dev->persist->nvfs[0]); i++) { 3538 unsigned j; 3539 3540 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3541 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3542 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3543 dev->caps.num_ports; 3544 } 3545 } 3546 3547 /* In master functions, the communication channel 3548 * must be initialized after obtaining its address from fw 3549 */ 3550 err = mlx4_multi_func_init(dev); 3551 if (err) { 3552 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3553 goto err_close; 3554 } 3555 } 3556 3557 err = mlx4_alloc_eq_table(dev); 3558 if (err) 3559 goto err_master_mfunc; 3560 3561 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3562 mutex_init(&priv->msix_ctl.pool_lock); 3563 3564 mlx4_enable_msi_x(dev); 3565 if ((mlx4_is_mfunc(dev)) && 3566 !(dev->flags & MLX4_FLAG_MSI_X)) { 3567 err = -EOPNOTSUPP; 3568 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3569 goto err_free_eq; 3570 } 3571 3572 if (!mlx4_is_slave(dev)) { 3573 err = mlx4_init_steering(dev); 3574 if (err) 3575 goto err_disable_msix; 3576 } 3577 3578 mlx4_init_quotas(dev); 3579 3580 err = mlx4_setup_hca(dev); 3581 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3582 !mlx4_is_mfunc(dev)) { 3583 dev->flags &= ~MLX4_FLAG_MSI_X; 3584 dev->caps.num_comp_vectors = 1; 3585 pci_disable_msix(pdev); 3586 err = mlx4_setup_hca(dev); 3587 } 3588 3589 if (err) 3590 goto err_steer; 3591 3592 /* When PF resources are ready arm its comm channel to enable 3593 * getting commands 3594 */ 3595 if (mlx4_is_master(dev)) { 3596 err = mlx4_ARM_COMM_CHANNEL(dev); 3597 if (err) { 3598 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3599 err); 3600 goto err_steer; 3601 } 3602 } 3603 3604 for (port = 1; port <= dev->caps.num_ports; port++) { 3605 err = mlx4_init_port_info(dev, port); 3606 if (err) 3607 goto err_port; 3608 } 3609 3610 priv->v2p.port1 = 1; 3611 priv->v2p.port2 = 2; 3612 3613 err = mlx4_register_device(dev); 3614 if (err) 3615 goto err_port; 3616 3617 mlx4_request_modules(dev); 3618 3619 mlx4_sense_init(dev); 3620 mlx4_start_sense(dev); 3621 3622 priv->removed = 0; 3623 3624 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3625 atomic_dec(&pf_loading); 3626 3627 kfree(dev_cap); 3628 return 0; 3629 3630 err_port: 3631 for (--port; port >= 1; --port) 3632 mlx4_cleanup_port_info(&priv->port[port]); 3633 3634 mlx4_cleanup_default_counters(dev); 3635 if (!mlx4_is_slave(dev)) 3636 mlx4_cleanup_counters_table(dev); 3637 mlx4_cleanup_qp_table(dev); 3638 mlx4_cleanup_srq_table(dev); 3639 mlx4_cleanup_cq_table(dev); 3640 mlx4_cmd_use_polling(dev); 3641 mlx4_cleanup_eq_table(dev); 3642 mlx4_cleanup_mcg_table(dev); 3643 mlx4_cleanup_mr_table(dev); 3644 mlx4_cleanup_xrcd_table(dev); 3645 mlx4_cleanup_pd_table(dev); 3646 mlx4_cleanup_uar_table(dev); 3647 3648 err_steer: 3649 if (!mlx4_is_slave(dev)) 3650 mlx4_clear_steering(dev); 3651 3652 err_disable_msix: 3653 if (dev->flags & MLX4_FLAG_MSI_X) 3654 pci_disable_msix(pdev); 3655 3656 err_free_eq: 3657 mlx4_free_eq_table(dev); 3658 3659 err_master_mfunc: 3660 if (mlx4_is_master(dev)) { 3661 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3662 mlx4_multi_func_cleanup(dev); 3663 } 3664 3665 if (mlx4_is_slave(dev)) 3666 mlx4_slave_destroy_special_qp_cap(dev); 3667 3668 err_close: 3669 mlx4_close_hca(dev); 3670 3671 err_fw: 3672 mlx4_close_fw(dev); 3673 3674 err_mfunc: 3675 if (mlx4_is_slave(dev)) 3676 mlx4_multi_func_cleanup(dev); 3677 3678 err_cmd: 3679 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3680 3681 err_sriov: 3682 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3683 pci_disable_sriov(pdev); 3684 dev->flags &= ~MLX4_FLAG_SRIOV; 3685 } 3686 3687 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3688 atomic_dec(&pf_loading); 3689 3690 kfree(priv->dev.dev_vfs); 3691 3692 if (!mlx4_is_slave(dev)) 3693 mlx4_free_ownership(dev); 3694 3695 kfree(dev_cap); 3696 return err; 3697 } 3698 3699 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3700 struct mlx4_priv *priv) 3701 { 3702 int err; 3703 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3704 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3705 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3706 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3707 unsigned total_vfs = 0; 3708 unsigned int i; 3709 3710 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3711 3712 err = mlx4_pci_enable_device(&priv->dev); 3713 if (err) { 3714 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3715 return err; 3716 } 3717 3718 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3719 * per port, we must limit the number of VFs to 63 (since their are 3720 * 128 MACs) 3721 */ 3722 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3723 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3724 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3725 if (nvfs[i] < 0) { 3726 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3727 err = -EINVAL; 3728 goto err_disable_pdev; 3729 } 3730 } 3731 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3732 i++) { 3733 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3734 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3735 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3736 err = -EINVAL; 3737 goto err_disable_pdev; 3738 } 3739 } 3740 if (total_vfs > MLX4_MAX_NUM_VF) { 3741 dev_err(&pdev->dev, 3742 "Requested more VF's (%d) than allowed by hw (%d)\n", 3743 total_vfs, MLX4_MAX_NUM_VF); 3744 err = -EINVAL; 3745 goto err_disable_pdev; 3746 } 3747 3748 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3749 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3750 dev_err(&pdev->dev, 3751 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3752 nvfs[i] + nvfs[2], i + 1, 3753 MLX4_MAX_NUM_VF_P_PORT); 3754 err = -EINVAL; 3755 goto err_disable_pdev; 3756 } 3757 } 3758 3759 /* Check for BARs. */ 3760 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3761 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3762 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3763 pci_dev_data, pci_resource_flags(pdev, 0)); 3764 err = -ENODEV; 3765 goto err_disable_pdev; 3766 } 3767 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3768 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3769 err = -ENODEV; 3770 goto err_disable_pdev; 3771 } 3772 3773 err = pci_request_regions(pdev, DRV_NAME); 3774 if (err) { 3775 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3776 goto err_disable_pdev; 3777 } 3778 3779 pci_set_master(pdev); 3780 3781 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3782 if (err) { 3783 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3784 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3785 if (err) { 3786 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3787 goto err_release_regions; 3788 } 3789 } 3790 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3791 if (err) { 3792 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3793 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3794 if (err) { 3795 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3796 goto err_release_regions; 3797 } 3798 } 3799 3800 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3801 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3802 /* Detect if this device is a virtual function */ 3803 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3804 /* When acting as pf, we normally skip vfs unless explicitly 3805 * requested to probe them. 3806 */ 3807 if (total_vfs) { 3808 unsigned vfs_offset = 0; 3809 3810 for (i = 0; i < ARRAY_SIZE(nvfs) && 3811 vfs_offset + nvfs[i] < extended_func_num(pdev); 3812 vfs_offset += nvfs[i], i++) 3813 ; 3814 if (i == ARRAY_SIZE(nvfs)) { 3815 err = -ENODEV; 3816 goto err_release_regions; 3817 } 3818 if ((extended_func_num(pdev) - vfs_offset) 3819 > prb_vf[i]) { 3820 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3821 extended_func_num(pdev)); 3822 err = -ENODEV; 3823 goto err_release_regions; 3824 } 3825 } 3826 } 3827 3828 err = mlx4_crdump_init(&priv->dev); 3829 if (err) 3830 goto err_release_regions; 3831 3832 err = mlx4_catas_init(&priv->dev); 3833 if (err) 3834 goto err_crdump; 3835 3836 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3837 if (err) 3838 goto err_catas; 3839 3840 return 0; 3841 3842 err_catas: 3843 mlx4_catas_end(&priv->dev); 3844 3845 err_crdump: 3846 mlx4_crdump_end(&priv->dev); 3847 3848 err_release_regions: 3849 pci_release_regions(pdev); 3850 3851 err_disable_pdev: 3852 mlx4_pci_disable_device(&priv->dev); 3853 return err; 3854 } 3855 3856 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3857 enum devlink_port_type port_type) 3858 { 3859 struct mlx4_port_info *info = container_of(devlink_port, 3860 struct mlx4_port_info, 3861 devlink_port); 3862 enum mlx4_port_type mlx4_port_type; 3863 3864 switch (port_type) { 3865 case DEVLINK_PORT_TYPE_AUTO: 3866 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3867 break; 3868 case DEVLINK_PORT_TYPE_ETH: 3869 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3870 break; 3871 case DEVLINK_PORT_TYPE_IB: 3872 mlx4_port_type = MLX4_PORT_TYPE_IB; 3873 break; 3874 default: 3875 return -EOPNOTSUPP; 3876 } 3877 3878 return __set_port_type(info, mlx4_port_type); 3879 } 3880 3881 static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3882 { 3883 struct mlx4_priv *priv = devlink_priv(devlink); 3884 struct mlx4_dev *dev = &priv->dev; 3885 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3886 union devlink_param_value saved_value; 3887 int err; 3888 3889 err = devlink_param_driverinit_value_get(devlink, 3890 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3891 &saved_value); 3892 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3893 mlx4_internal_err_reset = saved_value.vbool; 3894 /* Notify on value changed on runtime configuration mode */ 3895 devlink_param_value_changed(devlink, 3896 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3897 } 3898 err = devlink_param_driverinit_value_get(devlink, 3899 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3900 &saved_value); 3901 if (!err) 3902 log_num_mac = order_base_2(saved_value.vu32); 3903 err = devlink_param_driverinit_value_get(devlink, 3904 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3905 &saved_value); 3906 if (!err) 3907 enable_64b_cqe_eqe = saved_value.vbool; 3908 err = devlink_param_driverinit_value_get(devlink, 3909 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3910 &saved_value); 3911 if (!err) 3912 enable_4k_uar = saved_value.vbool; 3913 err = devlink_param_driverinit_value_get(devlink, 3914 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3915 &saved_value); 3916 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3917 crdump->snapshot_enable = saved_value.vbool; 3918 devlink_param_value_changed(devlink, 3919 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3920 } 3921 } 3922 3923 static int mlx4_devlink_reload(struct devlink *devlink, 3924 struct netlink_ext_ack *extack) 3925 { 3926 struct mlx4_priv *priv = devlink_priv(devlink); 3927 struct mlx4_dev *dev = &priv->dev; 3928 struct mlx4_dev_persistent *persist = dev->persist; 3929 int err; 3930 3931 if (persist->num_vfs) 3932 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 3933 err = mlx4_restart_one(persist->pdev, true, devlink); 3934 if (err) 3935 mlx4_err(persist->dev, "mlx4_restart_one failed, ret=%d\n", err); 3936 3937 return err; 3938 } 3939 3940 static const struct devlink_ops mlx4_devlink_ops = { 3941 .port_type_set = mlx4_devlink_port_type_set, 3942 .reload = mlx4_devlink_reload, 3943 }; 3944 3945 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3946 { 3947 struct devlink *devlink; 3948 struct mlx4_priv *priv; 3949 struct mlx4_dev *dev; 3950 int ret; 3951 3952 printk_once(KERN_INFO "%s", mlx4_version); 3953 3954 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 3955 if (!devlink) 3956 return -ENOMEM; 3957 priv = devlink_priv(devlink); 3958 3959 dev = &priv->dev; 3960 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 3961 if (!dev->persist) { 3962 ret = -ENOMEM; 3963 goto err_devlink_free; 3964 } 3965 dev->persist->pdev = pdev; 3966 dev->persist->dev = dev; 3967 pci_set_drvdata(pdev, dev->persist); 3968 priv->pci_dev_data = id->driver_data; 3969 mutex_init(&dev->persist->device_state_mutex); 3970 mutex_init(&dev->persist->interface_state_mutex); 3971 mutex_init(&dev->persist->pci_status_mutex); 3972 3973 ret = devlink_register(devlink, &pdev->dev); 3974 if (ret) 3975 goto err_persist_free; 3976 ret = devlink_params_register(devlink, mlx4_devlink_params, 3977 ARRAY_SIZE(mlx4_devlink_params)); 3978 if (ret) 3979 goto err_devlink_unregister; 3980 mlx4_devlink_set_params_init_values(devlink); 3981 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3982 if (ret) 3983 goto err_params_unregister; 3984 3985 pci_save_state(pdev); 3986 return 0; 3987 3988 err_params_unregister: 3989 devlink_params_unregister(devlink, mlx4_devlink_params, 3990 ARRAY_SIZE(mlx4_devlink_params)); 3991 err_devlink_unregister: 3992 devlink_unregister(devlink); 3993 err_persist_free: 3994 kfree(dev->persist); 3995 err_devlink_free: 3996 devlink_free(devlink); 3997 return ret; 3998 } 3999 4000 static void mlx4_clean_dev(struct mlx4_dev *dev) 4001 { 4002 struct mlx4_dev_persistent *persist = dev->persist; 4003 struct mlx4_priv *priv = mlx4_priv(dev); 4004 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4005 4006 memset(priv, 0, sizeof(*priv)); 4007 priv->dev.persist = persist; 4008 priv->dev.flags = flags; 4009 } 4010 4011 static void mlx4_unload_one(struct pci_dev *pdev) 4012 { 4013 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4014 struct mlx4_dev *dev = persist->dev; 4015 struct mlx4_priv *priv = mlx4_priv(dev); 4016 int pci_dev_data; 4017 int p, i; 4018 4019 if (priv->removed) 4020 return; 4021 4022 /* saving current ports type for further use */ 4023 for (i = 0; i < dev->caps.num_ports; i++) { 4024 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4025 dev->persist->curr_port_poss_type[i] = dev->caps. 4026 possible_type[i + 1]; 4027 } 4028 4029 pci_dev_data = priv->pci_dev_data; 4030 4031 mlx4_stop_sense(dev); 4032 mlx4_unregister_device(dev); 4033 4034 for (p = 1; p <= dev->caps.num_ports; p++) { 4035 mlx4_cleanup_port_info(&priv->port[p]); 4036 mlx4_CLOSE_PORT(dev, p); 4037 } 4038 4039 if (mlx4_is_master(dev)) 4040 mlx4_free_resource_tracker(dev, 4041 RES_TR_FREE_SLAVES_ONLY); 4042 4043 mlx4_cleanup_default_counters(dev); 4044 if (!mlx4_is_slave(dev)) 4045 mlx4_cleanup_counters_table(dev); 4046 mlx4_cleanup_qp_table(dev); 4047 mlx4_cleanup_srq_table(dev); 4048 mlx4_cleanup_cq_table(dev); 4049 mlx4_cmd_use_polling(dev); 4050 mlx4_cleanup_eq_table(dev); 4051 mlx4_cleanup_mcg_table(dev); 4052 mlx4_cleanup_mr_table(dev); 4053 mlx4_cleanup_xrcd_table(dev); 4054 mlx4_cleanup_pd_table(dev); 4055 4056 if (mlx4_is_master(dev)) 4057 mlx4_free_resource_tracker(dev, 4058 RES_TR_FREE_STRUCTS_ONLY); 4059 4060 iounmap(priv->kar); 4061 mlx4_uar_free(dev, &priv->driver_uar); 4062 mlx4_cleanup_uar_table(dev); 4063 if (!mlx4_is_slave(dev)) 4064 mlx4_clear_steering(dev); 4065 mlx4_free_eq_table(dev); 4066 if (mlx4_is_master(dev)) 4067 mlx4_multi_func_cleanup(dev); 4068 mlx4_close_hca(dev); 4069 mlx4_close_fw(dev); 4070 if (mlx4_is_slave(dev)) 4071 mlx4_multi_func_cleanup(dev); 4072 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4073 4074 if (dev->flags & MLX4_FLAG_MSI_X) 4075 pci_disable_msix(pdev); 4076 4077 if (!mlx4_is_slave(dev)) 4078 mlx4_free_ownership(dev); 4079 4080 mlx4_slave_destroy_special_qp_cap(dev); 4081 kfree(dev->dev_vfs); 4082 4083 mlx4_clean_dev(dev); 4084 priv->pci_dev_data = pci_dev_data; 4085 priv->removed = 1; 4086 } 4087 4088 static void mlx4_remove_one(struct pci_dev *pdev) 4089 { 4090 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4091 struct mlx4_dev *dev = persist->dev; 4092 struct mlx4_priv *priv = mlx4_priv(dev); 4093 struct devlink *devlink = priv_to_devlink(priv); 4094 int active_vfs = 0; 4095 4096 if (mlx4_is_slave(dev)) 4097 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4098 4099 mutex_lock(&persist->interface_state_mutex); 4100 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4101 mutex_unlock(&persist->interface_state_mutex); 4102 4103 /* Disabling SR-IOV is not allowed while there are active vf's */ 4104 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4105 active_vfs = mlx4_how_many_lives_vf(dev); 4106 if (active_vfs) { 4107 pr_warn("Removing PF when there are active VF's !!\n"); 4108 pr_warn("Will not disable SR-IOV.\n"); 4109 } 4110 } 4111 4112 /* device marked to be under deletion running now without the lock 4113 * letting other tasks to be terminated 4114 */ 4115 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4116 mlx4_unload_one(pdev); 4117 else 4118 mlx4_info(dev, "%s: interface is down\n", __func__); 4119 mlx4_catas_end(dev); 4120 mlx4_crdump_end(dev); 4121 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4122 mlx4_warn(dev, "Disabling SR-IOV\n"); 4123 pci_disable_sriov(pdev); 4124 } 4125 4126 pci_release_regions(pdev); 4127 mlx4_pci_disable_device(dev); 4128 devlink_params_unregister(devlink, mlx4_devlink_params, 4129 ARRAY_SIZE(mlx4_devlink_params)); 4130 devlink_unregister(devlink); 4131 kfree(dev->persist); 4132 devlink_free(devlink); 4133 } 4134 4135 static int restore_current_port_types(struct mlx4_dev *dev, 4136 enum mlx4_port_type *types, 4137 enum mlx4_port_type *poss_types) 4138 { 4139 struct mlx4_priv *priv = mlx4_priv(dev); 4140 int err, i; 4141 4142 mlx4_stop_sense(dev); 4143 4144 mutex_lock(&priv->port_mutex); 4145 for (i = 0; i < dev->caps.num_ports; i++) 4146 dev->caps.possible_type[i + 1] = poss_types[i]; 4147 err = mlx4_change_port_types(dev, types); 4148 mlx4_start_sense(dev); 4149 mutex_unlock(&priv->port_mutex); 4150 4151 return err; 4152 } 4153 4154 int mlx4_restart_one(struct pci_dev *pdev, bool reload, struct devlink *devlink) 4155 { 4156 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4157 struct mlx4_dev *dev = persist->dev; 4158 struct mlx4_priv *priv = mlx4_priv(dev); 4159 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4160 int pci_dev_data, err, total_vfs; 4161 4162 pci_dev_data = priv->pci_dev_data; 4163 total_vfs = dev->persist->num_vfs; 4164 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4165 4166 mlx4_unload_one(pdev); 4167 if (reload) 4168 mlx4_devlink_param_load_driverinit_values(devlink); 4169 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4170 if (err) { 4171 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4172 __func__, pci_name(pdev), err); 4173 return err; 4174 } 4175 4176 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4177 dev->persist->curr_port_poss_type); 4178 if (err) 4179 mlx4_err(dev, "could not restore original port types (%d)\n", 4180 err); 4181 4182 return err; 4183 } 4184 4185 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4186 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4187 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4188 4189 static const struct pci_device_id mlx4_pci_table[] = { 4190 #ifdef CONFIG_MLX4_CORE_GEN2 4191 /* MT25408 "Hermon" */ 4192 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4193 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4194 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4195 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4196 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4197 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4198 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4199 /* MT25458 ConnectX EN 10GBASE-T */ 4200 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4201 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4202 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4203 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4204 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4205 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4206 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4207 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4208 /* MT25400 Family [ConnectX-2] */ 4209 MLX_VF(0x1002), /* Virtual Function */ 4210 #endif /* CONFIG_MLX4_CORE_GEN2 */ 4211 /* MT27500 Family [ConnectX-3] */ 4212 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4213 MLX_VF(0x1004), /* Virtual Function */ 4214 MLX_GN(0x1005), /* MT27510 Family */ 4215 MLX_GN(0x1006), /* MT27511 Family */ 4216 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4217 MLX_GN(0x1008), /* MT27521 Family */ 4218 MLX_GN(0x1009), /* MT27530 Family */ 4219 MLX_GN(0x100a), /* MT27531 Family */ 4220 MLX_GN(0x100b), /* MT27540 Family */ 4221 MLX_GN(0x100c), /* MT27541 Family */ 4222 MLX_GN(0x100d), /* MT27550 Family */ 4223 MLX_GN(0x100e), /* MT27551 Family */ 4224 MLX_GN(0x100f), /* MT27560 Family */ 4225 MLX_GN(0x1010), /* MT27561 Family */ 4226 4227 /* 4228 * See the mellanox_check_broken_intx_masking() quirk when 4229 * adding devices 4230 */ 4231 4232 { 0, } 4233 }; 4234 4235 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4236 4237 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4238 pci_channel_state_t state) 4239 { 4240 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4241 4242 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4243 mlx4_enter_error_state(persist); 4244 4245 mutex_lock(&persist->interface_state_mutex); 4246 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4247 mlx4_unload_one(pdev); 4248 4249 mutex_unlock(&persist->interface_state_mutex); 4250 if (state == pci_channel_io_perm_failure) 4251 return PCI_ERS_RESULT_DISCONNECT; 4252 4253 mlx4_pci_disable_device(persist->dev); 4254 return PCI_ERS_RESULT_NEED_RESET; 4255 } 4256 4257 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4258 { 4259 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4260 struct mlx4_dev *dev = persist->dev; 4261 int err; 4262 4263 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4264 err = mlx4_pci_enable_device(dev); 4265 if (err) { 4266 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4267 return PCI_ERS_RESULT_DISCONNECT; 4268 } 4269 4270 pci_set_master(pdev); 4271 pci_restore_state(pdev); 4272 pci_save_state(pdev); 4273 return PCI_ERS_RESULT_RECOVERED; 4274 } 4275 4276 static void mlx4_pci_resume(struct pci_dev *pdev) 4277 { 4278 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4279 struct mlx4_dev *dev = persist->dev; 4280 struct mlx4_priv *priv = mlx4_priv(dev); 4281 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4282 int total_vfs; 4283 int err; 4284 4285 mlx4_err(dev, "%s was called\n", __func__); 4286 total_vfs = dev->persist->num_vfs; 4287 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4288 4289 mutex_lock(&persist->interface_state_mutex); 4290 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4291 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4292 priv, 1); 4293 if (err) { 4294 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4295 __func__, err); 4296 goto end; 4297 } 4298 4299 err = restore_current_port_types(dev, dev->persist-> 4300 curr_port_type, dev->persist-> 4301 curr_port_poss_type); 4302 if (err) 4303 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4304 } 4305 end: 4306 mutex_unlock(&persist->interface_state_mutex); 4307 4308 } 4309 4310 static void mlx4_shutdown(struct pci_dev *pdev) 4311 { 4312 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4313 4314 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4315 mutex_lock(&persist->interface_state_mutex); 4316 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4317 mlx4_unload_one(pdev); 4318 mutex_unlock(&persist->interface_state_mutex); 4319 } 4320 4321 static const struct pci_error_handlers mlx4_err_handler = { 4322 .error_detected = mlx4_pci_err_detected, 4323 .slot_reset = mlx4_pci_slot_reset, 4324 .resume = mlx4_pci_resume, 4325 }; 4326 4327 static int mlx4_suspend(struct pci_dev *pdev, pm_message_t state) 4328 { 4329 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4330 struct mlx4_dev *dev = persist->dev; 4331 4332 mlx4_err(dev, "suspend was called\n"); 4333 mutex_lock(&persist->interface_state_mutex); 4334 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4335 mlx4_unload_one(pdev); 4336 mutex_unlock(&persist->interface_state_mutex); 4337 4338 return 0; 4339 } 4340 4341 static int mlx4_resume(struct pci_dev *pdev) 4342 { 4343 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4344 struct mlx4_dev *dev = persist->dev; 4345 struct mlx4_priv *priv = mlx4_priv(dev); 4346 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4347 int total_vfs; 4348 int ret = 0; 4349 4350 mlx4_err(dev, "resume was called\n"); 4351 total_vfs = dev->persist->num_vfs; 4352 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4353 4354 mutex_lock(&persist->interface_state_mutex); 4355 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4356 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4357 nvfs, priv, 1); 4358 if (!ret) { 4359 ret = restore_current_port_types(dev, 4360 dev->persist->curr_port_type, 4361 dev->persist->curr_port_poss_type); 4362 if (ret) 4363 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4364 } 4365 } 4366 mutex_unlock(&persist->interface_state_mutex); 4367 4368 return ret; 4369 } 4370 4371 static struct pci_driver mlx4_driver = { 4372 .name = DRV_NAME, 4373 .id_table = mlx4_pci_table, 4374 .probe = mlx4_init_one, 4375 .shutdown = mlx4_shutdown, 4376 .remove = mlx4_remove_one, 4377 .suspend = mlx4_suspend, 4378 .resume = mlx4_resume, 4379 .err_handler = &mlx4_err_handler, 4380 }; 4381 4382 static int __init mlx4_verify_params(void) 4383 { 4384 if (msi_x < 0) { 4385 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4386 return -1; 4387 } 4388 4389 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4390 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4391 return -1; 4392 } 4393 4394 if (log_num_vlan != 0) 4395 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4396 MLX4_LOG_NUM_VLANS); 4397 4398 if (use_prio != 0) 4399 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4400 4401 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 4402 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4403 log_mtts_per_seg); 4404 return -1; 4405 } 4406 4407 /* Check if module param for ports type has legal combination */ 4408 if (port_type_array[0] == false && port_type_array[1] == true) { 4409 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4410 port_type_array[0] = true; 4411 } 4412 4413 if (mlx4_log_num_mgm_entry_size < -7 || 4414 (mlx4_log_num_mgm_entry_size > 0 && 4415 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4416 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4417 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4418 mlx4_log_num_mgm_entry_size, 4419 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4420 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4421 return -1; 4422 } 4423 4424 return 0; 4425 } 4426 4427 static int __init mlx4_init(void) 4428 { 4429 int ret; 4430 4431 if (mlx4_verify_params()) 4432 return -EINVAL; 4433 4434 4435 mlx4_wq = create_singlethread_workqueue("mlx4"); 4436 if (!mlx4_wq) 4437 return -ENOMEM; 4438 4439 ret = pci_register_driver(&mlx4_driver); 4440 if (ret < 0) 4441 destroy_workqueue(mlx4_wq); 4442 return ret < 0 ? ret : 0; 4443 } 4444 4445 static void __exit mlx4_cleanup(void) 4446 { 4447 pci_unregister_driver(&mlx4_driver); 4448 destroy_workqueue(mlx4_wq); 4449 } 4450 4451 module_init(mlx4_init); 4452 module_exit(mlx4_cleanup); 4453