1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 4] = "reliable multicast", 88 [ 5] = "FCoIB support", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [10] = "VMM", 94 [12] = "Dual Port Different Protocol (DPDP) support", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [24] = "Demand paging support", 103 [25] = "Router support", 104 [30] = "IBoE support", 105 [32] = "Unicast loopback support", 106 [34] = "FCS header control", 107 [38] = "Wake On LAN support", 108 [40] = "UDP RSS support", 109 [41] = "Unicast VEP steering support", 110 [42] = "Multicast VEP steering support", 111 [48] = "Counters support", 112 [53] = "Port ETS Scheduler support", 113 [55] = "Port link type sensing support", 114 [59] = "Port management change event support", 115 [61] = "64 byte EQE support", 116 [62] = "64 byte CQE support", 117 }; 118 int i; 119 120 mlx4_dbg(dev, "DEV_CAP flags:\n"); 121 for (i = 0; i < ARRAY_SIZE(fname); ++i) 122 if (fname[i] && (flags & (1LL << i))) 123 mlx4_dbg(dev, " %s\n", fname[i]); 124 } 125 126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127 { 128 static const char * const fname[] = { 129 [0] = "RSS support", 130 [1] = "RSS Toeplitz Hash Function support", 131 [2] = "RSS XOR Hash Function support", 132 [3] = "Device manage flow steering support", 133 [4] = "Automatic MAC reassignment support", 134 [5] = "Time stamping support" 135 }; 136 int i; 137 138 for (i = 0; i < ARRAY_SIZE(fname); ++i) 139 if (fname[i] && (flags & (1LL << i))) 140 mlx4_dbg(dev, " %s\n", fname[i]); 141 } 142 143 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 144 { 145 struct mlx4_cmd_mailbox *mailbox; 146 u32 *inbox; 147 int err = 0; 148 149 #define MOD_STAT_CFG_IN_SIZE 0x100 150 151 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 152 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 153 154 mailbox = mlx4_alloc_cmd_mailbox(dev); 155 if (IS_ERR(mailbox)) 156 return PTR_ERR(mailbox); 157 inbox = mailbox->buf; 158 159 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); 160 161 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 162 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 163 164 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 166 167 mlx4_free_cmd_mailbox(dev, mailbox); 168 return err; 169 } 170 171 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 172 struct mlx4_vhcr *vhcr, 173 struct mlx4_cmd_mailbox *inbox, 174 struct mlx4_cmd_mailbox *outbox, 175 struct mlx4_cmd_info *cmd) 176 { 177 u8 field; 178 u32 size; 179 int err = 0; 180 181 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 182 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 183 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 184 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 185 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 186 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 187 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 188 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 189 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 190 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 191 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 192 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 193 194 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 195 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 196 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 197 198 /* when opcode modifier = 1 */ 199 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 200 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 201 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc 202 203 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 204 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 205 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 206 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 207 208 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 209 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 210 211 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 212 213 if (vhcr->op_modifier == 1) { 214 field = 0; 215 /* ensure force vlan and force mac bits are not set */ 216 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 217 /* ensure that phy_wqe_gid bit is not set */ 218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 219 220 field = vhcr->in_modifier; /* phys-port = logical-port */ 221 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 222 223 /* size is now the QP number */ 224 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; 225 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 226 227 size += 2; 228 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 229 230 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; 231 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); 232 233 size += 2; 234 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); 235 236 } else if (vhcr->op_modifier == 0) { 237 /* enable rdma and ethernet interfaces */ 238 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); 239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 240 241 field = dev->caps.num_ports; 242 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 243 244 size = dev->caps.function_caps; /* set PF behaviours */ 245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 246 247 field = 0; /* protected FMR support not available as yet */ 248 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 249 250 size = dev->caps.num_qps; 251 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 252 253 size = dev->caps.num_srqs; 254 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 255 256 size = dev->caps.num_cqs; 257 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 258 259 size = dev->caps.num_eqs; 260 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 261 262 size = dev->caps.reserved_eqs; 263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 264 265 size = dev->caps.num_mpts; 266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 267 268 size = dev->caps.num_mtts; 269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 270 271 size = dev->caps.num_mgms + dev->caps.num_amgms; 272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 273 274 } else 275 err = -EINVAL; 276 277 return err; 278 } 279 280 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, 281 struct mlx4_func_cap *func_cap) 282 { 283 struct mlx4_cmd_mailbox *mailbox; 284 u32 *outbox; 285 u8 field, op_modifier; 286 u32 size; 287 int err = 0; 288 289 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 290 291 mailbox = mlx4_alloc_cmd_mailbox(dev); 292 if (IS_ERR(mailbox)) 293 return PTR_ERR(mailbox); 294 295 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, 296 MLX4_CMD_QUERY_FUNC_CAP, 297 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 298 if (err) 299 goto out; 300 301 outbox = mailbox->buf; 302 303 if (!op_modifier) { 304 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 305 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 306 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 307 err = -EPROTONOSUPPORT; 308 goto out; 309 } 310 func_cap->flags = field; 311 312 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 313 func_cap->num_ports = field; 314 315 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 316 func_cap->pf_context_behaviour = size; 317 318 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 319 func_cap->qp_quota = size & 0xFFFFFF; 320 321 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 322 func_cap->srq_quota = size & 0xFFFFFF; 323 324 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 325 func_cap->cq_quota = size & 0xFFFFFF; 326 327 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 328 func_cap->max_eq = size & 0xFFFFFF; 329 330 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 331 func_cap->reserved_eq = size & 0xFFFFFF; 332 333 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 334 func_cap->mpt_quota = size & 0xFFFFFF; 335 336 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 337 func_cap->mtt_quota = size & 0xFFFFFF; 338 339 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 340 func_cap->mcg_quota = size & 0xFFFFFF; 341 goto out; 342 } 343 344 /* logical port query */ 345 if (gen_or_port > dev->caps.num_ports) { 346 err = -EINVAL; 347 goto out; 348 } 349 350 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 351 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 352 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { 353 mlx4_err(dev, "VLAN is enforced on this port\n"); 354 err = -EPROTONOSUPPORT; 355 goto out; 356 } 357 358 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { 359 mlx4_err(dev, "Force mac is enabled on this port\n"); 360 err = -EPROTONOSUPPORT; 361 goto out; 362 } 363 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 364 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 365 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { 366 mlx4_err(dev, "phy_wqe_gid is " 367 "enforced on this ib port\n"); 368 err = -EPROTONOSUPPORT; 369 goto out; 370 } 371 } 372 373 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 374 func_cap->physical_port = field; 375 if (func_cap->physical_port != gen_or_port) { 376 err = -ENOSYS; 377 goto out; 378 } 379 380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 381 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 382 383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 384 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 385 386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 387 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 388 389 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 390 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 391 392 /* All other resources are allocated by the master, but we still report 393 * 'num' and 'reserved' capabilities as follows: 394 * - num remains the maximum resource index 395 * - 'num - reserved' is the total available objects of a resource, but 396 * resource indices may be less than 'reserved' 397 * TODO: set per-resource quotas */ 398 399 out: 400 mlx4_free_cmd_mailbox(dev, mailbox); 401 402 return err; 403 } 404 405 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 406 { 407 struct mlx4_cmd_mailbox *mailbox; 408 u32 *outbox; 409 u8 field; 410 u32 field32, flags, ext_flags; 411 u16 size; 412 u16 stat_rate; 413 int err; 414 int i; 415 416 #define QUERY_DEV_CAP_OUT_SIZE 0x100 417 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 418 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 419 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 420 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 421 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 422 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 423 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 424 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 425 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 426 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 427 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 428 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 429 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 430 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 431 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 432 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 433 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 434 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 435 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 436 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 437 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 438 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 439 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 440 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 441 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 442 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 443 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 444 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 445 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 446 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 447 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 448 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 449 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 450 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 451 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 452 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 453 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 454 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 455 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 456 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 457 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 458 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 459 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 460 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 461 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 462 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 463 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 464 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 465 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 466 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 467 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 468 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 469 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 470 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 471 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 472 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 473 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 474 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 475 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 476 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 477 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 478 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 479 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 480 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 481 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 482 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 483 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 484 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 485 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 486 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 487 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 488 489 dev_cap->flags2 = 0; 490 mailbox = mlx4_alloc_cmd_mailbox(dev); 491 if (IS_ERR(mailbox)) 492 return PTR_ERR(mailbox); 493 outbox = mailbox->buf; 494 495 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 496 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 497 if (err) 498 goto out; 499 500 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 501 dev_cap->reserved_qps = 1 << (field & 0xf); 502 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 503 dev_cap->max_qps = 1 << (field & 0x1f); 504 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 505 dev_cap->reserved_srqs = 1 << (field >> 4); 506 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 507 dev_cap->max_srqs = 1 << (field & 0x1f); 508 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 509 dev_cap->max_cq_sz = 1 << field; 510 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 511 dev_cap->reserved_cqs = 1 << (field & 0xf); 512 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 513 dev_cap->max_cqs = 1 << (field & 0x1f); 514 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 515 dev_cap->max_mpts = 1 << (field & 0x3f); 516 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 517 dev_cap->reserved_eqs = field & 0xf; 518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 519 dev_cap->max_eqs = 1 << (field & 0xf); 520 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 521 dev_cap->reserved_mtts = 1 << (field >> 4); 522 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 523 dev_cap->max_mrw_sz = 1 << field; 524 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 525 dev_cap->reserved_mrws = 1 << (field & 0xf); 526 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 527 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 528 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 529 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 530 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 531 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 532 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 533 field &= 0x1f; 534 if (!field) 535 dev_cap->max_gso_sz = 0; 536 else 537 dev_cap->max_gso_sz = 1 << field; 538 539 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 540 if (field & 0x20) 541 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 542 if (field & 0x10) 543 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 544 field &= 0xf; 545 if (field) { 546 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 547 dev_cap->max_rss_tbl_sz = 1 << field; 548 } else 549 dev_cap->max_rss_tbl_sz = 0; 550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 551 dev_cap->max_rdma_global = 1 << (field & 0x3f); 552 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 553 dev_cap->local_ca_ack_delay = field & 0x1f; 554 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 555 dev_cap->num_ports = field & 0xf; 556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 557 dev_cap->max_msg_sz = 1 << (field & 0x1f); 558 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 559 if (field & 0x80) 560 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 561 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 562 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 563 dev_cap->fs_max_num_qp_per_entry = field; 564 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 565 dev_cap->stat_rate_support = stat_rate; 566 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 567 if (field & 0x80) 568 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 569 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 570 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 571 dev_cap->flags = flags | (u64)ext_flags << 32; 572 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 573 dev_cap->reserved_uars = field >> 4; 574 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 575 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 576 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 577 dev_cap->min_page_sz = 1 << field; 578 579 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 580 if (field & 0x80) { 581 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 582 dev_cap->bf_reg_size = 1 << (field & 0x1f); 583 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 584 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 585 field = 3; 586 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 587 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 588 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 589 } else { 590 dev_cap->bf_reg_size = 0; 591 mlx4_dbg(dev, "BlueFlame not available\n"); 592 } 593 594 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 595 dev_cap->max_sq_sg = field; 596 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 597 dev_cap->max_sq_desc_sz = size; 598 599 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 600 dev_cap->max_qp_per_mcg = 1 << field; 601 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 602 dev_cap->reserved_mgms = field & 0xf; 603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 604 dev_cap->max_mcgs = 1 << field; 605 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 606 dev_cap->reserved_pds = field >> 4; 607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 608 dev_cap->max_pds = 1 << (field & 0x3f); 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 610 dev_cap->reserved_xrcds = field >> 4; 611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 612 dev_cap->max_xrcds = 1 << (field & 0x1f); 613 614 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 615 dev_cap->rdmarc_entry_sz = size; 616 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 617 dev_cap->qpc_entry_sz = size; 618 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 619 dev_cap->aux_entry_sz = size; 620 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 621 dev_cap->altc_entry_sz = size; 622 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 623 dev_cap->eqc_entry_sz = size; 624 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 625 dev_cap->cqc_entry_sz = size; 626 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 627 dev_cap->srq_entry_sz = size; 628 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 629 dev_cap->cmpt_entry_sz = size; 630 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 631 dev_cap->mtt_entry_sz = size; 632 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 633 dev_cap->dmpt_entry_sz = size; 634 635 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 636 dev_cap->max_srq_sz = 1 << field; 637 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 638 dev_cap->max_qp_sz = 1 << field; 639 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 640 dev_cap->resize_srq = field & 1; 641 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 642 dev_cap->max_rq_sg = field; 643 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 644 dev_cap->max_rq_desc_sz = size; 645 646 MLX4_GET(dev_cap->bmme_flags, outbox, 647 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 648 MLX4_GET(dev_cap->reserved_lkey, outbox, 649 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 650 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 651 if (field & 1<<6) 652 dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN; 653 MLX4_GET(dev_cap->max_icm_sz, outbox, 654 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 655 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 656 MLX4_GET(dev_cap->max_counters, outbox, 657 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 658 659 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 660 if (field32 & (1 << 26)) 661 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 662 if (field32 & (1 << 20)) 663 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 664 665 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 666 for (i = 1; i <= dev_cap->num_ports; ++i) { 667 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 668 dev_cap->max_vl[i] = field >> 4; 669 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 670 dev_cap->ib_mtu[i] = field >> 4; 671 dev_cap->max_port_width[i] = field & 0xf; 672 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 673 dev_cap->max_gids[i] = 1 << (field & 0xf); 674 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 675 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 676 } 677 } else { 678 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 679 #define QUERY_PORT_MTU_OFFSET 0x01 680 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 681 #define QUERY_PORT_WIDTH_OFFSET 0x06 682 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 683 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 684 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 685 #define QUERY_PORT_MAC_OFFSET 0x10 686 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 687 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 688 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 689 690 for (i = 1; i <= dev_cap->num_ports; ++i) { 691 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, 692 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 693 if (err) 694 goto out; 695 696 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 697 dev_cap->supported_port_types[i] = field & 3; 698 dev_cap->suggested_type[i] = (field >> 3) & 1; 699 dev_cap->default_sense[i] = (field >> 4) & 1; 700 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 701 dev_cap->ib_mtu[i] = field & 0xf; 702 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 703 dev_cap->max_port_width[i] = field & 0xf; 704 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 705 dev_cap->max_gids[i] = 1 << (field >> 4); 706 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 707 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 708 dev_cap->max_vl[i] = field & 0xf; 709 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 710 dev_cap->log_max_macs[i] = field & 0xf; 711 dev_cap->log_max_vlans[i] = field >> 4; 712 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); 713 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); 714 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 715 dev_cap->trans_type[i] = field32 >> 24; 716 dev_cap->vendor_oui[i] = field32 & 0xffffff; 717 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); 718 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); 719 } 720 } 721 722 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 723 dev_cap->bmme_flags, dev_cap->reserved_lkey); 724 725 /* 726 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 727 * we can't use any EQs whose doorbell falls on that page, 728 * even if the EQ itself isn't reserved. 729 */ 730 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 731 dev_cap->reserved_eqs); 732 733 mlx4_dbg(dev, "Max ICM size %lld MB\n", 734 (unsigned long long) dev_cap->max_icm_sz >> 20); 735 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 736 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 737 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 738 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 739 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 740 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 741 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 742 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); 743 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 744 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 745 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 746 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 747 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 748 dev_cap->max_pds, dev_cap->reserved_mgms); 749 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 750 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 751 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 752 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 753 dev_cap->max_port_width[1]); 754 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 755 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 756 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 757 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 758 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 759 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 760 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 761 762 dump_dev_cap_flags(dev, dev_cap->flags); 763 dump_dev_cap_flags2(dev, dev_cap->flags2); 764 765 out: 766 mlx4_free_cmd_mailbox(dev, mailbox); 767 return err; 768 } 769 770 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 771 struct mlx4_vhcr *vhcr, 772 struct mlx4_cmd_mailbox *inbox, 773 struct mlx4_cmd_mailbox *outbox, 774 struct mlx4_cmd_info *cmd) 775 { 776 u64 flags; 777 int err = 0; 778 u8 field; 779 u32 bmme_flags; 780 781 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 782 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 783 if (err) 784 return err; 785 786 /* add port mng change event capability and disable mw type 1 787 * unconditionally to slaves 788 */ 789 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 790 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 791 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 792 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 793 794 /* For guests, disable timestamp */ 795 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 796 field &= 0x7f; 797 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 798 799 /* For guests, report Blueflame disabled */ 800 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 801 field &= 0x7f; 802 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 803 804 /* For guests, disable mw type 2 */ 805 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 806 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 807 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 808 809 /* turn off device-managed steering capability if not enabled */ 810 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 811 MLX4_GET(field, outbox->buf, 812 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 813 field &= 0x7f; 814 MLX4_PUT(outbox->buf, field, 815 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 816 } 817 return 0; 818 } 819 820 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 821 struct mlx4_vhcr *vhcr, 822 struct mlx4_cmd_mailbox *inbox, 823 struct mlx4_cmd_mailbox *outbox, 824 struct mlx4_cmd_info *cmd) 825 { 826 struct mlx4_priv *priv = mlx4_priv(dev); 827 u64 def_mac; 828 u8 port_type; 829 u16 short_field; 830 int err; 831 832 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 833 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 834 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 835 836 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 837 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 838 MLX4_CMD_NATIVE); 839 840 if (!err && dev->caps.function != slave) { 841 /* set slave default_mac address */ 842 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); 843 def_mac += slave << 8; 844 /* if config MAC in DB use it */ 845 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac) 846 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 847 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 848 849 /* get port type - currently only eth is enabled */ 850 MLX4_GET(port_type, outbox->buf, 851 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 852 853 /* No link sensing allowed */ 854 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 855 /* set port type to currently operating port type */ 856 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 857 858 MLX4_PUT(outbox->buf, port_type, 859 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 860 861 short_field = 1; /* slave max gids */ 862 MLX4_PUT(outbox->buf, short_field, 863 QUERY_PORT_CUR_MAX_GID_OFFSET); 864 865 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 866 MLX4_PUT(outbox->buf, short_field, 867 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 868 } 869 870 return err; 871 } 872 873 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 874 int *gid_tbl_len, int *pkey_tbl_len) 875 { 876 struct mlx4_cmd_mailbox *mailbox; 877 u32 *outbox; 878 u16 field; 879 int err; 880 881 mailbox = mlx4_alloc_cmd_mailbox(dev); 882 if (IS_ERR(mailbox)) 883 return PTR_ERR(mailbox); 884 885 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 886 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 887 MLX4_CMD_WRAPPED); 888 if (err) 889 goto out; 890 891 outbox = mailbox->buf; 892 893 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 894 *gid_tbl_len = field; 895 896 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 897 *pkey_tbl_len = field; 898 899 out: 900 mlx4_free_cmd_mailbox(dev, mailbox); 901 return err; 902 } 903 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 904 905 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 906 { 907 struct mlx4_cmd_mailbox *mailbox; 908 struct mlx4_icm_iter iter; 909 __be64 *pages; 910 int lg; 911 int nent = 0; 912 int i; 913 int err = 0; 914 int ts = 0, tc = 0; 915 916 mailbox = mlx4_alloc_cmd_mailbox(dev); 917 if (IS_ERR(mailbox)) 918 return PTR_ERR(mailbox); 919 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 920 pages = mailbox->buf; 921 922 for (mlx4_icm_first(icm, &iter); 923 !mlx4_icm_last(&iter); 924 mlx4_icm_next(&iter)) { 925 /* 926 * We have to pass pages that are aligned to their 927 * size, so find the least significant 1 in the 928 * address or size and use that as our log2 size. 929 */ 930 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 931 if (lg < MLX4_ICM_PAGE_SHIFT) { 932 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 933 MLX4_ICM_PAGE_SIZE, 934 (unsigned long long) mlx4_icm_addr(&iter), 935 mlx4_icm_size(&iter)); 936 err = -EINVAL; 937 goto out; 938 } 939 940 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 941 if (virt != -1) { 942 pages[nent * 2] = cpu_to_be64(virt); 943 virt += 1 << lg; 944 } 945 946 pages[nent * 2 + 1] = 947 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 948 (lg - MLX4_ICM_PAGE_SHIFT)); 949 ts += 1 << (lg - 10); 950 ++tc; 951 952 if (++nent == MLX4_MAILBOX_SIZE / 16) { 953 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 954 MLX4_CMD_TIME_CLASS_B, 955 MLX4_CMD_NATIVE); 956 if (err) 957 goto out; 958 nent = 0; 959 } 960 } 961 } 962 963 if (nent) 964 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 965 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 966 if (err) 967 goto out; 968 969 switch (op) { 970 case MLX4_CMD_MAP_FA: 971 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 972 break; 973 case MLX4_CMD_MAP_ICM_AUX: 974 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 975 break; 976 case MLX4_CMD_MAP_ICM: 977 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 978 tc, ts, (unsigned long long) virt - (ts << 10)); 979 break; 980 } 981 982 out: 983 mlx4_free_cmd_mailbox(dev, mailbox); 984 return err; 985 } 986 987 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 988 { 989 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 990 } 991 992 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 993 { 994 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 995 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 996 } 997 998 999 int mlx4_RUN_FW(struct mlx4_dev *dev) 1000 { 1001 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1002 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1003 } 1004 1005 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1006 { 1007 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1008 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1009 struct mlx4_cmd_mailbox *mailbox; 1010 u32 *outbox; 1011 int err = 0; 1012 u64 fw_ver; 1013 u16 cmd_if_rev; 1014 u8 lg; 1015 1016 #define QUERY_FW_OUT_SIZE 0x100 1017 #define QUERY_FW_VER_OFFSET 0x00 1018 #define QUERY_FW_PPF_ID 0x09 1019 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1020 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1021 #define QUERY_FW_ERR_START_OFFSET 0x30 1022 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1023 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1024 1025 #define QUERY_FW_SIZE_OFFSET 0x00 1026 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1027 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1028 1029 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1030 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1031 1032 #define QUERY_FW_CLOCK_OFFSET 0x50 1033 #define QUERY_FW_CLOCK_BAR 0x58 1034 1035 mailbox = mlx4_alloc_cmd_mailbox(dev); 1036 if (IS_ERR(mailbox)) 1037 return PTR_ERR(mailbox); 1038 outbox = mailbox->buf; 1039 1040 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1041 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1042 if (err) 1043 goto out; 1044 1045 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1046 /* 1047 * FW subminor version is at more significant bits than minor 1048 * version, so swap here. 1049 */ 1050 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1051 ((fw_ver & 0xffff0000ull) >> 16) | 1052 ((fw_ver & 0x0000ffffull) << 16); 1053 1054 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1055 dev->caps.function = lg; 1056 1057 if (mlx4_is_slave(dev)) 1058 goto out; 1059 1060 1061 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1062 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1063 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1064 mlx4_err(dev, "Installed FW has unsupported " 1065 "command interface revision %d.\n", 1066 cmd_if_rev); 1067 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1068 (int) (dev->caps.fw_ver >> 32), 1069 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1070 (int) dev->caps.fw_ver & 0xffff); 1071 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", 1072 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1073 err = -ENODEV; 1074 goto out; 1075 } 1076 1077 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1078 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1079 1080 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1081 cmd->max_cmds = 1 << lg; 1082 1083 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1084 (int) (dev->caps.fw_ver >> 32), 1085 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1086 (int) dev->caps.fw_ver & 0xffff, 1087 cmd_if_rev, cmd->max_cmds); 1088 1089 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1090 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1091 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1092 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1093 1094 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1095 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1096 1097 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1098 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1099 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1100 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1101 1102 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1103 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1104 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1105 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1106 fw->comm_bar, fw->comm_base); 1107 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1108 1109 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1110 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1111 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1112 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1113 fw->clock_bar, fw->clock_offset); 1114 1115 /* 1116 * Round up number of system pages needed in case 1117 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1118 */ 1119 fw->fw_pages = 1120 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1121 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1122 1123 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1124 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1125 1126 out: 1127 mlx4_free_cmd_mailbox(dev, mailbox); 1128 return err; 1129 } 1130 1131 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1132 struct mlx4_vhcr *vhcr, 1133 struct mlx4_cmd_mailbox *inbox, 1134 struct mlx4_cmd_mailbox *outbox, 1135 struct mlx4_cmd_info *cmd) 1136 { 1137 u8 *outbuf; 1138 int err; 1139 1140 outbuf = outbox->buf; 1141 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1142 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1143 if (err) 1144 return err; 1145 1146 /* for slaves, set pci PPF ID to invalid and zero out everything 1147 * else except FW version */ 1148 outbuf[0] = outbuf[1] = 0; 1149 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1150 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1151 1152 return 0; 1153 } 1154 1155 static void get_board_id(void *vsd, char *board_id) 1156 { 1157 int i; 1158 1159 #define VSD_OFFSET_SIG1 0x00 1160 #define VSD_OFFSET_SIG2 0xde 1161 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1162 #define VSD_OFFSET_TS_BOARD_ID 0x20 1163 1164 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1165 1166 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1167 1168 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1169 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1170 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1171 } else { 1172 /* 1173 * The board ID is a string but the firmware byte 1174 * swaps each 4-byte word before passing it back to 1175 * us. Therefore we need to swab it before printing. 1176 */ 1177 for (i = 0; i < 4; ++i) 1178 ((u32 *) board_id)[i] = 1179 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1180 } 1181 } 1182 1183 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1184 { 1185 struct mlx4_cmd_mailbox *mailbox; 1186 u32 *outbox; 1187 int err; 1188 1189 #define QUERY_ADAPTER_OUT_SIZE 0x100 1190 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1191 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1192 1193 mailbox = mlx4_alloc_cmd_mailbox(dev); 1194 if (IS_ERR(mailbox)) 1195 return PTR_ERR(mailbox); 1196 outbox = mailbox->buf; 1197 1198 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1199 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1200 if (err) 1201 goto out; 1202 1203 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1204 1205 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1206 adapter->board_id); 1207 1208 out: 1209 mlx4_free_cmd_mailbox(dev, mailbox); 1210 return err; 1211 } 1212 1213 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1214 { 1215 struct mlx4_cmd_mailbox *mailbox; 1216 __be32 *inbox; 1217 int err; 1218 1219 #define INIT_HCA_IN_SIZE 0x200 1220 #define INIT_HCA_VERSION_OFFSET 0x000 1221 #define INIT_HCA_VERSION 2 1222 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1223 #define INIT_HCA_FLAGS_OFFSET 0x014 1224 #define INIT_HCA_QPC_OFFSET 0x020 1225 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1226 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1227 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1228 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1229 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1230 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1231 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1232 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1233 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1234 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1235 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1236 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1237 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1238 #define INIT_HCA_MCAST_OFFSET 0x0c0 1239 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1240 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1241 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1242 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1243 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1244 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1245 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1246 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1247 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1248 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1249 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1250 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1251 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1252 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1253 #define INIT_HCA_TPT_OFFSET 0x0f0 1254 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1255 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1256 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1257 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1258 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1259 #define INIT_HCA_UAR_OFFSET 0x120 1260 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1261 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1262 1263 mailbox = mlx4_alloc_cmd_mailbox(dev); 1264 if (IS_ERR(mailbox)) 1265 return PTR_ERR(mailbox); 1266 inbox = mailbox->buf; 1267 1268 memset(inbox, 0, INIT_HCA_IN_SIZE); 1269 1270 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1271 1272 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1273 (ilog2(cache_line_size()) - 4) << 5; 1274 1275 #if defined(__LITTLE_ENDIAN) 1276 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1277 #elif defined(__BIG_ENDIAN) 1278 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1279 #else 1280 #error Host endianness not defined 1281 #endif 1282 /* Check port for UD address vector: */ 1283 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1284 1285 /* Enable IPoIB checksumming if we can: */ 1286 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1287 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1288 1289 /* Enable QoS support if module parameter set */ 1290 if (enable_qos) 1291 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1292 1293 /* enable counters */ 1294 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1295 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1296 1297 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1298 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1299 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1300 dev->caps.eqe_size = 64; 1301 dev->caps.eqe_factor = 1; 1302 } else { 1303 dev->caps.eqe_size = 32; 1304 dev->caps.eqe_factor = 0; 1305 } 1306 1307 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1308 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1309 dev->caps.cqe_size = 64; 1310 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 1311 } else { 1312 dev->caps.cqe_size = 32; 1313 } 1314 1315 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1316 1317 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1318 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1319 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1320 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1321 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1322 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1323 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1324 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1325 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1326 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1327 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1328 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1329 1330 /* steering attributes */ 1331 if (dev->caps.steering_mode == 1332 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1333 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1334 cpu_to_be32(1 << 1335 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1336 1337 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1338 MLX4_PUT(inbox, param->log_mc_entry_sz, 1339 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1340 MLX4_PUT(inbox, param->log_mc_table_sz, 1341 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1342 /* Enable Ethernet flow steering 1343 * with udp unicast and tcp unicast 1344 */ 1345 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1346 INIT_HCA_FS_ETH_BITS_OFFSET); 1347 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1348 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1349 /* Enable IPoIB flow steering 1350 * with udp unicast and tcp unicast 1351 */ 1352 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1353 INIT_HCA_FS_IB_BITS_OFFSET); 1354 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1355 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1356 } else { 1357 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1358 MLX4_PUT(inbox, param->log_mc_entry_sz, 1359 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1360 MLX4_PUT(inbox, param->log_mc_hash_sz, 1361 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1362 MLX4_PUT(inbox, param->log_mc_table_sz, 1363 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1364 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1365 MLX4_PUT(inbox, (u8) (1 << 3), 1366 INIT_HCA_UC_STEERING_OFFSET); 1367 } 1368 1369 /* TPT attributes */ 1370 1371 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1372 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1373 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1374 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1375 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1376 1377 /* UAR attributes */ 1378 1379 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1380 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1381 1382 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1383 MLX4_CMD_NATIVE); 1384 1385 if (err) 1386 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1387 1388 mlx4_free_cmd_mailbox(dev, mailbox); 1389 return err; 1390 } 1391 1392 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1393 struct mlx4_init_hca_param *param) 1394 { 1395 struct mlx4_cmd_mailbox *mailbox; 1396 __be32 *outbox; 1397 u32 dword_field; 1398 int err; 1399 u8 byte_field; 1400 1401 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1402 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1403 1404 mailbox = mlx4_alloc_cmd_mailbox(dev); 1405 if (IS_ERR(mailbox)) 1406 return PTR_ERR(mailbox); 1407 outbox = mailbox->buf; 1408 1409 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1410 MLX4_CMD_QUERY_HCA, 1411 MLX4_CMD_TIME_CLASS_B, 1412 !mlx4_is_slave(dev)); 1413 if (err) 1414 goto out; 1415 1416 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1417 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1418 1419 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1420 1421 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1422 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1423 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1424 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1425 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1426 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1427 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1428 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1429 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1430 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1431 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1432 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1433 1434 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1435 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1436 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1437 } else { 1438 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1439 if (byte_field & 0x8) 1440 param->steering_mode = MLX4_STEERING_MODE_B0; 1441 else 1442 param->steering_mode = MLX4_STEERING_MODE_A0; 1443 } 1444 /* steering attributes */ 1445 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1446 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1447 MLX4_GET(param->log_mc_entry_sz, outbox, 1448 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1449 MLX4_GET(param->log_mc_table_sz, outbox, 1450 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1451 } else { 1452 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1453 MLX4_GET(param->log_mc_entry_sz, outbox, 1454 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1455 MLX4_GET(param->log_mc_hash_sz, outbox, 1456 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1457 MLX4_GET(param->log_mc_table_sz, outbox, 1458 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1459 } 1460 1461 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1462 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1463 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1464 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1465 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1466 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1467 1468 /* TPT attributes */ 1469 1470 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1471 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1472 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1473 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1474 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1475 1476 /* UAR attributes */ 1477 1478 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1479 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1480 1481 out: 1482 mlx4_free_cmd_mailbox(dev, mailbox); 1483 1484 return err; 1485 } 1486 1487 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 1488 * and real QP0 are active, so that the paravirtualized QP0 is ready 1489 * to operate */ 1490 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 1491 { 1492 struct mlx4_priv *priv = mlx4_priv(dev); 1493 /* irrelevant if not infiniband */ 1494 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 1495 priv->mfunc.master.qp0_state[port].qp0_active) 1496 return 1; 1497 return 0; 1498 } 1499 1500 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1501 struct mlx4_vhcr *vhcr, 1502 struct mlx4_cmd_mailbox *inbox, 1503 struct mlx4_cmd_mailbox *outbox, 1504 struct mlx4_cmd_info *cmd) 1505 { 1506 struct mlx4_priv *priv = mlx4_priv(dev); 1507 int port = vhcr->in_modifier; 1508 int err; 1509 1510 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 1511 return 0; 1512 1513 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1514 /* Enable port only if it was previously disabled */ 1515 if (!priv->mfunc.master.init_port_ref[port]) { 1516 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1517 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1518 if (err) 1519 return err; 1520 } 1521 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1522 } else { 1523 if (slave == mlx4_master_func_num(dev)) { 1524 if (check_qp0_state(dev, slave, port) && 1525 !priv->mfunc.master.qp0_state[port].port_active) { 1526 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1527 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1528 if (err) 1529 return err; 1530 priv->mfunc.master.qp0_state[port].port_active = 1; 1531 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1532 } 1533 } else 1534 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1535 } 1536 ++priv->mfunc.master.init_port_ref[port]; 1537 return 0; 1538 } 1539 1540 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 1541 { 1542 struct mlx4_cmd_mailbox *mailbox; 1543 u32 *inbox; 1544 int err; 1545 u32 flags; 1546 u16 field; 1547 1548 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1549 #define INIT_PORT_IN_SIZE 256 1550 #define INIT_PORT_FLAGS_OFFSET 0x00 1551 #define INIT_PORT_FLAG_SIG (1 << 18) 1552 #define INIT_PORT_FLAG_NG (1 << 17) 1553 #define INIT_PORT_FLAG_G0 (1 << 16) 1554 #define INIT_PORT_VL_SHIFT 4 1555 #define INIT_PORT_PORT_WIDTH_SHIFT 8 1556 #define INIT_PORT_MTU_OFFSET 0x04 1557 #define INIT_PORT_MAX_GID_OFFSET 0x06 1558 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 1559 #define INIT_PORT_GUID0_OFFSET 0x10 1560 #define INIT_PORT_NODE_GUID_OFFSET 0x18 1561 #define INIT_PORT_SI_GUID_OFFSET 0x20 1562 1563 mailbox = mlx4_alloc_cmd_mailbox(dev); 1564 if (IS_ERR(mailbox)) 1565 return PTR_ERR(mailbox); 1566 inbox = mailbox->buf; 1567 1568 memset(inbox, 0, INIT_PORT_IN_SIZE); 1569 1570 flags = 0; 1571 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 1572 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 1573 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 1574 1575 field = 128 << dev->caps.ib_mtu_cap[port]; 1576 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 1577 field = dev->caps.gid_table_len[port]; 1578 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 1579 field = dev->caps.pkey_table_len[port]; 1580 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 1581 1582 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1583 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1584 1585 mlx4_free_cmd_mailbox(dev, mailbox); 1586 } else 1587 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1588 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1589 1590 return err; 1591 } 1592 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 1593 1594 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1595 struct mlx4_vhcr *vhcr, 1596 struct mlx4_cmd_mailbox *inbox, 1597 struct mlx4_cmd_mailbox *outbox, 1598 struct mlx4_cmd_info *cmd) 1599 { 1600 struct mlx4_priv *priv = mlx4_priv(dev); 1601 int port = vhcr->in_modifier; 1602 int err; 1603 1604 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 1605 (1 << port))) 1606 return 0; 1607 1608 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1609 if (priv->mfunc.master.init_port_ref[port] == 1) { 1610 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1611 1000, MLX4_CMD_NATIVE); 1612 if (err) 1613 return err; 1614 } 1615 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1616 } else { 1617 /* infiniband port */ 1618 if (slave == mlx4_master_func_num(dev)) { 1619 if (!priv->mfunc.master.qp0_state[port].qp0_active && 1620 priv->mfunc.master.qp0_state[port].port_active) { 1621 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1622 1000, MLX4_CMD_NATIVE); 1623 if (err) 1624 return err; 1625 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1626 priv->mfunc.master.qp0_state[port].port_active = 0; 1627 } 1628 } else 1629 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1630 } 1631 --priv->mfunc.master.init_port_ref[port]; 1632 return 0; 1633 } 1634 1635 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 1636 { 1637 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1638 MLX4_CMD_WRAPPED); 1639 } 1640 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 1641 1642 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 1643 { 1644 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 1645 MLX4_CMD_NATIVE); 1646 } 1647 1648 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 1649 { 1650 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 1651 MLX4_CMD_SET_ICM_SIZE, 1652 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1653 if (ret) 1654 return ret; 1655 1656 /* 1657 * Round up number of system pages needed in case 1658 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1659 */ 1660 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1661 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1662 1663 return 0; 1664 } 1665 1666 int mlx4_NOP(struct mlx4_dev *dev) 1667 { 1668 /* Input modifier of 0x1f means "finish as soon as possible." */ 1669 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 1670 } 1671 1672 #define MLX4_WOL_SETUP_MODE (5 << 28) 1673 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 1674 { 1675 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1676 1677 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 1678 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1679 MLX4_CMD_NATIVE); 1680 } 1681 EXPORT_SYMBOL_GPL(mlx4_wol_read); 1682 1683 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 1684 { 1685 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1686 1687 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 1688 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1689 } 1690 EXPORT_SYMBOL_GPL(mlx4_wol_write); 1691