1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 4] = "reliable multicast", 88 [ 5] = "FCoIB support", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [10] = "VMM", 94 [12] = "Dual Port Different Protocol (DPDP) support", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [24] = "Demand paging support", 103 [25] = "Router support", 104 [30] = "IBoE support", 105 [32] = "Unicast loopback support", 106 [34] = "FCS header control", 107 [38] = "Wake On LAN support", 108 [40] = "UDP RSS support", 109 [41] = "Unicast VEP steering support", 110 [42] = "Multicast VEP steering support", 111 [48] = "Counters support", 112 [53] = "Port ETS Scheduler support", 113 [55] = "Port link type sensing support", 114 [59] = "Port management change event support", 115 [61] = "64 byte EQE support", 116 [62] = "64 byte CQE support", 117 }; 118 int i; 119 120 mlx4_dbg(dev, "DEV_CAP flags:\n"); 121 for (i = 0; i < ARRAY_SIZE(fname); ++i) 122 if (fname[i] && (flags & (1LL << i))) 123 mlx4_dbg(dev, " %s\n", fname[i]); 124 } 125 126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127 { 128 static const char * const fname[] = { 129 [0] = "RSS support", 130 [1] = "RSS Toeplitz Hash Function support", 131 [2] = "RSS XOR Hash Function support", 132 [3] = "Device managed flow steering support", 133 [4] = "Automatic MAC reassignment support", 134 [5] = "Time stamping support", 135 [6] = "VST (control vlan insertion/stripping) support", 136 [7] = "FSM (MAC anti-spoofing) support", 137 [8] = "Dynamic QP updates support", 138 [9] = "Device managed flow steering IPoIB support", 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 140 [11] = "MAD DEMUX (Secure-Host) support", 141 [12] = "Large cache line (>64B) CQE stride support", 142 [13] = "Large cache line (>64B) EQE stride support", 143 [14] = "Ethernet protocol control support", 144 [15] = "Ethernet Backplane autoneg support", 145 [16] = "CONFIG DEV support", 146 [17] = "Asymmetric EQs support", 147 [18] = "More than 80 VFs support", 148 [19] = "Performance optimized for limited rule configuration flow steering support" 149 }; 150 int i; 151 152 for (i = 0; i < ARRAY_SIZE(fname); ++i) 153 if (fname[i] && (flags & (1LL << i))) 154 mlx4_dbg(dev, " %s\n", fname[i]); 155 } 156 157 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 158 { 159 struct mlx4_cmd_mailbox *mailbox; 160 u32 *inbox; 161 int err = 0; 162 163 #define MOD_STAT_CFG_IN_SIZE 0x100 164 165 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 166 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 167 168 mailbox = mlx4_alloc_cmd_mailbox(dev); 169 if (IS_ERR(mailbox)) 170 return PTR_ERR(mailbox); 171 inbox = mailbox->buf; 172 173 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 174 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 175 176 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 177 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 178 179 mlx4_free_cmd_mailbox(dev, mailbox); 180 return err; 181 } 182 183 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 184 { 185 struct mlx4_cmd_mailbox *mailbox; 186 u32 *outbox; 187 u8 in_modifier; 188 u8 field; 189 u16 field16; 190 int err; 191 192 #define QUERY_FUNC_BUS_OFFSET 0x00 193 #define QUERY_FUNC_DEVICE_OFFSET 0x01 194 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 195 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 196 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 197 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 198 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 199 200 mailbox = mlx4_alloc_cmd_mailbox(dev); 201 if (IS_ERR(mailbox)) 202 return PTR_ERR(mailbox); 203 outbox = mailbox->buf; 204 205 in_modifier = slave; 206 207 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 208 MLX4_CMD_QUERY_FUNC, 209 MLX4_CMD_TIME_CLASS_A, 210 MLX4_CMD_NATIVE); 211 if (err) 212 goto out; 213 214 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 215 func->bus = field & 0xf; 216 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 217 func->device = field & 0xf1; 218 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 219 func->function = field & 0x7; 220 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 221 func->physical_function = field & 0xf; 222 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 223 func->rsvd_eqs = field16 & 0xffff; 224 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 225 func->max_eq = field16 & 0xffff; 226 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 227 func->rsvd_uars = field & 0x0f; 228 229 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 230 func->bus, func->device, func->function, func->physical_function, 231 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 232 233 out: 234 mlx4_free_cmd_mailbox(dev, mailbox); 235 return err; 236 } 237 238 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 239 struct mlx4_vhcr *vhcr, 240 struct mlx4_cmd_mailbox *inbox, 241 struct mlx4_cmd_mailbox *outbox, 242 struct mlx4_cmd_info *cmd) 243 { 244 struct mlx4_priv *priv = mlx4_priv(dev); 245 u8 field, port; 246 u32 size, proxy_qp, qkey; 247 int err = 0; 248 struct mlx4_func func; 249 250 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 251 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 252 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 253 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 254 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 255 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 256 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 257 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 258 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 259 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 260 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 261 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 262 263 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 264 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 265 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 266 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 267 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 268 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 269 270 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 271 272 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 273 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 274 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 275 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 276 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 277 278 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 279 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 280 281 /* when opcode modifier = 1 */ 282 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 283 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 284 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 285 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 286 287 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 288 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 289 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 290 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 291 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 292 293 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 294 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 295 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 296 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 297 298 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 299 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 300 301 if (vhcr->op_modifier == 1) { 302 struct mlx4_active_ports actv_ports = 303 mlx4_get_active_ports(dev, slave); 304 int converted_port = mlx4_slave_convert_port( 305 dev, slave, vhcr->in_modifier); 306 307 if (converted_port < 0) 308 return -EINVAL; 309 310 vhcr->in_modifier = converted_port; 311 /* phys-port = logical-port */ 312 field = vhcr->in_modifier - 313 find_first_bit(actv_ports.ports, dev->caps.num_ports); 314 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 315 316 port = vhcr->in_modifier; 317 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 318 319 /* Set nic_info bit to mark new fields support */ 320 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 321 322 if (mlx4_vf_smi_enabled(dev, slave, port) && 323 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 324 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 325 MLX4_PUT(outbox->buf, qkey, 326 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 327 } 328 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 329 330 /* size is now the QP number */ 331 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 332 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 333 334 size += 2; 335 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 336 337 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 338 proxy_qp += 2; 339 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 340 341 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 342 QUERY_FUNC_CAP_PHYS_PORT_ID); 343 344 } else if (vhcr->op_modifier == 0) { 345 struct mlx4_active_ports actv_ports = 346 mlx4_get_active_ports(dev, slave); 347 /* enable rdma and ethernet interfaces, and new quota locations */ 348 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 349 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX); 350 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 351 352 field = min( 353 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 354 dev->caps.num_ports); 355 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 356 357 size = dev->caps.function_caps; /* set PF behaviours */ 358 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 359 360 field = 0; /* protected FMR support not available as yet */ 361 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 362 363 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 364 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 365 size = dev->caps.num_qps; 366 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 367 368 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 370 size = dev->caps.num_srqs; 371 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 372 373 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 374 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 375 size = dev->caps.num_cqs; 376 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 377 378 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 379 mlx4_QUERY_FUNC(dev, &func, slave)) { 380 size = vhcr->in_modifier & 381 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 382 dev->caps.num_eqs : 383 rounddown_pow_of_two(dev->caps.num_eqs); 384 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 385 size = dev->caps.reserved_eqs; 386 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 387 } else { 388 size = vhcr->in_modifier & 389 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 390 func.max_eq : 391 rounddown_pow_of_two(func.max_eq); 392 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 393 size = func.rsvd_eqs; 394 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 395 } 396 397 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 398 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 399 size = dev->caps.num_mpts; 400 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 401 402 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 403 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 404 size = dev->caps.num_mtts; 405 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 406 407 size = dev->caps.num_mgms + dev->caps.num_amgms; 408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 410 411 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 412 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 413 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 414 } else 415 err = -EINVAL; 416 417 return err; 418 } 419 420 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 421 struct mlx4_func_cap *func_cap) 422 { 423 struct mlx4_cmd_mailbox *mailbox; 424 u32 *outbox; 425 u8 field, op_modifier; 426 u32 size, qkey; 427 int err = 0, quotas = 0; 428 u32 in_modifier; 429 430 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 431 in_modifier = op_modifier ? gen_or_port : 432 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 433 434 mailbox = mlx4_alloc_cmd_mailbox(dev); 435 if (IS_ERR(mailbox)) 436 return PTR_ERR(mailbox); 437 438 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 439 MLX4_CMD_QUERY_FUNC_CAP, 440 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 441 if (err) 442 goto out; 443 444 outbox = mailbox->buf; 445 446 if (!op_modifier) { 447 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 448 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 449 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 450 err = -EPROTONOSUPPORT; 451 goto out; 452 } 453 func_cap->flags = field; 454 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 455 456 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 457 func_cap->num_ports = field; 458 459 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 460 func_cap->pf_context_behaviour = size; 461 462 if (quotas) { 463 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 464 func_cap->qp_quota = size & 0xFFFFFF; 465 466 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 467 func_cap->srq_quota = size & 0xFFFFFF; 468 469 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 470 func_cap->cq_quota = size & 0xFFFFFF; 471 472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 473 func_cap->mpt_quota = size & 0xFFFFFF; 474 475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 476 func_cap->mtt_quota = size & 0xFFFFFF; 477 478 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 479 func_cap->mcg_quota = size & 0xFFFFFF; 480 481 } else { 482 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 483 func_cap->qp_quota = size & 0xFFFFFF; 484 485 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 486 func_cap->srq_quota = size & 0xFFFFFF; 487 488 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 489 func_cap->cq_quota = size & 0xFFFFFF; 490 491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 492 func_cap->mpt_quota = size & 0xFFFFFF; 493 494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 495 func_cap->mtt_quota = size & 0xFFFFFF; 496 497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 498 func_cap->mcg_quota = size & 0xFFFFFF; 499 } 500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 501 func_cap->max_eq = size & 0xFFFFFF; 502 503 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 504 func_cap->reserved_eq = size & 0xFFFFFF; 505 506 func_cap->extra_flags = 0; 507 508 /* Mailbox data from 0x6c and onward should only be treated if 509 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 510 */ 511 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 512 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 513 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 514 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 515 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 516 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 517 } 518 519 goto out; 520 } 521 522 /* logical port query */ 523 if (gen_or_port > dev->caps.num_ports) { 524 err = -EINVAL; 525 goto out; 526 } 527 528 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 529 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 530 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 531 mlx4_err(dev, "VLAN is enforced on this port\n"); 532 err = -EPROTONOSUPPORT; 533 goto out; 534 } 535 536 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 537 mlx4_err(dev, "Force mac is enabled on this port\n"); 538 err = -EPROTONOSUPPORT; 539 goto out; 540 } 541 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 542 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 543 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 544 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 545 err = -EPROTONOSUPPORT; 546 goto out; 547 } 548 } 549 550 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 551 func_cap->physical_port = field; 552 if (func_cap->physical_port != gen_or_port) { 553 err = -ENOSYS; 554 goto out; 555 } 556 557 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 558 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 559 func_cap->qp0_qkey = qkey; 560 } else { 561 func_cap->qp0_qkey = 0; 562 } 563 564 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 565 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 566 567 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 568 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 569 570 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 571 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 572 573 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 574 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 575 576 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 577 MLX4_GET(func_cap->phys_port_id, outbox, 578 QUERY_FUNC_CAP_PHYS_PORT_ID); 579 580 /* All other resources are allocated by the master, but we still report 581 * 'num' and 'reserved' capabilities as follows: 582 * - num remains the maximum resource index 583 * - 'num - reserved' is the total available objects of a resource, but 584 * resource indices may be less than 'reserved' 585 * TODO: set per-resource quotas */ 586 587 out: 588 mlx4_free_cmd_mailbox(dev, mailbox); 589 590 return err; 591 } 592 593 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 594 { 595 struct mlx4_cmd_mailbox *mailbox; 596 u32 *outbox; 597 u8 field; 598 u32 field32, flags, ext_flags; 599 u16 size; 600 u16 stat_rate; 601 int err; 602 int i; 603 604 #define QUERY_DEV_CAP_OUT_SIZE 0x100 605 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 606 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 607 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 608 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 609 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 610 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 611 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 612 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 613 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 614 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 615 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 616 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 617 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 618 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 619 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 620 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 621 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 622 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 623 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 624 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 625 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 626 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 627 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 628 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 629 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 630 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 631 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 632 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 633 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 634 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 635 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 636 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 637 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 638 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 639 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 640 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 641 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 642 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 643 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 644 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 645 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 646 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 647 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 648 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 649 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 650 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 651 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 652 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 653 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 654 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 655 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 656 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 657 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 658 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 659 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 660 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 661 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 662 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 663 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 664 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 665 #define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a 666 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 667 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 668 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 669 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 670 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 671 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 672 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 673 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 674 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 675 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 676 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 677 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 678 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 679 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 680 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 681 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 682 #define QUERY_DEV_CAP_VXLAN 0x9e 683 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 684 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 685 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 686 687 dev_cap->flags2 = 0; 688 mailbox = mlx4_alloc_cmd_mailbox(dev); 689 if (IS_ERR(mailbox)) 690 return PTR_ERR(mailbox); 691 outbox = mailbox->buf; 692 693 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 694 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 695 if (err) 696 goto out; 697 698 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 699 dev_cap->reserved_qps = 1 << (field & 0xf); 700 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 701 dev_cap->max_qps = 1 << (field & 0x1f); 702 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 703 dev_cap->reserved_srqs = 1 << (field >> 4); 704 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 705 dev_cap->max_srqs = 1 << (field & 0x1f); 706 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 707 dev_cap->max_cq_sz = 1 << field; 708 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 709 dev_cap->reserved_cqs = 1 << (field & 0xf); 710 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 711 dev_cap->max_cqs = 1 << (field & 0x1f); 712 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 713 dev_cap->max_mpts = 1 << (field & 0x3f); 714 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 715 dev_cap->reserved_eqs = 1 << (field & 0xf); 716 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 717 dev_cap->max_eqs = 1 << (field & 0xf); 718 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 719 dev_cap->reserved_mtts = 1 << (field >> 4); 720 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 721 dev_cap->max_mrw_sz = 1 << field; 722 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 723 dev_cap->reserved_mrws = 1 << (field & 0xf); 724 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 725 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 726 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 727 dev_cap->num_sys_eqs = size & 0xfff; 728 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 729 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 730 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 731 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 732 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 733 field &= 0x1f; 734 if (!field) 735 dev_cap->max_gso_sz = 0; 736 else 737 dev_cap->max_gso_sz = 1 << field; 738 739 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 740 if (field & 0x20) 741 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 742 if (field & 0x10) 743 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 744 field &= 0xf; 745 if (field) { 746 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 747 dev_cap->max_rss_tbl_sz = 1 << field; 748 } else 749 dev_cap->max_rss_tbl_sz = 0; 750 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 751 dev_cap->max_rdma_global = 1 << (field & 0x3f); 752 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 753 dev_cap->local_ca_ack_delay = field & 0x1f; 754 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 755 dev_cap->num_ports = field & 0xf; 756 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 757 dev_cap->max_msg_sz = 1 << (field & 0x1f); 758 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 759 if (field & 0x80) 760 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 761 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 762 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 763 if (field & 0x80) 764 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 765 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 766 dev_cap->fs_max_num_qp_per_entry = field; 767 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 768 dev_cap->stat_rate_support = stat_rate; 769 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 770 if (field & 0x80) 771 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 772 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 773 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 774 dev_cap->flags = flags | (u64)ext_flags << 32; 775 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 776 dev_cap->reserved_uars = field >> 4; 777 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 778 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 779 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 780 dev_cap->min_page_sz = 1 << field; 781 782 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 783 if (field & 0x80) { 784 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 785 dev_cap->bf_reg_size = 1 << (field & 0x1f); 786 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 787 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 788 field = 3; 789 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 790 } else { 791 dev_cap->bf_reg_size = 0; 792 } 793 794 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 795 dev_cap->max_sq_sg = field; 796 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 797 dev_cap->max_sq_desc_sz = size; 798 799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 800 dev_cap->max_qp_per_mcg = 1 << field; 801 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 802 dev_cap->reserved_mgms = field & 0xf; 803 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 804 dev_cap->max_mcgs = 1 << field; 805 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 806 dev_cap->reserved_pds = field >> 4; 807 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 808 dev_cap->max_pds = 1 << (field & 0x3f); 809 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 810 dev_cap->reserved_xrcds = field >> 4; 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 812 dev_cap->max_xrcds = 1 << (field & 0x1f); 813 814 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 815 dev_cap->rdmarc_entry_sz = size; 816 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 817 dev_cap->qpc_entry_sz = size; 818 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 819 dev_cap->aux_entry_sz = size; 820 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 821 dev_cap->altc_entry_sz = size; 822 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 823 dev_cap->eqc_entry_sz = size; 824 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 825 dev_cap->cqc_entry_sz = size; 826 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 827 dev_cap->srq_entry_sz = size; 828 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 829 dev_cap->cmpt_entry_sz = size; 830 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 831 dev_cap->mtt_entry_sz = size; 832 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 833 dev_cap->dmpt_entry_sz = size; 834 835 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 836 dev_cap->max_srq_sz = 1 << field; 837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 838 dev_cap->max_qp_sz = 1 << field; 839 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 840 dev_cap->resize_srq = field & 1; 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 842 dev_cap->max_rq_sg = field; 843 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 844 dev_cap->max_rq_desc_sz = size; 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 846 if (field & (1 << 5)) 847 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 848 if (field & (1 << 6)) 849 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 850 if (field & (1 << 7)) 851 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 852 MLX4_GET(dev_cap->bmme_flags, outbox, 853 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 854 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 855 if (field & 0x20) 856 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 857 MLX4_GET(dev_cap->reserved_lkey, outbox, 858 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 859 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 860 if (field32 & (1 << 0)) 861 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 862 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 863 if (field & 1<<6) 864 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 865 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 866 if (field & 1<<3) 867 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 868 MLX4_GET(dev_cap->max_icm_sz, outbox, 869 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 870 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 871 MLX4_GET(dev_cap->max_counters, outbox, 872 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 873 874 MLX4_GET(field32, outbox, 875 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 876 if (field32 & (1 << 0)) 877 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 878 879 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 880 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 881 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 882 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 883 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 884 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 885 886 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 887 if (field32 & (1 << 16)) 888 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 889 if (field32 & (1 << 26)) 890 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 891 if (field32 & (1 << 20)) 892 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 893 if (field32 & (1 << 21)) 894 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 895 896 for (i = 1; i <= dev_cap->num_ports; i++) { 897 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 898 if (err) 899 goto out; 900 } 901 902 /* 903 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 904 * we can't use any EQs whose doorbell falls on that page, 905 * even if the EQ itself isn't reserved. 906 */ 907 if (dev_cap->num_sys_eqs == 0) 908 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 909 dev_cap->reserved_eqs); 910 else 911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 912 913 out: 914 mlx4_free_cmd_mailbox(dev, mailbox); 915 return err; 916 } 917 918 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 919 { 920 if (dev_cap->bf_reg_size > 0) 921 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 922 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 923 else 924 mlx4_dbg(dev, "BlueFlame not available\n"); 925 926 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 927 dev_cap->bmme_flags, dev_cap->reserved_lkey); 928 mlx4_dbg(dev, "Max ICM size %lld MB\n", 929 (unsigned long long) dev_cap->max_icm_sz >> 20); 930 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 931 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 932 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 933 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 934 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 935 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 936 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 937 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 938 dev_cap->eqc_entry_sz); 939 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 940 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 941 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 942 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 943 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 944 dev_cap->max_pds, dev_cap->reserved_mgms); 945 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 946 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 947 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 948 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 949 dev_cap->port_cap[1].max_port_width); 950 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 951 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 952 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 953 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 954 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 955 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 956 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 957 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 958 dev_cap->dmfs_high_rate_qpn_base); 959 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 960 dev_cap->dmfs_high_rate_qpn_range); 961 dump_dev_cap_flags(dev, dev_cap->flags); 962 dump_dev_cap_flags2(dev, dev_cap->flags2); 963 } 964 965 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 966 { 967 struct mlx4_cmd_mailbox *mailbox; 968 u32 *outbox; 969 u8 field; 970 u32 field32; 971 int err; 972 973 mailbox = mlx4_alloc_cmd_mailbox(dev); 974 if (IS_ERR(mailbox)) 975 return PTR_ERR(mailbox); 976 outbox = mailbox->buf; 977 978 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 979 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 980 MLX4_CMD_TIME_CLASS_A, 981 MLX4_CMD_NATIVE); 982 983 if (err) 984 goto out; 985 986 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 987 port_cap->max_vl = field >> 4; 988 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 989 port_cap->ib_mtu = field >> 4; 990 port_cap->max_port_width = field & 0xf; 991 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 992 port_cap->max_gids = 1 << (field & 0xf); 993 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 994 port_cap->max_pkeys = 1 << (field & 0xf); 995 } else { 996 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 997 #define QUERY_PORT_MTU_OFFSET 0x01 998 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 999 #define QUERY_PORT_WIDTH_OFFSET 0x06 1000 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1001 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1002 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1003 #define QUERY_PORT_MAC_OFFSET 0x10 1004 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1005 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1006 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1007 1008 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1009 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1010 if (err) 1011 goto out; 1012 1013 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1014 port_cap->supported_port_types = field & 3; 1015 port_cap->suggested_type = (field >> 3) & 1; 1016 port_cap->default_sense = (field >> 4) & 1; 1017 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1018 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1019 port_cap->ib_mtu = field & 0xf; 1020 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1021 port_cap->max_port_width = field & 0xf; 1022 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1023 port_cap->max_gids = 1 << (field >> 4); 1024 port_cap->max_pkeys = 1 << (field & 0xf); 1025 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1026 port_cap->max_vl = field & 0xf; 1027 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1028 port_cap->log_max_macs = field & 0xf; 1029 port_cap->log_max_vlans = field >> 4; 1030 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1031 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1032 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1033 port_cap->trans_type = field32 >> 24; 1034 port_cap->vendor_oui = field32 & 0xffffff; 1035 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1036 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1037 } 1038 1039 out: 1040 mlx4_free_cmd_mailbox(dev, mailbox); 1041 return err; 1042 } 1043 1044 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1045 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1046 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1047 1048 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1049 struct mlx4_vhcr *vhcr, 1050 struct mlx4_cmd_mailbox *inbox, 1051 struct mlx4_cmd_mailbox *outbox, 1052 struct mlx4_cmd_info *cmd) 1053 { 1054 u64 flags; 1055 int err = 0; 1056 u8 field; 1057 u32 bmme_flags, field32; 1058 int real_port; 1059 int slave_port; 1060 int first_port; 1061 struct mlx4_active_ports actv_ports; 1062 1063 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1064 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1065 if (err) 1066 return err; 1067 1068 /* add port mng change event capability and disable mw type 1 1069 * unconditionally to slaves 1070 */ 1071 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1072 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1073 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1074 actv_ports = mlx4_get_active_ports(dev, slave); 1075 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1076 for (slave_port = 0, real_port = first_port; 1077 real_port < first_port + 1078 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1079 ++real_port, ++slave_port) { 1080 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1081 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1082 else 1083 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1084 } 1085 for (; slave_port < dev->caps.num_ports; ++slave_port) 1086 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1087 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1088 1089 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1090 field &= ~0x0F; 1091 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1092 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1093 1094 /* For guests, disable timestamp */ 1095 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1096 field &= 0x7f; 1097 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1098 1099 /* For guests, disable vxlan tunneling */ 1100 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1101 field &= 0xf7; 1102 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1103 1104 /* For guests, report Blueflame disabled */ 1105 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1106 field &= 0x7f; 1107 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1108 1109 /* For guests, disable mw type 2 */ 1110 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1111 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1112 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1113 1114 /* turn off device-managed steering capability if not enabled */ 1115 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1116 MLX4_GET(field, outbox->buf, 1117 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1118 field &= 0x7f; 1119 MLX4_PUT(outbox->buf, field, 1120 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1121 } 1122 1123 /* turn off ipoib managed steering for guests */ 1124 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1125 field &= ~0x80; 1126 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1127 1128 /* turn off host side virt features (VST, FSM, etc) for guests */ 1129 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1130 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1131 DEV_CAP_EXT_2_FLAG_FSM); 1132 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1133 1134 return 0; 1135 } 1136 1137 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1138 struct mlx4_vhcr *vhcr, 1139 struct mlx4_cmd_mailbox *inbox, 1140 struct mlx4_cmd_mailbox *outbox, 1141 struct mlx4_cmd_info *cmd) 1142 { 1143 struct mlx4_priv *priv = mlx4_priv(dev); 1144 u64 def_mac; 1145 u8 port_type; 1146 u16 short_field; 1147 int err; 1148 int admin_link_state; 1149 int port = mlx4_slave_convert_port(dev, slave, 1150 vhcr->in_modifier & 0xFF); 1151 1152 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1153 #define MLX4_PORT_LINK_UP_MASK 0x80 1154 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1155 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1156 1157 if (port < 0) 1158 return -EINVAL; 1159 1160 /* Protect against untrusted guests: enforce that this is the 1161 * QUERY_PORT general query. 1162 */ 1163 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1164 return -EINVAL; 1165 1166 vhcr->in_modifier = port; 1167 1168 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1169 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1170 MLX4_CMD_NATIVE); 1171 1172 if (!err && dev->caps.function != slave) { 1173 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1174 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1175 1176 /* get port type - currently only eth is enabled */ 1177 MLX4_GET(port_type, outbox->buf, 1178 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1179 1180 /* No link sensing allowed */ 1181 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1182 /* set port type to currently operating port type */ 1183 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1184 1185 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1186 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1187 port_type |= MLX4_PORT_LINK_UP_MASK; 1188 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1189 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1190 1191 MLX4_PUT(outbox->buf, port_type, 1192 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1193 1194 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1195 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1196 else 1197 short_field = 1; /* slave max gids */ 1198 MLX4_PUT(outbox->buf, short_field, 1199 QUERY_PORT_CUR_MAX_GID_OFFSET); 1200 1201 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1202 MLX4_PUT(outbox->buf, short_field, 1203 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1204 } 1205 1206 return err; 1207 } 1208 1209 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1210 int *gid_tbl_len, int *pkey_tbl_len) 1211 { 1212 struct mlx4_cmd_mailbox *mailbox; 1213 u32 *outbox; 1214 u16 field; 1215 int err; 1216 1217 mailbox = mlx4_alloc_cmd_mailbox(dev); 1218 if (IS_ERR(mailbox)) 1219 return PTR_ERR(mailbox); 1220 1221 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1222 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1223 MLX4_CMD_WRAPPED); 1224 if (err) 1225 goto out; 1226 1227 outbox = mailbox->buf; 1228 1229 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1230 *gid_tbl_len = field; 1231 1232 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1233 *pkey_tbl_len = field; 1234 1235 out: 1236 mlx4_free_cmd_mailbox(dev, mailbox); 1237 return err; 1238 } 1239 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1240 1241 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1242 { 1243 struct mlx4_cmd_mailbox *mailbox; 1244 struct mlx4_icm_iter iter; 1245 __be64 *pages; 1246 int lg; 1247 int nent = 0; 1248 int i; 1249 int err = 0; 1250 int ts = 0, tc = 0; 1251 1252 mailbox = mlx4_alloc_cmd_mailbox(dev); 1253 if (IS_ERR(mailbox)) 1254 return PTR_ERR(mailbox); 1255 pages = mailbox->buf; 1256 1257 for (mlx4_icm_first(icm, &iter); 1258 !mlx4_icm_last(&iter); 1259 mlx4_icm_next(&iter)) { 1260 /* 1261 * We have to pass pages that are aligned to their 1262 * size, so find the least significant 1 in the 1263 * address or size and use that as our log2 size. 1264 */ 1265 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1266 if (lg < MLX4_ICM_PAGE_SHIFT) { 1267 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1268 MLX4_ICM_PAGE_SIZE, 1269 (unsigned long long) mlx4_icm_addr(&iter), 1270 mlx4_icm_size(&iter)); 1271 err = -EINVAL; 1272 goto out; 1273 } 1274 1275 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1276 if (virt != -1) { 1277 pages[nent * 2] = cpu_to_be64(virt); 1278 virt += 1 << lg; 1279 } 1280 1281 pages[nent * 2 + 1] = 1282 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1283 (lg - MLX4_ICM_PAGE_SHIFT)); 1284 ts += 1 << (lg - 10); 1285 ++tc; 1286 1287 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1288 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1289 MLX4_CMD_TIME_CLASS_B, 1290 MLX4_CMD_NATIVE); 1291 if (err) 1292 goto out; 1293 nent = 0; 1294 } 1295 } 1296 } 1297 1298 if (nent) 1299 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1300 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1301 if (err) 1302 goto out; 1303 1304 switch (op) { 1305 case MLX4_CMD_MAP_FA: 1306 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1307 break; 1308 case MLX4_CMD_MAP_ICM_AUX: 1309 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1310 break; 1311 case MLX4_CMD_MAP_ICM: 1312 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1313 tc, ts, (unsigned long long) virt - (ts << 10)); 1314 break; 1315 } 1316 1317 out: 1318 mlx4_free_cmd_mailbox(dev, mailbox); 1319 return err; 1320 } 1321 1322 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1323 { 1324 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1325 } 1326 1327 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1328 { 1329 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1330 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1331 } 1332 1333 1334 int mlx4_RUN_FW(struct mlx4_dev *dev) 1335 { 1336 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1337 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1338 } 1339 1340 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1341 { 1342 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1343 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1344 struct mlx4_cmd_mailbox *mailbox; 1345 u32 *outbox; 1346 int err = 0; 1347 u64 fw_ver; 1348 u16 cmd_if_rev; 1349 u8 lg; 1350 1351 #define QUERY_FW_OUT_SIZE 0x100 1352 #define QUERY_FW_VER_OFFSET 0x00 1353 #define QUERY_FW_PPF_ID 0x09 1354 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1355 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1356 #define QUERY_FW_ERR_START_OFFSET 0x30 1357 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1358 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1359 1360 #define QUERY_FW_SIZE_OFFSET 0x00 1361 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1362 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1363 1364 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1365 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1366 1367 #define QUERY_FW_CLOCK_OFFSET 0x50 1368 #define QUERY_FW_CLOCK_BAR 0x58 1369 1370 mailbox = mlx4_alloc_cmd_mailbox(dev); 1371 if (IS_ERR(mailbox)) 1372 return PTR_ERR(mailbox); 1373 outbox = mailbox->buf; 1374 1375 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1376 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1377 if (err) 1378 goto out; 1379 1380 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1381 /* 1382 * FW subminor version is at more significant bits than minor 1383 * version, so swap here. 1384 */ 1385 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1386 ((fw_ver & 0xffff0000ull) >> 16) | 1387 ((fw_ver & 0x0000ffffull) << 16); 1388 1389 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1390 dev->caps.function = lg; 1391 1392 if (mlx4_is_slave(dev)) 1393 goto out; 1394 1395 1396 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1397 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1398 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1399 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1400 cmd_if_rev); 1401 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1402 (int) (dev->caps.fw_ver >> 32), 1403 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1404 (int) dev->caps.fw_ver & 0xffff); 1405 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1406 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1407 err = -ENODEV; 1408 goto out; 1409 } 1410 1411 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1412 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1413 1414 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1415 cmd->max_cmds = 1 << lg; 1416 1417 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1418 (int) (dev->caps.fw_ver >> 32), 1419 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1420 (int) dev->caps.fw_ver & 0xffff, 1421 cmd_if_rev, cmd->max_cmds); 1422 1423 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1424 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1425 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1426 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1427 1428 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1429 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1430 1431 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1432 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1433 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1434 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1435 1436 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1437 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1438 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1439 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1440 fw->comm_bar, fw->comm_base); 1441 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1442 1443 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1444 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1445 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1446 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1447 fw->clock_bar, fw->clock_offset); 1448 1449 /* 1450 * Round up number of system pages needed in case 1451 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1452 */ 1453 fw->fw_pages = 1454 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1455 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1456 1457 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1458 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1459 1460 out: 1461 mlx4_free_cmd_mailbox(dev, mailbox); 1462 return err; 1463 } 1464 1465 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1466 struct mlx4_vhcr *vhcr, 1467 struct mlx4_cmd_mailbox *inbox, 1468 struct mlx4_cmd_mailbox *outbox, 1469 struct mlx4_cmd_info *cmd) 1470 { 1471 u8 *outbuf; 1472 int err; 1473 1474 outbuf = outbox->buf; 1475 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1476 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1477 if (err) 1478 return err; 1479 1480 /* for slaves, set pci PPF ID to invalid and zero out everything 1481 * else except FW version */ 1482 outbuf[0] = outbuf[1] = 0; 1483 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1484 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1485 1486 return 0; 1487 } 1488 1489 static void get_board_id(void *vsd, char *board_id) 1490 { 1491 int i; 1492 1493 #define VSD_OFFSET_SIG1 0x00 1494 #define VSD_OFFSET_SIG2 0xde 1495 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1496 #define VSD_OFFSET_TS_BOARD_ID 0x20 1497 1498 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1499 1500 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1501 1502 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1503 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1504 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1505 } else { 1506 /* 1507 * The board ID is a string but the firmware byte 1508 * swaps each 4-byte word before passing it back to 1509 * us. Therefore we need to swab it before printing. 1510 */ 1511 for (i = 0; i < 4; ++i) 1512 ((u32 *) board_id)[i] = 1513 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1514 } 1515 } 1516 1517 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1518 { 1519 struct mlx4_cmd_mailbox *mailbox; 1520 u32 *outbox; 1521 int err; 1522 1523 #define QUERY_ADAPTER_OUT_SIZE 0x100 1524 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1525 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1526 1527 mailbox = mlx4_alloc_cmd_mailbox(dev); 1528 if (IS_ERR(mailbox)) 1529 return PTR_ERR(mailbox); 1530 outbox = mailbox->buf; 1531 1532 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1533 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1534 if (err) 1535 goto out; 1536 1537 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1538 1539 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1540 adapter->board_id); 1541 1542 out: 1543 mlx4_free_cmd_mailbox(dev, mailbox); 1544 return err; 1545 } 1546 1547 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1548 { 1549 struct mlx4_cmd_mailbox *mailbox; 1550 __be32 *inbox; 1551 int err; 1552 static const u8 a0_dmfs_hw_steering[] = { 1553 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1554 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1555 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1556 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1557 }; 1558 1559 #define INIT_HCA_IN_SIZE 0x200 1560 #define INIT_HCA_VERSION_OFFSET 0x000 1561 #define INIT_HCA_VERSION 2 1562 #define INIT_HCA_VXLAN_OFFSET 0x0c 1563 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1564 #define INIT_HCA_FLAGS_OFFSET 0x014 1565 #define INIT_HCA_QPC_OFFSET 0x020 1566 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1567 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1568 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1569 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1570 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1571 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1572 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1573 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1574 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1575 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1576 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1577 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1578 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1579 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1580 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1581 #define INIT_HCA_MCAST_OFFSET 0x0c0 1582 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1583 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1584 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1585 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1586 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1587 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1588 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1589 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1590 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1591 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1592 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1593 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1594 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1595 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1596 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1597 #define INIT_HCA_TPT_OFFSET 0x0f0 1598 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1599 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1600 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1601 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1602 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1603 #define INIT_HCA_UAR_OFFSET 0x120 1604 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1605 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1606 1607 mailbox = mlx4_alloc_cmd_mailbox(dev); 1608 if (IS_ERR(mailbox)) 1609 return PTR_ERR(mailbox); 1610 inbox = mailbox->buf; 1611 1612 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1613 1614 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1615 (ilog2(cache_line_size()) - 4) << 5; 1616 1617 #if defined(__LITTLE_ENDIAN) 1618 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1619 #elif defined(__BIG_ENDIAN) 1620 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1621 #else 1622 #error Host endianness not defined 1623 #endif 1624 /* Check port for UD address vector: */ 1625 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1626 1627 /* Enable IPoIB checksumming if we can: */ 1628 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1629 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1630 1631 /* Enable QoS support if module parameter set */ 1632 if (enable_qos) 1633 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1634 1635 /* enable counters */ 1636 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1637 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1638 1639 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1640 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1641 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1642 dev->caps.eqe_size = 64; 1643 dev->caps.eqe_factor = 1; 1644 } else { 1645 dev->caps.eqe_size = 32; 1646 dev->caps.eqe_factor = 0; 1647 } 1648 1649 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1650 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1651 dev->caps.cqe_size = 64; 1652 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1653 } else { 1654 dev->caps.cqe_size = 32; 1655 } 1656 1657 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1658 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1659 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1660 dev->caps.eqe_size = cache_line_size(); 1661 dev->caps.cqe_size = cache_line_size(); 1662 dev->caps.eqe_factor = 0; 1663 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1664 (ilog2(dev->caps.eqe_size) - 5)), 1665 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1666 1667 /* User still need to know to support CQE > 32B */ 1668 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1669 } 1670 1671 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1672 1673 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1674 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1675 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1676 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1677 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1678 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1679 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1680 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1681 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1682 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1683 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1684 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1685 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1686 1687 /* steering attributes */ 1688 if (dev->caps.steering_mode == 1689 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1690 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1691 cpu_to_be32(1 << 1692 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1693 1694 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1695 MLX4_PUT(inbox, param->log_mc_entry_sz, 1696 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1697 MLX4_PUT(inbox, param->log_mc_table_sz, 1698 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1699 /* Enable Ethernet flow steering 1700 * with udp unicast and tcp unicast 1701 */ 1702 if (dev->caps.dmfs_high_steer_mode != 1703 MLX4_STEERING_DMFS_A0_STATIC) 1704 MLX4_PUT(inbox, 1705 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1706 INIT_HCA_FS_ETH_BITS_OFFSET); 1707 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1708 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1709 /* Enable IPoIB flow steering 1710 * with udp unicast and tcp unicast 1711 */ 1712 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1713 INIT_HCA_FS_IB_BITS_OFFSET); 1714 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1715 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1716 1717 if (dev->caps.dmfs_high_steer_mode != 1718 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1719 MLX4_PUT(inbox, 1720 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1721 << 6)), 1722 INIT_HCA_FS_A0_OFFSET); 1723 } else { 1724 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1725 MLX4_PUT(inbox, param->log_mc_entry_sz, 1726 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1727 MLX4_PUT(inbox, param->log_mc_hash_sz, 1728 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1729 MLX4_PUT(inbox, param->log_mc_table_sz, 1730 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1731 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1732 MLX4_PUT(inbox, (u8) (1 << 3), 1733 INIT_HCA_UC_STEERING_OFFSET); 1734 } 1735 1736 /* TPT attributes */ 1737 1738 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1739 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1740 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1741 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1742 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1743 1744 /* UAR attributes */ 1745 1746 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1747 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1748 1749 /* set parser VXLAN attributes */ 1750 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1751 u8 parser_params = 0; 1752 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1753 } 1754 1755 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1756 MLX4_CMD_NATIVE); 1757 1758 if (err) 1759 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1760 1761 mlx4_free_cmd_mailbox(dev, mailbox); 1762 return err; 1763 } 1764 1765 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1766 struct mlx4_init_hca_param *param) 1767 { 1768 struct mlx4_cmd_mailbox *mailbox; 1769 __be32 *outbox; 1770 u32 dword_field; 1771 int err; 1772 u8 byte_field; 1773 static const u8 a0_dmfs_query_hw_steering[] = { 1774 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1775 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1776 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1777 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1778 }; 1779 1780 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1781 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1782 1783 mailbox = mlx4_alloc_cmd_mailbox(dev); 1784 if (IS_ERR(mailbox)) 1785 return PTR_ERR(mailbox); 1786 outbox = mailbox->buf; 1787 1788 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1789 MLX4_CMD_QUERY_HCA, 1790 MLX4_CMD_TIME_CLASS_B, 1791 !mlx4_is_slave(dev)); 1792 if (err) 1793 goto out; 1794 1795 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1796 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1797 1798 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1799 1800 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1801 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1802 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1803 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1804 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1805 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1806 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1807 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1808 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1809 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1810 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1811 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1812 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1813 1814 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1815 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1816 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1817 } else { 1818 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1819 if (byte_field & 0x8) 1820 param->steering_mode = MLX4_STEERING_MODE_B0; 1821 else 1822 param->steering_mode = MLX4_STEERING_MODE_A0; 1823 } 1824 /* steering attributes */ 1825 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1826 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1827 MLX4_GET(param->log_mc_entry_sz, outbox, 1828 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1829 MLX4_GET(param->log_mc_table_sz, outbox, 1830 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1831 MLX4_GET(byte_field, outbox, 1832 INIT_HCA_FS_A0_OFFSET); 1833 param->dmfs_high_steer_mode = 1834 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 1835 } else { 1836 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1837 MLX4_GET(param->log_mc_entry_sz, outbox, 1838 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1839 MLX4_GET(param->log_mc_hash_sz, outbox, 1840 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1841 MLX4_GET(param->log_mc_table_sz, outbox, 1842 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1843 } 1844 1845 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1846 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1847 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1848 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1849 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1850 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1851 1852 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1853 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1854 if (byte_field) { 1855 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1856 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 1857 param->cqe_size = 1 << ((byte_field & 1858 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 1859 param->eqe_size = 1 << (((byte_field & 1860 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 1861 } 1862 1863 /* TPT attributes */ 1864 1865 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1866 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1867 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1868 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1869 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1870 1871 /* UAR attributes */ 1872 1873 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1874 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1875 1876 out: 1877 mlx4_free_cmd_mailbox(dev, mailbox); 1878 1879 return err; 1880 } 1881 1882 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 1883 * and real QP0 are active, so that the paravirtualized QP0 is ready 1884 * to operate */ 1885 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 1886 { 1887 struct mlx4_priv *priv = mlx4_priv(dev); 1888 /* irrelevant if not infiniband */ 1889 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 1890 priv->mfunc.master.qp0_state[port].qp0_active) 1891 return 1; 1892 return 0; 1893 } 1894 1895 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1896 struct mlx4_vhcr *vhcr, 1897 struct mlx4_cmd_mailbox *inbox, 1898 struct mlx4_cmd_mailbox *outbox, 1899 struct mlx4_cmd_info *cmd) 1900 { 1901 struct mlx4_priv *priv = mlx4_priv(dev); 1902 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 1903 int err; 1904 1905 if (port < 0) 1906 return -EINVAL; 1907 1908 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 1909 return 0; 1910 1911 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1912 /* Enable port only if it was previously disabled */ 1913 if (!priv->mfunc.master.init_port_ref[port]) { 1914 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1915 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1916 if (err) 1917 return err; 1918 } 1919 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1920 } else { 1921 if (slave == mlx4_master_func_num(dev)) { 1922 if (check_qp0_state(dev, slave, port) && 1923 !priv->mfunc.master.qp0_state[port].port_active) { 1924 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1925 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1926 if (err) 1927 return err; 1928 priv->mfunc.master.qp0_state[port].port_active = 1; 1929 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1930 } 1931 } else 1932 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1933 } 1934 ++priv->mfunc.master.init_port_ref[port]; 1935 return 0; 1936 } 1937 1938 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 1939 { 1940 struct mlx4_cmd_mailbox *mailbox; 1941 u32 *inbox; 1942 int err; 1943 u32 flags; 1944 u16 field; 1945 1946 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1947 #define INIT_PORT_IN_SIZE 256 1948 #define INIT_PORT_FLAGS_OFFSET 0x00 1949 #define INIT_PORT_FLAG_SIG (1 << 18) 1950 #define INIT_PORT_FLAG_NG (1 << 17) 1951 #define INIT_PORT_FLAG_G0 (1 << 16) 1952 #define INIT_PORT_VL_SHIFT 4 1953 #define INIT_PORT_PORT_WIDTH_SHIFT 8 1954 #define INIT_PORT_MTU_OFFSET 0x04 1955 #define INIT_PORT_MAX_GID_OFFSET 0x06 1956 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 1957 #define INIT_PORT_GUID0_OFFSET 0x10 1958 #define INIT_PORT_NODE_GUID_OFFSET 0x18 1959 #define INIT_PORT_SI_GUID_OFFSET 0x20 1960 1961 mailbox = mlx4_alloc_cmd_mailbox(dev); 1962 if (IS_ERR(mailbox)) 1963 return PTR_ERR(mailbox); 1964 inbox = mailbox->buf; 1965 1966 flags = 0; 1967 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 1968 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 1969 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 1970 1971 field = 128 << dev->caps.ib_mtu_cap[port]; 1972 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 1973 field = dev->caps.gid_table_len[port]; 1974 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 1975 field = dev->caps.pkey_table_len[port]; 1976 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 1977 1978 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1979 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1980 1981 mlx4_free_cmd_mailbox(dev, mailbox); 1982 } else 1983 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1984 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1985 1986 return err; 1987 } 1988 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 1989 1990 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1991 struct mlx4_vhcr *vhcr, 1992 struct mlx4_cmd_mailbox *inbox, 1993 struct mlx4_cmd_mailbox *outbox, 1994 struct mlx4_cmd_info *cmd) 1995 { 1996 struct mlx4_priv *priv = mlx4_priv(dev); 1997 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 1998 int err; 1999 2000 if (port < 0) 2001 return -EINVAL; 2002 2003 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2004 (1 << port))) 2005 return 0; 2006 2007 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2008 if (priv->mfunc.master.init_port_ref[port] == 1) { 2009 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2010 1000, MLX4_CMD_NATIVE); 2011 if (err) 2012 return err; 2013 } 2014 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2015 } else { 2016 /* infiniband port */ 2017 if (slave == mlx4_master_func_num(dev)) { 2018 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2019 priv->mfunc.master.qp0_state[port].port_active) { 2020 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2021 1000, MLX4_CMD_NATIVE); 2022 if (err) 2023 return err; 2024 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2025 priv->mfunc.master.qp0_state[port].port_active = 0; 2026 } 2027 } else 2028 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2029 } 2030 --priv->mfunc.master.init_port_ref[port]; 2031 return 0; 2032 } 2033 2034 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2035 { 2036 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 2037 MLX4_CMD_WRAPPED); 2038 } 2039 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2040 2041 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2042 { 2043 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 2044 MLX4_CMD_NATIVE); 2045 } 2046 2047 struct mlx4_config_dev { 2048 __be32 update_flags; 2049 __be32 rsvd1[3]; 2050 __be16 vxlan_udp_dport; 2051 __be16 rsvd2; 2052 __be32 rsvd3[27]; 2053 __be16 rsvd4; 2054 u8 rsvd5; 2055 u8 rx_checksum_val; 2056 }; 2057 2058 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2059 2060 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2061 { 2062 int err; 2063 struct mlx4_cmd_mailbox *mailbox; 2064 2065 mailbox = mlx4_alloc_cmd_mailbox(dev); 2066 if (IS_ERR(mailbox)) 2067 return PTR_ERR(mailbox); 2068 2069 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2070 2071 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2072 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2073 2074 mlx4_free_cmd_mailbox(dev, mailbox); 2075 return err; 2076 } 2077 2078 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2079 { 2080 int err; 2081 struct mlx4_cmd_mailbox *mailbox; 2082 2083 mailbox = mlx4_alloc_cmd_mailbox(dev); 2084 if (IS_ERR(mailbox)) 2085 return PTR_ERR(mailbox); 2086 2087 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2088 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2089 2090 if (!err) 2091 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2092 2093 mlx4_free_cmd_mailbox(dev, mailbox); 2094 return err; 2095 } 2096 2097 /* Conversion between the HW values and the actual functionality. 2098 * The value represented by the array index, 2099 * and the functionality determined by the flags. 2100 */ 2101 static const u8 config_dev_csum_flags[] = { 2102 [0] = 0, 2103 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2104 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2105 MLX4_RX_CSUM_MODE_L4, 2106 [3] = MLX4_RX_CSUM_MODE_L4 | 2107 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2108 MLX4_RX_CSUM_MODE_MULTI_VLAN 2109 }; 2110 2111 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2112 struct mlx4_config_dev_params *params) 2113 { 2114 struct mlx4_config_dev config_dev; 2115 int err; 2116 u8 csum_mask; 2117 2118 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2119 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2120 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2121 2122 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2123 return -ENOTSUPP; 2124 2125 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2126 if (err) 2127 return err; 2128 2129 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2130 CONFIG_DEV_RX_CSUM_MODE_MASK; 2131 2132 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2133 return -EINVAL; 2134 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2135 2136 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2137 CONFIG_DEV_RX_CSUM_MODE_MASK; 2138 2139 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2140 return -EINVAL; 2141 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2142 2143 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2144 2145 return 0; 2146 } 2147 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2148 2149 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2150 { 2151 struct mlx4_config_dev config_dev; 2152 2153 memset(&config_dev, 0, sizeof(config_dev)); 2154 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2155 config_dev.vxlan_udp_dport = udp_port; 2156 2157 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2158 } 2159 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2160 2161 2162 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2163 { 2164 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2165 MLX4_CMD_SET_ICM_SIZE, 2166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2167 if (ret) 2168 return ret; 2169 2170 /* 2171 * Round up number of system pages needed in case 2172 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2173 */ 2174 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2175 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2176 2177 return 0; 2178 } 2179 2180 int mlx4_NOP(struct mlx4_dev *dev) 2181 { 2182 /* Input modifier of 0x1f means "finish as soon as possible." */ 2183 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 2184 } 2185 2186 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2187 { 2188 u8 port; 2189 u32 *outbox; 2190 struct mlx4_cmd_mailbox *mailbox; 2191 u32 in_mod; 2192 u32 guid_hi, guid_lo; 2193 int err, ret = 0; 2194 #define MOD_STAT_CFG_PORT_OFFSET 8 2195 #define MOD_STAT_CFG_GUID_H 0X14 2196 #define MOD_STAT_CFG_GUID_L 0X1c 2197 2198 mailbox = mlx4_alloc_cmd_mailbox(dev); 2199 if (IS_ERR(mailbox)) 2200 return PTR_ERR(mailbox); 2201 outbox = mailbox->buf; 2202 2203 for (port = 1; port <= dev->caps.num_ports; port++) { 2204 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2205 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2206 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2207 MLX4_CMD_NATIVE); 2208 if (err) { 2209 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2210 port); 2211 ret = err; 2212 } else { 2213 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2214 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2215 dev->caps.phys_port_id[port] = (u64)guid_lo | 2216 (u64)guid_hi << 32; 2217 } 2218 } 2219 mlx4_free_cmd_mailbox(dev, mailbox); 2220 return ret; 2221 } 2222 2223 #define MLX4_WOL_SETUP_MODE (5 << 28) 2224 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2225 { 2226 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2227 2228 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2229 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2230 MLX4_CMD_NATIVE); 2231 } 2232 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2233 2234 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2235 { 2236 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2237 2238 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2239 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2240 } 2241 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2242 2243 enum { 2244 ADD_TO_MCG = 0x26, 2245 }; 2246 2247 2248 void mlx4_opreq_action(struct work_struct *work) 2249 { 2250 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2251 opreq_task); 2252 struct mlx4_dev *dev = &priv->dev; 2253 int num_tasks = atomic_read(&priv->opreq_count); 2254 struct mlx4_cmd_mailbox *mailbox; 2255 struct mlx4_mgm *mgm; 2256 u32 *outbox; 2257 u32 modifier; 2258 u16 token; 2259 u16 type; 2260 int err; 2261 u32 num_qps; 2262 struct mlx4_qp qp; 2263 int i; 2264 u8 rem_mcg; 2265 u8 prot; 2266 2267 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2268 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2269 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2270 #define GET_OP_REQ_DATA_OFFSET 0x20 2271 2272 mailbox = mlx4_alloc_cmd_mailbox(dev); 2273 if (IS_ERR(mailbox)) { 2274 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2275 return; 2276 } 2277 outbox = mailbox->buf; 2278 2279 while (num_tasks) { 2280 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2281 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2282 MLX4_CMD_NATIVE); 2283 if (err) { 2284 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2285 err); 2286 return; 2287 } 2288 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2289 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2290 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2291 type &= 0xfff; 2292 2293 switch (type) { 2294 case ADD_TO_MCG: 2295 if (dev->caps.steering_mode == 2296 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2297 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2298 err = EPERM; 2299 break; 2300 } 2301 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2302 GET_OP_REQ_DATA_OFFSET); 2303 num_qps = be32_to_cpu(mgm->members_count) & 2304 MGM_QPN_MASK; 2305 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2306 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2307 2308 for (i = 0; i < num_qps; i++) { 2309 qp.qpn = be32_to_cpu(mgm->qp[i]); 2310 if (rem_mcg) 2311 err = mlx4_multicast_detach(dev, &qp, 2312 mgm->gid, 2313 prot, 0); 2314 else 2315 err = mlx4_multicast_attach(dev, &qp, 2316 mgm->gid, 2317 mgm->gid[5] 2318 , 0, prot, 2319 NULL); 2320 if (err) 2321 break; 2322 } 2323 break; 2324 default: 2325 mlx4_warn(dev, "Bad type for required operation\n"); 2326 err = EINVAL; 2327 break; 2328 } 2329 err = mlx4_cmd(dev, 0, ((u32) err | 2330 (__force u32)cpu_to_be32(token) << 16), 2331 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2332 MLX4_CMD_NATIVE); 2333 if (err) { 2334 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2335 err); 2336 goto out; 2337 } 2338 memset(outbox, 0, 0xffc); 2339 num_tasks = atomic_dec_return(&priv->opreq_count); 2340 } 2341 2342 out: 2343 mlx4_free_cmd_mailbox(dev, mailbox); 2344 } 2345 2346 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2347 struct mlx4_cmd_mailbox *mailbox) 2348 { 2349 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2350 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2351 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2352 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2353 2354 u32 set_attr_mask, getresp_attr_mask; 2355 u32 trap_attr_mask, traprepress_attr_mask; 2356 2357 MLX4_GET(set_attr_mask, mailbox->buf, 2358 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2359 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2360 set_attr_mask); 2361 2362 MLX4_GET(getresp_attr_mask, mailbox->buf, 2363 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2364 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2365 getresp_attr_mask); 2366 2367 MLX4_GET(trap_attr_mask, mailbox->buf, 2368 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2369 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2370 trap_attr_mask); 2371 2372 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2373 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2374 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2375 traprepress_attr_mask); 2376 2377 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2378 traprepress_attr_mask) 2379 return 1; 2380 2381 return 0; 2382 } 2383 2384 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2385 { 2386 struct mlx4_cmd_mailbox *mailbox; 2387 int secure_host_active; 2388 int err; 2389 2390 /* Check if mad_demux is supported */ 2391 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2392 return 0; 2393 2394 mailbox = mlx4_alloc_cmd_mailbox(dev); 2395 if (IS_ERR(mailbox)) { 2396 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2397 return -ENOMEM; 2398 } 2399 2400 /* Query mad_demux to find out which MADs are handled by internal sma */ 2401 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2402 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2403 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2404 if (err) { 2405 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2406 err); 2407 goto out; 2408 } 2409 2410 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2411 2412 /* Config mad_demux to handle all MADs returned by the query above */ 2413 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2414 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2415 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2416 if (err) { 2417 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2418 goto out; 2419 } 2420 2421 if (secure_host_active) 2422 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2423 out: 2424 mlx4_free_cmd_mailbox(dev, mailbox); 2425 return err; 2426 } 2427 2428 /* Access Reg commands */ 2429 enum mlx4_access_reg_masks { 2430 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2431 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2432 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2433 }; 2434 2435 struct mlx4_access_reg { 2436 __be16 constant1; 2437 u8 status; 2438 u8 resrvd1; 2439 __be16 reg_id; 2440 u8 method; 2441 u8 constant2; 2442 __be32 resrvd2[2]; 2443 __be16 len_const; 2444 __be16 resrvd3; 2445 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2446 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2447 } __attribute__((__packed__)); 2448 2449 /** 2450 * mlx4_ACCESS_REG - Generic access reg command. 2451 * @dev: mlx4_dev. 2452 * @reg_id: register ID to access. 2453 * @method: Access method Read/Write. 2454 * @reg_len: register length to Read/Write in bytes. 2455 * @reg_data: reg_data pointer to Read/Write From/To. 2456 * 2457 * Access ConnectX registers FW command. 2458 * Returns 0 on success and copies outbox mlx4_access_reg data 2459 * field into reg_data or a negative error code. 2460 */ 2461 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2462 enum mlx4_access_reg_method method, 2463 u16 reg_len, void *reg_data) 2464 { 2465 struct mlx4_cmd_mailbox *inbox, *outbox; 2466 struct mlx4_access_reg *inbuf, *outbuf; 2467 int err; 2468 2469 inbox = mlx4_alloc_cmd_mailbox(dev); 2470 if (IS_ERR(inbox)) 2471 return PTR_ERR(inbox); 2472 2473 outbox = mlx4_alloc_cmd_mailbox(dev); 2474 if (IS_ERR(outbox)) { 2475 mlx4_free_cmd_mailbox(dev, inbox); 2476 return PTR_ERR(outbox); 2477 } 2478 2479 inbuf = inbox->buf; 2480 outbuf = outbox->buf; 2481 2482 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2483 inbuf->constant2 = 0x1; 2484 inbuf->reg_id = cpu_to_be16(reg_id); 2485 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2486 2487 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2488 inbuf->len_const = 2489 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2490 ((0x3) << 12)); 2491 2492 memcpy(inbuf->reg_data, reg_data, reg_len); 2493 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2494 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2495 MLX4_CMD_WRAPPED); 2496 if (err) 2497 goto out; 2498 2499 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2500 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2501 mlx4_err(dev, 2502 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2503 reg_id, err); 2504 goto out; 2505 } 2506 2507 memcpy(reg_data, outbuf->reg_data, reg_len); 2508 out: 2509 mlx4_free_cmd_mailbox(dev, inbox); 2510 mlx4_free_cmd_mailbox(dev, outbox); 2511 return err; 2512 } 2513 2514 /* ConnectX registers IDs */ 2515 enum mlx4_reg_id { 2516 MLX4_REG_ID_PTYS = 0x5004, 2517 }; 2518 2519 /** 2520 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2521 * register 2522 * @dev: mlx4_dev. 2523 * @method: Access method Read/Write. 2524 * @ptys_reg: PTYS register data pointer. 2525 * 2526 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2527 * configuration 2528 * Returns 0 on success or a negative error code. 2529 */ 2530 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2531 enum mlx4_access_reg_method method, 2532 struct mlx4_ptys_reg *ptys_reg) 2533 { 2534 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2535 method, sizeof(*ptys_reg), ptys_reg); 2536 } 2537 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2538 2539 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2540 struct mlx4_vhcr *vhcr, 2541 struct mlx4_cmd_mailbox *inbox, 2542 struct mlx4_cmd_mailbox *outbox, 2543 struct mlx4_cmd_info *cmd) 2544 { 2545 struct mlx4_access_reg *inbuf = inbox->buf; 2546 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2547 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2548 2549 if (slave != mlx4_master_func_num(dev) && 2550 method == MLX4_ACCESS_REG_WRITE) 2551 return -EPERM; 2552 2553 if (reg_id == MLX4_REG_ID_PTYS) { 2554 struct mlx4_ptys_reg *ptys_reg = 2555 (struct mlx4_ptys_reg *)inbuf->reg_data; 2556 2557 ptys_reg->local_port = 2558 mlx4_slave_convert_port(dev, slave, 2559 ptys_reg->local_port); 2560 } 2561 2562 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2563 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2564 MLX4_CMD_NATIVE); 2565 } 2566