1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 #include <linux/kernel.h> 40 41 #include "fw.h" 42 #include "icm.h" 43 44 enum { 45 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 46 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 47 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 48 }; 49 50 extern void __buggy_use_of_MLX4_GET(void); 51 extern void __buggy_use_of_MLX4_PUT(void); 52 53 static bool enable_qos; 54 module_param(enable_qos, bool, 0444); 55 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: off)"); 56 57 #define MLX4_GET(dest, source, offset) \ 58 do { \ 59 void *__p = (char *) (source) + (offset); \ 60 __be64 val; \ 61 switch (sizeof(dest)) { \ 62 case 1: (dest) = *(u8 *) __p; break; \ 63 case 2: (dest) = be16_to_cpup(__p); break; \ 64 case 4: (dest) = be32_to_cpup(__p); break; \ 65 case 8: val = get_unaligned((__be64 *)__p); \ 66 (dest) = be64_to_cpu(val); break; \ 67 default: __buggy_use_of_MLX4_GET(); \ 68 } \ 69 } while (0) 70 71 #define MLX4_PUT(dest, source, offset) \ 72 do { \ 73 void *__d = ((char *) (dest) + (offset)); \ 74 switch (sizeof(source)) { \ 75 case 1: *(u8 *) __d = (source); break; \ 76 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 77 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 78 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 79 default: __buggy_use_of_MLX4_PUT(); \ 80 } \ 81 } while (0) 82 83 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 84 { 85 static const char *fname[] = { 86 [ 0] = "RC transport", 87 [ 1] = "UC transport", 88 [ 2] = "UD transport", 89 [ 3] = "XRC transport", 90 [ 6] = "SRQ support", 91 [ 7] = "IPoIB checksum offload", 92 [ 8] = "P_Key violation counter", 93 [ 9] = "Q_Key violation counter", 94 [12] = "Dual Port Different Protocol (DPDP) support", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [30] = "IBoE support", 103 [32] = "Unicast loopback support", 104 [34] = "FCS header control", 105 [37] = "Wake On LAN (port1) support", 106 [38] = "Wake On LAN (port2) support", 107 [40] = "UDP RSS support", 108 [41] = "Unicast VEP steering support", 109 [42] = "Multicast VEP steering support", 110 [48] = "Counters support", 111 [52] = "RSS IP fragments support", 112 [53] = "Port ETS Scheduler support", 113 [55] = "Port link type sensing support", 114 [59] = "Port management change event support", 115 [61] = "64 byte EQE support", 116 [62] = "64 byte CQE support", 117 }; 118 int i; 119 120 mlx4_dbg(dev, "DEV_CAP flags:\n"); 121 for (i = 0; i < ARRAY_SIZE(fname); ++i) 122 if (fname[i] && (flags & (1LL << i))) 123 mlx4_dbg(dev, " %s\n", fname[i]); 124 } 125 126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127 { 128 static const char * const fname[] = { 129 [0] = "RSS support", 130 [1] = "RSS Toeplitz Hash Function support", 131 [2] = "RSS XOR Hash Function support", 132 [3] = "Device managed flow steering support", 133 [4] = "Automatic MAC reassignment support", 134 [5] = "Time stamping support", 135 [6] = "VST (control vlan insertion/stripping) support", 136 [7] = "FSM (MAC anti-spoofing) support", 137 [8] = "Dynamic QP updates support", 138 [9] = "Device managed flow steering IPoIB support", 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 140 [11] = "MAD DEMUX (Secure-Host) support", 141 [12] = "Large cache line (>64B) CQE stride support", 142 [13] = "Large cache line (>64B) EQE stride support", 143 [14] = "Ethernet protocol control support", 144 [15] = "Ethernet Backplane autoneg support", 145 [16] = "CONFIG DEV support", 146 [17] = "Asymmetric EQs support", 147 [18] = "More than 80 VFs support", 148 [19] = "Performance optimized for limited rule configuration flow steering support", 149 [20] = "Recoverable error events support", 150 [21] = "Port Remap support", 151 [22] = "QCN support", 152 [23] = "QP rate limiting support", 153 [24] = "Ethernet Flow control statistics support", 154 [25] = "Granular QoS per VF support", 155 [26] = "Port ETS Scheduler support", 156 [27] = "Port beacon support", 157 [28] = "RX-ALL support", 158 [29] = "802.1ad offload support", 159 [31] = "Modifying loopback source checks using UPDATE_QP support", 160 [32] = "Loopback source checks support", 161 [33] = "RoCEv2 support", 162 [34] = "DMFS Sniffer support (UC & MC)", 163 [35] = "Diag counters per port", 164 [36] = "QinQ VST mode support", 165 [37] = "sl to vl mapping table change event support", 166 [38] = "user MAC support", 167 }; 168 int i; 169 170 for (i = 0; i < ARRAY_SIZE(fname); ++i) 171 if (fname[i] && (flags & (1LL << i))) 172 mlx4_dbg(dev, " %s\n", fname[i]); 173 } 174 175 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 176 { 177 struct mlx4_cmd_mailbox *mailbox; 178 u32 *inbox; 179 int err = 0; 180 181 #define MOD_STAT_CFG_IN_SIZE 0x100 182 183 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 184 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 185 186 mailbox = mlx4_alloc_cmd_mailbox(dev); 187 if (IS_ERR(mailbox)) 188 return PTR_ERR(mailbox); 189 inbox = mailbox->buf; 190 191 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 192 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 193 194 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 195 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 196 197 mlx4_free_cmd_mailbox(dev, mailbox); 198 return err; 199 } 200 201 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 202 { 203 struct mlx4_cmd_mailbox *mailbox; 204 u32 *outbox; 205 u8 in_modifier; 206 u8 field; 207 u16 field16; 208 int err; 209 210 #define QUERY_FUNC_BUS_OFFSET 0x00 211 #define QUERY_FUNC_DEVICE_OFFSET 0x01 212 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 213 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 214 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 215 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 216 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 217 218 mailbox = mlx4_alloc_cmd_mailbox(dev); 219 if (IS_ERR(mailbox)) 220 return PTR_ERR(mailbox); 221 outbox = mailbox->buf; 222 223 in_modifier = slave; 224 225 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 226 MLX4_CMD_QUERY_FUNC, 227 MLX4_CMD_TIME_CLASS_A, 228 MLX4_CMD_NATIVE); 229 if (err) 230 goto out; 231 232 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 233 func->bus = field & 0xf; 234 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 235 func->device = field & 0xf1; 236 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 237 func->function = field & 0x7; 238 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 239 func->physical_function = field & 0xf; 240 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 241 func->rsvd_eqs = field16 & 0xffff; 242 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 243 func->max_eq = field16 & 0xffff; 244 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 245 func->rsvd_uars = field & 0x0f; 246 247 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 248 func->bus, func->device, func->function, func->physical_function, 249 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 250 251 out: 252 mlx4_free_cmd_mailbox(dev, mailbox); 253 return err; 254 } 255 256 static int mlx4_activate_vst_qinq(struct mlx4_priv *priv, int slave, int port) 257 { 258 struct mlx4_vport_oper_state *vp_oper; 259 struct mlx4_vport_state *vp_admin; 260 int err; 261 262 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 263 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 264 265 if (vp_admin->default_vlan != vp_oper->state.default_vlan) { 266 err = __mlx4_register_vlan(&priv->dev, port, 267 vp_admin->default_vlan, 268 &vp_oper->vlan_idx); 269 if (err) { 270 vp_oper->vlan_idx = NO_INDX; 271 mlx4_warn(&priv->dev, 272 "No vlan resources slave %d, port %d\n", 273 slave, port); 274 return err; 275 } 276 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n", 277 (int)(vp_oper->state.default_vlan), 278 vp_oper->vlan_idx, slave, port); 279 } 280 vp_oper->state.vlan_proto = vp_admin->vlan_proto; 281 vp_oper->state.default_vlan = vp_admin->default_vlan; 282 vp_oper->state.default_qos = vp_admin->default_qos; 283 284 return 0; 285 } 286 287 static int mlx4_handle_vst_qinq(struct mlx4_priv *priv, int slave, int port) 288 { 289 struct mlx4_vport_oper_state *vp_oper; 290 struct mlx4_slave_state *slave_state; 291 struct mlx4_vport_state *vp_admin; 292 int err; 293 294 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 295 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 296 slave_state = &priv->mfunc.master.slave_state[slave]; 297 298 if ((vp_admin->vlan_proto != htons(ETH_P_8021AD)) || 299 (!slave_state->active)) 300 return 0; 301 302 if (vp_oper->state.vlan_proto == vp_admin->vlan_proto && 303 vp_oper->state.default_vlan == vp_admin->default_vlan && 304 vp_oper->state.default_qos == vp_admin->default_qos) 305 return 0; 306 307 if (!slave_state->vst_qinq_supported) { 308 /* Warn and revert the request to set vst QinQ mode */ 309 vp_admin->vlan_proto = vp_oper->state.vlan_proto; 310 vp_admin->default_vlan = vp_oper->state.default_vlan; 311 vp_admin->default_qos = vp_oper->state.default_qos; 312 313 mlx4_warn(&priv->dev, 314 "Slave %d does not support VST QinQ mode\n", slave); 315 return 0; 316 } 317 318 err = mlx4_activate_vst_qinq(priv, slave, port); 319 return err; 320 } 321 322 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 323 struct mlx4_vhcr *vhcr, 324 struct mlx4_cmd_mailbox *inbox, 325 struct mlx4_cmd_mailbox *outbox, 326 struct mlx4_cmd_info *cmd) 327 { 328 struct mlx4_priv *priv = mlx4_priv(dev); 329 u8 field, port; 330 u32 size, proxy_qp, qkey; 331 int err = 0; 332 struct mlx4_func func; 333 334 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 335 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 336 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 337 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 338 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 339 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 340 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 341 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 342 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 343 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 344 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 345 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 346 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 347 348 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 349 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 350 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 351 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 352 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 353 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 354 355 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 356 357 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 358 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 359 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 360 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 361 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 362 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 363 364 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 365 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 366 367 /* when opcode modifier = 1 */ 368 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 369 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 370 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 371 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 372 373 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 374 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 375 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 376 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 377 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 378 379 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 380 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 381 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 382 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 383 384 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 385 #define QUERY_FUNC_CAP_PHV_BIT 0x40 386 #define QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE 0x20 387 388 #define QUERY_FUNC_CAP_SUPPORTS_VST_QINQ BIT(30) 389 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS BIT(31) 390 391 if (vhcr->op_modifier == 1) { 392 struct mlx4_active_ports actv_ports = 393 mlx4_get_active_ports(dev, slave); 394 int converted_port = mlx4_slave_convert_port( 395 dev, slave, vhcr->in_modifier); 396 struct mlx4_vport_oper_state *vp_oper; 397 398 if (converted_port < 0) 399 return -EINVAL; 400 401 vhcr->in_modifier = converted_port; 402 /* phys-port = logical-port */ 403 field = vhcr->in_modifier - 404 find_first_bit(actv_ports.ports, dev->caps.num_ports); 405 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 406 407 port = vhcr->in_modifier; 408 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 409 410 /* Set nic_info bit to mark new fields support */ 411 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 412 413 if (mlx4_vf_smi_enabled(dev, slave, port) && 414 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 415 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 416 MLX4_PUT(outbox->buf, qkey, 417 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 418 } 419 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 420 421 /* size is now the QP number */ 422 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 423 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 424 425 size += 2; 426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 427 428 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 429 proxy_qp += 2; 430 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 431 432 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 433 QUERY_FUNC_CAP_PHYS_PORT_ID); 434 435 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 436 err = mlx4_handle_vst_qinq(priv, slave, port); 437 if (err) 438 return err; 439 440 field = 0; 441 if (dev->caps.phv_bit[port]) 442 field |= QUERY_FUNC_CAP_PHV_BIT; 443 if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) 444 field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE; 445 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET); 446 447 } else if (vhcr->op_modifier == 0) { 448 struct mlx4_active_ports actv_ports = 449 mlx4_get_active_ports(dev, slave); 450 struct mlx4_slave_state *slave_state = 451 &priv->mfunc.master.slave_state[slave]; 452 453 /* enable rdma and ethernet interfaces, new quota locations, 454 * and reserved lkey 455 */ 456 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 457 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 458 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 459 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 460 461 field = min( 462 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 463 dev->caps.num_ports); 464 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 465 466 size = dev->caps.function_caps; /* set PF behaviours */ 467 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 468 469 field = 0; /* protected FMR support not available as yet */ 470 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 471 472 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 473 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 474 size = dev->caps.num_qps; 475 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 476 477 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 478 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 479 size = dev->caps.num_srqs; 480 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 481 482 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 483 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 484 size = dev->caps.num_cqs; 485 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 486 487 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 488 mlx4_QUERY_FUNC(dev, &func, slave)) { 489 size = vhcr->in_modifier & 490 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 491 dev->caps.num_eqs : 492 rounddown_pow_of_two(dev->caps.num_eqs); 493 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 494 size = dev->caps.reserved_eqs; 495 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 496 } else { 497 size = vhcr->in_modifier & 498 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 499 func.max_eq : 500 rounddown_pow_of_two(func.max_eq); 501 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 502 size = func.rsvd_eqs; 503 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 504 } 505 506 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 507 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 508 size = dev->caps.num_mpts; 509 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 510 511 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 512 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 513 size = dev->caps.num_mtts; 514 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 515 516 size = dev->caps.num_mgms + dev->caps.num_amgms; 517 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 518 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 519 520 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 521 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 522 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 523 524 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 525 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 526 527 if (vhcr->in_modifier & QUERY_FUNC_CAP_SUPPORTS_VST_QINQ) 528 slave_state->vst_qinq_supported = true; 529 530 } else 531 err = -EINVAL; 532 533 return err; 534 } 535 536 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 537 struct mlx4_func_cap *func_cap) 538 { 539 struct mlx4_cmd_mailbox *mailbox; 540 u32 *outbox; 541 u8 field, op_modifier; 542 u32 size, qkey; 543 int err = 0, quotas = 0; 544 u32 in_modifier; 545 u32 slave_caps; 546 547 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 548 slave_caps = QUERY_FUNC_CAP_SUPPORTS_VST_QINQ | 549 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 550 in_modifier = op_modifier ? gen_or_port : slave_caps; 551 552 mailbox = mlx4_alloc_cmd_mailbox(dev); 553 if (IS_ERR(mailbox)) 554 return PTR_ERR(mailbox); 555 556 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 557 MLX4_CMD_QUERY_FUNC_CAP, 558 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 559 if (err) 560 goto out; 561 562 outbox = mailbox->buf; 563 564 if (!op_modifier) { 565 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 566 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 567 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 568 err = -EPROTONOSUPPORT; 569 goto out; 570 } 571 func_cap->flags = field; 572 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 573 574 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 575 func_cap->num_ports = field; 576 577 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 578 func_cap->pf_context_behaviour = size; 579 580 if (quotas) { 581 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 582 func_cap->qp_quota = size & 0xFFFFFF; 583 584 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 585 func_cap->srq_quota = size & 0xFFFFFF; 586 587 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 588 func_cap->cq_quota = size & 0xFFFFFF; 589 590 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 591 func_cap->mpt_quota = size & 0xFFFFFF; 592 593 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 594 func_cap->mtt_quota = size & 0xFFFFFF; 595 596 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 597 func_cap->mcg_quota = size & 0xFFFFFF; 598 599 } else { 600 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 601 func_cap->qp_quota = size & 0xFFFFFF; 602 603 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 604 func_cap->srq_quota = size & 0xFFFFFF; 605 606 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 607 func_cap->cq_quota = size & 0xFFFFFF; 608 609 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 610 func_cap->mpt_quota = size & 0xFFFFFF; 611 612 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 613 func_cap->mtt_quota = size & 0xFFFFFF; 614 615 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 616 func_cap->mcg_quota = size & 0xFFFFFF; 617 } 618 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 619 func_cap->max_eq = size & 0xFFFFFF; 620 621 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 622 func_cap->reserved_eq = size & 0xFFFFFF; 623 624 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 625 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 626 func_cap->reserved_lkey = size; 627 } else { 628 func_cap->reserved_lkey = 0; 629 } 630 631 func_cap->extra_flags = 0; 632 633 /* Mailbox data from 0x6c and onward should only be treated if 634 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 635 */ 636 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 637 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 638 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 639 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 640 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 641 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 642 } 643 644 goto out; 645 } 646 647 /* logical port query */ 648 if (gen_or_port > dev->caps.num_ports) { 649 err = -EINVAL; 650 goto out; 651 } 652 653 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 654 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 655 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 656 mlx4_err(dev, "VLAN is enforced on this port\n"); 657 err = -EPROTONOSUPPORT; 658 goto out; 659 } 660 661 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 662 mlx4_err(dev, "Force mac is enabled on this port\n"); 663 err = -EPROTONOSUPPORT; 664 goto out; 665 } 666 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 667 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 668 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 669 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 670 err = -EPROTONOSUPPORT; 671 goto out; 672 } 673 } 674 675 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 676 func_cap->physical_port = field; 677 if (func_cap->physical_port != gen_or_port) { 678 err = -EINVAL; 679 goto out; 680 } 681 682 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 683 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 684 func_cap->spec_qps.qp0_qkey = qkey; 685 } else { 686 func_cap->spec_qps.qp0_qkey = 0; 687 } 688 689 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 690 func_cap->spec_qps.qp0_tunnel = size & 0xFFFFFF; 691 692 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 693 func_cap->spec_qps.qp0_proxy = size & 0xFFFFFF; 694 695 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 696 func_cap->spec_qps.qp1_tunnel = size & 0xFFFFFF; 697 698 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 699 func_cap->spec_qps.qp1_proxy = size & 0xFFFFFF; 700 701 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 702 MLX4_GET(func_cap->phys_port_id, outbox, 703 QUERY_FUNC_CAP_PHYS_PORT_ID); 704 705 MLX4_GET(func_cap->flags0, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 706 707 /* All other resources are allocated by the master, but we still report 708 * 'num' and 'reserved' capabilities as follows: 709 * - num remains the maximum resource index 710 * - 'num - reserved' is the total available objects of a resource, but 711 * resource indices may be less than 'reserved' 712 * TODO: set per-resource quotas */ 713 714 out: 715 mlx4_free_cmd_mailbox(dev, mailbox); 716 717 return err; 718 } 719 720 static void disable_unsupported_roce_caps(void *buf); 721 722 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 723 { 724 struct mlx4_cmd_mailbox *mailbox; 725 u32 *outbox; 726 u8 field; 727 u32 field32, flags, ext_flags; 728 u16 size; 729 u16 stat_rate; 730 int err; 731 int i; 732 733 #define QUERY_DEV_CAP_OUT_SIZE 0x100 734 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 735 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 736 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 737 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 738 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 739 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 740 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 741 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 742 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 743 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 744 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 745 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 746 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 747 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 748 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 749 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 750 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 751 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 752 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 753 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 754 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 755 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 756 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 757 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 758 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 759 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 760 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 761 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 762 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 763 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 764 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 765 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 766 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 767 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 768 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 769 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 770 #define QUERY_DEV_CAP_WOL_OFFSET 0x43 771 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 772 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 773 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 774 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 775 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 776 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 777 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 778 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 779 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 780 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 781 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 782 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 783 #define QUERY_DEV_CAP_USER_MAC_EN_OFFSET 0x5C 784 #define QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET 0x5D 785 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 786 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 787 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 788 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 789 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 790 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 791 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 792 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 793 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 794 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 795 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 796 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 797 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 798 #define QUERY_DEV_CAP_SL2VL_EVENT_OFFSET 0x78 799 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 800 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 801 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 802 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 803 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 804 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 805 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 806 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 807 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 808 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 809 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 810 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 811 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 812 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 813 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 814 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 815 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 816 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 817 #define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c 818 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 819 #define QUERY_DEV_CAP_VXLAN 0x9e 820 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 821 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 822 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 823 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 824 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 825 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 826 827 828 dev_cap->flags2 = 0; 829 mailbox = mlx4_alloc_cmd_mailbox(dev); 830 if (IS_ERR(mailbox)) 831 return PTR_ERR(mailbox); 832 outbox = mailbox->buf; 833 834 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 835 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 836 if (err) 837 goto out; 838 839 if (mlx4_is_mfunc(dev)) 840 disable_unsupported_roce_caps(outbox); 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 842 dev_cap->reserved_qps = 1 << (field & 0xf); 843 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 844 dev_cap->max_qps = 1 << (field & 0x1f); 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 846 dev_cap->reserved_srqs = 1 << (field >> 4); 847 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 848 dev_cap->max_srqs = 1 << (field & 0x1f); 849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 850 dev_cap->max_cq_sz = 1 << field; 851 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 852 dev_cap->reserved_cqs = 1 << (field & 0xf); 853 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 854 dev_cap->max_cqs = 1 << (field & 0x1f); 855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 856 dev_cap->max_mpts = 1 << (field & 0x3f); 857 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 858 dev_cap->reserved_eqs = 1 << (field & 0xf); 859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 860 dev_cap->max_eqs = 1 << (field & 0xf); 861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 862 dev_cap->reserved_mtts = 1 << (field >> 4); 863 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 864 dev_cap->reserved_mrws = 1 << (field & 0xf); 865 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 866 dev_cap->num_sys_eqs = size & 0xfff; 867 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 868 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 869 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 870 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 872 field &= 0x1f; 873 if (!field) 874 dev_cap->max_gso_sz = 0; 875 else 876 dev_cap->max_gso_sz = 1 << field; 877 878 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 879 if (field & 0x20) 880 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 881 if (field & 0x10) 882 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 883 field &= 0xf; 884 if (field) { 885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 886 dev_cap->max_rss_tbl_sz = 1 << field; 887 } else 888 dev_cap->max_rss_tbl_sz = 0; 889 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 890 dev_cap->max_rdma_global = 1 << (field & 0x3f); 891 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 892 dev_cap->local_ca_ack_delay = field & 0x1f; 893 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 894 dev_cap->num_ports = field & 0xf; 895 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 896 dev_cap->max_msg_sz = 1 << (field & 0x1f); 897 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 898 if (field & 0x10) 899 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 900 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 901 if (field & 0x80) 902 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 903 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 904 if (field & 0x20) 905 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER; 906 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 907 if (field & 0x80) 908 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 909 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 910 if (field & 0x80) 911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 912 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 913 dev_cap->fs_max_num_qp_per_entry = field; 914 MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET); 915 if (field & (1 << 5)) 916 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT; 917 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 918 if (field & 0x1) 919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 920 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 921 dev_cap->stat_rate_support = stat_rate; 922 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 923 if (field & 0x80) 924 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 925 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 926 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 927 dev_cap->flags = flags | (u64)ext_flags << 32; 928 MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET); 929 dev_cap->wol_port[1] = !!(field & 0x20); 930 dev_cap->wol_port[2] = !!(field & 0x40); 931 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 932 dev_cap->reserved_uars = field >> 4; 933 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 934 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 935 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 936 dev_cap->min_page_sz = 1 << field; 937 938 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 939 if (field & 0x80) { 940 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 941 dev_cap->bf_reg_size = 1 << (field & 0x1f); 942 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 943 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 944 field = 3; 945 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 946 } else { 947 dev_cap->bf_reg_size = 0; 948 } 949 950 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 951 dev_cap->max_sq_sg = field; 952 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 953 dev_cap->max_sq_desc_sz = size; 954 955 MLX4_GET(field, outbox, QUERY_DEV_CAP_USER_MAC_EN_OFFSET); 956 if (field & (1 << 2)) 957 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 958 MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET); 959 if (field & 0x1) 960 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP; 961 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 962 dev_cap->max_qp_per_mcg = 1 << field; 963 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 964 dev_cap->reserved_mgms = field & 0xf; 965 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 966 dev_cap->max_mcgs = 1 << field; 967 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 968 dev_cap->reserved_pds = field >> 4; 969 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 970 dev_cap->max_pds = 1 << (field & 0x3f); 971 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 972 dev_cap->reserved_xrcds = field >> 4; 973 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 974 dev_cap->max_xrcds = 1 << (field & 0x1f); 975 976 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 977 dev_cap->rdmarc_entry_sz = size; 978 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 979 dev_cap->qpc_entry_sz = size; 980 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 981 dev_cap->aux_entry_sz = size; 982 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 983 dev_cap->altc_entry_sz = size; 984 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 985 dev_cap->eqc_entry_sz = size; 986 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 987 dev_cap->cqc_entry_sz = size; 988 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 989 dev_cap->srq_entry_sz = size; 990 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 991 dev_cap->cmpt_entry_sz = size; 992 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 993 dev_cap->mtt_entry_sz = size; 994 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 995 dev_cap->dmpt_entry_sz = size; 996 997 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 998 dev_cap->max_srq_sz = 1 << field; 999 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 1000 dev_cap->max_qp_sz = 1 << field; 1001 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 1002 dev_cap->resize_srq = field & 1; 1003 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 1004 dev_cap->max_rq_sg = field; 1005 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 1006 dev_cap->max_rq_desc_sz = size; 1007 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1008 if (field & (1 << 4)) 1009 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 1010 if (field & (1 << 5)) 1011 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 1012 if (field & (1 << 6)) 1013 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 1014 if (field & (1 << 7)) 1015 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 1016 MLX4_GET(dev_cap->bmme_flags, outbox, 1017 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1018 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2) 1019 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2; 1020 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 1021 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 1022 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1023 if (field & 0x20) 1024 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 1025 if (field & (1 << 2)) 1026 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 1027 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); 1028 if (field & 0x80) 1029 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; 1030 if (field & 0x40) 1031 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; 1032 1033 MLX4_GET(dev_cap->reserved_lkey, outbox, 1034 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 1035 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 1036 if (field32 & (1 << 0)) 1037 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 1038 if (field32 & (1 << 7)) 1039 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 1040 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT); 1041 if (field32 & (1 << 17)) 1042 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT; 1043 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 1044 if (field & 1<<6) 1045 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 1046 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 1047 if (field & 1<<3) 1048 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 1049 if (field & (1 << 5)) 1050 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 1051 MLX4_GET(dev_cap->max_icm_sz, outbox, 1052 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 1053 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1054 MLX4_GET(dev_cap->max_counters, outbox, 1055 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 1056 1057 MLX4_GET(field32, outbox, 1058 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 1059 if (field32 & (1 << 0)) 1060 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 1061 1062 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 1063 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 1064 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 1065 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 1066 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 1067 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 1068 1069 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1070 dev_cap->rl_caps.num_rates = size; 1071 if (dev_cap->rl_caps.num_rates) { 1072 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 1073 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 1074 dev_cap->rl_caps.max_val = size & 0xfff; 1075 dev_cap->rl_caps.max_unit = size >> 14; 1076 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 1077 dev_cap->rl_caps.min_val = size & 0xfff; 1078 dev_cap->rl_caps.min_unit = size >> 14; 1079 } 1080 1081 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1082 if (field32 & (1 << 16)) 1083 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 1084 if (field32 & (1 << 18)) 1085 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; 1086 if (field32 & (1 << 19)) 1087 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; 1088 if (field32 & (1 << 26)) 1089 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 1090 if (field32 & (1 << 20)) 1091 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 1092 if (field32 & (1 << 21)) 1093 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 1094 1095 for (i = 1; i <= dev_cap->num_ports; i++) { 1096 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 1097 if (err) 1098 goto out; 1099 } 1100 1101 /* 1102 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 1103 * we can't use any EQs whose doorbell falls on that page, 1104 * even if the EQ itself isn't reserved. 1105 */ 1106 if (dev_cap->num_sys_eqs == 0) 1107 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 1108 dev_cap->reserved_eqs); 1109 else 1110 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 1111 1112 out: 1113 mlx4_free_cmd_mailbox(dev, mailbox); 1114 return err; 1115 } 1116 1117 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 1118 { 1119 if (dev_cap->bf_reg_size > 0) 1120 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 1121 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 1122 else 1123 mlx4_dbg(dev, "BlueFlame not available\n"); 1124 1125 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 1126 dev_cap->bmme_flags, dev_cap->reserved_lkey); 1127 mlx4_dbg(dev, "Max ICM size %lld MB\n", 1128 (unsigned long long) dev_cap->max_icm_sz >> 20); 1129 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1130 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 1131 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1132 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 1133 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1134 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 1135 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 1136 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 1137 dev_cap->eqc_entry_sz); 1138 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1139 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1140 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1141 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1142 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1143 dev_cap->max_pds, dev_cap->reserved_mgms); 1144 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1145 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1146 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1147 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1148 dev_cap->port_cap[1].max_port_width); 1149 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1150 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1151 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1152 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1153 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1154 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1155 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1156 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1157 dev_cap->dmfs_high_rate_qpn_base); 1158 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1159 dev_cap->dmfs_high_rate_qpn_range); 1160 1161 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1162 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1163 1164 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1165 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1166 rl_caps->min_unit, rl_caps->min_val); 1167 } 1168 1169 dump_dev_cap_flags(dev, dev_cap->flags); 1170 dump_dev_cap_flags2(dev, dev_cap->flags2); 1171 } 1172 1173 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1174 { 1175 struct mlx4_cmd_mailbox *mailbox; 1176 u32 *outbox; 1177 u8 field; 1178 u32 field32; 1179 int err; 1180 1181 mailbox = mlx4_alloc_cmd_mailbox(dev); 1182 if (IS_ERR(mailbox)) 1183 return PTR_ERR(mailbox); 1184 outbox = mailbox->buf; 1185 1186 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1187 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1188 MLX4_CMD_TIME_CLASS_A, 1189 MLX4_CMD_NATIVE); 1190 1191 if (err) 1192 goto out; 1193 1194 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1195 port_cap->max_vl = field >> 4; 1196 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1197 port_cap->ib_mtu = field >> 4; 1198 port_cap->max_port_width = field & 0xf; 1199 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1200 port_cap->max_gids = 1 << (field & 0xf); 1201 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1202 port_cap->max_pkeys = 1 << (field & 0xf); 1203 } else { 1204 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1205 #define QUERY_PORT_MTU_OFFSET 0x01 1206 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1207 #define QUERY_PORT_WIDTH_OFFSET 0x06 1208 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1209 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1210 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1211 #define QUERY_PORT_MAC_OFFSET 0x10 1212 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1213 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1214 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1215 1216 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1217 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1218 if (err) 1219 goto out; 1220 1221 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1222 port_cap->link_state = (field & 0x80) >> 7; 1223 port_cap->supported_port_types = field & 3; 1224 port_cap->suggested_type = (field >> 3) & 1; 1225 port_cap->default_sense = (field >> 4) & 1; 1226 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1227 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1228 port_cap->ib_mtu = field & 0xf; 1229 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1230 port_cap->max_port_width = field & 0xf; 1231 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1232 port_cap->max_gids = 1 << (field >> 4); 1233 port_cap->max_pkeys = 1 << (field & 0xf); 1234 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1235 port_cap->max_vl = field & 0xf; 1236 port_cap->max_tc_eth = field >> 4; 1237 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1238 port_cap->log_max_macs = field & 0xf; 1239 port_cap->log_max_vlans = field >> 4; 1240 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1241 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1242 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1243 port_cap->trans_type = field32 >> 24; 1244 port_cap->vendor_oui = field32 & 0xffffff; 1245 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1246 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1247 } 1248 1249 out: 1250 mlx4_free_cmd_mailbox(dev, mailbox); 1251 return err; 1252 } 1253 1254 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1255 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1256 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1257 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1258 1259 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1260 struct mlx4_vhcr *vhcr, 1261 struct mlx4_cmd_mailbox *inbox, 1262 struct mlx4_cmd_mailbox *outbox, 1263 struct mlx4_cmd_info *cmd) 1264 { 1265 u64 flags; 1266 int err = 0; 1267 u8 field; 1268 u16 field16; 1269 u32 bmme_flags, field32; 1270 int real_port; 1271 int slave_port; 1272 int first_port; 1273 struct mlx4_active_ports actv_ports; 1274 1275 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1276 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1277 if (err) 1278 return err; 1279 1280 disable_unsupported_roce_caps(outbox->buf); 1281 /* add port mng change event capability and disable mw type 1 1282 * unconditionally to slaves 1283 */ 1284 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1285 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1286 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1287 actv_ports = mlx4_get_active_ports(dev, slave); 1288 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1289 for (slave_port = 0, real_port = first_port; 1290 real_port < first_port + 1291 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1292 ++real_port, ++slave_port) { 1293 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1294 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1295 else 1296 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1297 } 1298 for (; slave_port < dev->caps.num_ports; ++slave_port) 1299 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1300 1301 /* Not exposing RSS IP fragments to guests */ 1302 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1303 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1304 1305 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1306 field &= ~0x0F; 1307 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1308 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1309 1310 /* For guests, disable timestamp */ 1311 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1312 field &= 0x7f; 1313 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1314 1315 /* For guests, disable vxlan tunneling and QoS support */ 1316 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1317 field &= 0xd7; 1318 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1319 1320 /* For guests, disable port BEACON */ 1321 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1322 field &= 0x7f; 1323 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1324 1325 /* For guests, report Blueflame disabled */ 1326 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1327 field &= 0x7f; 1328 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1329 1330 /* For guests, disable mw type 2 and port remap*/ 1331 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1332 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1333 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1334 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1335 1336 /* turn off device-managed steering capability if not enabled */ 1337 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1338 MLX4_GET(field, outbox->buf, 1339 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1340 field &= 0x7f; 1341 MLX4_PUT(outbox->buf, field, 1342 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1343 } 1344 1345 /* turn off ipoib managed steering for guests */ 1346 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1347 field &= ~0x80; 1348 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1349 1350 /* turn off host side virt features (VST, FSM, etc) for guests */ 1351 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1352 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1353 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1354 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1355 1356 /* turn off QCN for guests */ 1357 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1358 field &= 0xfe; 1359 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1360 1361 /* turn off QP max-rate limiting for guests */ 1362 field16 = 0; 1363 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1364 1365 /* turn off QoS per VF support for guests */ 1366 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1367 field &= 0xef; 1368 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1369 1370 /* turn off ignore FCS feature for guests */ 1371 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1372 field &= 0xfb; 1373 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1374 1375 return 0; 1376 } 1377 1378 static void disable_unsupported_roce_caps(void *buf) 1379 { 1380 u32 flags; 1381 1382 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1383 flags &= ~(1UL << 31); 1384 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1385 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1386 flags &= ~(1UL << 24); 1387 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1388 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1389 flags &= ~(MLX4_FLAG_ROCE_V1_V2); 1390 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1391 } 1392 1393 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1394 struct mlx4_vhcr *vhcr, 1395 struct mlx4_cmd_mailbox *inbox, 1396 struct mlx4_cmd_mailbox *outbox, 1397 struct mlx4_cmd_info *cmd) 1398 { 1399 struct mlx4_priv *priv = mlx4_priv(dev); 1400 u64 def_mac; 1401 u8 port_type; 1402 u16 short_field; 1403 int err; 1404 int admin_link_state; 1405 int port = mlx4_slave_convert_port(dev, slave, 1406 vhcr->in_modifier & 0xFF); 1407 1408 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1409 #define MLX4_PORT_LINK_UP_MASK 0x80 1410 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1411 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1412 1413 if (port < 0) 1414 return -EINVAL; 1415 1416 /* Protect against untrusted guests: enforce that this is the 1417 * QUERY_PORT general query. 1418 */ 1419 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1420 return -EINVAL; 1421 1422 vhcr->in_modifier = port; 1423 1424 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1425 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1426 MLX4_CMD_NATIVE); 1427 1428 if (!err && dev->caps.function != slave) { 1429 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1430 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1431 1432 /* get port type - currently only eth is enabled */ 1433 MLX4_GET(port_type, outbox->buf, 1434 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1435 1436 /* No link sensing allowed */ 1437 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1438 /* set port type to currently operating port type */ 1439 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1440 1441 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1442 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1443 port_type |= MLX4_PORT_LINK_UP_MASK; 1444 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1445 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1446 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) { 1447 int other_port = (port == 1) ? 2 : 1; 1448 struct mlx4_port_cap port_cap; 1449 1450 err = mlx4_QUERY_PORT(dev, other_port, &port_cap); 1451 if (err) 1452 goto out; 1453 port_type |= (port_cap.link_state << 7); 1454 } 1455 1456 MLX4_PUT(outbox->buf, port_type, 1457 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1458 1459 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1460 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1461 else 1462 short_field = 1; /* slave max gids */ 1463 MLX4_PUT(outbox->buf, short_field, 1464 QUERY_PORT_CUR_MAX_GID_OFFSET); 1465 1466 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1467 MLX4_PUT(outbox->buf, short_field, 1468 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1469 } 1470 out: 1471 return err; 1472 } 1473 1474 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1475 int *gid_tbl_len, int *pkey_tbl_len) 1476 { 1477 struct mlx4_cmd_mailbox *mailbox; 1478 u32 *outbox; 1479 u16 field; 1480 int err; 1481 1482 mailbox = mlx4_alloc_cmd_mailbox(dev); 1483 if (IS_ERR(mailbox)) 1484 return PTR_ERR(mailbox); 1485 1486 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1487 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1488 MLX4_CMD_WRAPPED); 1489 if (err) 1490 goto out; 1491 1492 outbox = mailbox->buf; 1493 1494 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1495 *gid_tbl_len = field; 1496 1497 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1498 *pkey_tbl_len = field; 1499 1500 out: 1501 mlx4_free_cmd_mailbox(dev, mailbox); 1502 return err; 1503 } 1504 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1505 1506 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1507 { 1508 struct mlx4_cmd_mailbox *mailbox; 1509 struct mlx4_icm_iter iter; 1510 __be64 *pages; 1511 int lg; 1512 int nent = 0; 1513 int i; 1514 int err = 0; 1515 int ts = 0, tc = 0; 1516 1517 mailbox = mlx4_alloc_cmd_mailbox(dev); 1518 if (IS_ERR(mailbox)) 1519 return PTR_ERR(mailbox); 1520 pages = mailbox->buf; 1521 1522 for (mlx4_icm_first(icm, &iter); 1523 !mlx4_icm_last(&iter); 1524 mlx4_icm_next(&iter)) { 1525 /* 1526 * We have to pass pages that are aligned to their 1527 * size, so find the least significant 1 in the 1528 * address or size and use that as our log2 size. 1529 */ 1530 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1531 if (lg < MLX4_ICM_PAGE_SHIFT) { 1532 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1533 MLX4_ICM_PAGE_SIZE, 1534 (unsigned long long) mlx4_icm_addr(&iter), 1535 mlx4_icm_size(&iter)); 1536 err = -EINVAL; 1537 goto out; 1538 } 1539 1540 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1541 if (virt != -1) { 1542 pages[nent * 2] = cpu_to_be64(virt); 1543 virt += 1ULL << lg; 1544 } 1545 1546 pages[nent * 2 + 1] = 1547 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1548 (lg - MLX4_ICM_PAGE_SHIFT)); 1549 ts += 1 << (lg - 10); 1550 ++tc; 1551 1552 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1553 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1554 MLX4_CMD_TIME_CLASS_B, 1555 MLX4_CMD_NATIVE); 1556 if (err) 1557 goto out; 1558 nent = 0; 1559 } 1560 } 1561 } 1562 1563 if (nent) 1564 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1565 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1566 if (err) 1567 goto out; 1568 1569 switch (op) { 1570 case MLX4_CMD_MAP_FA: 1571 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1572 break; 1573 case MLX4_CMD_MAP_ICM_AUX: 1574 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1575 break; 1576 case MLX4_CMD_MAP_ICM: 1577 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1578 tc, ts, (unsigned long long) virt - (ts << 10)); 1579 break; 1580 } 1581 1582 out: 1583 mlx4_free_cmd_mailbox(dev, mailbox); 1584 return err; 1585 } 1586 1587 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1588 { 1589 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1590 } 1591 1592 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1593 { 1594 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1595 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1596 } 1597 1598 1599 int mlx4_RUN_FW(struct mlx4_dev *dev) 1600 { 1601 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1602 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1603 } 1604 1605 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1606 { 1607 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1608 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1609 struct mlx4_cmd_mailbox *mailbox; 1610 u32 *outbox; 1611 int err = 0; 1612 u64 fw_ver; 1613 u16 cmd_if_rev; 1614 u8 lg; 1615 1616 #define QUERY_FW_OUT_SIZE 0x100 1617 #define QUERY_FW_VER_OFFSET 0x00 1618 #define QUERY_FW_PPF_ID 0x09 1619 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1620 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1621 #define QUERY_FW_ERR_START_OFFSET 0x30 1622 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1623 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1624 1625 #define QUERY_FW_SIZE_OFFSET 0x00 1626 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1627 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1628 1629 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1630 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1631 1632 #define QUERY_FW_CLOCK_OFFSET 0x50 1633 #define QUERY_FW_CLOCK_BAR 0x58 1634 1635 mailbox = mlx4_alloc_cmd_mailbox(dev); 1636 if (IS_ERR(mailbox)) 1637 return PTR_ERR(mailbox); 1638 outbox = mailbox->buf; 1639 1640 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1641 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1642 if (err) 1643 goto out; 1644 1645 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1646 /* 1647 * FW subminor version is at more significant bits than minor 1648 * version, so swap here. 1649 */ 1650 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1651 ((fw_ver & 0xffff0000ull) >> 16) | 1652 ((fw_ver & 0x0000ffffull) << 16); 1653 1654 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1655 dev->caps.function = lg; 1656 1657 if (mlx4_is_slave(dev)) 1658 goto out; 1659 1660 1661 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1662 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1663 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1664 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1665 cmd_if_rev); 1666 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1667 (int) (dev->caps.fw_ver >> 32), 1668 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1669 (int) dev->caps.fw_ver & 0xffff); 1670 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1671 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1672 err = -ENODEV; 1673 goto out; 1674 } 1675 1676 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1677 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1678 1679 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1680 cmd->max_cmds = 1 << lg; 1681 1682 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1683 (int) (dev->caps.fw_ver >> 32), 1684 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1685 (int) dev->caps.fw_ver & 0xffff, 1686 cmd_if_rev, cmd->max_cmds); 1687 1688 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1689 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1690 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1691 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1692 1693 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1694 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1695 1696 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1697 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1698 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1699 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1700 1701 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1702 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1703 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1704 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1705 fw->comm_bar, fw->comm_base); 1706 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1707 1708 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1709 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1710 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1711 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1712 fw->clock_bar, fw->clock_offset); 1713 1714 /* 1715 * Round up number of system pages needed in case 1716 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1717 */ 1718 fw->fw_pages = 1719 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1720 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1721 1722 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1723 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1724 1725 out: 1726 mlx4_free_cmd_mailbox(dev, mailbox); 1727 return err; 1728 } 1729 1730 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1731 struct mlx4_vhcr *vhcr, 1732 struct mlx4_cmd_mailbox *inbox, 1733 struct mlx4_cmd_mailbox *outbox, 1734 struct mlx4_cmd_info *cmd) 1735 { 1736 u8 *outbuf; 1737 int err; 1738 1739 outbuf = outbox->buf; 1740 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1741 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1742 if (err) 1743 return err; 1744 1745 /* for slaves, set pci PPF ID to invalid and zero out everything 1746 * else except FW version */ 1747 outbuf[0] = outbuf[1] = 0; 1748 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1749 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1750 1751 return 0; 1752 } 1753 1754 static void get_board_id(void *vsd, char *board_id) 1755 { 1756 int i; 1757 1758 #define VSD_OFFSET_SIG1 0x00 1759 #define VSD_OFFSET_SIG2 0xde 1760 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1761 #define VSD_OFFSET_TS_BOARD_ID 0x20 1762 1763 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1764 1765 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1766 1767 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1768 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1769 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1770 } else { 1771 /* 1772 * The board ID is a string but the firmware byte 1773 * swaps each 4-byte word before passing it back to 1774 * us. Therefore we need to swab it before printing. 1775 */ 1776 u32 *bid_u32 = (u32 *)board_id; 1777 1778 for (i = 0; i < 4; ++i) { 1779 u32 *addr; 1780 u32 val; 1781 1782 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1783 val = get_unaligned(addr); 1784 val = swab32(val); 1785 put_unaligned(val, &bid_u32[i]); 1786 } 1787 } 1788 } 1789 1790 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1791 { 1792 struct mlx4_cmd_mailbox *mailbox; 1793 u32 *outbox; 1794 int err; 1795 1796 #define QUERY_ADAPTER_OUT_SIZE 0x100 1797 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1798 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1799 1800 mailbox = mlx4_alloc_cmd_mailbox(dev); 1801 if (IS_ERR(mailbox)) 1802 return PTR_ERR(mailbox); 1803 outbox = mailbox->buf; 1804 1805 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1806 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1807 if (err) 1808 goto out; 1809 1810 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1811 1812 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1813 adapter->board_id); 1814 1815 out: 1816 mlx4_free_cmd_mailbox(dev, mailbox); 1817 return err; 1818 } 1819 1820 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1821 { 1822 struct mlx4_cmd_mailbox *mailbox; 1823 __be32 *inbox; 1824 int err; 1825 static const u8 a0_dmfs_hw_steering[] = { 1826 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1827 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1828 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1829 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1830 }; 1831 1832 #define INIT_HCA_IN_SIZE 0x200 1833 #define INIT_HCA_VERSION_OFFSET 0x000 1834 #define INIT_HCA_VERSION 2 1835 #define INIT_HCA_VXLAN_OFFSET 0x0c 1836 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1837 #define INIT_HCA_FLAGS_OFFSET 0x014 1838 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1839 #define INIT_HCA_QPC_OFFSET 0x020 1840 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1841 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1842 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1843 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1844 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1845 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1846 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1847 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1848 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1849 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1850 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1851 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1852 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1853 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1854 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1855 #define INIT_HCA_MCAST_OFFSET 0x0c0 1856 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1857 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1858 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1859 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1860 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1861 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1862 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1863 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1864 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1865 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1866 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1867 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1868 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1869 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1870 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1871 #define INIT_HCA_TPT_OFFSET 0x0f0 1872 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1873 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1874 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1875 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1876 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1877 #define INIT_HCA_UAR_OFFSET 0x120 1878 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1879 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1880 1881 mailbox = mlx4_alloc_cmd_mailbox(dev); 1882 if (IS_ERR(mailbox)) 1883 return PTR_ERR(mailbox); 1884 inbox = mailbox->buf; 1885 1886 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1887 1888 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1889 ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4); 1890 1891 #if defined(__LITTLE_ENDIAN) 1892 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1893 #elif defined(__BIG_ENDIAN) 1894 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1895 #else 1896 #error Host endianness not defined 1897 #endif 1898 /* Check port for UD address vector: */ 1899 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1900 1901 /* Enable IPoIB checksumming if we can: */ 1902 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1903 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1904 1905 /* Enable QoS support if module parameter set */ 1906 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1907 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1908 1909 /* enable counters */ 1910 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1911 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1912 1913 /* Enable RSS spread to fragmented IP packets when supported */ 1914 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1915 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1916 1917 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1918 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1919 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1920 dev->caps.eqe_size = 64; 1921 dev->caps.eqe_factor = 1; 1922 } else { 1923 dev->caps.eqe_size = 32; 1924 dev->caps.eqe_factor = 0; 1925 } 1926 1927 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1928 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1929 dev->caps.cqe_size = 64; 1930 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1931 } else { 1932 dev->caps.cqe_size = 32; 1933 } 1934 1935 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1936 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1937 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1938 dev->caps.eqe_size = cache_line_size(); 1939 dev->caps.cqe_size = cache_line_size(); 1940 dev->caps.eqe_factor = 0; 1941 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1942 (ilog2(dev->caps.eqe_size) - 5)), 1943 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1944 1945 /* User still need to know to support CQE > 32B */ 1946 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1947 } 1948 1949 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1950 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1951 1952 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1953 1954 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1955 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1956 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1957 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1958 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1959 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1960 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1961 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1962 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1963 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1964 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1965 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1966 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1967 1968 /* steering attributes */ 1969 if (dev->caps.steering_mode == 1970 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1971 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1972 cpu_to_be32(1 << 1973 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1974 1975 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1976 MLX4_PUT(inbox, param->log_mc_entry_sz, 1977 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1978 MLX4_PUT(inbox, param->log_mc_table_sz, 1979 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1980 /* Enable Ethernet flow steering 1981 * with udp unicast and tcp unicast 1982 */ 1983 if (dev->caps.dmfs_high_steer_mode != 1984 MLX4_STEERING_DMFS_A0_STATIC) 1985 MLX4_PUT(inbox, 1986 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1987 INIT_HCA_FS_ETH_BITS_OFFSET); 1988 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1989 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1990 /* Enable IPoIB flow steering 1991 * with udp unicast and tcp unicast 1992 */ 1993 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1994 INIT_HCA_FS_IB_BITS_OFFSET); 1995 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1996 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1997 1998 if (dev->caps.dmfs_high_steer_mode != 1999 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2000 MLX4_PUT(inbox, 2001 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 2002 << 6)), 2003 INIT_HCA_FS_A0_OFFSET); 2004 } else { 2005 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 2006 MLX4_PUT(inbox, param->log_mc_entry_sz, 2007 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 2008 MLX4_PUT(inbox, param->log_mc_hash_sz, 2009 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 2010 MLX4_PUT(inbox, param->log_mc_table_sz, 2011 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 2012 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 2013 MLX4_PUT(inbox, (u8) (1 << 3), 2014 INIT_HCA_UC_STEERING_OFFSET); 2015 } 2016 2017 /* TPT attributes */ 2018 2019 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 2020 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 2021 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 2022 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 2023 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 2024 2025 /* UAR attributes */ 2026 2027 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2028 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 2029 2030 /* set parser VXLAN attributes */ 2031 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 2032 u8 parser_params = 0; 2033 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 2034 } 2035 2036 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 2037 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2038 2039 if (err) 2040 mlx4_err(dev, "INIT_HCA returns %d\n", err); 2041 2042 mlx4_free_cmd_mailbox(dev, mailbox); 2043 return err; 2044 } 2045 2046 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 2047 struct mlx4_init_hca_param *param) 2048 { 2049 struct mlx4_cmd_mailbox *mailbox; 2050 __be32 *outbox; 2051 u32 dword_field; 2052 int err; 2053 u8 byte_field; 2054 static const u8 a0_dmfs_query_hw_steering[] = { 2055 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 2056 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 2057 [2] = MLX4_STEERING_DMFS_A0_STATIC, 2058 [3] = MLX4_STEERING_DMFS_A0_DISABLE 2059 }; 2060 2061 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 2062 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 2063 2064 mailbox = mlx4_alloc_cmd_mailbox(dev); 2065 if (IS_ERR(mailbox)) 2066 return PTR_ERR(mailbox); 2067 outbox = mailbox->buf; 2068 2069 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2070 MLX4_CMD_QUERY_HCA, 2071 MLX4_CMD_TIME_CLASS_B, 2072 !mlx4_is_slave(dev)); 2073 if (err) 2074 goto out; 2075 2076 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 2077 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2078 2079 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 2080 2081 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 2082 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 2083 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 2084 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 2085 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 2086 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 2087 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 2088 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 2089 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 2090 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 2091 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 2092 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 2093 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 2094 2095 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 2096 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 2097 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2098 } else { 2099 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 2100 if (byte_field & 0x8) 2101 param->steering_mode = MLX4_STEERING_MODE_B0; 2102 else 2103 param->steering_mode = MLX4_STEERING_MODE_A0; 2104 } 2105 2106 if (dword_field & (1 << 13)) 2107 param->rss_ip_frags = 1; 2108 2109 /* steering attributes */ 2110 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 2111 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 2112 MLX4_GET(param->log_mc_entry_sz, outbox, 2113 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 2114 MLX4_GET(param->log_mc_table_sz, outbox, 2115 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 2116 MLX4_GET(byte_field, outbox, 2117 INIT_HCA_FS_A0_OFFSET); 2118 param->dmfs_high_steer_mode = 2119 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 2120 } else { 2121 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 2122 MLX4_GET(param->log_mc_entry_sz, outbox, 2123 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 2124 MLX4_GET(param->log_mc_hash_sz, outbox, 2125 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 2126 MLX4_GET(param->log_mc_table_sz, outbox, 2127 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 2128 } 2129 2130 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 2131 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 2132 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 2133 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 2134 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 2135 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 2136 2137 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 2138 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 2139 if (byte_field) { 2140 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 2141 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 2142 param->cqe_size = 1 << ((byte_field & 2143 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 2144 param->eqe_size = 1 << (((byte_field & 2145 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 2146 } 2147 2148 /* TPT attributes */ 2149 2150 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 2151 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 2152 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 2153 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 2154 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 2155 2156 /* UAR attributes */ 2157 2158 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2159 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 2160 2161 /* phv_check enable */ 2162 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); 2163 if (byte_field & 0x2) 2164 param->phv_check_en = 1; 2165 out: 2166 mlx4_free_cmd_mailbox(dev, mailbox); 2167 2168 return err; 2169 } 2170 2171 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2172 { 2173 struct mlx4_cmd_mailbox *mailbox; 2174 __be32 *outbox; 2175 int err; 2176 2177 mailbox = mlx4_alloc_cmd_mailbox(dev); 2178 if (IS_ERR(mailbox)) { 2179 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2180 return PTR_ERR(mailbox); 2181 } 2182 outbox = mailbox->buf; 2183 2184 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2185 MLX4_CMD_QUERY_HCA, 2186 MLX4_CMD_TIME_CLASS_B, 2187 !mlx4_is_slave(dev)); 2188 if (err) { 2189 mlx4_warn(dev, "hca_core_clock update failed\n"); 2190 goto out; 2191 } 2192 2193 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2194 2195 out: 2196 mlx4_free_cmd_mailbox(dev, mailbox); 2197 2198 return err; 2199 } 2200 2201 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2202 * and real QP0 are active, so that the paravirtualized QP0 is ready 2203 * to operate */ 2204 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2205 { 2206 struct mlx4_priv *priv = mlx4_priv(dev); 2207 /* irrelevant if not infiniband */ 2208 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2209 priv->mfunc.master.qp0_state[port].qp0_active) 2210 return 1; 2211 return 0; 2212 } 2213 2214 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2215 struct mlx4_vhcr *vhcr, 2216 struct mlx4_cmd_mailbox *inbox, 2217 struct mlx4_cmd_mailbox *outbox, 2218 struct mlx4_cmd_info *cmd) 2219 { 2220 struct mlx4_priv *priv = mlx4_priv(dev); 2221 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2222 int err; 2223 2224 if (port < 0) 2225 return -EINVAL; 2226 2227 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2228 return 0; 2229 2230 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2231 /* Enable port only if it was previously disabled */ 2232 if (!priv->mfunc.master.init_port_ref[port]) { 2233 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2234 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2235 if (err) 2236 return err; 2237 } 2238 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2239 } else { 2240 if (slave == mlx4_master_func_num(dev)) { 2241 if (check_qp0_state(dev, slave, port) && 2242 !priv->mfunc.master.qp0_state[port].port_active) { 2243 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2244 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2245 if (err) 2246 return err; 2247 priv->mfunc.master.qp0_state[port].port_active = 1; 2248 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2249 } 2250 } else 2251 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2252 } 2253 ++priv->mfunc.master.init_port_ref[port]; 2254 return 0; 2255 } 2256 2257 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2258 { 2259 struct mlx4_cmd_mailbox *mailbox; 2260 u32 *inbox; 2261 int err; 2262 u32 flags; 2263 u16 field; 2264 2265 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2266 #define INIT_PORT_IN_SIZE 256 2267 #define INIT_PORT_FLAGS_OFFSET 0x00 2268 #define INIT_PORT_FLAG_SIG (1 << 18) 2269 #define INIT_PORT_FLAG_NG (1 << 17) 2270 #define INIT_PORT_FLAG_G0 (1 << 16) 2271 #define INIT_PORT_VL_SHIFT 4 2272 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2273 #define INIT_PORT_MTU_OFFSET 0x04 2274 #define INIT_PORT_MAX_GID_OFFSET 0x06 2275 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2276 #define INIT_PORT_GUID0_OFFSET 0x10 2277 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2278 #define INIT_PORT_SI_GUID_OFFSET 0x20 2279 2280 mailbox = mlx4_alloc_cmd_mailbox(dev); 2281 if (IS_ERR(mailbox)) 2282 return PTR_ERR(mailbox); 2283 inbox = mailbox->buf; 2284 2285 flags = 0; 2286 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2287 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2288 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2289 2290 field = 128 << dev->caps.ib_mtu_cap[port]; 2291 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2292 field = dev->caps.gid_table_len[port]; 2293 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2294 field = dev->caps.pkey_table_len[port]; 2295 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2296 2297 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2298 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2299 2300 mlx4_free_cmd_mailbox(dev, mailbox); 2301 } else 2302 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2303 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2304 2305 if (!err) 2306 mlx4_hca_core_clock_update(dev); 2307 2308 return err; 2309 } 2310 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2311 2312 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2313 struct mlx4_vhcr *vhcr, 2314 struct mlx4_cmd_mailbox *inbox, 2315 struct mlx4_cmd_mailbox *outbox, 2316 struct mlx4_cmd_info *cmd) 2317 { 2318 struct mlx4_priv *priv = mlx4_priv(dev); 2319 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2320 int err; 2321 2322 if (port < 0) 2323 return -EINVAL; 2324 2325 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2326 (1 << port))) 2327 return 0; 2328 2329 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2330 if (priv->mfunc.master.init_port_ref[port] == 1) { 2331 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2332 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2333 if (err) 2334 return err; 2335 } 2336 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2337 } else { 2338 /* infiniband port */ 2339 if (slave == mlx4_master_func_num(dev)) { 2340 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2341 priv->mfunc.master.qp0_state[port].port_active) { 2342 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2343 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2344 if (err) 2345 return err; 2346 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2347 priv->mfunc.master.qp0_state[port].port_active = 0; 2348 } 2349 } else 2350 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2351 } 2352 --priv->mfunc.master.init_port_ref[port]; 2353 return 0; 2354 } 2355 2356 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2357 { 2358 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2359 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2360 } 2361 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2362 2363 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2364 { 2365 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2366 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2367 } 2368 2369 struct mlx4_config_dev { 2370 __be32 update_flags; 2371 __be32 rsvd1[3]; 2372 __be16 vxlan_udp_dport; 2373 __be16 rsvd2; 2374 __be16 roce_v2_entropy; 2375 __be16 roce_v2_udp_dport; 2376 __be32 roce_flags; 2377 __be32 rsvd4[25]; 2378 __be16 rsvd5; 2379 u8 rsvd6; 2380 u8 rx_checksum_val; 2381 }; 2382 2383 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2384 #define MLX4_ROCE_V2_UDP_DPORT BIT(3) 2385 #define MLX4_DISABLE_RX_PORT BIT(18) 2386 2387 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2388 { 2389 int err; 2390 struct mlx4_cmd_mailbox *mailbox; 2391 2392 mailbox = mlx4_alloc_cmd_mailbox(dev); 2393 if (IS_ERR(mailbox)) 2394 return PTR_ERR(mailbox); 2395 2396 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2397 2398 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2399 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2400 2401 mlx4_free_cmd_mailbox(dev, mailbox); 2402 return err; 2403 } 2404 2405 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2406 { 2407 int err; 2408 struct mlx4_cmd_mailbox *mailbox; 2409 2410 mailbox = mlx4_alloc_cmd_mailbox(dev); 2411 if (IS_ERR(mailbox)) 2412 return PTR_ERR(mailbox); 2413 2414 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2415 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2416 2417 if (!err) 2418 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2419 2420 mlx4_free_cmd_mailbox(dev, mailbox); 2421 return err; 2422 } 2423 2424 /* Conversion between the HW values and the actual functionality. 2425 * The value represented by the array index, 2426 * and the functionality determined by the flags. 2427 */ 2428 static const u8 config_dev_csum_flags[] = { 2429 [0] = 0, 2430 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2431 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2432 MLX4_RX_CSUM_MODE_L4, 2433 [3] = MLX4_RX_CSUM_MODE_L4 | 2434 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2435 MLX4_RX_CSUM_MODE_MULTI_VLAN 2436 }; 2437 2438 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2439 struct mlx4_config_dev_params *params) 2440 { 2441 struct mlx4_config_dev config_dev = {0}; 2442 int err; 2443 u8 csum_mask; 2444 2445 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2446 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2447 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2448 2449 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2450 return -EOPNOTSUPP; 2451 2452 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2453 if (err) 2454 return err; 2455 2456 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2457 CONFIG_DEV_RX_CSUM_MODE_MASK; 2458 2459 if (csum_mask >= ARRAY_SIZE(config_dev_csum_flags)) 2460 return -EINVAL; 2461 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2462 2463 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2464 CONFIG_DEV_RX_CSUM_MODE_MASK; 2465 2466 if (csum_mask >= ARRAY_SIZE(config_dev_csum_flags)) 2467 return -EINVAL; 2468 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2469 2470 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2471 2472 return 0; 2473 } 2474 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2475 2476 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2477 { 2478 struct mlx4_config_dev config_dev; 2479 2480 memset(&config_dev, 0, sizeof(config_dev)); 2481 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2482 config_dev.vxlan_udp_dport = udp_port; 2483 2484 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2485 } 2486 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2487 2488 #define CONFIG_DISABLE_RX_PORT BIT(15) 2489 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2490 { 2491 struct mlx4_config_dev config_dev; 2492 2493 memset(&config_dev, 0, sizeof(config_dev)); 2494 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2495 if (dis) 2496 config_dev.roce_flags = 2497 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2498 2499 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2500 } 2501 2502 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port) 2503 { 2504 struct mlx4_config_dev config_dev; 2505 2506 memset(&config_dev, 0, sizeof(config_dev)); 2507 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); 2508 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port); 2509 2510 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2511 } 2512 EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port); 2513 2514 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2515 { 2516 struct mlx4_cmd_mailbox *mailbox; 2517 struct { 2518 __be32 v_port1; 2519 __be32 v_port2; 2520 } *v2p; 2521 int err; 2522 2523 mailbox = mlx4_alloc_cmd_mailbox(dev); 2524 if (IS_ERR(mailbox)) 2525 return -ENOMEM; 2526 2527 v2p = mailbox->buf; 2528 v2p->v_port1 = cpu_to_be32(port1); 2529 v2p->v_port2 = cpu_to_be32(port2); 2530 2531 err = mlx4_cmd(dev, mailbox->dma, 0, 2532 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2533 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2534 2535 mlx4_free_cmd_mailbox(dev, mailbox); 2536 return err; 2537 } 2538 2539 2540 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2541 { 2542 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2543 MLX4_CMD_SET_ICM_SIZE, 2544 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2545 if (ret) 2546 return ret; 2547 2548 /* 2549 * Round up number of system pages needed in case 2550 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2551 */ 2552 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2553 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2554 2555 return 0; 2556 } 2557 2558 int mlx4_NOP(struct mlx4_dev *dev) 2559 { 2560 /* Input modifier of 0x1f means "finish as soon as possible." */ 2561 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2562 MLX4_CMD_NATIVE); 2563 } 2564 2565 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 2566 const u32 offset[], 2567 u32 value[], size_t array_len, u8 port) 2568 { 2569 struct mlx4_cmd_mailbox *mailbox; 2570 u32 *outbox; 2571 size_t i; 2572 int ret; 2573 2574 mailbox = mlx4_alloc_cmd_mailbox(dev); 2575 if (IS_ERR(mailbox)) 2576 return PTR_ERR(mailbox); 2577 2578 outbox = mailbox->buf; 2579 2580 ret = mlx4_cmd_box(dev, 0, mailbox->dma, port, op_modifier, 2581 MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A, 2582 MLX4_CMD_NATIVE); 2583 if (ret) 2584 goto out; 2585 2586 for (i = 0; i < array_len; i++) { 2587 if (offset[i] > MLX4_MAILBOX_SIZE) { 2588 ret = -EINVAL; 2589 goto out; 2590 } 2591 2592 MLX4_GET(value[i], outbox, offset[i]); 2593 } 2594 2595 out: 2596 mlx4_free_cmd_mailbox(dev, mailbox); 2597 return ret; 2598 } 2599 EXPORT_SYMBOL(mlx4_query_diag_counters); 2600 2601 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2602 { 2603 u8 port; 2604 u32 *outbox; 2605 struct mlx4_cmd_mailbox *mailbox; 2606 u32 in_mod; 2607 u32 guid_hi, guid_lo; 2608 int err, ret = 0; 2609 #define MOD_STAT_CFG_PORT_OFFSET 8 2610 #define MOD_STAT_CFG_GUID_H 0X14 2611 #define MOD_STAT_CFG_GUID_L 0X1c 2612 2613 mailbox = mlx4_alloc_cmd_mailbox(dev); 2614 if (IS_ERR(mailbox)) 2615 return PTR_ERR(mailbox); 2616 outbox = mailbox->buf; 2617 2618 for (port = 1; port <= dev->caps.num_ports; port++) { 2619 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2620 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2621 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2622 MLX4_CMD_NATIVE); 2623 if (err) { 2624 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2625 port); 2626 ret = err; 2627 } else { 2628 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2629 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2630 dev->caps.phys_port_id[port] = (u64)guid_lo | 2631 (u64)guid_hi << 32; 2632 } 2633 } 2634 mlx4_free_cmd_mailbox(dev, mailbox); 2635 return ret; 2636 } 2637 2638 #define MLX4_WOL_SETUP_MODE (5 << 28) 2639 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2640 { 2641 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2642 2643 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2644 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2645 MLX4_CMD_NATIVE); 2646 } 2647 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2648 2649 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2650 { 2651 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2652 2653 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2654 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2655 } 2656 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2657 2658 enum { 2659 ADD_TO_MCG = 0x26, 2660 }; 2661 2662 2663 void mlx4_opreq_action(struct work_struct *work) 2664 { 2665 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2666 opreq_task); 2667 struct mlx4_dev *dev = &priv->dev; 2668 int num_tasks = atomic_read(&priv->opreq_count); 2669 struct mlx4_cmd_mailbox *mailbox; 2670 struct mlx4_mgm *mgm; 2671 u32 *outbox; 2672 u32 modifier; 2673 u16 token; 2674 u16 type; 2675 int err; 2676 u32 num_qps; 2677 struct mlx4_qp qp; 2678 int i; 2679 u8 rem_mcg; 2680 u8 prot; 2681 2682 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2683 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2684 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2685 #define GET_OP_REQ_DATA_OFFSET 0x20 2686 2687 mailbox = mlx4_alloc_cmd_mailbox(dev); 2688 if (IS_ERR(mailbox)) { 2689 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2690 return; 2691 } 2692 outbox = mailbox->buf; 2693 2694 while (num_tasks) { 2695 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2696 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2697 MLX4_CMD_NATIVE); 2698 if (err) { 2699 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2700 err); 2701 return; 2702 } 2703 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2704 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2705 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2706 type &= 0xfff; 2707 2708 switch (type) { 2709 case ADD_TO_MCG: 2710 if (dev->caps.steering_mode == 2711 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2712 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2713 err = EPERM; 2714 break; 2715 } 2716 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2717 GET_OP_REQ_DATA_OFFSET); 2718 num_qps = be32_to_cpu(mgm->members_count) & 2719 MGM_QPN_MASK; 2720 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2721 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2722 2723 for (i = 0; i < num_qps; i++) { 2724 qp.qpn = be32_to_cpu(mgm->qp[i]); 2725 if (rem_mcg) 2726 err = mlx4_multicast_detach(dev, &qp, 2727 mgm->gid, 2728 prot, 0); 2729 else 2730 err = mlx4_multicast_attach(dev, &qp, 2731 mgm->gid, 2732 mgm->gid[5] 2733 , 0, prot, 2734 NULL); 2735 if (err) 2736 break; 2737 } 2738 break; 2739 default: 2740 mlx4_warn(dev, "Bad type for required operation\n"); 2741 err = EINVAL; 2742 break; 2743 } 2744 err = mlx4_cmd(dev, 0, ((u32) err | 2745 (__force u32)cpu_to_be32(token) << 16), 2746 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2747 MLX4_CMD_NATIVE); 2748 if (err) { 2749 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2750 err); 2751 goto out; 2752 } 2753 memset(outbox, 0, 0xffc); 2754 num_tasks = atomic_dec_return(&priv->opreq_count); 2755 } 2756 2757 out: 2758 mlx4_free_cmd_mailbox(dev, mailbox); 2759 } 2760 2761 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2762 struct mlx4_cmd_mailbox *mailbox) 2763 { 2764 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2765 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2766 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2767 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2768 2769 u32 set_attr_mask, getresp_attr_mask; 2770 u32 trap_attr_mask, traprepress_attr_mask; 2771 2772 MLX4_GET(set_attr_mask, mailbox->buf, 2773 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2774 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2775 set_attr_mask); 2776 2777 MLX4_GET(getresp_attr_mask, mailbox->buf, 2778 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2779 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2780 getresp_attr_mask); 2781 2782 MLX4_GET(trap_attr_mask, mailbox->buf, 2783 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2784 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2785 trap_attr_mask); 2786 2787 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2788 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2789 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2790 traprepress_attr_mask); 2791 2792 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2793 traprepress_attr_mask) 2794 return 1; 2795 2796 return 0; 2797 } 2798 2799 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2800 { 2801 struct mlx4_cmd_mailbox *mailbox; 2802 int err; 2803 2804 /* Check if mad_demux is supported */ 2805 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2806 return 0; 2807 2808 mailbox = mlx4_alloc_cmd_mailbox(dev); 2809 if (IS_ERR(mailbox)) { 2810 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2811 return -ENOMEM; 2812 } 2813 2814 /* Query mad_demux to find out which MADs are handled by internal sma */ 2815 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2816 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2817 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2818 if (err) { 2819 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2820 err); 2821 goto out; 2822 } 2823 2824 if (mlx4_check_smp_firewall_active(dev, mailbox)) 2825 dev->flags |= MLX4_FLAG_SECURE_HOST; 2826 2827 /* Config mad_demux to handle all MADs returned by the query above */ 2828 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2829 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2830 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2831 if (err) { 2832 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2833 goto out; 2834 } 2835 2836 if (dev->flags & MLX4_FLAG_SECURE_HOST) 2837 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2838 out: 2839 mlx4_free_cmd_mailbox(dev, mailbox); 2840 return err; 2841 } 2842 2843 /* Access Reg commands */ 2844 enum mlx4_access_reg_masks { 2845 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2846 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2847 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2848 }; 2849 2850 struct mlx4_access_reg { 2851 __be16 constant1; 2852 u8 status; 2853 u8 resrvd1; 2854 __be16 reg_id; 2855 u8 method; 2856 u8 constant2; 2857 __be32 resrvd2[2]; 2858 __be16 len_const; 2859 __be16 resrvd3; 2860 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2861 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2862 } __attribute__((__packed__)); 2863 2864 /** 2865 * mlx4_ACCESS_REG - Generic access reg command. 2866 * @dev: mlx4_dev. 2867 * @reg_id: register ID to access. 2868 * @method: Access method Read/Write. 2869 * @reg_len: register length to Read/Write in bytes. 2870 * @reg_data: reg_data pointer to Read/Write From/To. 2871 * 2872 * Access ConnectX registers FW command. 2873 * Returns 0 on success and copies outbox mlx4_access_reg data 2874 * field into reg_data or a negative error code. 2875 */ 2876 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2877 enum mlx4_access_reg_method method, 2878 u16 reg_len, void *reg_data) 2879 { 2880 struct mlx4_cmd_mailbox *inbox, *outbox; 2881 struct mlx4_access_reg *inbuf, *outbuf; 2882 int err; 2883 2884 inbox = mlx4_alloc_cmd_mailbox(dev); 2885 if (IS_ERR(inbox)) 2886 return PTR_ERR(inbox); 2887 2888 outbox = mlx4_alloc_cmd_mailbox(dev); 2889 if (IS_ERR(outbox)) { 2890 mlx4_free_cmd_mailbox(dev, inbox); 2891 return PTR_ERR(outbox); 2892 } 2893 2894 inbuf = inbox->buf; 2895 outbuf = outbox->buf; 2896 2897 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2898 inbuf->constant2 = 0x1; 2899 inbuf->reg_id = cpu_to_be16(reg_id); 2900 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2901 2902 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2903 inbuf->len_const = 2904 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2905 ((0x3) << 12)); 2906 2907 memcpy(inbuf->reg_data, reg_data, reg_len); 2908 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2909 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2910 MLX4_CMD_WRAPPED); 2911 if (err) 2912 goto out; 2913 2914 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2915 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2916 mlx4_err(dev, 2917 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2918 reg_id, err); 2919 goto out; 2920 } 2921 2922 memcpy(reg_data, outbuf->reg_data, reg_len); 2923 out: 2924 mlx4_free_cmd_mailbox(dev, inbox); 2925 mlx4_free_cmd_mailbox(dev, outbox); 2926 return err; 2927 } 2928 2929 /* ConnectX registers IDs */ 2930 enum mlx4_reg_id { 2931 MLX4_REG_ID_PTYS = 0x5004, 2932 }; 2933 2934 /** 2935 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2936 * register 2937 * @dev: mlx4_dev. 2938 * @method: Access method Read/Write. 2939 * @ptys_reg: PTYS register data pointer. 2940 * 2941 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2942 * configuration 2943 * Returns 0 on success or a negative error code. 2944 */ 2945 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2946 enum mlx4_access_reg_method method, 2947 struct mlx4_ptys_reg *ptys_reg) 2948 { 2949 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2950 method, sizeof(*ptys_reg), ptys_reg); 2951 } 2952 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2953 2954 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2955 struct mlx4_vhcr *vhcr, 2956 struct mlx4_cmd_mailbox *inbox, 2957 struct mlx4_cmd_mailbox *outbox, 2958 struct mlx4_cmd_info *cmd) 2959 { 2960 struct mlx4_access_reg *inbuf = inbox->buf; 2961 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2962 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2963 2964 if (slave != mlx4_master_func_num(dev) && 2965 method == MLX4_ACCESS_REG_WRITE) 2966 return -EPERM; 2967 2968 if (reg_id == MLX4_REG_ID_PTYS) { 2969 struct mlx4_ptys_reg *ptys_reg = 2970 (struct mlx4_ptys_reg *)inbuf->reg_data; 2971 2972 ptys_reg->local_port = 2973 mlx4_slave_convert_port(dev, slave, 2974 ptys_reg->local_port); 2975 } 2976 2977 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2978 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2979 MLX4_CMD_NATIVE); 2980 } 2981 2982 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) 2983 { 2984 #define SET_PORT_GEN_PHV_VALID 0x10 2985 #define SET_PORT_GEN_PHV_EN 0x80 2986 2987 struct mlx4_cmd_mailbox *mailbox; 2988 struct mlx4_set_port_general_context *context; 2989 u32 in_mod; 2990 int err; 2991 2992 mailbox = mlx4_alloc_cmd_mailbox(dev); 2993 if (IS_ERR(mailbox)) 2994 return PTR_ERR(mailbox); 2995 context = mailbox->buf; 2996 2997 context->flags2 |= SET_PORT_GEN_PHV_VALID; 2998 if (phv_bit) 2999 context->phv_en |= SET_PORT_GEN_PHV_EN; 3000 3001 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 3002 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 3003 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 3004 MLX4_CMD_NATIVE); 3005 3006 mlx4_free_cmd_mailbox(dev, mailbox); 3007 return err; 3008 } 3009 3010 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) 3011 { 3012 int err; 3013 struct mlx4_func_cap func_cap; 3014 3015 memset(&func_cap, 0, sizeof(func_cap)); 3016 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 3017 if (!err) 3018 *phv = func_cap.flags0 & QUERY_FUNC_CAP_PHV_BIT; 3019 return err; 3020 } 3021 EXPORT_SYMBOL(get_phv_bit); 3022 3023 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 3024 { 3025 int ret; 3026 3027 if (mlx4_is_slave(dev)) 3028 return -EPERM; 3029 3030 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && 3031 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { 3032 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); 3033 if (!ret) 3034 dev->caps.phv_bit[port] = new_val; 3035 return ret; 3036 } 3037 3038 return -EOPNOTSUPP; 3039 } 3040 EXPORT_SYMBOL(set_phv_bit); 3041 3042 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 3043 bool *vlan_offload_disabled) 3044 { 3045 struct mlx4_func_cap func_cap; 3046 int err; 3047 3048 memset(&func_cap, 0, sizeof(func_cap)); 3049 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 3050 if (!err) 3051 *vlan_offload_disabled = 3052 !!(func_cap.flags0 & 3053 QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE); 3054 return err; 3055 } 3056 EXPORT_SYMBOL(mlx4_get_is_vlan_offload_disabled); 3057 3058 void mlx4_replace_zero_macs(struct mlx4_dev *dev) 3059 { 3060 int i; 3061 u8 mac_addr[ETH_ALEN]; 3062 3063 dev->port_random_macs = 0; 3064 for (i = 1; i <= dev->caps.num_ports; ++i) 3065 if (!dev->caps.def_mac[i] && 3066 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { 3067 eth_random_addr(mac_addr); 3068 dev->port_random_macs |= 1 << i; 3069 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); 3070 } 3071 } 3072 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); 3073