1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 4] = "reliable multicast", 88 [ 5] = "FCoIB support", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [10] = "VMM", 94 [12] = "Dual Port Different Protocol (DPDP) support", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [24] = "Demand paging support", 103 [25] = "Router support", 104 [30] = "IBoE support", 105 [32] = "Unicast loopback support", 106 [34] = "FCS header control", 107 [38] = "Wake On LAN support", 108 [40] = "UDP RSS support", 109 [41] = "Unicast VEP steering support", 110 [42] = "Multicast VEP steering support", 111 [48] = "Counters support", 112 [53] = "Port ETS Scheduler support", 113 [55] = "Port link type sensing support", 114 [59] = "Port management change event support", 115 [61] = "64 byte EQE support", 116 [62] = "64 byte CQE support", 117 }; 118 int i; 119 120 mlx4_dbg(dev, "DEV_CAP flags:\n"); 121 for (i = 0; i < ARRAY_SIZE(fname); ++i) 122 if (fname[i] && (flags & (1LL << i))) 123 mlx4_dbg(dev, " %s\n", fname[i]); 124 } 125 126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127 { 128 static const char * const fname[] = { 129 [0] = "RSS support", 130 [1] = "RSS Toeplitz Hash Function support", 131 [2] = "RSS XOR Hash Function support", 132 [3] = "Device managed flow steering support", 133 [4] = "Automatic MAC reassignment support", 134 [5] = "Time stamping support", 135 [6] = "VST (control vlan insertion/stripping) support", 136 [7] = "FSM (MAC anti-spoofing) support", 137 [8] = "Dynamic QP updates support", 138 [9] = "Device managed flow steering IPoIB support", 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support" 140 }; 141 int i; 142 143 for (i = 0; i < ARRAY_SIZE(fname); ++i) 144 if (fname[i] && (flags & (1LL << i))) 145 mlx4_dbg(dev, " %s\n", fname[i]); 146 } 147 148 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 149 { 150 struct mlx4_cmd_mailbox *mailbox; 151 u32 *inbox; 152 int err = 0; 153 154 #define MOD_STAT_CFG_IN_SIZE 0x100 155 156 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 157 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 158 159 mailbox = mlx4_alloc_cmd_mailbox(dev); 160 if (IS_ERR(mailbox)) 161 return PTR_ERR(mailbox); 162 inbox = mailbox->buf; 163 164 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 165 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 166 167 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 168 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 169 170 mlx4_free_cmd_mailbox(dev, mailbox); 171 return err; 172 } 173 174 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 175 struct mlx4_vhcr *vhcr, 176 struct mlx4_cmd_mailbox *inbox, 177 struct mlx4_cmd_mailbox *outbox, 178 struct mlx4_cmd_info *cmd) 179 { 180 struct mlx4_priv *priv = mlx4_priv(dev); 181 u8 field; 182 u32 size; 183 int err = 0; 184 185 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 186 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 187 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 188 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 189 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 190 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 191 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 192 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 193 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 194 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 195 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 196 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 197 198 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 199 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 200 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 201 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 202 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 203 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 204 205 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 206 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 207 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 208 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 209 210 /* when opcode modifier = 1 */ 211 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 212 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 213 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 214 215 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 216 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 217 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 218 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 219 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 220 221 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 222 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 223 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 224 225 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 226 227 if (vhcr->op_modifier == 1) { 228 /* Set nic_info bit to mark new fields support */ 229 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 230 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 231 232 field = vhcr->in_modifier; /* phys-port = logical-port */ 233 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 234 235 /* size is now the QP number */ 236 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; 237 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 238 239 size += 2; 240 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 241 242 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; 243 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); 244 245 size += 2; 246 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); 247 248 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 249 QUERY_FUNC_CAP_PHYS_PORT_ID); 250 251 } else if (vhcr->op_modifier == 0) { 252 /* enable rdma and ethernet interfaces, and new quota locations */ 253 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 254 QUERY_FUNC_CAP_FLAG_QUOTAS); 255 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 256 257 field = dev->caps.num_ports; 258 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 259 260 size = dev->caps.function_caps; /* set PF behaviours */ 261 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 262 263 field = 0; /* protected FMR support not available as yet */ 264 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 265 266 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 267 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 268 size = dev->caps.num_qps; 269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 270 271 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 273 size = dev->caps.num_srqs; 274 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 275 276 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 278 size = dev->caps.num_cqs; 279 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 280 281 size = dev->caps.num_eqs; 282 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 283 284 size = dev->caps.reserved_eqs; 285 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 286 287 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 289 size = dev->caps.num_mpts; 290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 291 292 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 293 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 294 size = dev->caps.num_mtts; 295 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 296 297 size = dev->caps.num_mgms + dev->caps.num_amgms; 298 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 299 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 300 301 } else 302 err = -EINVAL; 303 304 return err; 305 } 306 307 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, 308 struct mlx4_func_cap *func_cap) 309 { 310 struct mlx4_cmd_mailbox *mailbox; 311 u32 *outbox; 312 u8 field, op_modifier; 313 u32 size; 314 int err = 0, quotas = 0; 315 316 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 317 318 mailbox = mlx4_alloc_cmd_mailbox(dev); 319 if (IS_ERR(mailbox)) 320 return PTR_ERR(mailbox); 321 322 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, 323 MLX4_CMD_QUERY_FUNC_CAP, 324 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 325 if (err) 326 goto out; 327 328 outbox = mailbox->buf; 329 330 if (!op_modifier) { 331 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 332 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 333 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 334 err = -EPROTONOSUPPORT; 335 goto out; 336 } 337 func_cap->flags = field; 338 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 339 340 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 341 func_cap->num_ports = field; 342 343 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 344 func_cap->pf_context_behaviour = size; 345 346 if (quotas) { 347 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 348 func_cap->qp_quota = size & 0xFFFFFF; 349 350 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 351 func_cap->srq_quota = size & 0xFFFFFF; 352 353 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 354 func_cap->cq_quota = size & 0xFFFFFF; 355 356 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 357 func_cap->mpt_quota = size & 0xFFFFFF; 358 359 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 360 func_cap->mtt_quota = size & 0xFFFFFF; 361 362 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 363 func_cap->mcg_quota = size & 0xFFFFFF; 364 365 } else { 366 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 367 func_cap->qp_quota = size & 0xFFFFFF; 368 369 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 370 func_cap->srq_quota = size & 0xFFFFFF; 371 372 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 373 func_cap->cq_quota = size & 0xFFFFFF; 374 375 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 376 func_cap->mpt_quota = size & 0xFFFFFF; 377 378 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 379 func_cap->mtt_quota = size & 0xFFFFFF; 380 381 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 382 func_cap->mcg_quota = size & 0xFFFFFF; 383 } 384 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 385 func_cap->max_eq = size & 0xFFFFFF; 386 387 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 388 func_cap->reserved_eq = size & 0xFFFFFF; 389 390 goto out; 391 } 392 393 /* logical port query */ 394 if (gen_or_port > dev->caps.num_ports) { 395 err = -EINVAL; 396 goto out; 397 } 398 399 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 400 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 401 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_OFFSET) { 402 mlx4_err(dev, "VLAN is enforced on this port\n"); 403 err = -EPROTONOSUPPORT; 404 goto out; 405 } 406 407 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 408 mlx4_err(dev, "Force mac is enabled on this port\n"); 409 err = -EPROTONOSUPPORT; 410 goto out; 411 } 412 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 413 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 414 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 415 mlx4_err(dev, "phy_wqe_gid is " 416 "enforced on this ib port\n"); 417 err = -EPROTONOSUPPORT; 418 goto out; 419 } 420 } 421 422 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 423 func_cap->physical_port = field; 424 if (func_cap->physical_port != gen_or_port) { 425 err = -ENOSYS; 426 goto out; 427 } 428 429 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 430 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 431 432 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 433 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 434 435 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 436 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 437 438 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 439 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 440 441 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 442 MLX4_GET(func_cap->phys_port_id, outbox, 443 QUERY_FUNC_CAP_PHYS_PORT_ID); 444 445 /* All other resources are allocated by the master, but we still report 446 * 'num' and 'reserved' capabilities as follows: 447 * - num remains the maximum resource index 448 * - 'num - reserved' is the total available objects of a resource, but 449 * resource indices may be less than 'reserved' 450 * TODO: set per-resource quotas */ 451 452 out: 453 mlx4_free_cmd_mailbox(dev, mailbox); 454 455 return err; 456 } 457 458 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 459 { 460 struct mlx4_cmd_mailbox *mailbox; 461 u32 *outbox; 462 u8 field; 463 u32 field32, flags, ext_flags; 464 u16 size; 465 u16 stat_rate; 466 int err; 467 int i; 468 469 #define QUERY_DEV_CAP_OUT_SIZE 0x100 470 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 471 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 472 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 473 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 474 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 475 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 476 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 477 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 478 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 479 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 480 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 481 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 482 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 483 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 484 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 485 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 486 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 487 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 488 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 489 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 490 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 491 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 492 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 493 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 494 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 495 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 496 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 497 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 498 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 499 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 500 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 501 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 502 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 503 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 504 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 505 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 506 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 507 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 508 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 509 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 510 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 511 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 512 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 513 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 514 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 515 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 516 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 517 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 518 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 519 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 520 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 521 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 522 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 523 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 524 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 525 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 526 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 527 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 528 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 529 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 530 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 531 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 532 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 533 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 534 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 535 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 536 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 537 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 538 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 539 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 540 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 541 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 542 #define QUERY_DEV_CAP_VXLAN 0x9e 543 544 dev_cap->flags2 = 0; 545 mailbox = mlx4_alloc_cmd_mailbox(dev); 546 if (IS_ERR(mailbox)) 547 return PTR_ERR(mailbox); 548 outbox = mailbox->buf; 549 550 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 551 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 552 if (err) 553 goto out; 554 555 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 556 dev_cap->reserved_qps = 1 << (field & 0xf); 557 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 558 dev_cap->max_qps = 1 << (field & 0x1f); 559 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 560 dev_cap->reserved_srqs = 1 << (field >> 4); 561 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 562 dev_cap->max_srqs = 1 << (field & 0x1f); 563 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 564 dev_cap->max_cq_sz = 1 << field; 565 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 566 dev_cap->reserved_cqs = 1 << (field & 0xf); 567 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 568 dev_cap->max_cqs = 1 << (field & 0x1f); 569 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 570 dev_cap->max_mpts = 1 << (field & 0x3f); 571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 572 dev_cap->reserved_eqs = field & 0xf; 573 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 574 dev_cap->max_eqs = 1 << (field & 0xf); 575 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 576 dev_cap->reserved_mtts = 1 << (field >> 4); 577 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 578 dev_cap->max_mrw_sz = 1 << field; 579 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 580 dev_cap->reserved_mrws = 1 << (field & 0xf); 581 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 582 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 583 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 584 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 585 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 586 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 587 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 588 field &= 0x1f; 589 if (!field) 590 dev_cap->max_gso_sz = 0; 591 else 592 dev_cap->max_gso_sz = 1 << field; 593 594 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 595 if (field & 0x20) 596 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 597 if (field & 0x10) 598 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 599 field &= 0xf; 600 if (field) { 601 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 602 dev_cap->max_rss_tbl_sz = 1 << field; 603 } else 604 dev_cap->max_rss_tbl_sz = 0; 605 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 606 dev_cap->max_rdma_global = 1 << (field & 0x3f); 607 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 608 dev_cap->local_ca_ack_delay = field & 0x1f; 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 610 dev_cap->num_ports = field & 0xf; 611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 612 dev_cap->max_msg_sz = 1 << (field & 0x1f); 613 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 614 if (field & 0x80) 615 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 616 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 617 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 618 if (field & 0x80) 619 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 620 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 621 dev_cap->fs_max_num_qp_per_entry = field; 622 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 623 dev_cap->stat_rate_support = stat_rate; 624 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 625 if (field & 0x80) 626 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 627 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 628 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 629 dev_cap->flags = flags | (u64)ext_flags << 32; 630 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 631 dev_cap->reserved_uars = field >> 4; 632 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 633 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 634 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 635 dev_cap->min_page_sz = 1 << field; 636 637 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 638 if (field & 0x80) { 639 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 640 dev_cap->bf_reg_size = 1 << (field & 0x1f); 641 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 642 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 643 field = 3; 644 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 645 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 646 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 647 } else { 648 dev_cap->bf_reg_size = 0; 649 mlx4_dbg(dev, "BlueFlame not available\n"); 650 } 651 652 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 653 dev_cap->max_sq_sg = field; 654 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 655 dev_cap->max_sq_desc_sz = size; 656 657 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 658 dev_cap->max_qp_per_mcg = 1 << field; 659 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 660 dev_cap->reserved_mgms = field & 0xf; 661 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 662 dev_cap->max_mcgs = 1 << field; 663 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 664 dev_cap->reserved_pds = field >> 4; 665 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 666 dev_cap->max_pds = 1 << (field & 0x3f); 667 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 668 dev_cap->reserved_xrcds = field >> 4; 669 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 670 dev_cap->max_xrcds = 1 << (field & 0x1f); 671 672 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 673 dev_cap->rdmarc_entry_sz = size; 674 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 675 dev_cap->qpc_entry_sz = size; 676 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 677 dev_cap->aux_entry_sz = size; 678 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 679 dev_cap->altc_entry_sz = size; 680 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 681 dev_cap->eqc_entry_sz = size; 682 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 683 dev_cap->cqc_entry_sz = size; 684 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 685 dev_cap->srq_entry_sz = size; 686 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 687 dev_cap->cmpt_entry_sz = size; 688 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 689 dev_cap->mtt_entry_sz = size; 690 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 691 dev_cap->dmpt_entry_sz = size; 692 693 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 694 dev_cap->max_srq_sz = 1 << field; 695 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 696 dev_cap->max_qp_sz = 1 << field; 697 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 698 dev_cap->resize_srq = field & 1; 699 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 700 dev_cap->max_rq_sg = field; 701 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 702 dev_cap->max_rq_desc_sz = size; 703 704 MLX4_GET(dev_cap->bmme_flags, outbox, 705 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 706 MLX4_GET(dev_cap->reserved_lkey, outbox, 707 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 708 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 709 if (field & 1<<6) 710 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 711 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 712 if (field & 1<<3) 713 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 714 MLX4_GET(dev_cap->max_icm_sz, outbox, 715 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 716 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 717 MLX4_GET(dev_cap->max_counters, outbox, 718 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 719 720 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 721 if (field32 & (1 << 16)) 722 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 723 if (field32 & (1 << 26)) 724 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 725 if (field32 & (1 << 20)) 726 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 727 728 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 729 for (i = 1; i <= dev_cap->num_ports; ++i) { 730 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 731 dev_cap->max_vl[i] = field >> 4; 732 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 733 dev_cap->ib_mtu[i] = field >> 4; 734 dev_cap->max_port_width[i] = field & 0xf; 735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 736 dev_cap->max_gids[i] = 1 << (field & 0xf); 737 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 738 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 739 } 740 } else { 741 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 742 #define QUERY_PORT_MTU_OFFSET 0x01 743 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 744 #define QUERY_PORT_WIDTH_OFFSET 0x06 745 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 746 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 747 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 748 #define QUERY_PORT_MAC_OFFSET 0x10 749 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 750 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 751 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 752 753 for (i = 1; i <= dev_cap->num_ports; ++i) { 754 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, 755 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 756 if (err) 757 goto out; 758 759 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 760 dev_cap->supported_port_types[i] = field & 3; 761 dev_cap->suggested_type[i] = (field >> 3) & 1; 762 dev_cap->default_sense[i] = (field >> 4) & 1; 763 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 764 dev_cap->ib_mtu[i] = field & 0xf; 765 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 766 dev_cap->max_port_width[i] = field & 0xf; 767 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 768 dev_cap->max_gids[i] = 1 << (field >> 4); 769 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 770 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 771 dev_cap->max_vl[i] = field & 0xf; 772 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 773 dev_cap->log_max_macs[i] = field & 0xf; 774 dev_cap->log_max_vlans[i] = field >> 4; 775 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); 776 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); 777 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 778 dev_cap->trans_type[i] = field32 >> 24; 779 dev_cap->vendor_oui[i] = field32 & 0xffffff; 780 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); 781 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); 782 } 783 } 784 785 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 786 dev_cap->bmme_flags, dev_cap->reserved_lkey); 787 788 /* 789 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 790 * we can't use any EQs whose doorbell falls on that page, 791 * even if the EQ itself isn't reserved. 792 */ 793 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 794 dev_cap->reserved_eqs); 795 796 mlx4_dbg(dev, "Max ICM size %lld MB\n", 797 (unsigned long long) dev_cap->max_icm_sz >> 20); 798 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 799 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 800 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 801 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 802 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 803 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 804 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 805 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); 806 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 807 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 808 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 809 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 810 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 811 dev_cap->max_pds, dev_cap->reserved_mgms); 812 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 813 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 814 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 815 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 816 dev_cap->max_port_width[1]); 817 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 818 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 819 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 820 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 821 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 822 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 823 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 824 825 dump_dev_cap_flags(dev, dev_cap->flags); 826 dump_dev_cap_flags2(dev, dev_cap->flags2); 827 828 out: 829 mlx4_free_cmd_mailbox(dev, mailbox); 830 return err; 831 } 832 833 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 834 struct mlx4_vhcr *vhcr, 835 struct mlx4_cmd_mailbox *inbox, 836 struct mlx4_cmd_mailbox *outbox, 837 struct mlx4_cmd_info *cmd) 838 { 839 u64 flags; 840 int err = 0; 841 u8 field; 842 u32 bmme_flags; 843 844 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 845 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 846 if (err) 847 return err; 848 849 /* add port mng change event capability and disable mw type 1 850 * unconditionally to slaves 851 */ 852 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 853 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 854 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 855 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 856 857 /* For guests, disable timestamp */ 858 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 859 field &= 0x7f; 860 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 861 862 /* For guests, disable vxlan tunneling */ 863 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 864 field &= 0xf7; 865 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 866 867 /* For guests, report Blueflame disabled */ 868 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 869 field &= 0x7f; 870 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 871 872 /* For guests, disable mw type 2 */ 873 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 874 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 875 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 876 877 /* turn off device-managed steering capability if not enabled */ 878 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 879 MLX4_GET(field, outbox->buf, 880 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 881 field &= 0x7f; 882 MLX4_PUT(outbox->buf, field, 883 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 884 } 885 886 /* turn off ipoib managed steering for guests */ 887 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 888 field &= ~0x80; 889 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 890 891 return 0; 892 } 893 894 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 895 struct mlx4_vhcr *vhcr, 896 struct mlx4_cmd_mailbox *inbox, 897 struct mlx4_cmd_mailbox *outbox, 898 struct mlx4_cmd_info *cmd) 899 { 900 struct mlx4_priv *priv = mlx4_priv(dev); 901 u64 def_mac; 902 u8 port_type; 903 u16 short_field; 904 int err; 905 int admin_link_state; 906 907 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 908 #define MLX4_PORT_LINK_UP_MASK 0x80 909 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 910 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 911 912 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 913 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 914 MLX4_CMD_NATIVE); 915 916 if (!err && dev->caps.function != slave) { 917 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 918 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 919 920 /* get port type - currently only eth is enabled */ 921 MLX4_GET(port_type, outbox->buf, 922 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 923 924 /* No link sensing allowed */ 925 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 926 /* set port type to currently operating port type */ 927 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 928 929 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 930 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 931 port_type |= MLX4_PORT_LINK_UP_MASK; 932 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 933 port_type &= ~MLX4_PORT_LINK_UP_MASK; 934 935 MLX4_PUT(outbox->buf, port_type, 936 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 937 938 short_field = 1; /* slave max gids */ 939 MLX4_PUT(outbox->buf, short_field, 940 QUERY_PORT_CUR_MAX_GID_OFFSET); 941 942 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 943 MLX4_PUT(outbox->buf, short_field, 944 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 945 } 946 947 return err; 948 } 949 950 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 951 int *gid_tbl_len, int *pkey_tbl_len) 952 { 953 struct mlx4_cmd_mailbox *mailbox; 954 u32 *outbox; 955 u16 field; 956 int err; 957 958 mailbox = mlx4_alloc_cmd_mailbox(dev); 959 if (IS_ERR(mailbox)) 960 return PTR_ERR(mailbox); 961 962 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 963 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 964 MLX4_CMD_WRAPPED); 965 if (err) 966 goto out; 967 968 outbox = mailbox->buf; 969 970 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 971 *gid_tbl_len = field; 972 973 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 974 *pkey_tbl_len = field; 975 976 out: 977 mlx4_free_cmd_mailbox(dev, mailbox); 978 return err; 979 } 980 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 981 982 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 983 { 984 struct mlx4_cmd_mailbox *mailbox; 985 struct mlx4_icm_iter iter; 986 __be64 *pages; 987 int lg; 988 int nent = 0; 989 int i; 990 int err = 0; 991 int ts = 0, tc = 0; 992 993 mailbox = mlx4_alloc_cmd_mailbox(dev); 994 if (IS_ERR(mailbox)) 995 return PTR_ERR(mailbox); 996 pages = mailbox->buf; 997 998 for (mlx4_icm_first(icm, &iter); 999 !mlx4_icm_last(&iter); 1000 mlx4_icm_next(&iter)) { 1001 /* 1002 * We have to pass pages that are aligned to their 1003 * size, so find the least significant 1 in the 1004 * address or size and use that as our log2 size. 1005 */ 1006 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1007 if (lg < MLX4_ICM_PAGE_SHIFT) { 1008 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 1009 MLX4_ICM_PAGE_SIZE, 1010 (unsigned long long) mlx4_icm_addr(&iter), 1011 mlx4_icm_size(&iter)); 1012 err = -EINVAL; 1013 goto out; 1014 } 1015 1016 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1017 if (virt != -1) { 1018 pages[nent * 2] = cpu_to_be64(virt); 1019 virt += 1 << lg; 1020 } 1021 1022 pages[nent * 2 + 1] = 1023 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1024 (lg - MLX4_ICM_PAGE_SHIFT)); 1025 ts += 1 << (lg - 10); 1026 ++tc; 1027 1028 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1029 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1030 MLX4_CMD_TIME_CLASS_B, 1031 MLX4_CMD_NATIVE); 1032 if (err) 1033 goto out; 1034 nent = 0; 1035 } 1036 } 1037 } 1038 1039 if (nent) 1040 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1041 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1042 if (err) 1043 goto out; 1044 1045 switch (op) { 1046 case MLX4_CMD_MAP_FA: 1047 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 1048 break; 1049 case MLX4_CMD_MAP_ICM_AUX: 1050 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 1051 break; 1052 case MLX4_CMD_MAP_ICM: 1053 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 1054 tc, ts, (unsigned long long) virt - (ts << 10)); 1055 break; 1056 } 1057 1058 out: 1059 mlx4_free_cmd_mailbox(dev, mailbox); 1060 return err; 1061 } 1062 1063 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1064 { 1065 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1066 } 1067 1068 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1069 { 1070 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1071 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1072 } 1073 1074 1075 int mlx4_RUN_FW(struct mlx4_dev *dev) 1076 { 1077 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1078 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1079 } 1080 1081 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1082 { 1083 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1084 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1085 struct mlx4_cmd_mailbox *mailbox; 1086 u32 *outbox; 1087 int err = 0; 1088 u64 fw_ver; 1089 u16 cmd_if_rev; 1090 u8 lg; 1091 1092 #define QUERY_FW_OUT_SIZE 0x100 1093 #define QUERY_FW_VER_OFFSET 0x00 1094 #define QUERY_FW_PPF_ID 0x09 1095 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1096 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1097 #define QUERY_FW_ERR_START_OFFSET 0x30 1098 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1099 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1100 1101 #define QUERY_FW_SIZE_OFFSET 0x00 1102 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1103 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1104 1105 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1106 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1107 1108 #define QUERY_FW_CLOCK_OFFSET 0x50 1109 #define QUERY_FW_CLOCK_BAR 0x58 1110 1111 mailbox = mlx4_alloc_cmd_mailbox(dev); 1112 if (IS_ERR(mailbox)) 1113 return PTR_ERR(mailbox); 1114 outbox = mailbox->buf; 1115 1116 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1117 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1118 if (err) 1119 goto out; 1120 1121 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1122 /* 1123 * FW subminor version is at more significant bits than minor 1124 * version, so swap here. 1125 */ 1126 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1127 ((fw_ver & 0xffff0000ull) >> 16) | 1128 ((fw_ver & 0x0000ffffull) << 16); 1129 1130 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1131 dev->caps.function = lg; 1132 1133 if (mlx4_is_slave(dev)) 1134 goto out; 1135 1136 1137 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1138 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1139 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1140 mlx4_err(dev, "Installed FW has unsupported " 1141 "command interface revision %d.\n", 1142 cmd_if_rev); 1143 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1144 (int) (dev->caps.fw_ver >> 32), 1145 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1146 (int) dev->caps.fw_ver & 0xffff); 1147 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", 1148 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1149 err = -ENODEV; 1150 goto out; 1151 } 1152 1153 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1154 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1155 1156 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1157 cmd->max_cmds = 1 << lg; 1158 1159 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1160 (int) (dev->caps.fw_ver >> 32), 1161 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1162 (int) dev->caps.fw_ver & 0xffff, 1163 cmd_if_rev, cmd->max_cmds); 1164 1165 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1166 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1167 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1168 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1169 1170 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1171 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1172 1173 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1174 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1175 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1176 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1177 1178 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1179 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1180 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1181 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1182 fw->comm_bar, fw->comm_base); 1183 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1184 1185 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1186 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1187 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1188 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1189 fw->clock_bar, fw->clock_offset); 1190 1191 /* 1192 * Round up number of system pages needed in case 1193 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1194 */ 1195 fw->fw_pages = 1196 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1197 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1198 1199 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1200 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1201 1202 out: 1203 mlx4_free_cmd_mailbox(dev, mailbox); 1204 return err; 1205 } 1206 1207 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1208 struct mlx4_vhcr *vhcr, 1209 struct mlx4_cmd_mailbox *inbox, 1210 struct mlx4_cmd_mailbox *outbox, 1211 struct mlx4_cmd_info *cmd) 1212 { 1213 u8 *outbuf; 1214 int err; 1215 1216 outbuf = outbox->buf; 1217 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1218 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1219 if (err) 1220 return err; 1221 1222 /* for slaves, set pci PPF ID to invalid and zero out everything 1223 * else except FW version */ 1224 outbuf[0] = outbuf[1] = 0; 1225 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1226 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1227 1228 return 0; 1229 } 1230 1231 static void get_board_id(void *vsd, char *board_id) 1232 { 1233 int i; 1234 1235 #define VSD_OFFSET_SIG1 0x00 1236 #define VSD_OFFSET_SIG2 0xde 1237 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1238 #define VSD_OFFSET_TS_BOARD_ID 0x20 1239 1240 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1241 1242 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1243 1244 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1245 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1246 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1247 } else { 1248 /* 1249 * The board ID is a string but the firmware byte 1250 * swaps each 4-byte word before passing it back to 1251 * us. Therefore we need to swab it before printing. 1252 */ 1253 for (i = 0; i < 4; ++i) 1254 ((u32 *) board_id)[i] = 1255 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1256 } 1257 } 1258 1259 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1260 { 1261 struct mlx4_cmd_mailbox *mailbox; 1262 u32 *outbox; 1263 int err; 1264 1265 #define QUERY_ADAPTER_OUT_SIZE 0x100 1266 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1267 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1268 1269 mailbox = mlx4_alloc_cmd_mailbox(dev); 1270 if (IS_ERR(mailbox)) 1271 return PTR_ERR(mailbox); 1272 outbox = mailbox->buf; 1273 1274 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1275 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1276 if (err) 1277 goto out; 1278 1279 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1280 1281 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1282 adapter->board_id); 1283 1284 out: 1285 mlx4_free_cmd_mailbox(dev, mailbox); 1286 return err; 1287 } 1288 1289 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1290 { 1291 struct mlx4_cmd_mailbox *mailbox; 1292 __be32 *inbox; 1293 int err; 1294 1295 #define INIT_HCA_IN_SIZE 0x200 1296 #define INIT_HCA_VERSION_OFFSET 0x000 1297 #define INIT_HCA_VERSION 2 1298 #define INIT_HCA_VXLAN_OFFSET 0x0c 1299 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1300 #define INIT_HCA_FLAGS_OFFSET 0x014 1301 #define INIT_HCA_QPC_OFFSET 0x020 1302 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1303 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1304 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1305 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1306 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1307 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1308 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1309 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1310 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1311 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1312 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1313 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1314 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1315 #define INIT_HCA_MCAST_OFFSET 0x0c0 1316 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1317 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1318 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1319 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1320 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1321 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1322 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1323 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1324 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1325 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1326 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1327 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1328 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1329 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1330 #define INIT_HCA_TPT_OFFSET 0x0f0 1331 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1332 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1333 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1334 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1335 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1336 #define INIT_HCA_UAR_OFFSET 0x120 1337 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1338 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1339 1340 mailbox = mlx4_alloc_cmd_mailbox(dev); 1341 if (IS_ERR(mailbox)) 1342 return PTR_ERR(mailbox); 1343 inbox = mailbox->buf; 1344 1345 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1346 1347 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1348 (ilog2(cache_line_size()) - 4) << 5; 1349 1350 #if defined(__LITTLE_ENDIAN) 1351 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1352 #elif defined(__BIG_ENDIAN) 1353 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1354 #else 1355 #error Host endianness not defined 1356 #endif 1357 /* Check port for UD address vector: */ 1358 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1359 1360 /* Enable IPoIB checksumming if we can: */ 1361 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1362 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1363 1364 /* Enable QoS support if module parameter set */ 1365 if (enable_qos) 1366 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1367 1368 /* enable counters */ 1369 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1370 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1371 1372 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1373 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1374 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1375 dev->caps.eqe_size = 64; 1376 dev->caps.eqe_factor = 1; 1377 } else { 1378 dev->caps.eqe_size = 32; 1379 dev->caps.eqe_factor = 0; 1380 } 1381 1382 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1383 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1384 dev->caps.cqe_size = 64; 1385 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 1386 } else { 1387 dev->caps.cqe_size = 32; 1388 } 1389 1390 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1391 1392 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1393 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1394 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1395 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1396 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1397 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1398 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1399 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1400 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1401 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1402 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1403 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1404 1405 /* steering attributes */ 1406 if (dev->caps.steering_mode == 1407 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1408 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1409 cpu_to_be32(1 << 1410 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1411 1412 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1413 MLX4_PUT(inbox, param->log_mc_entry_sz, 1414 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1415 MLX4_PUT(inbox, param->log_mc_table_sz, 1416 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1417 /* Enable Ethernet flow steering 1418 * with udp unicast and tcp unicast 1419 */ 1420 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1421 INIT_HCA_FS_ETH_BITS_OFFSET); 1422 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1423 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1424 /* Enable IPoIB flow steering 1425 * with udp unicast and tcp unicast 1426 */ 1427 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1428 INIT_HCA_FS_IB_BITS_OFFSET); 1429 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1430 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1431 } else { 1432 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1433 MLX4_PUT(inbox, param->log_mc_entry_sz, 1434 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1435 MLX4_PUT(inbox, param->log_mc_hash_sz, 1436 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1437 MLX4_PUT(inbox, param->log_mc_table_sz, 1438 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1439 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1440 MLX4_PUT(inbox, (u8) (1 << 3), 1441 INIT_HCA_UC_STEERING_OFFSET); 1442 } 1443 1444 /* TPT attributes */ 1445 1446 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1447 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1448 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1449 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1450 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1451 1452 /* UAR attributes */ 1453 1454 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1455 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1456 1457 /* set parser VXLAN attributes */ 1458 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1459 u8 parser_params = 0; 1460 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1461 } 1462 1463 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1464 MLX4_CMD_NATIVE); 1465 1466 if (err) 1467 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1468 1469 mlx4_free_cmd_mailbox(dev, mailbox); 1470 return err; 1471 } 1472 1473 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1474 struct mlx4_init_hca_param *param) 1475 { 1476 struct mlx4_cmd_mailbox *mailbox; 1477 __be32 *outbox; 1478 u32 dword_field; 1479 int err; 1480 u8 byte_field; 1481 1482 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1483 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1484 1485 mailbox = mlx4_alloc_cmd_mailbox(dev); 1486 if (IS_ERR(mailbox)) 1487 return PTR_ERR(mailbox); 1488 outbox = mailbox->buf; 1489 1490 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1491 MLX4_CMD_QUERY_HCA, 1492 MLX4_CMD_TIME_CLASS_B, 1493 !mlx4_is_slave(dev)); 1494 if (err) 1495 goto out; 1496 1497 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1498 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1499 1500 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1501 1502 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1503 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1504 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1505 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1506 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1507 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1508 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1509 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1510 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1511 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1512 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1513 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1514 1515 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1516 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1517 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1518 } else { 1519 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1520 if (byte_field & 0x8) 1521 param->steering_mode = MLX4_STEERING_MODE_B0; 1522 else 1523 param->steering_mode = MLX4_STEERING_MODE_A0; 1524 } 1525 /* steering attributes */ 1526 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1527 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1528 MLX4_GET(param->log_mc_entry_sz, outbox, 1529 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1530 MLX4_GET(param->log_mc_table_sz, outbox, 1531 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1532 } else { 1533 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1534 MLX4_GET(param->log_mc_entry_sz, outbox, 1535 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1536 MLX4_GET(param->log_mc_hash_sz, outbox, 1537 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1538 MLX4_GET(param->log_mc_table_sz, outbox, 1539 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1540 } 1541 1542 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1543 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1544 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1545 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1546 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1547 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1548 1549 /* TPT attributes */ 1550 1551 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1552 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1553 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1554 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1555 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1556 1557 /* UAR attributes */ 1558 1559 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1560 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1561 1562 out: 1563 mlx4_free_cmd_mailbox(dev, mailbox); 1564 1565 return err; 1566 } 1567 1568 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 1569 * and real QP0 are active, so that the paravirtualized QP0 is ready 1570 * to operate */ 1571 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 1572 { 1573 struct mlx4_priv *priv = mlx4_priv(dev); 1574 /* irrelevant if not infiniband */ 1575 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 1576 priv->mfunc.master.qp0_state[port].qp0_active) 1577 return 1; 1578 return 0; 1579 } 1580 1581 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1582 struct mlx4_vhcr *vhcr, 1583 struct mlx4_cmd_mailbox *inbox, 1584 struct mlx4_cmd_mailbox *outbox, 1585 struct mlx4_cmd_info *cmd) 1586 { 1587 struct mlx4_priv *priv = mlx4_priv(dev); 1588 int port = vhcr->in_modifier; 1589 int err; 1590 1591 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 1592 return 0; 1593 1594 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1595 /* Enable port only if it was previously disabled */ 1596 if (!priv->mfunc.master.init_port_ref[port]) { 1597 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1598 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1599 if (err) 1600 return err; 1601 } 1602 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1603 } else { 1604 if (slave == mlx4_master_func_num(dev)) { 1605 if (check_qp0_state(dev, slave, port) && 1606 !priv->mfunc.master.qp0_state[port].port_active) { 1607 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1608 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1609 if (err) 1610 return err; 1611 priv->mfunc.master.qp0_state[port].port_active = 1; 1612 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1613 } 1614 } else 1615 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1616 } 1617 ++priv->mfunc.master.init_port_ref[port]; 1618 return 0; 1619 } 1620 1621 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 1622 { 1623 struct mlx4_cmd_mailbox *mailbox; 1624 u32 *inbox; 1625 int err; 1626 u32 flags; 1627 u16 field; 1628 1629 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1630 #define INIT_PORT_IN_SIZE 256 1631 #define INIT_PORT_FLAGS_OFFSET 0x00 1632 #define INIT_PORT_FLAG_SIG (1 << 18) 1633 #define INIT_PORT_FLAG_NG (1 << 17) 1634 #define INIT_PORT_FLAG_G0 (1 << 16) 1635 #define INIT_PORT_VL_SHIFT 4 1636 #define INIT_PORT_PORT_WIDTH_SHIFT 8 1637 #define INIT_PORT_MTU_OFFSET 0x04 1638 #define INIT_PORT_MAX_GID_OFFSET 0x06 1639 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 1640 #define INIT_PORT_GUID0_OFFSET 0x10 1641 #define INIT_PORT_NODE_GUID_OFFSET 0x18 1642 #define INIT_PORT_SI_GUID_OFFSET 0x20 1643 1644 mailbox = mlx4_alloc_cmd_mailbox(dev); 1645 if (IS_ERR(mailbox)) 1646 return PTR_ERR(mailbox); 1647 inbox = mailbox->buf; 1648 1649 flags = 0; 1650 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 1651 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 1652 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 1653 1654 field = 128 << dev->caps.ib_mtu_cap[port]; 1655 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 1656 field = dev->caps.gid_table_len[port]; 1657 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 1658 field = dev->caps.pkey_table_len[port]; 1659 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 1660 1661 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1662 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1663 1664 mlx4_free_cmd_mailbox(dev, mailbox); 1665 } else 1666 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1667 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1668 1669 return err; 1670 } 1671 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 1672 1673 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1674 struct mlx4_vhcr *vhcr, 1675 struct mlx4_cmd_mailbox *inbox, 1676 struct mlx4_cmd_mailbox *outbox, 1677 struct mlx4_cmd_info *cmd) 1678 { 1679 struct mlx4_priv *priv = mlx4_priv(dev); 1680 int port = vhcr->in_modifier; 1681 int err; 1682 1683 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 1684 (1 << port))) 1685 return 0; 1686 1687 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1688 if (priv->mfunc.master.init_port_ref[port] == 1) { 1689 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1690 1000, MLX4_CMD_NATIVE); 1691 if (err) 1692 return err; 1693 } 1694 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1695 } else { 1696 /* infiniband port */ 1697 if (slave == mlx4_master_func_num(dev)) { 1698 if (!priv->mfunc.master.qp0_state[port].qp0_active && 1699 priv->mfunc.master.qp0_state[port].port_active) { 1700 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1701 1000, MLX4_CMD_NATIVE); 1702 if (err) 1703 return err; 1704 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1705 priv->mfunc.master.qp0_state[port].port_active = 0; 1706 } 1707 } else 1708 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1709 } 1710 --priv->mfunc.master.init_port_ref[port]; 1711 return 0; 1712 } 1713 1714 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 1715 { 1716 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1717 MLX4_CMD_WRAPPED); 1718 } 1719 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 1720 1721 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 1722 { 1723 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 1724 MLX4_CMD_NATIVE); 1725 } 1726 1727 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 1728 { 1729 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 1730 MLX4_CMD_SET_ICM_SIZE, 1731 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1732 if (ret) 1733 return ret; 1734 1735 /* 1736 * Round up number of system pages needed in case 1737 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1738 */ 1739 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1740 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1741 1742 return 0; 1743 } 1744 1745 int mlx4_NOP(struct mlx4_dev *dev) 1746 { 1747 /* Input modifier of 0x1f means "finish as soon as possible." */ 1748 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 1749 } 1750 1751 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 1752 { 1753 u8 port; 1754 u32 *outbox; 1755 struct mlx4_cmd_mailbox *mailbox; 1756 u32 in_mod; 1757 u32 guid_hi, guid_lo; 1758 int err, ret = 0; 1759 #define MOD_STAT_CFG_PORT_OFFSET 8 1760 #define MOD_STAT_CFG_GUID_H 0X14 1761 #define MOD_STAT_CFG_GUID_L 0X1c 1762 1763 mailbox = mlx4_alloc_cmd_mailbox(dev); 1764 if (IS_ERR(mailbox)) 1765 return PTR_ERR(mailbox); 1766 outbox = mailbox->buf; 1767 1768 for (port = 1; port <= dev->caps.num_ports; port++) { 1769 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 1770 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 1771 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1772 MLX4_CMD_NATIVE); 1773 if (err) { 1774 mlx4_err(dev, "Fail to get port %d uplink guid\n", 1775 port); 1776 ret = err; 1777 } else { 1778 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 1779 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 1780 dev->caps.phys_port_id[port] = (u64)guid_lo | 1781 (u64)guid_hi << 32; 1782 } 1783 } 1784 mlx4_free_cmd_mailbox(dev, mailbox); 1785 return ret; 1786 } 1787 1788 #define MLX4_WOL_SETUP_MODE (5 << 28) 1789 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 1790 { 1791 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1792 1793 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 1794 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1795 MLX4_CMD_NATIVE); 1796 } 1797 EXPORT_SYMBOL_GPL(mlx4_wol_read); 1798 1799 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 1800 { 1801 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1802 1803 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 1804 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1805 } 1806 EXPORT_SYMBOL_GPL(mlx4_wol_write); 1807 1808 enum { 1809 ADD_TO_MCG = 0x26, 1810 }; 1811 1812 1813 void mlx4_opreq_action(struct work_struct *work) 1814 { 1815 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 1816 opreq_task); 1817 struct mlx4_dev *dev = &priv->dev; 1818 int num_tasks = atomic_read(&priv->opreq_count); 1819 struct mlx4_cmd_mailbox *mailbox; 1820 struct mlx4_mgm *mgm; 1821 u32 *outbox; 1822 u32 modifier; 1823 u16 token; 1824 u16 type; 1825 int err; 1826 u32 num_qps; 1827 struct mlx4_qp qp; 1828 int i; 1829 u8 rem_mcg; 1830 u8 prot; 1831 1832 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 1833 #define GET_OP_REQ_TOKEN_OFFSET 0x14 1834 #define GET_OP_REQ_TYPE_OFFSET 0x1a 1835 #define GET_OP_REQ_DATA_OFFSET 0x20 1836 1837 mailbox = mlx4_alloc_cmd_mailbox(dev); 1838 if (IS_ERR(mailbox)) { 1839 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 1840 return; 1841 } 1842 outbox = mailbox->buf; 1843 1844 while (num_tasks) { 1845 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1846 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 1847 MLX4_CMD_NATIVE); 1848 if (err) { 1849 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 1850 err); 1851 return; 1852 } 1853 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 1854 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 1855 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 1856 type &= 0xfff; 1857 1858 switch (type) { 1859 case ADD_TO_MCG: 1860 if (dev->caps.steering_mode == 1861 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1862 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 1863 err = EPERM; 1864 break; 1865 } 1866 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 1867 GET_OP_REQ_DATA_OFFSET); 1868 num_qps = be32_to_cpu(mgm->members_count) & 1869 MGM_QPN_MASK; 1870 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 1871 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 1872 1873 for (i = 0; i < num_qps; i++) { 1874 qp.qpn = be32_to_cpu(mgm->qp[i]); 1875 if (rem_mcg) 1876 err = mlx4_multicast_detach(dev, &qp, 1877 mgm->gid, 1878 prot, 0); 1879 else 1880 err = mlx4_multicast_attach(dev, &qp, 1881 mgm->gid, 1882 mgm->gid[5] 1883 , 0, prot, 1884 NULL); 1885 if (err) 1886 break; 1887 } 1888 break; 1889 default: 1890 mlx4_warn(dev, "Bad type for required operation\n"); 1891 err = EINVAL; 1892 break; 1893 } 1894 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16), 1895 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 1896 MLX4_CMD_NATIVE); 1897 if (err) { 1898 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 1899 err); 1900 goto out; 1901 } 1902 memset(outbox, 0, 0xffc); 1903 num_tasks = atomic_dec_return(&priv->opreq_count); 1904 } 1905 1906 out: 1907 mlx4_free_cmd_mailbox(dev, mailbox); 1908 } 1909