1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos = true; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 u64 val; \ 60 switch (sizeof (dest)) { \ 61 case 1: (dest) = *(u8 *) __p; break; \ 62 case 2: (dest) = be16_to_cpup(__p); break; \ 63 case 4: (dest) = be32_to_cpup(__p); break; \ 64 case 8: val = get_unaligned((u64 *)__p); \ 65 (dest) = be64_to_cpu(val); break; \ 66 default: __buggy_use_of_MLX4_GET(); \ 67 } \ 68 } while (0) 69 70 #define MLX4_PUT(dest, source, offset) \ 71 do { \ 72 void *__d = ((char *) (dest) + (offset)); \ 73 switch (sizeof(source)) { \ 74 case 1: *(u8 *) __d = (source); break; \ 75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 78 default: __buggy_use_of_MLX4_PUT(); \ 79 } \ 80 } while (0) 81 82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 83 { 84 static const char *fname[] = { 85 [ 0] = "RC transport", 86 [ 1] = "UC transport", 87 [ 2] = "UD transport", 88 [ 3] = "XRC transport", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [12] = "Dual Port Different Protocol (DPDP) support", 94 [15] = "Big LSO headers", 95 [16] = "MW support", 96 [17] = "APM support", 97 [18] = "Atomic ops support", 98 [19] = "Raw multicast support", 99 [20] = "Address vector port checking support", 100 [21] = "UD multicast support", 101 [30] = "IBoE support", 102 [32] = "Unicast loopback support", 103 [34] = "FCS header control", 104 [37] = "Wake On LAN (port1) support", 105 [38] = "Wake On LAN (port2) support", 106 [40] = "UDP RSS support", 107 [41] = "Unicast VEP steering support", 108 [42] = "Multicast VEP steering support", 109 [48] = "Counters support", 110 [52] = "RSS IP fragments support", 111 [53] = "Port ETS Scheduler support", 112 [55] = "Port link type sensing support", 113 [59] = "Port management change event support", 114 [61] = "64 byte EQE support", 115 [62] = "64 byte CQE support", 116 }; 117 int i; 118 119 mlx4_dbg(dev, "DEV_CAP flags:\n"); 120 for (i = 0; i < ARRAY_SIZE(fname); ++i) 121 if (fname[i] && (flags & (1LL << i))) 122 mlx4_dbg(dev, " %s\n", fname[i]); 123 } 124 125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 126 { 127 static const char * const fname[] = { 128 [0] = "RSS support", 129 [1] = "RSS Toeplitz Hash Function support", 130 [2] = "RSS XOR Hash Function support", 131 [3] = "Device managed flow steering support", 132 [4] = "Automatic MAC reassignment support", 133 [5] = "Time stamping support", 134 [6] = "VST (control vlan insertion/stripping) support", 135 [7] = "FSM (MAC anti-spoofing) support", 136 [8] = "Dynamic QP updates support", 137 [9] = "Device managed flow steering IPoIB support", 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 139 [11] = "MAD DEMUX (Secure-Host) support", 140 [12] = "Large cache line (>64B) CQE stride support", 141 [13] = "Large cache line (>64B) EQE stride support", 142 [14] = "Ethernet protocol control support", 143 [15] = "Ethernet Backplane autoneg support", 144 [16] = "CONFIG DEV support", 145 [17] = "Asymmetric EQs support", 146 [18] = "More than 80 VFs support", 147 [19] = "Performance optimized for limited rule configuration flow steering support", 148 [20] = "Recoverable error events support", 149 [21] = "Port Remap support", 150 [22] = "QCN support", 151 [23] = "QP rate limiting support", 152 [24] = "Ethernet Flow control statistics support", 153 [25] = "Granular QoS per VF support", 154 [26] = "Port ETS Scheduler support", 155 [27] = "Port beacon support", 156 [28] = "RX-ALL support", 157 [29] = "802.1ad offload support", 158 [31] = "Modifying loopback source checks using UPDATE_QP support", 159 [32] = "Loopback source checks support", 160 [33] = "RoCEv2 support" 161 }; 162 int i; 163 164 for (i = 0; i < ARRAY_SIZE(fname); ++i) 165 if (fname[i] && (flags & (1LL << i))) 166 mlx4_dbg(dev, " %s\n", fname[i]); 167 } 168 169 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 170 { 171 struct mlx4_cmd_mailbox *mailbox; 172 u32 *inbox; 173 int err = 0; 174 175 #define MOD_STAT_CFG_IN_SIZE 0x100 176 177 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 178 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 179 180 mailbox = mlx4_alloc_cmd_mailbox(dev); 181 if (IS_ERR(mailbox)) 182 return PTR_ERR(mailbox); 183 inbox = mailbox->buf; 184 185 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 186 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 187 188 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 189 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 190 191 mlx4_free_cmd_mailbox(dev, mailbox); 192 return err; 193 } 194 195 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 196 { 197 struct mlx4_cmd_mailbox *mailbox; 198 u32 *outbox; 199 u8 in_modifier; 200 u8 field; 201 u16 field16; 202 int err; 203 204 #define QUERY_FUNC_BUS_OFFSET 0x00 205 #define QUERY_FUNC_DEVICE_OFFSET 0x01 206 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 207 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 208 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 209 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 210 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 211 212 mailbox = mlx4_alloc_cmd_mailbox(dev); 213 if (IS_ERR(mailbox)) 214 return PTR_ERR(mailbox); 215 outbox = mailbox->buf; 216 217 in_modifier = slave; 218 219 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 220 MLX4_CMD_QUERY_FUNC, 221 MLX4_CMD_TIME_CLASS_A, 222 MLX4_CMD_NATIVE); 223 if (err) 224 goto out; 225 226 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 227 func->bus = field & 0xf; 228 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 229 func->device = field & 0xf1; 230 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 231 func->function = field & 0x7; 232 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 233 func->physical_function = field & 0xf; 234 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 235 func->rsvd_eqs = field16 & 0xffff; 236 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 237 func->max_eq = field16 & 0xffff; 238 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 239 func->rsvd_uars = field & 0x0f; 240 241 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 242 func->bus, func->device, func->function, func->physical_function, 243 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 244 245 out: 246 mlx4_free_cmd_mailbox(dev, mailbox); 247 return err; 248 } 249 250 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 251 struct mlx4_vhcr *vhcr, 252 struct mlx4_cmd_mailbox *inbox, 253 struct mlx4_cmd_mailbox *outbox, 254 struct mlx4_cmd_info *cmd) 255 { 256 struct mlx4_priv *priv = mlx4_priv(dev); 257 u8 field, port; 258 u32 size, proxy_qp, qkey; 259 int err = 0; 260 struct mlx4_func func; 261 262 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 263 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 264 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 265 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 266 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 267 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 268 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 269 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 270 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 271 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 272 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 273 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 274 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 275 276 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 277 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 278 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 279 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 280 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 281 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 282 283 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 284 285 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 286 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 287 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 288 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 289 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 290 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 291 292 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 293 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 294 295 /* when opcode modifier = 1 */ 296 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 297 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 298 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 299 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 300 301 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 302 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 303 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 304 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 305 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 306 307 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 308 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 309 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 310 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 311 312 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 313 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 314 #define QUERY_FUNC_CAP_PHV_BIT 0x40 315 316 if (vhcr->op_modifier == 1) { 317 struct mlx4_active_ports actv_ports = 318 mlx4_get_active_ports(dev, slave); 319 int converted_port = mlx4_slave_convert_port( 320 dev, slave, vhcr->in_modifier); 321 322 if (converted_port < 0) 323 return -EINVAL; 324 325 vhcr->in_modifier = converted_port; 326 /* phys-port = logical-port */ 327 field = vhcr->in_modifier - 328 find_first_bit(actv_ports.ports, dev->caps.num_ports); 329 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 330 331 port = vhcr->in_modifier; 332 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 333 334 /* Set nic_info bit to mark new fields support */ 335 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 336 337 if (mlx4_vf_smi_enabled(dev, slave, port) && 338 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 339 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 340 MLX4_PUT(outbox->buf, qkey, 341 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 342 } 343 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 344 345 /* size is now the QP number */ 346 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 347 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 348 349 size += 2; 350 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 351 352 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 353 proxy_qp += 2; 354 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 355 356 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 357 QUERY_FUNC_CAP_PHYS_PORT_ID); 358 359 if (dev->caps.phv_bit[port]) { 360 field = QUERY_FUNC_CAP_PHV_BIT; 361 MLX4_PUT(outbox->buf, field, 362 QUERY_FUNC_CAP_FLAGS0_OFFSET); 363 } 364 365 } else if (vhcr->op_modifier == 0) { 366 struct mlx4_active_ports actv_ports = 367 mlx4_get_active_ports(dev, slave); 368 /* enable rdma and ethernet interfaces, new quota locations, 369 * and reserved lkey 370 */ 371 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 372 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 373 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 374 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 375 376 field = min( 377 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 378 dev->caps.num_ports); 379 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 380 381 size = dev->caps.function_caps; /* set PF behaviours */ 382 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 383 384 field = 0; /* protected FMR support not available as yet */ 385 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 386 387 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 388 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 389 size = dev->caps.num_qps; 390 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 391 392 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 393 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 394 size = dev->caps.num_srqs; 395 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 396 397 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 398 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 399 size = dev->caps.num_cqs; 400 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 401 402 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 403 mlx4_QUERY_FUNC(dev, &func, slave)) { 404 size = vhcr->in_modifier & 405 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 406 dev->caps.num_eqs : 407 rounddown_pow_of_two(dev->caps.num_eqs); 408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 409 size = dev->caps.reserved_eqs; 410 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 411 } else { 412 size = vhcr->in_modifier & 413 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 414 func.max_eq : 415 rounddown_pow_of_two(func.max_eq); 416 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 417 size = func.rsvd_eqs; 418 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 419 } 420 421 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 422 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 423 size = dev->caps.num_mpts; 424 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 425 426 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 427 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 428 size = dev->caps.num_mtts; 429 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 430 431 size = dev->caps.num_mgms + dev->caps.num_amgms; 432 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 433 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 434 435 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 436 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 437 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 438 439 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 440 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 441 } else 442 err = -EINVAL; 443 444 return err; 445 } 446 447 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 448 struct mlx4_func_cap *func_cap) 449 { 450 struct mlx4_cmd_mailbox *mailbox; 451 u32 *outbox; 452 u8 field, op_modifier; 453 u32 size, qkey; 454 int err = 0, quotas = 0; 455 u32 in_modifier; 456 457 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 458 in_modifier = op_modifier ? gen_or_port : 459 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 460 461 mailbox = mlx4_alloc_cmd_mailbox(dev); 462 if (IS_ERR(mailbox)) 463 return PTR_ERR(mailbox); 464 465 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 466 MLX4_CMD_QUERY_FUNC_CAP, 467 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 468 if (err) 469 goto out; 470 471 outbox = mailbox->buf; 472 473 if (!op_modifier) { 474 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 475 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 476 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 477 err = -EPROTONOSUPPORT; 478 goto out; 479 } 480 func_cap->flags = field; 481 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 482 483 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 484 func_cap->num_ports = field; 485 486 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 487 func_cap->pf_context_behaviour = size; 488 489 if (quotas) { 490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 491 func_cap->qp_quota = size & 0xFFFFFF; 492 493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 494 func_cap->srq_quota = size & 0xFFFFFF; 495 496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 497 func_cap->cq_quota = size & 0xFFFFFF; 498 499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 500 func_cap->mpt_quota = size & 0xFFFFFF; 501 502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 503 func_cap->mtt_quota = size & 0xFFFFFF; 504 505 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 506 func_cap->mcg_quota = size & 0xFFFFFF; 507 508 } else { 509 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 510 func_cap->qp_quota = size & 0xFFFFFF; 511 512 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 513 func_cap->srq_quota = size & 0xFFFFFF; 514 515 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 516 func_cap->cq_quota = size & 0xFFFFFF; 517 518 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 519 func_cap->mpt_quota = size & 0xFFFFFF; 520 521 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 522 func_cap->mtt_quota = size & 0xFFFFFF; 523 524 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 525 func_cap->mcg_quota = size & 0xFFFFFF; 526 } 527 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 528 func_cap->max_eq = size & 0xFFFFFF; 529 530 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 531 func_cap->reserved_eq = size & 0xFFFFFF; 532 533 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 534 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 535 func_cap->reserved_lkey = size; 536 } else { 537 func_cap->reserved_lkey = 0; 538 } 539 540 func_cap->extra_flags = 0; 541 542 /* Mailbox data from 0x6c and onward should only be treated if 543 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 544 */ 545 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 546 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 547 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 548 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 549 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 550 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 551 } 552 553 goto out; 554 } 555 556 /* logical port query */ 557 if (gen_or_port > dev->caps.num_ports) { 558 err = -EINVAL; 559 goto out; 560 } 561 562 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 563 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 564 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 565 mlx4_err(dev, "VLAN is enforced on this port\n"); 566 err = -EPROTONOSUPPORT; 567 goto out; 568 } 569 570 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 571 mlx4_err(dev, "Force mac is enabled on this port\n"); 572 err = -EPROTONOSUPPORT; 573 goto out; 574 } 575 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 576 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 577 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 578 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 579 err = -EPROTONOSUPPORT; 580 goto out; 581 } 582 } 583 584 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 585 func_cap->physical_port = field; 586 if (func_cap->physical_port != gen_or_port) { 587 err = -ENOSYS; 588 goto out; 589 } 590 591 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 592 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 593 func_cap->qp0_qkey = qkey; 594 } else { 595 func_cap->qp0_qkey = 0; 596 } 597 598 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 599 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 600 601 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 602 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 603 604 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 605 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 606 607 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 608 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 609 610 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 611 MLX4_GET(func_cap->phys_port_id, outbox, 612 QUERY_FUNC_CAP_PHYS_PORT_ID); 613 614 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 615 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT); 616 617 /* All other resources are allocated by the master, but we still report 618 * 'num' and 'reserved' capabilities as follows: 619 * - num remains the maximum resource index 620 * - 'num - reserved' is the total available objects of a resource, but 621 * resource indices may be less than 'reserved' 622 * TODO: set per-resource quotas */ 623 624 out: 625 mlx4_free_cmd_mailbox(dev, mailbox); 626 627 return err; 628 } 629 630 static void disable_unsupported_roce_caps(void *buf); 631 632 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 633 { 634 struct mlx4_cmd_mailbox *mailbox; 635 u32 *outbox; 636 u8 field; 637 u32 field32, flags, ext_flags; 638 u16 size; 639 u16 stat_rate; 640 int err; 641 int i; 642 643 #define QUERY_DEV_CAP_OUT_SIZE 0x100 644 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 645 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 646 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 647 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 648 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 649 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 650 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 651 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 652 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 653 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 654 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 655 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 656 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 657 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 658 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 659 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 660 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 661 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 662 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 663 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 664 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 665 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 666 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 667 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 668 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 669 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 670 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 671 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 672 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 673 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 674 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 675 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 676 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 677 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 678 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 679 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 680 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 681 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 682 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 683 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 684 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 685 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 686 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 687 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 688 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 689 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 690 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 691 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 692 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 693 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 694 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 695 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 696 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 697 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 698 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 699 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 700 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 701 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 702 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 703 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 704 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 705 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 706 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 707 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 708 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 709 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 710 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 711 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 712 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 713 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 714 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 715 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 716 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 717 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 718 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 719 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 720 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 721 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 722 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 723 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 724 #define QUERY_DEV_CAP_VXLAN 0x9e 725 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 726 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 727 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 728 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 729 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 730 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 731 732 733 dev_cap->flags2 = 0; 734 mailbox = mlx4_alloc_cmd_mailbox(dev); 735 if (IS_ERR(mailbox)) 736 return PTR_ERR(mailbox); 737 outbox = mailbox->buf; 738 739 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 740 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 741 if (err) 742 goto out; 743 744 if (mlx4_is_mfunc(dev)) 745 disable_unsupported_roce_caps(outbox); 746 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 747 dev_cap->reserved_qps = 1 << (field & 0xf); 748 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 749 dev_cap->max_qps = 1 << (field & 0x1f); 750 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 751 dev_cap->reserved_srqs = 1 << (field >> 4); 752 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 753 dev_cap->max_srqs = 1 << (field & 0x1f); 754 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 755 dev_cap->max_cq_sz = 1 << field; 756 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 757 dev_cap->reserved_cqs = 1 << (field & 0xf); 758 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 759 dev_cap->max_cqs = 1 << (field & 0x1f); 760 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 761 dev_cap->max_mpts = 1 << (field & 0x3f); 762 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 763 dev_cap->reserved_eqs = 1 << (field & 0xf); 764 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 765 dev_cap->max_eqs = 1 << (field & 0xf); 766 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 767 dev_cap->reserved_mtts = 1 << (field >> 4); 768 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 769 dev_cap->max_mrw_sz = 1 << field; 770 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 771 dev_cap->reserved_mrws = 1 << (field & 0xf); 772 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 773 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 774 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 775 dev_cap->num_sys_eqs = size & 0xfff; 776 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 777 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 778 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 779 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 780 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 781 field &= 0x1f; 782 if (!field) 783 dev_cap->max_gso_sz = 0; 784 else 785 dev_cap->max_gso_sz = 1 << field; 786 787 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 788 if (field & 0x20) 789 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 790 if (field & 0x10) 791 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 792 field &= 0xf; 793 if (field) { 794 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 795 dev_cap->max_rss_tbl_sz = 1 << field; 796 } else 797 dev_cap->max_rss_tbl_sz = 0; 798 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 799 dev_cap->max_rdma_global = 1 << (field & 0x3f); 800 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 801 dev_cap->local_ca_ack_delay = field & 0x1f; 802 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 803 dev_cap->num_ports = field & 0xf; 804 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 805 dev_cap->max_msg_sz = 1 << (field & 0x1f); 806 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 807 if (field & 0x10) 808 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 809 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 810 if (field & 0x80) 811 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 812 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 813 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 814 if (field & 0x80) 815 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 816 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 817 if (field & 0x80) 818 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 819 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 820 dev_cap->fs_max_num_qp_per_entry = field; 821 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 822 if (field & 0x1) 823 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 824 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 825 dev_cap->stat_rate_support = stat_rate; 826 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 827 if (field & 0x80) 828 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 829 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 830 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 831 dev_cap->flags = flags | (u64)ext_flags << 32; 832 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 833 dev_cap->reserved_uars = field >> 4; 834 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 835 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 836 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 837 dev_cap->min_page_sz = 1 << field; 838 839 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 840 if (field & 0x80) { 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 842 dev_cap->bf_reg_size = 1 << (field & 0x1f); 843 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 844 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 845 field = 3; 846 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 847 } else { 848 dev_cap->bf_reg_size = 0; 849 } 850 851 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 852 dev_cap->max_sq_sg = field; 853 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 854 dev_cap->max_sq_desc_sz = size; 855 856 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 857 dev_cap->max_qp_per_mcg = 1 << field; 858 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 859 dev_cap->reserved_mgms = field & 0xf; 860 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 861 dev_cap->max_mcgs = 1 << field; 862 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 863 dev_cap->reserved_pds = field >> 4; 864 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 865 dev_cap->max_pds = 1 << (field & 0x3f); 866 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 867 dev_cap->reserved_xrcds = field >> 4; 868 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 869 dev_cap->max_xrcds = 1 << (field & 0x1f); 870 871 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 872 dev_cap->rdmarc_entry_sz = size; 873 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 874 dev_cap->qpc_entry_sz = size; 875 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 876 dev_cap->aux_entry_sz = size; 877 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 878 dev_cap->altc_entry_sz = size; 879 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 880 dev_cap->eqc_entry_sz = size; 881 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 882 dev_cap->cqc_entry_sz = size; 883 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 884 dev_cap->srq_entry_sz = size; 885 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 886 dev_cap->cmpt_entry_sz = size; 887 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 888 dev_cap->mtt_entry_sz = size; 889 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 890 dev_cap->dmpt_entry_sz = size; 891 892 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 893 dev_cap->max_srq_sz = 1 << field; 894 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 895 dev_cap->max_qp_sz = 1 << field; 896 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 897 dev_cap->resize_srq = field & 1; 898 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 899 dev_cap->max_rq_sg = field; 900 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 901 dev_cap->max_rq_desc_sz = size; 902 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 903 if (field & (1 << 4)) 904 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 905 if (field & (1 << 5)) 906 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 907 if (field & (1 << 6)) 908 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 909 if (field & (1 << 7)) 910 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 911 MLX4_GET(dev_cap->bmme_flags, outbox, 912 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 913 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2) 914 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2; 915 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 916 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 917 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 918 if (field & 0x20) 919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 920 if (field & (1 << 2)) 921 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 922 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); 923 if (field & 0x80) 924 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; 925 if (field & 0x40) 926 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; 927 928 MLX4_GET(dev_cap->reserved_lkey, outbox, 929 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 930 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 931 if (field32 & (1 << 0)) 932 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 933 if (field32 & (1 << 7)) 934 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 935 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 936 if (field & 1<<6) 937 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 938 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 939 if (field & 1<<3) 940 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 941 if (field & (1 << 5)) 942 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 943 MLX4_GET(dev_cap->max_icm_sz, outbox, 944 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 945 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 946 MLX4_GET(dev_cap->max_counters, outbox, 947 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 948 949 MLX4_GET(field32, outbox, 950 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 951 if (field32 & (1 << 0)) 952 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 953 954 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 955 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 956 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 957 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 958 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 959 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 960 961 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 962 dev_cap->rl_caps.num_rates = size; 963 if (dev_cap->rl_caps.num_rates) { 964 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 965 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 966 dev_cap->rl_caps.max_val = size & 0xfff; 967 dev_cap->rl_caps.max_unit = size >> 14; 968 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 969 dev_cap->rl_caps.min_val = size & 0xfff; 970 dev_cap->rl_caps.min_unit = size >> 14; 971 } 972 973 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 974 if (field32 & (1 << 16)) 975 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 976 if (field32 & (1 << 18)) 977 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; 978 if (field32 & (1 << 19)) 979 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; 980 if (field32 & (1 << 26)) 981 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 982 if (field32 & (1 << 20)) 983 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 984 if (field32 & (1 << 21)) 985 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 986 987 for (i = 1; i <= dev_cap->num_ports; i++) { 988 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 989 if (err) 990 goto out; 991 } 992 993 /* 994 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 995 * we can't use any EQs whose doorbell falls on that page, 996 * even if the EQ itself isn't reserved. 997 */ 998 if (dev_cap->num_sys_eqs == 0) 999 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 1000 dev_cap->reserved_eqs); 1001 else 1002 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 1003 1004 out: 1005 mlx4_free_cmd_mailbox(dev, mailbox); 1006 return err; 1007 } 1008 1009 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 1010 { 1011 if (dev_cap->bf_reg_size > 0) 1012 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 1013 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 1014 else 1015 mlx4_dbg(dev, "BlueFlame not available\n"); 1016 1017 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 1018 dev_cap->bmme_flags, dev_cap->reserved_lkey); 1019 mlx4_dbg(dev, "Max ICM size %lld MB\n", 1020 (unsigned long long) dev_cap->max_icm_sz >> 20); 1021 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1022 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 1023 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1024 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 1025 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1026 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 1027 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 1028 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 1029 dev_cap->eqc_entry_sz); 1030 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1031 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1032 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1033 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1034 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1035 dev_cap->max_pds, dev_cap->reserved_mgms); 1036 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1037 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1038 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1039 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1040 dev_cap->port_cap[1].max_port_width); 1041 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1042 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1043 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1044 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1045 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1046 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1047 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1048 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1049 dev_cap->dmfs_high_rate_qpn_base); 1050 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1051 dev_cap->dmfs_high_rate_qpn_range); 1052 1053 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1054 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1055 1056 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1057 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1058 rl_caps->min_unit, rl_caps->min_val); 1059 } 1060 1061 dump_dev_cap_flags(dev, dev_cap->flags); 1062 dump_dev_cap_flags2(dev, dev_cap->flags2); 1063 } 1064 1065 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1066 { 1067 struct mlx4_cmd_mailbox *mailbox; 1068 u32 *outbox; 1069 u8 field; 1070 u32 field32; 1071 int err; 1072 1073 mailbox = mlx4_alloc_cmd_mailbox(dev); 1074 if (IS_ERR(mailbox)) 1075 return PTR_ERR(mailbox); 1076 outbox = mailbox->buf; 1077 1078 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1079 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1080 MLX4_CMD_TIME_CLASS_A, 1081 MLX4_CMD_NATIVE); 1082 1083 if (err) 1084 goto out; 1085 1086 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1087 port_cap->max_vl = field >> 4; 1088 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1089 port_cap->ib_mtu = field >> 4; 1090 port_cap->max_port_width = field & 0xf; 1091 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1092 port_cap->max_gids = 1 << (field & 0xf); 1093 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1094 port_cap->max_pkeys = 1 << (field & 0xf); 1095 } else { 1096 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1097 #define QUERY_PORT_MTU_OFFSET 0x01 1098 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1099 #define QUERY_PORT_WIDTH_OFFSET 0x06 1100 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1101 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1102 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1103 #define QUERY_PORT_MAC_OFFSET 0x10 1104 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1105 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1106 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1107 1108 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1109 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1110 if (err) 1111 goto out; 1112 1113 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1114 port_cap->link_state = (field & 0x80) >> 7; 1115 port_cap->supported_port_types = field & 3; 1116 port_cap->suggested_type = (field >> 3) & 1; 1117 port_cap->default_sense = (field >> 4) & 1; 1118 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1119 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1120 port_cap->ib_mtu = field & 0xf; 1121 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1122 port_cap->max_port_width = field & 0xf; 1123 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1124 port_cap->max_gids = 1 << (field >> 4); 1125 port_cap->max_pkeys = 1 << (field & 0xf); 1126 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1127 port_cap->max_vl = field & 0xf; 1128 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1129 port_cap->log_max_macs = field & 0xf; 1130 port_cap->log_max_vlans = field >> 4; 1131 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1132 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1133 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1134 port_cap->trans_type = field32 >> 24; 1135 port_cap->vendor_oui = field32 & 0xffffff; 1136 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1137 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1138 } 1139 1140 out: 1141 mlx4_free_cmd_mailbox(dev, mailbox); 1142 return err; 1143 } 1144 1145 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1146 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1147 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1148 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1149 1150 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1151 struct mlx4_vhcr *vhcr, 1152 struct mlx4_cmd_mailbox *inbox, 1153 struct mlx4_cmd_mailbox *outbox, 1154 struct mlx4_cmd_info *cmd) 1155 { 1156 u64 flags; 1157 int err = 0; 1158 u8 field; 1159 u16 field16; 1160 u32 bmme_flags, field32; 1161 int real_port; 1162 int slave_port; 1163 int first_port; 1164 struct mlx4_active_ports actv_ports; 1165 1166 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1167 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1168 if (err) 1169 return err; 1170 1171 disable_unsupported_roce_caps(outbox->buf); 1172 /* add port mng change event capability and disable mw type 1 1173 * unconditionally to slaves 1174 */ 1175 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1176 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1177 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1178 actv_ports = mlx4_get_active_ports(dev, slave); 1179 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1180 for (slave_port = 0, real_port = first_port; 1181 real_port < first_port + 1182 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1183 ++real_port, ++slave_port) { 1184 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1185 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1186 else 1187 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1188 } 1189 for (; slave_port < dev->caps.num_ports; ++slave_port) 1190 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1191 1192 /* Not exposing RSS IP fragments to guests */ 1193 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1194 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1195 1196 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1197 field &= ~0x0F; 1198 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1199 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1200 1201 /* For guests, disable timestamp */ 1202 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1203 field &= 0x7f; 1204 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1205 1206 /* For guests, disable vxlan tunneling and QoS support */ 1207 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1208 field &= 0xd7; 1209 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1210 1211 /* For guests, disable port BEACON */ 1212 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1213 field &= 0x7f; 1214 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1215 1216 /* For guests, report Blueflame disabled */ 1217 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1218 field &= 0x7f; 1219 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1220 1221 /* For guests, disable mw type 2 and port remap*/ 1222 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1223 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1224 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1225 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1226 1227 /* turn off device-managed steering capability if not enabled */ 1228 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1229 MLX4_GET(field, outbox->buf, 1230 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1231 field &= 0x7f; 1232 MLX4_PUT(outbox->buf, field, 1233 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1234 } 1235 1236 /* turn off ipoib managed steering for guests */ 1237 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1238 field &= ~0x80; 1239 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1240 1241 /* turn off host side virt features (VST, FSM, etc) for guests */ 1242 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1243 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1244 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1245 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1246 1247 /* turn off QCN for guests */ 1248 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1249 field &= 0xfe; 1250 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1251 1252 /* turn off QP max-rate limiting for guests */ 1253 field16 = 0; 1254 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1255 1256 /* turn off QoS per VF support for guests */ 1257 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1258 field &= 0xef; 1259 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1260 1261 /* turn off ignore FCS feature for guests */ 1262 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1263 field &= 0xfb; 1264 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1265 1266 return 0; 1267 } 1268 1269 static void disable_unsupported_roce_caps(void *buf) 1270 { 1271 u32 flags; 1272 1273 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1274 flags &= ~(1UL << 31); 1275 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1276 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1277 flags &= ~(1UL << 24); 1278 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1279 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1280 flags &= ~(MLX4_FLAG_ROCE_V1_V2); 1281 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1282 } 1283 1284 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1285 struct mlx4_vhcr *vhcr, 1286 struct mlx4_cmd_mailbox *inbox, 1287 struct mlx4_cmd_mailbox *outbox, 1288 struct mlx4_cmd_info *cmd) 1289 { 1290 struct mlx4_priv *priv = mlx4_priv(dev); 1291 u64 def_mac; 1292 u8 port_type; 1293 u16 short_field; 1294 int err; 1295 int admin_link_state; 1296 int port = mlx4_slave_convert_port(dev, slave, 1297 vhcr->in_modifier & 0xFF); 1298 1299 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1300 #define MLX4_PORT_LINK_UP_MASK 0x80 1301 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1302 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1303 1304 if (port < 0) 1305 return -EINVAL; 1306 1307 /* Protect against untrusted guests: enforce that this is the 1308 * QUERY_PORT general query. 1309 */ 1310 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1311 return -EINVAL; 1312 1313 vhcr->in_modifier = port; 1314 1315 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1316 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1317 MLX4_CMD_NATIVE); 1318 1319 if (!err && dev->caps.function != slave) { 1320 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1321 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1322 1323 /* get port type - currently only eth is enabled */ 1324 MLX4_GET(port_type, outbox->buf, 1325 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1326 1327 /* No link sensing allowed */ 1328 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1329 /* set port type to currently operating port type */ 1330 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1331 1332 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1333 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1334 port_type |= MLX4_PORT_LINK_UP_MASK; 1335 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1336 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1337 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) { 1338 int other_port = (port == 1) ? 2 : 1; 1339 struct mlx4_port_cap port_cap; 1340 1341 err = mlx4_QUERY_PORT(dev, other_port, &port_cap); 1342 if (err) 1343 goto out; 1344 port_type |= (port_cap.link_state << 7); 1345 } 1346 1347 MLX4_PUT(outbox->buf, port_type, 1348 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1349 1350 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1351 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1352 else 1353 short_field = 1; /* slave max gids */ 1354 MLX4_PUT(outbox->buf, short_field, 1355 QUERY_PORT_CUR_MAX_GID_OFFSET); 1356 1357 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1358 MLX4_PUT(outbox->buf, short_field, 1359 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1360 } 1361 out: 1362 return err; 1363 } 1364 1365 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1366 int *gid_tbl_len, int *pkey_tbl_len) 1367 { 1368 struct mlx4_cmd_mailbox *mailbox; 1369 u32 *outbox; 1370 u16 field; 1371 int err; 1372 1373 mailbox = mlx4_alloc_cmd_mailbox(dev); 1374 if (IS_ERR(mailbox)) 1375 return PTR_ERR(mailbox); 1376 1377 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1378 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1379 MLX4_CMD_WRAPPED); 1380 if (err) 1381 goto out; 1382 1383 outbox = mailbox->buf; 1384 1385 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1386 *gid_tbl_len = field; 1387 1388 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1389 *pkey_tbl_len = field; 1390 1391 out: 1392 mlx4_free_cmd_mailbox(dev, mailbox); 1393 return err; 1394 } 1395 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1396 1397 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1398 { 1399 struct mlx4_cmd_mailbox *mailbox; 1400 struct mlx4_icm_iter iter; 1401 __be64 *pages; 1402 int lg; 1403 int nent = 0; 1404 int i; 1405 int err = 0; 1406 int ts = 0, tc = 0; 1407 1408 mailbox = mlx4_alloc_cmd_mailbox(dev); 1409 if (IS_ERR(mailbox)) 1410 return PTR_ERR(mailbox); 1411 pages = mailbox->buf; 1412 1413 for (mlx4_icm_first(icm, &iter); 1414 !mlx4_icm_last(&iter); 1415 mlx4_icm_next(&iter)) { 1416 /* 1417 * We have to pass pages that are aligned to their 1418 * size, so find the least significant 1 in the 1419 * address or size and use that as our log2 size. 1420 */ 1421 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1422 if (lg < MLX4_ICM_PAGE_SHIFT) { 1423 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1424 MLX4_ICM_PAGE_SIZE, 1425 (unsigned long long) mlx4_icm_addr(&iter), 1426 mlx4_icm_size(&iter)); 1427 err = -EINVAL; 1428 goto out; 1429 } 1430 1431 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1432 if (virt != -1) { 1433 pages[nent * 2] = cpu_to_be64(virt); 1434 virt += 1 << lg; 1435 } 1436 1437 pages[nent * 2 + 1] = 1438 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1439 (lg - MLX4_ICM_PAGE_SHIFT)); 1440 ts += 1 << (lg - 10); 1441 ++tc; 1442 1443 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1444 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1445 MLX4_CMD_TIME_CLASS_B, 1446 MLX4_CMD_NATIVE); 1447 if (err) 1448 goto out; 1449 nent = 0; 1450 } 1451 } 1452 } 1453 1454 if (nent) 1455 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1456 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1457 if (err) 1458 goto out; 1459 1460 switch (op) { 1461 case MLX4_CMD_MAP_FA: 1462 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1463 break; 1464 case MLX4_CMD_MAP_ICM_AUX: 1465 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1466 break; 1467 case MLX4_CMD_MAP_ICM: 1468 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1469 tc, ts, (unsigned long long) virt - (ts << 10)); 1470 break; 1471 } 1472 1473 out: 1474 mlx4_free_cmd_mailbox(dev, mailbox); 1475 return err; 1476 } 1477 1478 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1479 { 1480 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1481 } 1482 1483 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1484 { 1485 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1486 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1487 } 1488 1489 1490 int mlx4_RUN_FW(struct mlx4_dev *dev) 1491 { 1492 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1493 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1494 } 1495 1496 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1497 { 1498 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1499 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1500 struct mlx4_cmd_mailbox *mailbox; 1501 u32 *outbox; 1502 int err = 0; 1503 u64 fw_ver; 1504 u16 cmd_if_rev; 1505 u8 lg; 1506 1507 #define QUERY_FW_OUT_SIZE 0x100 1508 #define QUERY_FW_VER_OFFSET 0x00 1509 #define QUERY_FW_PPF_ID 0x09 1510 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1511 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1512 #define QUERY_FW_ERR_START_OFFSET 0x30 1513 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1514 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1515 1516 #define QUERY_FW_SIZE_OFFSET 0x00 1517 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1518 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1519 1520 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1521 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1522 1523 #define QUERY_FW_CLOCK_OFFSET 0x50 1524 #define QUERY_FW_CLOCK_BAR 0x58 1525 1526 mailbox = mlx4_alloc_cmd_mailbox(dev); 1527 if (IS_ERR(mailbox)) 1528 return PTR_ERR(mailbox); 1529 outbox = mailbox->buf; 1530 1531 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1532 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1533 if (err) 1534 goto out; 1535 1536 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1537 /* 1538 * FW subminor version is at more significant bits than minor 1539 * version, so swap here. 1540 */ 1541 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1542 ((fw_ver & 0xffff0000ull) >> 16) | 1543 ((fw_ver & 0x0000ffffull) << 16); 1544 1545 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1546 dev->caps.function = lg; 1547 1548 if (mlx4_is_slave(dev)) 1549 goto out; 1550 1551 1552 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1553 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1554 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1555 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1556 cmd_if_rev); 1557 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1558 (int) (dev->caps.fw_ver >> 32), 1559 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1560 (int) dev->caps.fw_ver & 0xffff); 1561 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1562 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1563 err = -ENODEV; 1564 goto out; 1565 } 1566 1567 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1568 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1569 1570 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1571 cmd->max_cmds = 1 << lg; 1572 1573 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1574 (int) (dev->caps.fw_ver >> 32), 1575 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1576 (int) dev->caps.fw_ver & 0xffff, 1577 cmd_if_rev, cmd->max_cmds); 1578 1579 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1580 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1581 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1582 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1583 1584 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1585 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1586 1587 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1588 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1589 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1590 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1591 1592 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1593 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1594 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1595 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1596 fw->comm_bar, fw->comm_base); 1597 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1598 1599 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1600 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1601 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1602 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1603 fw->clock_bar, fw->clock_offset); 1604 1605 /* 1606 * Round up number of system pages needed in case 1607 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1608 */ 1609 fw->fw_pages = 1610 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1611 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1612 1613 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1614 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1615 1616 out: 1617 mlx4_free_cmd_mailbox(dev, mailbox); 1618 return err; 1619 } 1620 1621 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1622 struct mlx4_vhcr *vhcr, 1623 struct mlx4_cmd_mailbox *inbox, 1624 struct mlx4_cmd_mailbox *outbox, 1625 struct mlx4_cmd_info *cmd) 1626 { 1627 u8 *outbuf; 1628 int err; 1629 1630 outbuf = outbox->buf; 1631 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1632 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1633 if (err) 1634 return err; 1635 1636 /* for slaves, set pci PPF ID to invalid and zero out everything 1637 * else except FW version */ 1638 outbuf[0] = outbuf[1] = 0; 1639 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1640 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1641 1642 return 0; 1643 } 1644 1645 static void get_board_id(void *vsd, char *board_id) 1646 { 1647 int i; 1648 1649 #define VSD_OFFSET_SIG1 0x00 1650 #define VSD_OFFSET_SIG2 0xde 1651 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1652 #define VSD_OFFSET_TS_BOARD_ID 0x20 1653 1654 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1655 1656 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1657 1658 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1659 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1660 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1661 } else { 1662 /* 1663 * The board ID is a string but the firmware byte 1664 * swaps each 4-byte word before passing it back to 1665 * us. Therefore we need to swab it before printing. 1666 */ 1667 u32 *bid_u32 = (u32 *)board_id; 1668 1669 for (i = 0; i < 4; ++i) { 1670 u32 *addr; 1671 u32 val; 1672 1673 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1674 val = get_unaligned(addr); 1675 val = swab32(val); 1676 put_unaligned(val, &bid_u32[i]); 1677 } 1678 } 1679 } 1680 1681 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1682 { 1683 struct mlx4_cmd_mailbox *mailbox; 1684 u32 *outbox; 1685 int err; 1686 1687 #define QUERY_ADAPTER_OUT_SIZE 0x100 1688 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1689 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1690 1691 mailbox = mlx4_alloc_cmd_mailbox(dev); 1692 if (IS_ERR(mailbox)) 1693 return PTR_ERR(mailbox); 1694 outbox = mailbox->buf; 1695 1696 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1697 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1698 if (err) 1699 goto out; 1700 1701 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1702 1703 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1704 adapter->board_id); 1705 1706 out: 1707 mlx4_free_cmd_mailbox(dev, mailbox); 1708 return err; 1709 } 1710 1711 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1712 { 1713 struct mlx4_cmd_mailbox *mailbox; 1714 __be32 *inbox; 1715 int err; 1716 static const u8 a0_dmfs_hw_steering[] = { 1717 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1718 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1719 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1720 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1721 }; 1722 1723 #define INIT_HCA_IN_SIZE 0x200 1724 #define INIT_HCA_VERSION_OFFSET 0x000 1725 #define INIT_HCA_VERSION 2 1726 #define INIT_HCA_VXLAN_OFFSET 0x0c 1727 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1728 #define INIT_HCA_FLAGS_OFFSET 0x014 1729 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1730 #define INIT_HCA_QPC_OFFSET 0x020 1731 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1732 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1733 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1734 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1735 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1736 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1737 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1738 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1739 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1740 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1741 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1742 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1743 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1744 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1745 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1746 #define INIT_HCA_MCAST_OFFSET 0x0c0 1747 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1748 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1749 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1750 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1751 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1752 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1753 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1754 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1755 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1756 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1757 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1758 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1759 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1760 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1761 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1762 #define INIT_HCA_TPT_OFFSET 0x0f0 1763 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1764 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1765 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1766 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1767 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1768 #define INIT_HCA_UAR_OFFSET 0x120 1769 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1770 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1771 1772 mailbox = mlx4_alloc_cmd_mailbox(dev); 1773 if (IS_ERR(mailbox)) 1774 return PTR_ERR(mailbox); 1775 inbox = mailbox->buf; 1776 1777 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1778 1779 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1780 (ilog2(cache_line_size()) - 4) << 5; 1781 1782 #if defined(__LITTLE_ENDIAN) 1783 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1784 #elif defined(__BIG_ENDIAN) 1785 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1786 #else 1787 #error Host endianness not defined 1788 #endif 1789 /* Check port for UD address vector: */ 1790 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1791 1792 /* Enable IPoIB checksumming if we can: */ 1793 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1794 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1795 1796 /* Enable QoS support if module parameter set */ 1797 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1798 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1799 1800 /* enable counters */ 1801 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1802 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1803 1804 /* Enable RSS spread to fragmented IP packets when supported */ 1805 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1806 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1807 1808 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1809 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1810 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1811 dev->caps.eqe_size = 64; 1812 dev->caps.eqe_factor = 1; 1813 } else { 1814 dev->caps.eqe_size = 32; 1815 dev->caps.eqe_factor = 0; 1816 } 1817 1818 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1819 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1820 dev->caps.cqe_size = 64; 1821 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1822 } else { 1823 dev->caps.cqe_size = 32; 1824 } 1825 1826 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1827 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1828 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1829 dev->caps.eqe_size = cache_line_size(); 1830 dev->caps.cqe_size = cache_line_size(); 1831 dev->caps.eqe_factor = 0; 1832 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1833 (ilog2(dev->caps.eqe_size) - 5)), 1834 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1835 1836 /* User still need to know to support CQE > 32B */ 1837 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1838 } 1839 1840 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1841 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1842 1843 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1844 1845 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1846 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1847 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1848 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1849 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1850 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1851 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1852 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1853 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1854 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1855 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1856 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1857 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1858 1859 /* steering attributes */ 1860 if (dev->caps.steering_mode == 1861 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1862 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1863 cpu_to_be32(1 << 1864 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1865 1866 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1867 MLX4_PUT(inbox, param->log_mc_entry_sz, 1868 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1869 MLX4_PUT(inbox, param->log_mc_table_sz, 1870 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1871 /* Enable Ethernet flow steering 1872 * with udp unicast and tcp unicast 1873 */ 1874 if (dev->caps.dmfs_high_steer_mode != 1875 MLX4_STEERING_DMFS_A0_STATIC) 1876 MLX4_PUT(inbox, 1877 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1878 INIT_HCA_FS_ETH_BITS_OFFSET); 1879 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1880 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1881 /* Enable IPoIB flow steering 1882 * with udp unicast and tcp unicast 1883 */ 1884 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1885 INIT_HCA_FS_IB_BITS_OFFSET); 1886 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1887 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1888 1889 if (dev->caps.dmfs_high_steer_mode != 1890 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1891 MLX4_PUT(inbox, 1892 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1893 << 6)), 1894 INIT_HCA_FS_A0_OFFSET); 1895 } else { 1896 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1897 MLX4_PUT(inbox, param->log_mc_entry_sz, 1898 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1899 MLX4_PUT(inbox, param->log_mc_hash_sz, 1900 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1901 MLX4_PUT(inbox, param->log_mc_table_sz, 1902 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1903 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1904 MLX4_PUT(inbox, (u8) (1 << 3), 1905 INIT_HCA_UC_STEERING_OFFSET); 1906 } 1907 1908 /* TPT attributes */ 1909 1910 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1911 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1912 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1913 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1914 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1915 1916 /* UAR attributes */ 1917 1918 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1919 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1920 1921 /* set parser VXLAN attributes */ 1922 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1923 u8 parser_params = 0; 1924 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1925 } 1926 1927 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1928 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 1929 1930 if (err) 1931 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1932 1933 mlx4_free_cmd_mailbox(dev, mailbox); 1934 return err; 1935 } 1936 1937 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1938 struct mlx4_init_hca_param *param) 1939 { 1940 struct mlx4_cmd_mailbox *mailbox; 1941 __be32 *outbox; 1942 u32 dword_field; 1943 int err; 1944 u8 byte_field; 1945 static const u8 a0_dmfs_query_hw_steering[] = { 1946 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1947 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1948 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1949 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1950 }; 1951 1952 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1953 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1954 1955 mailbox = mlx4_alloc_cmd_mailbox(dev); 1956 if (IS_ERR(mailbox)) 1957 return PTR_ERR(mailbox); 1958 outbox = mailbox->buf; 1959 1960 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1961 MLX4_CMD_QUERY_HCA, 1962 MLX4_CMD_TIME_CLASS_B, 1963 !mlx4_is_slave(dev)); 1964 if (err) 1965 goto out; 1966 1967 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1968 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1969 1970 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1971 1972 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1973 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1974 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1975 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1976 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1977 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1978 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1979 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1980 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1981 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1982 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1983 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1984 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1985 1986 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1987 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1988 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1989 } else { 1990 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1991 if (byte_field & 0x8) 1992 param->steering_mode = MLX4_STEERING_MODE_B0; 1993 else 1994 param->steering_mode = MLX4_STEERING_MODE_A0; 1995 } 1996 1997 if (dword_field & (1 << 13)) 1998 param->rss_ip_frags = 1; 1999 2000 /* steering attributes */ 2001 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 2002 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 2003 MLX4_GET(param->log_mc_entry_sz, outbox, 2004 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 2005 MLX4_GET(param->log_mc_table_sz, outbox, 2006 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 2007 MLX4_GET(byte_field, outbox, 2008 INIT_HCA_FS_A0_OFFSET); 2009 param->dmfs_high_steer_mode = 2010 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 2011 } else { 2012 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 2013 MLX4_GET(param->log_mc_entry_sz, outbox, 2014 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 2015 MLX4_GET(param->log_mc_hash_sz, outbox, 2016 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 2017 MLX4_GET(param->log_mc_table_sz, outbox, 2018 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 2019 } 2020 2021 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 2022 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 2023 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 2024 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 2025 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 2026 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 2027 2028 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 2029 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 2030 if (byte_field) { 2031 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 2032 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 2033 param->cqe_size = 1 << ((byte_field & 2034 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 2035 param->eqe_size = 1 << (((byte_field & 2036 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 2037 } 2038 2039 /* TPT attributes */ 2040 2041 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 2042 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 2043 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 2044 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 2045 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 2046 2047 /* UAR attributes */ 2048 2049 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2050 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 2051 2052 /* phv_check enable */ 2053 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); 2054 if (byte_field & 0x2) 2055 param->phv_check_en = 1; 2056 out: 2057 mlx4_free_cmd_mailbox(dev, mailbox); 2058 2059 return err; 2060 } 2061 2062 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2063 { 2064 struct mlx4_cmd_mailbox *mailbox; 2065 __be32 *outbox; 2066 int err; 2067 2068 mailbox = mlx4_alloc_cmd_mailbox(dev); 2069 if (IS_ERR(mailbox)) { 2070 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2071 return PTR_ERR(mailbox); 2072 } 2073 outbox = mailbox->buf; 2074 2075 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2076 MLX4_CMD_QUERY_HCA, 2077 MLX4_CMD_TIME_CLASS_B, 2078 !mlx4_is_slave(dev)); 2079 if (err) { 2080 mlx4_warn(dev, "hca_core_clock update failed\n"); 2081 goto out; 2082 } 2083 2084 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2085 2086 out: 2087 mlx4_free_cmd_mailbox(dev, mailbox); 2088 2089 return err; 2090 } 2091 2092 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2093 * and real QP0 are active, so that the paravirtualized QP0 is ready 2094 * to operate */ 2095 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2096 { 2097 struct mlx4_priv *priv = mlx4_priv(dev); 2098 /* irrelevant if not infiniband */ 2099 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2100 priv->mfunc.master.qp0_state[port].qp0_active) 2101 return 1; 2102 return 0; 2103 } 2104 2105 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2106 struct mlx4_vhcr *vhcr, 2107 struct mlx4_cmd_mailbox *inbox, 2108 struct mlx4_cmd_mailbox *outbox, 2109 struct mlx4_cmd_info *cmd) 2110 { 2111 struct mlx4_priv *priv = mlx4_priv(dev); 2112 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2113 int err; 2114 2115 if (port < 0) 2116 return -EINVAL; 2117 2118 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2119 return 0; 2120 2121 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2122 /* Enable port only if it was previously disabled */ 2123 if (!priv->mfunc.master.init_port_ref[port]) { 2124 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2125 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2126 if (err) 2127 return err; 2128 } 2129 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2130 } else { 2131 if (slave == mlx4_master_func_num(dev)) { 2132 if (check_qp0_state(dev, slave, port) && 2133 !priv->mfunc.master.qp0_state[port].port_active) { 2134 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2135 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2136 if (err) 2137 return err; 2138 priv->mfunc.master.qp0_state[port].port_active = 1; 2139 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2140 } 2141 } else 2142 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2143 } 2144 ++priv->mfunc.master.init_port_ref[port]; 2145 return 0; 2146 } 2147 2148 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2149 { 2150 struct mlx4_cmd_mailbox *mailbox; 2151 u32 *inbox; 2152 int err; 2153 u32 flags; 2154 u16 field; 2155 2156 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2157 #define INIT_PORT_IN_SIZE 256 2158 #define INIT_PORT_FLAGS_OFFSET 0x00 2159 #define INIT_PORT_FLAG_SIG (1 << 18) 2160 #define INIT_PORT_FLAG_NG (1 << 17) 2161 #define INIT_PORT_FLAG_G0 (1 << 16) 2162 #define INIT_PORT_VL_SHIFT 4 2163 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2164 #define INIT_PORT_MTU_OFFSET 0x04 2165 #define INIT_PORT_MAX_GID_OFFSET 0x06 2166 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2167 #define INIT_PORT_GUID0_OFFSET 0x10 2168 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2169 #define INIT_PORT_SI_GUID_OFFSET 0x20 2170 2171 mailbox = mlx4_alloc_cmd_mailbox(dev); 2172 if (IS_ERR(mailbox)) 2173 return PTR_ERR(mailbox); 2174 inbox = mailbox->buf; 2175 2176 flags = 0; 2177 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2178 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2179 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2180 2181 field = 128 << dev->caps.ib_mtu_cap[port]; 2182 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2183 field = dev->caps.gid_table_len[port]; 2184 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2185 field = dev->caps.pkey_table_len[port]; 2186 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2187 2188 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2189 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2190 2191 mlx4_free_cmd_mailbox(dev, mailbox); 2192 } else 2193 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2194 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2195 2196 if (!err) 2197 mlx4_hca_core_clock_update(dev); 2198 2199 return err; 2200 } 2201 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2202 2203 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2204 struct mlx4_vhcr *vhcr, 2205 struct mlx4_cmd_mailbox *inbox, 2206 struct mlx4_cmd_mailbox *outbox, 2207 struct mlx4_cmd_info *cmd) 2208 { 2209 struct mlx4_priv *priv = mlx4_priv(dev); 2210 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2211 int err; 2212 2213 if (port < 0) 2214 return -EINVAL; 2215 2216 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2217 (1 << port))) 2218 return 0; 2219 2220 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2221 if (priv->mfunc.master.init_port_ref[port] == 1) { 2222 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2223 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2224 if (err) 2225 return err; 2226 } 2227 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2228 } else { 2229 /* infiniband port */ 2230 if (slave == mlx4_master_func_num(dev)) { 2231 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2232 priv->mfunc.master.qp0_state[port].port_active) { 2233 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2234 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2235 if (err) 2236 return err; 2237 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2238 priv->mfunc.master.qp0_state[port].port_active = 0; 2239 } 2240 } else 2241 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2242 } 2243 --priv->mfunc.master.init_port_ref[port]; 2244 return 0; 2245 } 2246 2247 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2248 { 2249 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2250 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2251 } 2252 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2253 2254 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2255 { 2256 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2257 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2258 } 2259 2260 struct mlx4_config_dev { 2261 __be32 update_flags; 2262 __be32 rsvd1[3]; 2263 __be16 vxlan_udp_dport; 2264 __be16 rsvd2; 2265 __be16 roce_v2_entropy; 2266 __be16 roce_v2_udp_dport; 2267 __be32 roce_flags; 2268 __be32 rsvd4[25]; 2269 __be16 rsvd5; 2270 u8 rsvd6; 2271 u8 rx_checksum_val; 2272 }; 2273 2274 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2275 #define MLX4_ROCE_V2_UDP_DPORT BIT(3) 2276 #define MLX4_DISABLE_RX_PORT BIT(18) 2277 2278 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2279 { 2280 int err; 2281 struct mlx4_cmd_mailbox *mailbox; 2282 2283 mailbox = mlx4_alloc_cmd_mailbox(dev); 2284 if (IS_ERR(mailbox)) 2285 return PTR_ERR(mailbox); 2286 2287 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2288 2289 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2290 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2291 2292 mlx4_free_cmd_mailbox(dev, mailbox); 2293 return err; 2294 } 2295 2296 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2297 { 2298 int err; 2299 struct mlx4_cmd_mailbox *mailbox; 2300 2301 mailbox = mlx4_alloc_cmd_mailbox(dev); 2302 if (IS_ERR(mailbox)) 2303 return PTR_ERR(mailbox); 2304 2305 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2306 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2307 2308 if (!err) 2309 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2310 2311 mlx4_free_cmd_mailbox(dev, mailbox); 2312 return err; 2313 } 2314 2315 /* Conversion between the HW values and the actual functionality. 2316 * The value represented by the array index, 2317 * and the functionality determined by the flags. 2318 */ 2319 static const u8 config_dev_csum_flags[] = { 2320 [0] = 0, 2321 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2322 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2323 MLX4_RX_CSUM_MODE_L4, 2324 [3] = MLX4_RX_CSUM_MODE_L4 | 2325 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2326 MLX4_RX_CSUM_MODE_MULTI_VLAN 2327 }; 2328 2329 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2330 struct mlx4_config_dev_params *params) 2331 { 2332 struct mlx4_config_dev config_dev = {0}; 2333 int err; 2334 u8 csum_mask; 2335 2336 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2337 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2338 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2339 2340 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2341 return -ENOTSUPP; 2342 2343 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2344 if (err) 2345 return err; 2346 2347 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2348 CONFIG_DEV_RX_CSUM_MODE_MASK; 2349 2350 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2351 return -EINVAL; 2352 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2353 2354 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2355 CONFIG_DEV_RX_CSUM_MODE_MASK; 2356 2357 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2358 return -EINVAL; 2359 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2360 2361 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2362 2363 return 0; 2364 } 2365 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2366 2367 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2368 { 2369 struct mlx4_config_dev config_dev; 2370 2371 memset(&config_dev, 0, sizeof(config_dev)); 2372 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2373 config_dev.vxlan_udp_dport = udp_port; 2374 2375 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2376 } 2377 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2378 2379 #define CONFIG_DISABLE_RX_PORT BIT(15) 2380 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2381 { 2382 struct mlx4_config_dev config_dev; 2383 2384 memset(&config_dev, 0, sizeof(config_dev)); 2385 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2386 if (dis) 2387 config_dev.roce_flags = 2388 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2389 2390 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2391 } 2392 2393 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port) 2394 { 2395 struct mlx4_config_dev config_dev; 2396 2397 memset(&config_dev, 0, sizeof(config_dev)); 2398 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); 2399 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port); 2400 2401 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2402 } 2403 EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port); 2404 2405 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2406 { 2407 struct mlx4_cmd_mailbox *mailbox; 2408 struct { 2409 __be32 v_port1; 2410 __be32 v_port2; 2411 } *v2p; 2412 int err; 2413 2414 mailbox = mlx4_alloc_cmd_mailbox(dev); 2415 if (IS_ERR(mailbox)) 2416 return -ENOMEM; 2417 2418 v2p = mailbox->buf; 2419 v2p->v_port1 = cpu_to_be32(port1); 2420 v2p->v_port2 = cpu_to_be32(port2); 2421 2422 err = mlx4_cmd(dev, mailbox->dma, 0, 2423 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2424 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2425 2426 mlx4_free_cmd_mailbox(dev, mailbox); 2427 return err; 2428 } 2429 2430 2431 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2432 { 2433 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2434 MLX4_CMD_SET_ICM_SIZE, 2435 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2436 if (ret) 2437 return ret; 2438 2439 /* 2440 * Round up number of system pages needed in case 2441 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2442 */ 2443 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2444 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2445 2446 return 0; 2447 } 2448 2449 int mlx4_NOP(struct mlx4_dev *dev) 2450 { 2451 /* Input modifier of 0x1f means "finish as soon as possible." */ 2452 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2453 MLX4_CMD_NATIVE); 2454 } 2455 2456 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2457 { 2458 u8 port; 2459 u32 *outbox; 2460 struct mlx4_cmd_mailbox *mailbox; 2461 u32 in_mod; 2462 u32 guid_hi, guid_lo; 2463 int err, ret = 0; 2464 #define MOD_STAT_CFG_PORT_OFFSET 8 2465 #define MOD_STAT_CFG_GUID_H 0X14 2466 #define MOD_STAT_CFG_GUID_L 0X1c 2467 2468 mailbox = mlx4_alloc_cmd_mailbox(dev); 2469 if (IS_ERR(mailbox)) 2470 return PTR_ERR(mailbox); 2471 outbox = mailbox->buf; 2472 2473 for (port = 1; port <= dev->caps.num_ports; port++) { 2474 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2475 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2476 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2477 MLX4_CMD_NATIVE); 2478 if (err) { 2479 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2480 port); 2481 ret = err; 2482 } else { 2483 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2484 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2485 dev->caps.phys_port_id[port] = (u64)guid_lo | 2486 (u64)guid_hi << 32; 2487 } 2488 } 2489 mlx4_free_cmd_mailbox(dev, mailbox); 2490 return ret; 2491 } 2492 2493 #define MLX4_WOL_SETUP_MODE (5 << 28) 2494 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2495 { 2496 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2497 2498 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2499 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2500 MLX4_CMD_NATIVE); 2501 } 2502 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2503 2504 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2505 { 2506 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2507 2508 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2509 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2510 } 2511 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2512 2513 enum { 2514 ADD_TO_MCG = 0x26, 2515 }; 2516 2517 2518 void mlx4_opreq_action(struct work_struct *work) 2519 { 2520 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2521 opreq_task); 2522 struct mlx4_dev *dev = &priv->dev; 2523 int num_tasks = atomic_read(&priv->opreq_count); 2524 struct mlx4_cmd_mailbox *mailbox; 2525 struct mlx4_mgm *mgm; 2526 u32 *outbox; 2527 u32 modifier; 2528 u16 token; 2529 u16 type; 2530 int err; 2531 u32 num_qps; 2532 struct mlx4_qp qp; 2533 int i; 2534 u8 rem_mcg; 2535 u8 prot; 2536 2537 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2538 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2539 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2540 #define GET_OP_REQ_DATA_OFFSET 0x20 2541 2542 mailbox = mlx4_alloc_cmd_mailbox(dev); 2543 if (IS_ERR(mailbox)) { 2544 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2545 return; 2546 } 2547 outbox = mailbox->buf; 2548 2549 while (num_tasks) { 2550 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2551 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2552 MLX4_CMD_NATIVE); 2553 if (err) { 2554 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2555 err); 2556 return; 2557 } 2558 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2559 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2560 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2561 type &= 0xfff; 2562 2563 switch (type) { 2564 case ADD_TO_MCG: 2565 if (dev->caps.steering_mode == 2566 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2567 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2568 err = EPERM; 2569 break; 2570 } 2571 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2572 GET_OP_REQ_DATA_OFFSET); 2573 num_qps = be32_to_cpu(mgm->members_count) & 2574 MGM_QPN_MASK; 2575 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2576 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2577 2578 for (i = 0; i < num_qps; i++) { 2579 qp.qpn = be32_to_cpu(mgm->qp[i]); 2580 if (rem_mcg) 2581 err = mlx4_multicast_detach(dev, &qp, 2582 mgm->gid, 2583 prot, 0); 2584 else 2585 err = mlx4_multicast_attach(dev, &qp, 2586 mgm->gid, 2587 mgm->gid[5] 2588 , 0, prot, 2589 NULL); 2590 if (err) 2591 break; 2592 } 2593 break; 2594 default: 2595 mlx4_warn(dev, "Bad type for required operation\n"); 2596 err = EINVAL; 2597 break; 2598 } 2599 err = mlx4_cmd(dev, 0, ((u32) err | 2600 (__force u32)cpu_to_be32(token) << 16), 2601 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2602 MLX4_CMD_NATIVE); 2603 if (err) { 2604 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2605 err); 2606 goto out; 2607 } 2608 memset(outbox, 0, 0xffc); 2609 num_tasks = atomic_dec_return(&priv->opreq_count); 2610 } 2611 2612 out: 2613 mlx4_free_cmd_mailbox(dev, mailbox); 2614 } 2615 2616 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2617 struct mlx4_cmd_mailbox *mailbox) 2618 { 2619 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2620 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2621 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2622 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2623 2624 u32 set_attr_mask, getresp_attr_mask; 2625 u32 trap_attr_mask, traprepress_attr_mask; 2626 2627 MLX4_GET(set_attr_mask, mailbox->buf, 2628 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2629 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2630 set_attr_mask); 2631 2632 MLX4_GET(getresp_attr_mask, mailbox->buf, 2633 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2634 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2635 getresp_attr_mask); 2636 2637 MLX4_GET(trap_attr_mask, mailbox->buf, 2638 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2639 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2640 trap_attr_mask); 2641 2642 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2643 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2644 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2645 traprepress_attr_mask); 2646 2647 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2648 traprepress_attr_mask) 2649 return 1; 2650 2651 return 0; 2652 } 2653 2654 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2655 { 2656 struct mlx4_cmd_mailbox *mailbox; 2657 int secure_host_active; 2658 int err; 2659 2660 /* Check if mad_demux is supported */ 2661 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2662 return 0; 2663 2664 mailbox = mlx4_alloc_cmd_mailbox(dev); 2665 if (IS_ERR(mailbox)) { 2666 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2667 return -ENOMEM; 2668 } 2669 2670 /* Query mad_demux to find out which MADs are handled by internal sma */ 2671 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2672 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2673 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2674 if (err) { 2675 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2676 err); 2677 goto out; 2678 } 2679 2680 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2681 2682 /* Config mad_demux to handle all MADs returned by the query above */ 2683 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2684 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2685 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2686 if (err) { 2687 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2688 goto out; 2689 } 2690 2691 if (secure_host_active) 2692 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2693 out: 2694 mlx4_free_cmd_mailbox(dev, mailbox); 2695 return err; 2696 } 2697 2698 /* Access Reg commands */ 2699 enum mlx4_access_reg_masks { 2700 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2701 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2702 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2703 }; 2704 2705 struct mlx4_access_reg { 2706 __be16 constant1; 2707 u8 status; 2708 u8 resrvd1; 2709 __be16 reg_id; 2710 u8 method; 2711 u8 constant2; 2712 __be32 resrvd2[2]; 2713 __be16 len_const; 2714 __be16 resrvd3; 2715 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2716 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2717 } __attribute__((__packed__)); 2718 2719 /** 2720 * mlx4_ACCESS_REG - Generic access reg command. 2721 * @dev: mlx4_dev. 2722 * @reg_id: register ID to access. 2723 * @method: Access method Read/Write. 2724 * @reg_len: register length to Read/Write in bytes. 2725 * @reg_data: reg_data pointer to Read/Write From/To. 2726 * 2727 * Access ConnectX registers FW command. 2728 * Returns 0 on success and copies outbox mlx4_access_reg data 2729 * field into reg_data or a negative error code. 2730 */ 2731 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2732 enum mlx4_access_reg_method method, 2733 u16 reg_len, void *reg_data) 2734 { 2735 struct mlx4_cmd_mailbox *inbox, *outbox; 2736 struct mlx4_access_reg *inbuf, *outbuf; 2737 int err; 2738 2739 inbox = mlx4_alloc_cmd_mailbox(dev); 2740 if (IS_ERR(inbox)) 2741 return PTR_ERR(inbox); 2742 2743 outbox = mlx4_alloc_cmd_mailbox(dev); 2744 if (IS_ERR(outbox)) { 2745 mlx4_free_cmd_mailbox(dev, inbox); 2746 return PTR_ERR(outbox); 2747 } 2748 2749 inbuf = inbox->buf; 2750 outbuf = outbox->buf; 2751 2752 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2753 inbuf->constant2 = 0x1; 2754 inbuf->reg_id = cpu_to_be16(reg_id); 2755 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2756 2757 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2758 inbuf->len_const = 2759 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2760 ((0x3) << 12)); 2761 2762 memcpy(inbuf->reg_data, reg_data, reg_len); 2763 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2764 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2765 MLX4_CMD_WRAPPED); 2766 if (err) 2767 goto out; 2768 2769 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2770 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2771 mlx4_err(dev, 2772 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2773 reg_id, err); 2774 goto out; 2775 } 2776 2777 memcpy(reg_data, outbuf->reg_data, reg_len); 2778 out: 2779 mlx4_free_cmd_mailbox(dev, inbox); 2780 mlx4_free_cmd_mailbox(dev, outbox); 2781 return err; 2782 } 2783 2784 /* ConnectX registers IDs */ 2785 enum mlx4_reg_id { 2786 MLX4_REG_ID_PTYS = 0x5004, 2787 }; 2788 2789 /** 2790 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2791 * register 2792 * @dev: mlx4_dev. 2793 * @method: Access method Read/Write. 2794 * @ptys_reg: PTYS register data pointer. 2795 * 2796 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2797 * configuration 2798 * Returns 0 on success or a negative error code. 2799 */ 2800 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2801 enum mlx4_access_reg_method method, 2802 struct mlx4_ptys_reg *ptys_reg) 2803 { 2804 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2805 method, sizeof(*ptys_reg), ptys_reg); 2806 } 2807 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2808 2809 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2810 struct mlx4_vhcr *vhcr, 2811 struct mlx4_cmd_mailbox *inbox, 2812 struct mlx4_cmd_mailbox *outbox, 2813 struct mlx4_cmd_info *cmd) 2814 { 2815 struct mlx4_access_reg *inbuf = inbox->buf; 2816 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2817 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2818 2819 if (slave != mlx4_master_func_num(dev) && 2820 method == MLX4_ACCESS_REG_WRITE) 2821 return -EPERM; 2822 2823 if (reg_id == MLX4_REG_ID_PTYS) { 2824 struct mlx4_ptys_reg *ptys_reg = 2825 (struct mlx4_ptys_reg *)inbuf->reg_data; 2826 2827 ptys_reg->local_port = 2828 mlx4_slave_convert_port(dev, slave, 2829 ptys_reg->local_port); 2830 } 2831 2832 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2833 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2834 MLX4_CMD_NATIVE); 2835 } 2836 2837 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) 2838 { 2839 #define SET_PORT_GEN_PHV_VALID 0x10 2840 #define SET_PORT_GEN_PHV_EN 0x80 2841 2842 struct mlx4_cmd_mailbox *mailbox; 2843 struct mlx4_set_port_general_context *context; 2844 u32 in_mod; 2845 int err; 2846 2847 mailbox = mlx4_alloc_cmd_mailbox(dev); 2848 if (IS_ERR(mailbox)) 2849 return PTR_ERR(mailbox); 2850 context = mailbox->buf; 2851 2852 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; 2853 if (phv_bit) 2854 context->phv_en |= SET_PORT_GEN_PHV_EN; 2855 2856 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 2857 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 2858 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 2859 MLX4_CMD_NATIVE); 2860 2861 mlx4_free_cmd_mailbox(dev, mailbox); 2862 return err; 2863 } 2864 2865 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) 2866 { 2867 int err; 2868 struct mlx4_func_cap func_cap; 2869 2870 memset(&func_cap, 0, sizeof(func_cap)); 2871 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 2872 if (!err) 2873 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT; 2874 return err; 2875 } 2876 EXPORT_SYMBOL(get_phv_bit); 2877 2878 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 2879 { 2880 int ret; 2881 2882 if (mlx4_is_slave(dev)) 2883 return -EPERM; 2884 2885 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && 2886 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { 2887 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); 2888 if (!ret) 2889 dev->caps.phv_bit[port] = new_val; 2890 return ret; 2891 } 2892 2893 return -EOPNOTSUPP; 2894 } 2895 EXPORT_SYMBOL(set_phv_bit); 2896 2897 void mlx4_replace_zero_macs(struct mlx4_dev *dev) 2898 { 2899 int i; 2900 u8 mac_addr[ETH_ALEN]; 2901 2902 dev->port_random_macs = 0; 2903 for (i = 1; i <= dev->caps.num_ports; ++i) 2904 if (!dev->caps.def_mac[i] && 2905 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { 2906 eth_random_addr(mac_addr); 2907 dev->port_random_macs |= 1 << i; 2908 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); 2909 } 2910 } 2911 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); 2912