1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos = true; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 u64 val; \ 60 switch (sizeof (dest)) { \ 61 case 1: (dest) = *(u8 *) __p; break; \ 62 case 2: (dest) = be16_to_cpup(__p); break; \ 63 case 4: (dest) = be32_to_cpup(__p); break; \ 64 case 8: val = get_unaligned((u64 *)__p); \ 65 (dest) = be64_to_cpu(val); break; \ 66 default: __buggy_use_of_MLX4_GET(); \ 67 } \ 68 } while (0) 69 70 #define MLX4_PUT(dest, source, offset) \ 71 do { \ 72 void *__d = ((char *) (dest) + (offset)); \ 73 switch (sizeof(source)) { \ 74 case 1: *(u8 *) __d = (source); break; \ 75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 78 default: __buggy_use_of_MLX4_PUT(); \ 79 } \ 80 } while (0) 81 82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 83 { 84 static const char *fname[] = { 85 [ 0] = "RC transport", 86 [ 1] = "UC transport", 87 [ 2] = "UD transport", 88 [ 3] = "XRC transport", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [12] = "Dual Port Different Protocol (DPDP) support", 94 [15] = "Big LSO headers", 95 [16] = "MW support", 96 [17] = "APM support", 97 [18] = "Atomic ops support", 98 [19] = "Raw multicast support", 99 [20] = "Address vector port checking support", 100 [21] = "UD multicast support", 101 [30] = "IBoE support", 102 [32] = "Unicast loopback support", 103 [34] = "FCS header control", 104 [37] = "Wake On LAN (port1) support", 105 [38] = "Wake On LAN (port2) support", 106 [40] = "UDP RSS support", 107 [41] = "Unicast VEP steering support", 108 [42] = "Multicast VEP steering support", 109 [48] = "Counters support", 110 [52] = "RSS IP fragments support", 111 [53] = "Port ETS Scheduler support", 112 [55] = "Port link type sensing support", 113 [59] = "Port management change event support", 114 [61] = "64 byte EQE support", 115 [62] = "64 byte CQE support", 116 }; 117 int i; 118 119 mlx4_dbg(dev, "DEV_CAP flags:\n"); 120 for (i = 0; i < ARRAY_SIZE(fname); ++i) 121 if (fname[i] && (flags & (1LL << i))) 122 mlx4_dbg(dev, " %s\n", fname[i]); 123 } 124 125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 126 { 127 static const char * const fname[] = { 128 [0] = "RSS support", 129 [1] = "RSS Toeplitz Hash Function support", 130 [2] = "RSS XOR Hash Function support", 131 [3] = "Device managed flow steering support", 132 [4] = "Automatic MAC reassignment support", 133 [5] = "Time stamping support", 134 [6] = "VST (control vlan insertion/stripping) support", 135 [7] = "FSM (MAC anti-spoofing) support", 136 [8] = "Dynamic QP updates support", 137 [9] = "Device managed flow steering IPoIB support", 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 139 [11] = "MAD DEMUX (Secure-Host) support", 140 [12] = "Large cache line (>64B) CQE stride support", 141 [13] = "Large cache line (>64B) EQE stride support", 142 [14] = "Ethernet protocol control support", 143 [15] = "Ethernet Backplane autoneg support", 144 [16] = "CONFIG DEV support", 145 [17] = "Asymmetric EQs support", 146 [18] = "More than 80 VFs support", 147 [19] = "Performance optimized for limited rule configuration flow steering support", 148 [20] = "Recoverable error events support", 149 [21] = "Port Remap support", 150 [22] = "QCN support", 151 [23] = "QP rate limiting support", 152 [24] = "Ethernet Flow control statistics support", 153 [25] = "Granular QoS per VF support", 154 [26] = "Port ETS Scheduler support", 155 [27] = "Port beacon support", 156 [28] = "RX-ALL support", 157 [29] = "802.1ad offload support", 158 [31] = "Modifying loopback source checks using UPDATE_QP support", 159 [32] = "Loopback source checks support", 160 }; 161 int i; 162 163 for (i = 0; i < ARRAY_SIZE(fname); ++i) 164 if (fname[i] && (flags & (1LL << i))) 165 mlx4_dbg(dev, " %s\n", fname[i]); 166 } 167 168 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 169 { 170 struct mlx4_cmd_mailbox *mailbox; 171 u32 *inbox; 172 int err = 0; 173 174 #define MOD_STAT_CFG_IN_SIZE 0x100 175 176 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 177 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 178 179 mailbox = mlx4_alloc_cmd_mailbox(dev); 180 if (IS_ERR(mailbox)) 181 return PTR_ERR(mailbox); 182 inbox = mailbox->buf; 183 184 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 185 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 186 187 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 188 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 195 { 196 struct mlx4_cmd_mailbox *mailbox; 197 u32 *outbox; 198 u8 in_modifier; 199 u8 field; 200 u16 field16; 201 int err; 202 203 #define QUERY_FUNC_BUS_OFFSET 0x00 204 #define QUERY_FUNC_DEVICE_OFFSET 0x01 205 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 206 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 207 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 208 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 209 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return PTR_ERR(mailbox); 214 outbox = mailbox->buf; 215 216 in_modifier = slave; 217 218 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 219 MLX4_CMD_QUERY_FUNC, 220 MLX4_CMD_TIME_CLASS_A, 221 MLX4_CMD_NATIVE); 222 if (err) 223 goto out; 224 225 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 226 func->bus = field & 0xf; 227 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 228 func->device = field & 0xf1; 229 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 230 func->function = field & 0x7; 231 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 232 func->physical_function = field & 0xf; 233 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 234 func->rsvd_eqs = field16 & 0xffff; 235 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 236 func->max_eq = field16 & 0xffff; 237 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 238 func->rsvd_uars = field & 0x0f; 239 240 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 241 func->bus, func->device, func->function, func->physical_function, 242 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 243 244 out: 245 mlx4_free_cmd_mailbox(dev, mailbox); 246 return err; 247 } 248 249 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 250 struct mlx4_vhcr *vhcr, 251 struct mlx4_cmd_mailbox *inbox, 252 struct mlx4_cmd_mailbox *outbox, 253 struct mlx4_cmd_info *cmd) 254 { 255 struct mlx4_priv *priv = mlx4_priv(dev); 256 u8 field, port; 257 u32 size, proxy_qp, qkey; 258 int err = 0; 259 struct mlx4_func func; 260 261 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 262 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 263 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 264 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 265 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 266 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 267 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 268 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 269 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 270 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 271 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 272 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 273 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 274 275 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 276 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 277 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 278 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 279 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 280 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 281 282 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 283 284 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 285 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 286 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 287 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 288 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 289 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 290 291 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 292 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 293 294 /* when opcode modifier = 1 */ 295 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 296 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 297 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 298 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 299 300 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 301 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 302 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 303 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 304 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 305 306 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 307 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 308 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 309 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 310 311 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 312 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 313 #define QUERY_FUNC_CAP_PHV_BIT 0x40 314 315 if (vhcr->op_modifier == 1) { 316 struct mlx4_active_ports actv_ports = 317 mlx4_get_active_ports(dev, slave); 318 int converted_port = mlx4_slave_convert_port( 319 dev, slave, vhcr->in_modifier); 320 321 if (converted_port < 0) 322 return -EINVAL; 323 324 vhcr->in_modifier = converted_port; 325 /* phys-port = logical-port */ 326 field = vhcr->in_modifier - 327 find_first_bit(actv_ports.ports, dev->caps.num_ports); 328 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 329 330 port = vhcr->in_modifier; 331 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 332 333 /* Set nic_info bit to mark new fields support */ 334 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 335 336 if (mlx4_vf_smi_enabled(dev, slave, port) && 337 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 338 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 339 MLX4_PUT(outbox->buf, qkey, 340 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 341 } 342 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 343 344 /* size is now the QP number */ 345 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 346 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 347 348 size += 2; 349 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 350 351 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 352 proxy_qp += 2; 353 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 354 355 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 356 QUERY_FUNC_CAP_PHYS_PORT_ID); 357 358 if (dev->caps.phv_bit[port]) { 359 field = QUERY_FUNC_CAP_PHV_BIT; 360 MLX4_PUT(outbox->buf, field, 361 QUERY_FUNC_CAP_FLAGS0_OFFSET); 362 } 363 364 } else if (vhcr->op_modifier == 0) { 365 struct mlx4_active_ports actv_ports = 366 mlx4_get_active_ports(dev, slave); 367 /* enable rdma and ethernet interfaces, new quota locations, 368 * and reserved lkey 369 */ 370 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 371 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 372 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 373 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 374 375 field = min( 376 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 377 dev->caps.num_ports); 378 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 379 380 size = dev->caps.function_caps; /* set PF behaviours */ 381 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 382 383 field = 0; /* protected FMR support not available as yet */ 384 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 385 386 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 388 size = dev->caps.num_qps; 389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 390 391 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 392 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 393 size = dev->caps.num_srqs; 394 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 395 396 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 398 size = dev->caps.num_cqs; 399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 400 401 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 402 mlx4_QUERY_FUNC(dev, &func, slave)) { 403 size = vhcr->in_modifier & 404 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 405 dev->caps.num_eqs : 406 rounddown_pow_of_two(dev->caps.num_eqs); 407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 408 size = dev->caps.reserved_eqs; 409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 410 } else { 411 size = vhcr->in_modifier & 412 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 413 func.max_eq : 414 rounddown_pow_of_two(func.max_eq); 415 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 416 size = func.rsvd_eqs; 417 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 418 } 419 420 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 421 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 422 size = dev->caps.num_mpts; 423 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 424 425 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 427 size = dev->caps.num_mtts; 428 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 429 430 size = dev->caps.num_mgms + dev->caps.num_amgms; 431 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 432 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 433 434 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 435 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 436 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 437 438 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 439 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 440 } else 441 err = -EINVAL; 442 443 return err; 444 } 445 446 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 447 struct mlx4_func_cap *func_cap) 448 { 449 struct mlx4_cmd_mailbox *mailbox; 450 u32 *outbox; 451 u8 field, op_modifier; 452 u32 size, qkey; 453 int err = 0, quotas = 0; 454 u32 in_modifier; 455 456 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 457 in_modifier = op_modifier ? gen_or_port : 458 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 459 460 mailbox = mlx4_alloc_cmd_mailbox(dev); 461 if (IS_ERR(mailbox)) 462 return PTR_ERR(mailbox); 463 464 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 465 MLX4_CMD_QUERY_FUNC_CAP, 466 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 467 if (err) 468 goto out; 469 470 outbox = mailbox->buf; 471 472 if (!op_modifier) { 473 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 474 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 475 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 476 err = -EPROTONOSUPPORT; 477 goto out; 478 } 479 func_cap->flags = field; 480 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 481 482 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 483 func_cap->num_ports = field; 484 485 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 486 func_cap->pf_context_behaviour = size; 487 488 if (quotas) { 489 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 490 func_cap->qp_quota = size & 0xFFFFFF; 491 492 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 493 func_cap->srq_quota = size & 0xFFFFFF; 494 495 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 496 func_cap->cq_quota = size & 0xFFFFFF; 497 498 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 499 func_cap->mpt_quota = size & 0xFFFFFF; 500 501 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 502 func_cap->mtt_quota = size & 0xFFFFFF; 503 504 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 505 func_cap->mcg_quota = size & 0xFFFFFF; 506 507 } else { 508 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 509 func_cap->qp_quota = size & 0xFFFFFF; 510 511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 512 func_cap->srq_quota = size & 0xFFFFFF; 513 514 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 515 func_cap->cq_quota = size & 0xFFFFFF; 516 517 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 518 func_cap->mpt_quota = size & 0xFFFFFF; 519 520 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 521 func_cap->mtt_quota = size & 0xFFFFFF; 522 523 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 524 func_cap->mcg_quota = size & 0xFFFFFF; 525 } 526 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 527 func_cap->max_eq = size & 0xFFFFFF; 528 529 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 530 func_cap->reserved_eq = size & 0xFFFFFF; 531 532 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 533 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 534 func_cap->reserved_lkey = size; 535 } else { 536 func_cap->reserved_lkey = 0; 537 } 538 539 func_cap->extra_flags = 0; 540 541 /* Mailbox data from 0x6c and onward should only be treated if 542 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 543 */ 544 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 545 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 546 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 547 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 548 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 549 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 550 } 551 552 goto out; 553 } 554 555 /* logical port query */ 556 if (gen_or_port > dev->caps.num_ports) { 557 err = -EINVAL; 558 goto out; 559 } 560 561 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 562 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 563 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 564 mlx4_err(dev, "VLAN is enforced on this port\n"); 565 err = -EPROTONOSUPPORT; 566 goto out; 567 } 568 569 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 570 mlx4_err(dev, "Force mac is enabled on this port\n"); 571 err = -EPROTONOSUPPORT; 572 goto out; 573 } 574 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 575 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 576 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 577 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 578 err = -EPROTONOSUPPORT; 579 goto out; 580 } 581 } 582 583 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 584 func_cap->physical_port = field; 585 if (func_cap->physical_port != gen_or_port) { 586 err = -ENOSYS; 587 goto out; 588 } 589 590 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 591 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 592 func_cap->qp0_qkey = qkey; 593 } else { 594 func_cap->qp0_qkey = 0; 595 } 596 597 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 598 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 599 600 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 601 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 602 603 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 604 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 605 606 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 607 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 608 609 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 610 MLX4_GET(func_cap->phys_port_id, outbox, 611 QUERY_FUNC_CAP_PHYS_PORT_ID); 612 613 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 614 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT); 615 616 /* All other resources are allocated by the master, but we still report 617 * 'num' and 'reserved' capabilities as follows: 618 * - num remains the maximum resource index 619 * - 'num - reserved' is the total available objects of a resource, but 620 * resource indices may be less than 'reserved' 621 * TODO: set per-resource quotas */ 622 623 out: 624 mlx4_free_cmd_mailbox(dev, mailbox); 625 626 return err; 627 } 628 629 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 630 { 631 struct mlx4_cmd_mailbox *mailbox; 632 u32 *outbox; 633 u8 field; 634 u32 field32, flags, ext_flags; 635 u16 size; 636 u16 stat_rate; 637 int err; 638 int i; 639 640 #define QUERY_DEV_CAP_OUT_SIZE 0x100 641 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 642 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 643 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 644 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 645 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 646 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 647 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 648 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 649 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 650 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 651 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 652 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 653 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 654 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 655 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 656 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 657 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 658 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 659 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 660 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 661 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 662 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 663 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 664 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 665 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 666 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 667 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 668 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 669 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 670 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 671 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 672 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 673 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 674 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 675 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 676 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 677 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 678 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 679 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 680 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 681 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 682 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 683 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 684 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 685 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 686 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 687 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 688 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 689 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 690 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 691 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 692 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 693 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 694 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 695 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 696 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 697 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 698 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 699 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 700 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 701 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 702 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 703 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 704 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 705 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 706 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 707 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 708 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 709 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 710 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 711 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 712 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 713 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 714 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 715 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 716 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 717 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 718 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 719 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 720 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 721 #define QUERY_DEV_CAP_VXLAN 0x9e 722 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 723 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 724 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 725 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 726 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 727 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 728 729 730 dev_cap->flags2 = 0; 731 mailbox = mlx4_alloc_cmd_mailbox(dev); 732 if (IS_ERR(mailbox)) 733 return PTR_ERR(mailbox); 734 outbox = mailbox->buf; 735 736 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 737 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 738 if (err) 739 goto out; 740 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 742 dev_cap->reserved_qps = 1 << (field & 0xf); 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 744 dev_cap->max_qps = 1 << (field & 0x1f); 745 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 746 dev_cap->reserved_srqs = 1 << (field >> 4); 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 748 dev_cap->max_srqs = 1 << (field & 0x1f); 749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 750 dev_cap->max_cq_sz = 1 << field; 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 752 dev_cap->reserved_cqs = 1 << (field & 0xf); 753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 754 dev_cap->max_cqs = 1 << (field & 0x1f); 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 756 dev_cap->max_mpts = 1 << (field & 0x3f); 757 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 758 dev_cap->reserved_eqs = 1 << (field & 0xf); 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 760 dev_cap->max_eqs = 1 << (field & 0xf); 761 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 762 dev_cap->reserved_mtts = 1 << (field >> 4); 763 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 764 dev_cap->max_mrw_sz = 1 << field; 765 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 766 dev_cap->reserved_mrws = 1 << (field & 0xf); 767 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 768 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 769 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 770 dev_cap->num_sys_eqs = size & 0xfff; 771 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 772 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 773 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 774 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 775 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 776 field &= 0x1f; 777 if (!field) 778 dev_cap->max_gso_sz = 0; 779 else 780 dev_cap->max_gso_sz = 1 << field; 781 782 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 783 if (field & 0x20) 784 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 785 if (field & 0x10) 786 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 787 field &= 0xf; 788 if (field) { 789 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 790 dev_cap->max_rss_tbl_sz = 1 << field; 791 } else 792 dev_cap->max_rss_tbl_sz = 0; 793 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 794 dev_cap->max_rdma_global = 1 << (field & 0x3f); 795 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 796 dev_cap->local_ca_ack_delay = field & 0x1f; 797 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 798 dev_cap->num_ports = field & 0xf; 799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 800 dev_cap->max_msg_sz = 1 << (field & 0x1f); 801 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 802 if (field & 0x10) 803 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 804 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 805 if (field & 0x80) 806 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 807 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 808 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 809 if (field & 0x80) 810 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 812 if (field & 0x80) 813 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 814 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 815 dev_cap->fs_max_num_qp_per_entry = field; 816 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 817 if (field & 0x1) 818 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 819 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 820 dev_cap->stat_rate_support = stat_rate; 821 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 822 if (field & 0x80) 823 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 824 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 825 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 826 dev_cap->flags = flags | (u64)ext_flags << 32; 827 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 828 dev_cap->reserved_uars = field >> 4; 829 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 830 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 831 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 832 dev_cap->min_page_sz = 1 << field; 833 834 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 835 if (field & 0x80) { 836 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 837 dev_cap->bf_reg_size = 1 << (field & 0x1f); 838 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 839 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 840 field = 3; 841 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 842 } else { 843 dev_cap->bf_reg_size = 0; 844 } 845 846 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 847 dev_cap->max_sq_sg = field; 848 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 849 dev_cap->max_sq_desc_sz = size; 850 851 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 852 dev_cap->max_qp_per_mcg = 1 << field; 853 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 854 dev_cap->reserved_mgms = field & 0xf; 855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 856 dev_cap->max_mcgs = 1 << field; 857 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 858 dev_cap->reserved_pds = field >> 4; 859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 860 dev_cap->max_pds = 1 << (field & 0x3f); 861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 862 dev_cap->reserved_xrcds = field >> 4; 863 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 864 dev_cap->max_xrcds = 1 << (field & 0x1f); 865 866 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 867 dev_cap->rdmarc_entry_sz = size; 868 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 869 dev_cap->qpc_entry_sz = size; 870 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 871 dev_cap->aux_entry_sz = size; 872 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 873 dev_cap->altc_entry_sz = size; 874 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 875 dev_cap->eqc_entry_sz = size; 876 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 877 dev_cap->cqc_entry_sz = size; 878 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 879 dev_cap->srq_entry_sz = size; 880 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 881 dev_cap->cmpt_entry_sz = size; 882 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 883 dev_cap->mtt_entry_sz = size; 884 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 885 dev_cap->dmpt_entry_sz = size; 886 887 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 888 dev_cap->max_srq_sz = 1 << field; 889 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 890 dev_cap->max_qp_sz = 1 << field; 891 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 892 dev_cap->resize_srq = field & 1; 893 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 894 dev_cap->max_rq_sg = field; 895 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 896 dev_cap->max_rq_desc_sz = size; 897 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 898 if (field & (1 << 4)) 899 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 900 if (field & (1 << 5)) 901 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 902 if (field & (1 << 6)) 903 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 904 if (field & (1 << 7)) 905 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 906 MLX4_GET(dev_cap->bmme_flags, outbox, 907 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 908 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 909 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 910 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 911 if (field & 0x20) 912 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 913 if (field & (1 << 2)) 914 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 915 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); 916 if (field & 0x80) 917 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; 918 if (field & 0x40) 919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; 920 921 MLX4_GET(dev_cap->reserved_lkey, outbox, 922 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 923 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 924 if (field32 & (1 << 0)) 925 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 926 if (field32 & (1 << 7)) 927 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 928 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 929 if (field & 1<<6) 930 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 931 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 932 if (field & 1<<3) 933 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 934 if (field & (1 << 5)) 935 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 936 MLX4_GET(dev_cap->max_icm_sz, outbox, 937 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 938 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 939 MLX4_GET(dev_cap->max_counters, outbox, 940 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 941 942 MLX4_GET(field32, outbox, 943 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 944 if (field32 & (1 << 0)) 945 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 946 947 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 948 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 949 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 950 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 951 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 952 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 953 954 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 955 dev_cap->rl_caps.num_rates = size; 956 if (dev_cap->rl_caps.num_rates) { 957 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 958 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 959 dev_cap->rl_caps.max_val = size & 0xfff; 960 dev_cap->rl_caps.max_unit = size >> 14; 961 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 962 dev_cap->rl_caps.min_val = size & 0xfff; 963 dev_cap->rl_caps.min_unit = size >> 14; 964 } 965 966 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 967 if (field32 & (1 << 16)) 968 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 969 if (field32 & (1 << 18)) 970 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; 971 if (field32 & (1 << 19)) 972 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; 973 if (field32 & (1 << 26)) 974 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 975 if (field32 & (1 << 20)) 976 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 977 if (field32 & (1 << 21)) 978 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 979 980 for (i = 1; i <= dev_cap->num_ports; i++) { 981 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 982 if (err) 983 goto out; 984 } 985 986 /* 987 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 988 * we can't use any EQs whose doorbell falls on that page, 989 * even if the EQ itself isn't reserved. 990 */ 991 if (dev_cap->num_sys_eqs == 0) 992 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 993 dev_cap->reserved_eqs); 994 else 995 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 996 997 out: 998 mlx4_free_cmd_mailbox(dev, mailbox); 999 return err; 1000 } 1001 1002 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 1003 { 1004 if (dev_cap->bf_reg_size > 0) 1005 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 1006 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 1007 else 1008 mlx4_dbg(dev, "BlueFlame not available\n"); 1009 1010 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 1011 dev_cap->bmme_flags, dev_cap->reserved_lkey); 1012 mlx4_dbg(dev, "Max ICM size %lld MB\n", 1013 (unsigned long long) dev_cap->max_icm_sz >> 20); 1014 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1015 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 1016 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1017 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 1018 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1019 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 1020 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 1021 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 1022 dev_cap->eqc_entry_sz); 1023 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1024 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1025 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1026 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1027 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1028 dev_cap->max_pds, dev_cap->reserved_mgms); 1029 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1030 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1031 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1032 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1033 dev_cap->port_cap[1].max_port_width); 1034 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1035 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1036 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1037 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1038 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1039 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1040 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1041 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1042 dev_cap->dmfs_high_rate_qpn_base); 1043 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1044 dev_cap->dmfs_high_rate_qpn_range); 1045 1046 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1047 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1048 1049 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1050 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1051 rl_caps->min_unit, rl_caps->min_val); 1052 } 1053 1054 dump_dev_cap_flags(dev, dev_cap->flags); 1055 dump_dev_cap_flags2(dev, dev_cap->flags2); 1056 } 1057 1058 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1059 { 1060 struct mlx4_cmd_mailbox *mailbox; 1061 u32 *outbox; 1062 u8 field; 1063 u32 field32; 1064 int err; 1065 1066 mailbox = mlx4_alloc_cmd_mailbox(dev); 1067 if (IS_ERR(mailbox)) 1068 return PTR_ERR(mailbox); 1069 outbox = mailbox->buf; 1070 1071 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1072 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1073 MLX4_CMD_TIME_CLASS_A, 1074 MLX4_CMD_NATIVE); 1075 1076 if (err) 1077 goto out; 1078 1079 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1080 port_cap->max_vl = field >> 4; 1081 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1082 port_cap->ib_mtu = field >> 4; 1083 port_cap->max_port_width = field & 0xf; 1084 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1085 port_cap->max_gids = 1 << (field & 0xf); 1086 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1087 port_cap->max_pkeys = 1 << (field & 0xf); 1088 } else { 1089 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1090 #define QUERY_PORT_MTU_OFFSET 0x01 1091 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1092 #define QUERY_PORT_WIDTH_OFFSET 0x06 1093 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1094 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1095 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1096 #define QUERY_PORT_MAC_OFFSET 0x10 1097 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1098 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1099 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1100 1101 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1102 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1103 if (err) 1104 goto out; 1105 1106 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1107 port_cap->supported_port_types = field & 3; 1108 port_cap->suggested_type = (field >> 3) & 1; 1109 port_cap->default_sense = (field >> 4) & 1; 1110 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1111 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1112 port_cap->ib_mtu = field & 0xf; 1113 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1114 port_cap->max_port_width = field & 0xf; 1115 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1116 port_cap->max_gids = 1 << (field >> 4); 1117 port_cap->max_pkeys = 1 << (field & 0xf); 1118 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1119 port_cap->max_vl = field & 0xf; 1120 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1121 port_cap->log_max_macs = field & 0xf; 1122 port_cap->log_max_vlans = field >> 4; 1123 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1124 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1125 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1126 port_cap->trans_type = field32 >> 24; 1127 port_cap->vendor_oui = field32 & 0xffffff; 1128 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1129 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1130 } 1131 1132 out: 1133 mlx4_free_cmd_mailbox(dev, mailbox); 1134 return err; 1135 } 1136 1137 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1138 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1139 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1140 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1141 1142 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1143 struct mlx4_vhcr *vhcr, 1144 struct mlx4_cmd_mailbox *inbox, 1145 struct mlx4_cmd_mailbox *outbox, 1146 struct mlx4_cmd_info *cmd) 1147 { 1148 u64 flags; 1149 int err = 0; 1150 u8 field; 1151 u16 field16; 1152 u32 bmme_flags, field32; 1153 int real_port; 1154 int slave_port; 1155 int first_port; 1156 struct mlx4_active_ports actv_ports; 1157 1158 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1159 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1160 if (err) 1161 return err; 1162 1163 /* add port mng change event capability and disable mw type 1 1164 * unconditionally to slaves 1165 */ 1166 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1167 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1168 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1169 actv_ports = mlx4_get_active_ports(dev, slave); 1170 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1171 for (slave_port = 0, real_port = first_port; 1172 real_port < first_port + 1173 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1174 ++real_port, ++slave_port) { 1175 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1176 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1177 else 1178 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1179 } 1180 for (; slave_port < dev->caps.num_ports; ++slave_port) 1181 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1182 1183 /* Not exposing RSS IP fragments to guests */ 1184 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1185 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1186 1187 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1188 field &= ~0x0F; 1189 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1190 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1191 1192 /* For guests, disable timestamp */ 1193 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1194 field &= 0x7f; 1195 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1196 1197 /* For guests, disable vxlan tunneling and QoS support */ 1198 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1199 field &= 0xd7; 1200 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1201 1202 /* For guests, disable port BEACON */ 1203 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1204 field &= 0x7f; 1205 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1206 1207 /* For guests, report Blueflame disabled */ 1208 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1209 field &= 0x7f; 1210 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1211 1212 /* For guests, disable mw type 2 and port remap*/ 1213 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1214 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1215 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1216 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1217 1218 /* turn off device-managed steering capability if not enabled */ 1219 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1220 MLX4_GET(field, outbox->buf, 1221 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1222 field &= 0x7f; 1223 MLX4_PUT(outbox->buf, field, 1224 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1225 } 1226 1227 /* turn off ipoib managed steering for guests */ 1228 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1229 field &= ~0x80; 1230 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1231 1232 /* turn off host side virt features (VST, FSM, etc) for guests */ 1233 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1234 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1235 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1236 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1237 1238 /* turn off QCN for guests */ 1239 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1240 field &= 0xfe; 1241 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1242 1243 /* turn off QP max-rate limiting for guests */ 1244 field16 = 0; 1245 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1246 1247 /* turn off QoS per VF support for guests */ 1248 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1249 field &= 0xef; 1250 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1251 1252 /* turn off ignore FCS feature for guests */ 1253 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1254 field &= 0xfb; 1255 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1256 1257 return 0; 1258 } 1259 1260 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1261 struct mlx4_vhcr *vhcr, 1262 struct mlx4_cmd_mailbox *inbox, 1263 struct mlx4_cmd_mailbox *outbox, 1264 struct mlx4_cmd_info *cmd) 1265 { 1266 struct mlx4_priv *priv = mlx4_priv(dev); 1267 u64 def_mac; 1268 u8 port_type; 1269 u16 short_field; 1270 int err; 1271 int admin_link_state; 1272 int port = mlx4_slave_convert_port(dev, slave, 1273 vhcr->in_modifier & 0xFF); 1274 1275 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1276 #define MLX4_PORT_LINK_UP_MASK 0x80 1277 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1278 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1279 1280 if (port < 0) 1281 return -EINVAL; 1282 1283 /* Protect against untrusted guests: enforce that this is the 1284 * QUERY_PORT general query. 1285 */ 1286 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1287 return -EINVAL; 1288 1289 vhcr->in_modifier = port; 1290 1291 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1292 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1293 MLX4_CMD_NATIVE); 1294 1295 if (!err && dev->caps.function != slave) { 1296 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1297 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1298 1299 /* get port type - currently only eth is enabled */ 1300 MLX4_GET(port_type, outbox->buf, 1301 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1302 1303 /* No link sensing allowed */ 1304 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1305 /* set port type to currently operating port type */ 1306 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1307 1308 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1309 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1310 port_type |= MLX4_PORT_LINK_UP_MASK; 1311 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1312 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1313 1314 MLX4_PUT(outbox->buf, port_type, 1315 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1316 1317 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1318 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1319 else 1320 short_field = 1; /* slave max gids */ 1321 MLX4_PUT(outbox->buf, short_field, 1322 QUERY_PORT_CUR_MAX_GID_OFFSET); 1323 1324 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1325 MLX4_PUT(outbox->buf, short_field, 1326 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1327 } 1328 1329 return err; 1330 } 1331 1332 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1333 int *gid_tbl_len, int *pkey_tbl_len) 1334 { 1335 struct mlx4_cmd_mailbox *mailbox; 1336 u32 *outbox; 1337 u16 field; 1338 int err; 1339 1340 mailbox = mlx4_alloc_cmd_mailbox(dev); 1341 if (IS_ERR(mailbox)) 1342 return PTR_ERR(mailbox); 1343 1344 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1345 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1346 MLX4_CMD_WRAPPED); 1347 if (err) 1348 goto out; 1349 1350 outbox = mailbox->buf; 1351 1352 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1353 *gid_tbl_len = field; 1354 1355 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1356 *pkey_tbl_len = field; 1357 1358 out: 1359 mlx4_free_cmd_mailbox(dev, mailbox); 1360 return err; 1361 } 1362 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1363 1364 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1365 { 1366 struct mlx4_cmd_mailbox *mailbox; 1367 struct mlx4_icm_iter iter; 1368 __be64 *pages; 1369 int lg; 1370 int nent = 0; 1371 int i; 1372 int err = 0; 1373 int ts = 0, tc = 0; 1374 1375 mailbox = mlx4_alloc_cmd_mailbox(dev); 1376 if (IS_ERR(mailbox)) 1377 return PTR_ERR(mailbox); 1378 pages = mailbox->buf; 1379 1380 for (mlx4_icm_first(icm, &iter); 1381 !mlx4_icm_last(&iter); 1382 mlx4_icm_next(&iter)) { 1383 /* 1384 * We have to pass pages that are aligned to their 1385 * size, so find the least significant 1 in the 1386 * address or size and use that as our log2 size. 1387 */ 1388 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1389 if (lg < MLX4_ICM_PAGE_SHIFT) { 1390 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1391 MLX4_ICM_PAGE_SIZE, 1392 (unsigned long long) mlx4_icm_addr(&iter), 1393 mlx4_icm_size(&iter)); 1394 err = -EINVAL; 1395 goto out; 1396 } 1397 1398 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1399 if (virt != -1) { 1400 pages[nent * 2] = cpu_to_be64(virt); 1401 virt += 1 << lg; 1402 } 1403 1404 pages[nent * 2 + 1] = 1405 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1406 (lg - MLX4_ICM_PAGE_SHIFT)); 1407 ts += 1 << (lg - 10); 1408 ++tc; 1409 1410 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1411 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1412 MLX4_CMD_TIME_CLASS_B, 1413 MLX4_CMD_NATIVE); 1414 if (err) 1415 goto out; 1416 nent = 0; 1417 } 1418 } 1419 } 1420 1421 if (nent) 1422 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1423 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1424 if (err) 1425 goto out; 1426 1427 switch (op) { 1428 case MLX4_CMD_MAP_FA: 1429 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1430 break; 1431 case MLX4_CMD_MAP_ICM_AUX: 1432 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1433 break; 1434 case MLX4_CMD_MAP_ICM: 1435 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1436 tc, ts, (unsigned long long) virt - (ts << 10)); 1437 break; 1438 } 1439 1440 out: 1441 mlx4_free_cmd_mailbox(dev, mailbox); 1442 return err; 1443 } 1444 1445 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1446 { 1447 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1448 } 1449 1450 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1451 { 1452 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1453 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1454 } 1455 1456 1457 int mlx4_RUN_FW(struct mlx4_dev *dev) 1458 { 1459 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1460 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1461 } 1462 1463 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1464 { 1465 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1466 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1467 struct mlx4_cmd_mailbox *mailbox; 1468 u32 *outbox; 1469 int err = 0; 1470 u64 fw_ver; 1471 u16 cmd_if_rev; 1472 u8 lg; 1473 1474 #define QUERY_FW_OUT_SIZE 0x100 1475 #define QUERY_FW_VER_OFFSET 0x00 1476 #define QUERY_FW_PPF_ID 0x09 1477 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1478 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1479 #define QUERY_FW_ERR_START_OFFSET 0x30 1480 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1481 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1482 1483 #define QUERY_FW_SIZE_OFFSET 0x00 1484 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1485 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1486 1487 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1488 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1489 1490 #define QUERY_FW_CLOCK_OFFSET 0x50 1491 #define QUERY_FW_CLOCK_BAR 0x58 1492 1493 mailbox = mlx4_alloc_cmd_mailbox(dev); 1494 if (IS_ERR(mailbox)) 1495 return PTR_ERR(mailbox); 1496 outbox = mailbox->buf; 1497 1498 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1499 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1500 if (err) 1501 goto out; 1502 1503 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1504 /* 1505 * FW subminor version is at more significant bits than minor 1506 * version, so swap here. 1507 */ 1508 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1509 ((fw_ver & 0xffff0000ull) >> 16) | 1510 ((fw_ver & 0x0000ffffull) << 16); 1511 1512 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1513 dev->caps.function = lg; 1514 1515 if (mlx4_is_slave(dev)) 1516 goto out; 1517 1518 1519 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1520 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1521 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1522 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1523 cmd_if_rev); 1524 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1525 (int) (dev->caps.fw_ver >> 32), 1526 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1527 (int) dev->caps.fw_ver & 0xffff); 1528 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1529 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1530 err = -ENODEV; 1531 goto out; 1532 } 1533 1534 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1535 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1536 1537 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1538 cmd->max_cmds = 1 << lg; 1539 1540 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1541 (int) (dev->caps.fw_ver >> 32), 1542 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1543 (int) dev->caps.fw_ver & 0xffff, 1544 cmd_if_rev, cmd->max_cmds); 1545 1546 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1547 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1548 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1549 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1550 1551 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1552 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1553 1554 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1555 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1556 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1557 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1558 1559 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1560 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1561 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1562 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1563 fw->comm_bar, fw->comm_base); 1564 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1565 1566 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1567 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1568 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1569 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1570 fw->clock_bar, fw->clock_offset); 1571 1572 /* 1573 * Round up number of system pages needed in case 1574 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1575 */ 1576 fw->fw_pages = 1577 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1578 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1579 1580 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1581 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1582 1583 out: 1584 mlx4_free_cmd_mailbox(dev, mailbox); 1585 return err; 1586 } 1587 1588 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1589 struct mlx4_vhcr *vhcr, 1590 struct mlx4_cmd_mailbox *inbox, 1591 struct mlx4_cmd_mailbox *outbox, 1592 struct mlx4_cmd_info *cmd) 1593 { 1594 u8 *outbuf; 1595 int err; 1596 1597 outbuf = outbox->buf; 1598 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1599 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1600 if (err) 1601 return err; 1602 1603 /* for slaves, set pci PPF ID to invalid and zero out everything 1604 * else except FW version */ 1605 outbuf[0] = outbuf[1] = 0; 1606 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1607 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1608 1609 return 0; 1610 } 1611 1612 static void get_board_id(void *vsd, char *board_id) 1613 { 1614 int i; 1615 1616 #define VSD_OFFSET_SIG1 0x00 1617 #define VSD_OFFSET_SIG2 0xde 1618 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1619 #define VSD_OFFSET_TS_BOARD_ID 0x20 1620 1621 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1622 1623 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1624 1625 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1626 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1627 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1628 } else { 1629 /* 1630 * The board ID is a string but the firmware byte 1631 * swaps each 4-byte word before passing it back to 1632 * us. Therefore we need to swab it before printing. 1633 */ 1634 u32 *bid_u32 = (u32 *)board_id; 1635 1636 for (i = 0; i < 4; ++i) { 1637 u32 *addr; 1638 u32 val; 1639 1640 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1641 val = get_unaligned(addr); 1642 val = swab32(val); 1643 put_unaligned(val, &bid_u32[i]); 1644 } 1645 } 1646 } 1647 1648 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1649 { 1650 struct mlx4_cmd_mailbox *mailbox; 1651 u32 *outbox; 1652 int err; 1653 1654 #define QUERY_ADAPTER_OUT_SIZE 0x100 1655 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1656 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1657 1658 mailbox = mlx4_alloc_cmd_mailbox(dev); 1659 if (IS_ERR(mailbox)) 1660 return PTR_ERR(mailbox); 1661 outbox = mailbox->buf; 1662 1663 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1664 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1665 if (err) 1666 goto out; 1667 1668 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1669 1670 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1671 adapter->board_id); 1672 1673 out: 1674 mlx4_free_cmd_mailbox(dev, mailbox); 1675 return err; 1676 } 1677 1678 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1679 { 1680 struct mlx4_cmd_mailbox *mailbox; 1681 __be32 *inbox; 1682 int err; 1683 static const u8 a0_dmfs_hw_steering[] = { 1684 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1685 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1686 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1687 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1688 }; 1689 1690 #define INIT_HCA_IN_SIZE 0x200 1691 #define INIT_HCA_VERSION_OFFSET 0x000 1692 #define INIT_HCA_VERSION 2 1693 #define INIT_HCA_VXLAN_OFFSET 0x0c 1694 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1695 #define INIT_HCA_FLAGS_OFFSET 0x014 1696 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1697 #define INIT_HCA_QPC_OFFSET 0x020 1698 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1699 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1700 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1701 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1702 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1703 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1704 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1705 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1706 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1707 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1708 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1709 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1710 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1711 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1712 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1713 #define INIT_HCA_MCAST_OFFSET 0x0c0 1714 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1715 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1716 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1717 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1718 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1719 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1720 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1721 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1722 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1723 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1724 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1725 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1726 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1727 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1728 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1729 #define INIT_HCA_TPT_OFFSET 0x0f0 1730 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1731 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1732 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1733 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1734 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1735 #define INIT_HCA_UAR_OFFSET 0x120 1736 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1737 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1738 1739 mailbox = mlx4_alloc_cmd_mailbox(dev); 1740 if (IS_ERR(mailbox)) 1741 return PTR_ERR(mailbox); 1742 inbox = mailbox->buf; 1743 1744 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1745 1746 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1747 (ilog2(cache_line_size()) - 4) << 5; 1748 1749 #if defined(__LITTLE_ENDIAN) 1750 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1751 #elif defined(__BIG_ENDIAN) 1752 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1753 #else 1754 #error Host endianness not defined 1755 #endif 1756 /* Check port for UD address vector: */ 1757 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1758 1759 /* Enable IPoIB checksumming if we can: */ 1760 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1761 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1762 1763 /* Enable QoS support if module parameter set */ 1764 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1765 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1766 1767 /* enable counters */ 1768 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1769 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1770 1771 /* Enable RSS spread to fragmented IP packets when supported */ 1772 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1773 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1774 1775 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1776 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1777 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1778 dev->caps.eqe_size = 64; 1779 dev->caps.eqe_factor = 1; 1780 } else { 1781 dev->caps.eqe_size = 32; 1782 dev->caps.eqe_factor = 0; 1783 } 1784 1785 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1786 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1787 dev->caps.cqe_size = 64; 1788 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1789 } else { 1790 dev->caps.cqe_size = 32; 1791 } 1792 1793 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1794 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1795 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1796 dev->caps.eqe_size = cache_line_size(); 1797 dev->caps.cqe_size = cache_line_size(); 1798 dev->caps.eqe_factor = 0; 1799 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1800 (ilog2(dev->caps.eqe_size) - 5)), 1801 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1802 1803 /* User still need to know to support CQE > 32B */ 1804 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1805 } 1806 1807 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1808 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1809 1810 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1811 1812 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1813 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1814 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1815 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1816 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1817 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1818 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1819 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1820 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1821 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1822 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1823 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1824 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1825 1826 /* steering attributes */ 1827 if (dev->caps.steering_mode == 1828 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1829 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1830 cpu_to_be32(1 << 1831 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1832 1833 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1834 MLX4_PUT(inbox, param->log_mc_entry_sz, 1835 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1836 MLX4_PUT(inbox, param->log_mc_table_sz, 1837 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1838 /* Enable Ethernet flow steering 1839 * with udp unicast and tcp unicast 1840 */ 1841 if (dev->caps.dmfs_high_steer_mode != 1842 MLX4_STEERING_DMFS_A0_STATIC) 1843 MLX4_PUT(inbox, 1844 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1845 INIT_HCA_FS_ETH_BITS_OFFSET); 1846 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1847 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1848 /* Enable IPoIB flow steering 1849 * with udp unicast and tcp unicast 1850 */ 1851 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1852 INIT_HCA_FS_IB_BITS_OFFSET); 1853 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1854 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1855 1856 if (dev->caps.dmfs_high_steer_mode != 1857 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1858 MLX4_PUT(inbox, 1859 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1860 << 6)), 1861 INIT_HCA_FS_A0_OFFSET); 1862 } else { 1863 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1864 MLX4_PUT(inbox, param->log_mc_entry_sz, 1865 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1866 MLX4_PUT(inbox, param->log_mc_hash_sz, 1867 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1868 MLX4_PUT(inbox, param->log_mc_table_sz, 1869 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1870 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1871 MLX4_PUT(inbox, (u8) (1 << 3), 1872 INIT_HCA_UC_STEERING_OFFSET); 1873 } 1874 1875 /* TPT attributes */ 1876 1877 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1878 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1879 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1880 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1881 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1882 1883 /* UAR attributes */ 1884 1885 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1886 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1887 1888 /* set parser VXLAN attributes */ 1889 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1890 u8 parser_params = 0; 1891 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1892 } 1893 1894 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1895 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 1896 1897 if (err) 1898 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1899 1900 mlx4_free_cmd_mailbox(dev, mailbox); 1901 return err; 1902 } 1903 1904 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1905 struct mlx4_init_hca_param *param) 1906 { 1907 struct mlx4_cmd_mailbox *mailbox; 1908 __be32 *outbox; 1909 u32 dword_field; 1910 int err; 1911 u8 byte_field; 1912 static const u8 a0_dmfs_query_hw_steering[] = { 1913 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1914 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1915 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1916 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1917 }; 1918 1919 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1920 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1921 1922 mailbox = mlx4_alloc_cmd_mailbox(dev); 1923 if (IS_ERR(mailbox)) 1924 return PTR_ERR(mailbox); 1925 outbox = mailbox->buf; 1926 1927 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1928 MLX4_CMD_QUERY_HCA, 1929 MLX4_CMD_TIME_CLASS_B, 1930 !mlx4_is_slave(dev)); 1931 if (err) 1932 goto out; 1933 1934 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1935 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1936 1937 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1938 1939 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1940 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1941 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1942 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1943 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1944 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1945 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1946 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1947 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1948 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1949 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1950 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1951 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1952 1953 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1954 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1955 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1956 } else { 1957 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1958 if (byte_field & 0x8) 1959 param->steering_mode = MLX4_STEERING_MODE_B0; 1960 else 1961 param->steering_mode = MLX4_STEERING_MODE_A0; 1962 } 1963 1964 if (dword_field & (1 << 13)) 1965 param->rss_ip_frags = 1; 1966 1967 /* steering attributes */ 1968 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1969 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1970 MLX4_GET(param->log_mc_entry_sz, outbox, 1971 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1972 MLX4_GET(param->log_mc_table_sz, outbox, 1973 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1974 MLX4_GET(byte_field, outbox, 1975 INIT_HCA_FS_A0_OFFSET); 1976 param->dmfs_high_steer_mode = 1977 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 1978 } else { 1979 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1980 MLX4_GET(param->log_mc_entry_sz, outbox, 1981 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1982 MLX4_GET(param->log_mc_hash_sz, outbox, 1983 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1984 MLX4_GET(param->log_mc_table_sz, outbox, 1985 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1986 } 1987 1988 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1989 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1990 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1991 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1992 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1993 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1994 1995 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1996 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1997 if (byte_field) { 1998 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1999 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 2000 param->cqe_size = 1 << ((byte_field & 2001 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 2002 param->eqe_size = 1 << (((byte_field & 2003 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 2004 } 2005 2006 /* TPT attributes */ 2007 2008 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 2009 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 2010 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 2011 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 2012 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 2013 2014 /* UAR attributes */ 2015 2016 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2017 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 2018 2019 /* phv_check enable */ 2020 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); 2021 if (byte_field & 0x2) 2022 param->phv_check_en = 1; 2023 out: 2024 mlx4_free_cmd_mailbox(dev, mailbox); 2025 2026 return err; 2027 } 2028 2029 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2030 { 2031 struct mlx4_cmd_mailbox *mailbox; 2032 __be32 *outbox; 2033 int err; 2034 2035 mailbox = mlx4_alloc_cmd_mailbox(dev); 2036 if (IS_ERR(mailbox)) { 2037 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2038 return PTR_ERR(mailbox); 2039 } 2040 outbox = mailbox->buf; 2041 2042 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2043 MLX4_CMD_QUERY_HCA, 2044 MLX4_CMD_TIME_CLASS_B, 2045 !mlx4_is_slave(dev)); 2046 if (err) { 2047 mlx4_warn(dev, "hca_core_clock update failed\n"); 2048 goto out; 2049 } 2050 2051 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2052 2053 out: 2054 mlx4_free_cmd_mailbox(dev, mailbox); 2055 2056 return err; 2057 } 2058 2059 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2060 * and real QP0 are active, so that the paravirtualized QP0 is ready 2061 * to operate */ 2062 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2063 { 2064 struct mlx4_priv *priv = mlx4_priv(dev); 2065 /* irrelevant if not infiniband */ 2066 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2067 priv->mfunc.master.qp0_state[port].qp0_active) 2068 return 1; 2069 return 0; 2070 } 2071 2072 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2073 struct mlx4_vhcr *vhcr, 2074 struct mlx4_cmd_mailbox *inbox, 2075 struct mlx4_cmd_mailbox *outbox, 2076 struct mlx4_cmd_info *cmd) 2077 { 2078 struct mlx4_priv *priv = mlx4_priv(dev); 2079 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2080 int err; 2081 2082 if (port < 0) 2083 return -EINVAL; 2084 2085 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2086 return 0; 2087 2088 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2089 /* Enable port only if it was previously disabled */ 2090 if (!priv->mfunc.master.init_port_ref[port]) { 2091 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2092 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2093 if (err) 2094 return err; 2095 } 2096 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2097 } else { 2098 if (slave == mlx4_master_func_num(dev)) { 2099 if (check_qp0_state(dev, slave, port) && 2100 !priv->mfunc.master.qp0_state[port].port_active) { 2101 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2102 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2103 if (err) 2104 return err; 2105 priv->mfunc.master.qp0_state[port].port_active = 1; 2106 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2107 } 2108 } else 2109 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2110 } 2111 ++priv->mfunc.master.init_port_ref[port]; 2112 return 0; 2113 } 2114 2115 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2116 { 2117 struct mlx4_cmd_mailbox *mailbox; 2118 u32 *inbox; 2119 int err; 2120 u32 flags; 2121 u16 field; 2122 2123 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2124 #define INIT_PORT_IN_SIZE 256 2125 #define INIT_PORT_FLAGS_OFFSET 0x00 2126 #define INIT_PORT_FLAG_SIG (1 << 18) 2127 #define INIT_PORT_FLAG_NG (1 << 17) 2128 #define INIT_PORT_FLAG_G0 (1 << 16) 2129 #define INIT_PORT_VL_SHIFT 4 2130 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2131 #define INIT_PORT_MTU_OFFSET 0x04 2132 #define INIT_PORT_MAX_GID_OFFSET 0x06 2133 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2134 #define INIT_PORT_GUID0_OFFSET 0x10 2135 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2136 #define INIT_PORT_SI_GUID_OFFSET 0x20 2137 2138 mailbox = mlx4_alloc_cmd_mailbox(dev); 2139 if (IS_ERR(mailbox)) 2140 return PTR_ERR(mailbox); 2141 inbox = mailbox->buf; 2142 2143 flags = 0; 2144 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2145 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2146 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2147 2148 field = 128 << dev->caps.ib_mtu_cap[port]; 2149 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2150 field = dev->caps.gid_table_len[port]; 2151 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2152 field = dev->caps.pkey_table_len[port]; 2153 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2154 2155 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2156 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2157 2158 mlx4_free_cmd_mailbox(dev, mailbox); 2159 } else 2160 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2161 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2162 2163 if (!err) 2164 mlx4_hca_core_clock_update(dev); 2165 2166 return err; 2167 } 2168 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2169 2170 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2171 struct mlx4_vhcr *vhcr, 2172 struct mlx4_cmd_mailbox *inbox, 2173 struct mlx4_cmd_mailbox *outbox, 2174 struct mlx4_cmd_info *cmd) 2175 { 2176 struct mlx4_priv *priv = mlx4_priv(dev); 2177 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2178 int err; 2179 2180 if (port < 0) 2181 return -EINVAL; 2182 2183 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2184 (1 << port))) 2185 return 0; 2186 2187 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2188 if (priv->mfunc.master.init_port_ref[port] == 1) { 2189 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2190 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2191 if (err) 2192 return err; 2193 } 2194 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2195 } else { 2196 /* infiniband port */ 2197 if (slave == mlx4_master_func_num(dev)) { 2198 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2199 priv->mfunc.master.qp0_state[port].port_active) { 2200 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2201 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2202 if (err) 2203 return err; 2204 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2205 priv->mfunc.master.qp0_state[port].port_active = 0; 2206 } 2207 } else 2208 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2209 } 2210 --priv->mfunc.master.init_port_ref[port]; 2211 return 0; 2212 } 2213 2214 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2215 { 2216 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2217 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2218 } 2219 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2220 2221 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2222 { 2223 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2224 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2225 } 2226 2227 struct mlx4_config_dev { 2228 __be32 update_flags; 2229 __be32 rsvd1[3]; 2230 __be16 vxlan_udp_dport; 2231 __be16 rsvd2; 2232 __be32 rsvd3; 2233 __be32 roce_flags; 2234 __be32 rsvd4[25]; 2235 __be16 rsvd5; 2236 u8 rsvd6; 2237 u8 rx_checksum_val; 2238 }; 2239 2240 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2241 #define MLX4_DISABLE_RX_PORT BIT(18) 2242 2243 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2244 { 2245 int err; 2246 struct mlx4_cmd_mailbox *mailbox; 2247 2248 mailbox = mlx4_alloc_cmd_mailbox(dev); 2249 if (IS_ERR(mailbox)) 2250 return PTR_ERR(mailbox); 2251 2252 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2253 2254 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2255 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2256 2257 mlx4_free_cmd_mailbox(dev, mailbox); 2258 return err; 2259 } 2260 2261 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2262 { 2263 int err; 2264 struct mlx4_cmd_mailbox *mailbox; 2265 2266 mailbox = mlx4_alloc_cmd_mailbox(dev); 2267 if (IS_ERR(mailbox)) 2268 return PTR_ERR(mailbox); 2269 2270 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2271 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2272 2273 if (!err) 2274 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2275 2276 mlx4_free_cmd_mailbox(dev, mailbox); 2277 return err; 2278 } 2279 2280 /* Conversion between the HW values and the actual functionality. 2281 * The value represented by the array index, 2282 * and the functionality determined by the flags. 2283 */ 2284 static const u8 config_dev_csum_flags[] = { 2285 [0] = 0, 2286 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2287 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2288 MLX4_RX_CSUM_MODE_L4, 2289 [3] = MLX4_RX_CSUM_MODE_L4 | 2290 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2291 MLX4_RX_CSUM_MODE_MULTI_VLAN 2292 }; 2293 2294 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2295 struct mlx4_config_dev_params *params) 2296 { 2297 struct mlx4_config_dev config_dev = {0}; 2298 int err; 2299 u8 csum_mask; 2300 2301 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2302 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2303 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2304 2305 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2306 return -ENOTSUPP; 2307 2308 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2309 if (err) 2310 return err; 2311 2312 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2313 CONFIG_DEV_RX_CSUM_MODE_MASK; 2314 2315 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2316 return -EINVAL; 2317 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2318 2319 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2320 CONFIG_DEV_RX_CSUM_MODE_MASK; 2321 2322 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2323 return -EINVAL; 2324 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2325 2326 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2327 2328 return 0; 2329 } 2330 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2331 2332 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2333 { 2334 struct mlx4_config_dev config_dev; 2335 2336 memset(&config_dev, 0, sizeof(config_dev)); 2337 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2338 config_dev.vxlan_udp_dport = udp_port; 2339 2340 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2341 } 2342 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2343 2344 #define CONFIG_DISABLE_RX_PORT BIT(15) 2345 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2346 { 2347 struct mlx4_config_dev config_dev; 2348 2349 memset(&config_dev, 0, sizeof(config_dev)); 2350 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2351 if (dis) 2352 config_dev.roce_flags = 2353 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2354 2355 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2356 } 2357 2358 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2359 { 2360 struct mlx4_cmd_mailbox *mailbox; 2361 struct { 2362 __be32 v_port1; 2363 __be32 v_port2; 2364 } *v2p; 2365 int err; 2366 2367 mailbox = mlx4_alloc_cmd_mailbox(dev); 2368 if (IS_ERR(mailbox)) 2369 return -ENOMEM; 2370 2371 v2p = mailbox->buf; 2372 v2p->v_port1 = cpu_to_be32(port1); 2373 v2p->v_port2 = cpu_to_be32(port2); 2374 2375 err = mlx4_cmd(dev, mailbox->dma, 0, 2376 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2377 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2378 2379 mlx4_free_cmd_mailbox(dev, mailbox); 2380 return err; 2381 } 2382 2383 2384 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2385 { 2386 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2387 MLX4_CMD_SET_ICM_SIZE, 2388 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2389 if (ret) 2390 return ret; 2391 2392 /* 2393 * Round up number of system pages needed in case 2394 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2395 */ 2396 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2397 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2398 2399 return 0; 2400 } 2401 2402 int mlx4_NOP(struct mlx4_dev *dev) 2403 { 2404 /* Input modifier of 0x1f means "finish as soon as possible." */ 2405 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2406 MLX4_CMD_NATIVE); 2407 } 2408 2409 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2410 { 2411 u8 port; 2412 u32 *outbox; 2413 struct mlx4_cmd_mailbox *mailbox; 2414 u32 in_mod; 2415 u32 guid_hi, guid_lo; 2416 int err, ret = 0; 2417 #define MOD_STAT_CFG_PORT_OFFSET 8 2418 #define MOD_STAT_CFG_GUID_H 0X14 2419 #define MOD_STAT_CFG_GUID_L 0X1c 2420 2421 mailbox = mlx4_alloc_cmd_mailbox(dev); 2422 if (IS_ERR(mailbox)) 2423 return PTR_ERR(mailbox); 2424 outbox = mailbox->buf; 2425 2426 for (port = 1; port <= dev->caps.num_ports; port++) { 2427 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2428 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2429 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2430 MLX4_CMD_NATIVE); 2431 if (err) { 2432 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2433 port); 2434 ret = err; 2435 } else { 2436 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2437 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2438 dev->caps.phys_port_id[port] = (u64)guid_lo | 2439 (u64)guid_hi << 32; 2440 } 2441 } 2442 mlx4_free_cmd_mailbox(dev, mailbox); 2443 return ret; 2444 } 2445 2446 #define MLX4_WOL_SETUP_MODE (5 << 28) 2447 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2448 { 2449 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2450 2451 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2452 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2453 MLX4_CMD_NATIVE); 2454 } 2455 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2456 2457 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2458 { 2459 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2460 2461 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2462 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2463 } 2464 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2465 2466 enum { 2467 ADD_TO_MCG = 0x26, 2468 }; 2469 2470 2471 void mlx4_opreq_action(struct work_struct *work) 2472 { 2473 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2474 opreq_task); 2475 struct mlx4_dev *dev = &priv->dev; 2476 int num_tasks = atomic_read(&priv->opreq_count); 2477 struct mlx4_cmd_mailbox *mailbox; 2478 struct mlx4_mgm *mgm; 2479 u32 *outbox; 2480 u32 modifier; 2481 u16 token; 2482 u16 type; 2483 int err; 2484 u32 num_qps; 2485 struct mlx4_qp qp; 2486 int i; 2487 u8 rem_mcg; 2488 u8 prot; 2489 2490 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2491 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2492 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2493 #define GET_OP_REQ_DATA_OFFSET 0x20 2494 2495 mailbox = mlx4_alloc_cmd_mailbox(dev); 2496 if (IS_ERR(mailbox)) { 2497 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2498 return; 2499 } 2500 outbox = mailbox->buf; 2501 2502 while (num_tasks) { 2503 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2504 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2505 MLX4_CMD_NATIVE); 2506 if (err) { 2507 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2508 err); 2509 return; 2510 } 2511 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2512 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2513 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2514 type &= 0xfff; 2515 2516 switch (type) { 2517 case ADD_TO_MCG: 2518 if (dev->caps.steering_mode == 2519 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2520 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2521 err = EPERM; 2522 break; 2523 } 2524 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2525 GET_OP_REQ_DATA_OFFSET); 2526 num_qps = be32_to_cpu(mgm->members_count) & 2527 MGM_QPN_MASK; 2528 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2529 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2530 2531 for (i = 0; i < num_qps; i++) { 2532 qp.qpn = be32_to_cpu(mgm->qp[i]); 2533 if (rem_mcg) 2534 err = mlx4_multicast_detach(dev, &qp, 2535 mgm->gid, 2536 prot, 0); 2537 else 2538 err = mlx4_multicast_attach(dev, &qp, 2539 mgm->gid, 2540 mgm->gid[5] 2541 , 0, prot, 2542 NULL); 2543 if (err) 2544 break; 2545 } 2546 break; 2547 default: 2548 mlx4_warn(dev, "Bad type for required operation\n"); 2549 err = EINVAL; 2550 break; 2551 } 2552 err = mlx4_cmd(dev, 0, ((u32) err | 2553 (__force u32)cpu_to_be32(token) << 16), 2554 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2555 MLX4_CMD_NATIVE); 2556 if (err) { 2557 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2558 err); 2559 goto out; 2560 } 2561 memset(outbox, 0, 0xffc); 2562 num_tasks = atomic_dec_return(&priv->opreq_count); 2563 } 2564 2565 out: 2566 mlx4_free_cmd_mailbox(dev, mailbox); 2567 } 2568 2569 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2570 struct mlx4_cmd_mailbox *mailbox) 2571 { 2572 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2573 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2574 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2575 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2576 2577 u32 set_attr_mask, getresp_attr_mask; 2578 u32 trap_attr_mask, traprepress_attr_mask; 2579 2580 MLX4_GET(set_attr_mask, mailbox->buf, 2581 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2582 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2583 set_attr_mask); 2584 2585 MLX4_GET(getresp_attr_mask, mailbox->buf, 2586 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2587 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2588 getresp_attr_mask); 2589 2590 MLX4_GET(trap_attr_mask, mailbox->buf, 2591 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2592 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2593 trap_attr_mask); 2594 2595 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2596 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2597 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2598 traprepress_attr_mask); 2599 2600 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2601 traprepress_attr_mask) 2602 return 1; 2603 2604 return 0; 2605 } 2606 2607 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2608 { 2609 struct mlx4_cmd_mailbox *mailbox; 2610 int secure_host_active; 2611 int err; 2612 2613 /* Check if mad_demux is supported */ 2614 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2615 return 0; 2616 2617 mailbox = mlx4_alloc_cmd_mailbox(dev); 2618 if (IS_ERR(mailbox)) { 2619 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2620 return -ENOMEM; 2621 } 2622 2623 /* Query mad_demux to find out which MADs are handled by internal sma */ 2624 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2625 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2626 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2627 if (err) { 2628 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2629 err); 2630 goto out; 2631 } 2632 2633 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2634 2635 /* Config mad_demux to handle all MADs returned by the query above */ 2636 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2637 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2638 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2639 if (err) { 2640 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2641 goto out; 2642 } 2643 2644 if (secure_host_active) 2645 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2646 out: 2647 mlx4_free_cmd_mailbox(dev, mailbox); 2648 return err; 2649 } 2650 2651 /* Access Reg commands */ 2652 enum mlx4_access_reg_masks { 2653 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2654 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2655 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2656 }; 2657 2658 struct mlx4_access_reg { 2659 __be16 constant1; 2660 u8 status; 2661 u8 resrvd1; 2662 __be16 reg_id; 2663 u8 method; 2664 u8 constant2; 2665 __be32 resrvd2[2]; 2666 __be16 len_const; 2667 __be16 resrvd3; 2668 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2669 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2670 } __attribute__((__packed__)); 2671 2672 /** 2673 * mlx4_ACCESS_REG - Generic access reg command. 2674 * @dev: mlx4_dev. 2675 * @reg_id: register ID to access. 2676 * @method: Access method Read/Write. 2677 * @reg_len: register length to Read/Write in bytes. 2678 * @reg_data: reg_data pointer to Read/Write From/To. 2679 * 2680 * Access ConnectX registers FW command. 2681 * Returns 0 on success and copies outbox mlx4_access_reg data 2682 * field into reg_data or a negative error code. 2683 */ 2684 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2685 enum mlx4_access_reg_method method, 2686 u16 reg_len, void *reg_data) 2687 { 2688 struct mlx4_cmd_mailbox *inbox, *outbox; 2689 struct mlx4_access_reg *inbuf, *outbuf; 2690 int err; 2691 2692 inbox = mlx4_alloc_cmd_mailbox(dev); 2693 if (IS_ERR(inbox)) 2694 return PTR_ERR(inbox); 2695 2696 outbox = mlx4_alloc_cmd_mailbox(dev); 2697 if (IS_ERR(outbox)) { 2698 mlx4_free_cmd_mailbox(dev, inbox); 2699 return PTR_ERR(outbox); 2700 } 2701 2702 inbuf = inbox->buf; 2703 outbuf = outbox->buf; 2704 2705 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2706 inbuf->constant2 = 0x1; 2707 inbuf->reg_id = cpu_to_be16(reg_id); 2708 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2709 2710 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2711 inbuf->len_const = 2712 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2713 ((0x3) << 12)); 2714 2715 memcpy(inbuf->reg_data, reg_data, reg_len); 2716 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2717 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2718 MLX4_CMD_WRAPPED); 2719 if (err) 2720 goto out; 2721 2722 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2723 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2724 mlx4_err(dev, 2725 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2726 reg_id, err); 2727 goto out; 2728 } 2729 2730 memcpy(reg_data, outbuf->reg_data, reg_len); 2731 out: 2732 mlx4_free_cmd_mailbox(dev, inbox); 2733 mlx4_free_cmd_mailbox(dev, outbox); 2734 return err; 2735 } 2736 2737 /* ConnectX registers IDs */ 2738 enum mlx4_reg_id { 2739 MLX4_REG_ID_PTYS = 0x5004, 2740 }; 2741 2742 /** 2743 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2744 * register 2745 * @dev: mlx4_dev. 2746 * @method: Access method Read/Write. 2747 * @ptys_reg: PTYS register data pointer. 2748 * 2749 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2750 * configuration 2751 * Returns 0 on success or a negative error code. 2752 */ 2753 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2754 enum mlx4_access_reg_method method, 2755 struct mlx4_ptys_reg *ptys_reg) 2756 { 2757 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2758 method, sizeof(*ptys_reg), ptys_reg); 2759 } 2760 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2761 2762 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2763 struct mlx4_vhcr *vhcr, 2764 struct mlx4_cmd_mailbox *inbox, 2765 struct mlx4_cmd_mailbox *outbox, 2766 struct mlx4_cmd_info *cmd) 2767 { 2768 struct mlx4_access_reg *inbuf = inbox->buf; 2769 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2770 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2771 2772 if (slave != mlx4_master_func_num(dev) && 2773 method == MLX4_ACCESS_REG_WRITE) 2774 return -EPERM; 2775 2776 if (reg_id == MLX4_REG_ID_PTYS) { 2777 struct mlx4_ptys_reg *ptys_reg = 2778 (struct mlx4_ptys_reg *)inbuf->reg_data; 2779 2780 ptys_reg->local_port = 2781 mlx4_slave_convert_port(dev, slave, 2782 ptys_reg->local_port); 2783 } 2784 2785 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2786 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2787 MLX4_CMD_NATIVE); 2788 } 2789 2790 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) 2791 { 2792 #define SET_PORT_GEN_PHV_VALID 0x10 2793 #define SET_PORT_GEN_PHV_EN 0x80 2794 2795 struct mlx4_cmd_mailbox *mailbox; 2796 struct mlx4_set_port_general_context *context; 2797 u32 in_mod; 2798 int err; 2799 2800 mailbox = mlx4_alloc_cmd_mailbox(dev); 2801 if (IS_ERR(mailbox)) 2802 return PTR_ERR(mailbox); 2803 context = mailbox->buf; 2804 2805 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; 2806 if (phv_bit) 2807 context->phv_en |= SET_PORT_GEN_PHV_EN; 2808 2809 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 2810 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 2811 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 2812 MLX4_CMD_NATIVE); 2813 2814 mlx4_free_cmd_mailbox(dev, mailbox); 2815 return err; 2816 } 2817 2818 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) 2819 { 2820 int err; 2821 struct mlx4_func_cap func_cap; 2822 2823 memset(&func_cap, 0, sizeof(func_cap)); 2824 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 2825 if (!err) 2826 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT; 2827 return err; 2828 } 2829 EXPORT_SYMBOL(get_phv_bit); 2830 2831 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 2832 { 2833 int ret; 2834 2835 if (mlx4_is_slave(dev)) 2836 return -EPERM; 2837 2838 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && 2839 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { 2840 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); 2841 if (!ret) 2842 dev->caps.phv_bit[port] = new_val; 2843 return ret; 2844 } 2845 2846 return -EOPNOTSUPP; 2847 } 2848 EXPORT_SYMBOL(set_phv_bit); 2849 2850 void mlx4_replace_zero_macs(struct mlx4_dev *dev) 2851 { 2852 int i; 2853 u8 mac_addr[ETH_ALEN]; 2854 2855 dev->port_random_macs = 0; 2856 for (i = 1; i <= dev->caps.num_ports; ++i) 2857 if (!dev->caps.def_mac[i] && 2858 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { 2859 eth_random_addr(mac_addr); 2860 dev->port_random_macs |= 1 << i; 2861 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); 2862 } 2863 } 2864 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); 2865