1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos = true; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 6] = "SRQ support", 88 [ 7] = "IPoIB checksum offload", 89 [ 8] = "P_Key violation counter", 90 [ 9] = "Q_Key violation counter", 91 [12] = "Dual Port Different Protocol (DPDP) support", 92 [15] = "Big LSO headers", 93 [16] = "MW support", 94 [17] = "APM support", 95 [18] = "Atomic ops support", 96 [19] = "Raw multicast support", 97 [20] = "Address vector port checking support", 98 [21] = "UD multicast support", 99 [30] = "IBoE support", 100 [32] = "Unicast loopback support", 101 [34] = "FCS header control", 102 [37] = "Wake On LAN (port1) support", 103 [38] = "Wake On LAN (port2) support", 104 [40] = "UDP RSS support", 105 [41] = "Unicast VEP steering support", 106 [42] = "Multicast VEP steering support", 107 [48] = "Counters support", 108 [52] = "RSS IP fragments support", 109 [53] = "Port ETS Scheduler support", 110 [55] = "Port link type sensing support", 111 [59] = "Port management change event support", 112 [61] = "64 byte EQE support", 113 [62] = "64 byte CQE support", 114 }; 115 int i; 116 117 mlx4_dbg(dev, "DEV_CAP flags:\n"); 118 for (i = 0; i < ARRAY_SIZE(fname); ++i) 119 if (fname[i] && (flags & (1LL << i))) 120 mlx4_dbg(dev, " %s\n", fname[i]); 121 } 122 123 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 124 { 125 static const char * const fname[] = { 126 [0] = "RSS support", 127 [1] = "RSS Toeplitz Hash Function support", 128 [2] = "RSS XOR Hash Function support", 129 [3] = "Device managed flow steering support", 130 [4] = "Automatic MAC reassignment support", 131 [5] = "Time stamping support", 132 [6] = "VST (control vlan insertion/stripping) support", 133 [7] = "FSM (MAC anti-spoofing) support", 134 [8] = "Dynamic QP updates support", 135 [9] = "Device managed flow steering IPoIB support", 136 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 137 [11] = "MAD DEMUX (Secure-Host) support", 138 [12] = "Large cache line (>64B) CQE stride support", 139 [13] = "Large cache line (>64B) EQE stride support", 140 [14] = "Ethernet protocol control support", 141 [15] = "Ethernet Backplane autoneg support", 142 [16] = "CONFIG DEV support", 143 [17] = "Asymmetric EQs support", 144 [18] = "More than 80 VFs support", 145 [19] = "Performance optimized for limited rule configuration flow steering support", 146 [20] = "Recoverable error events support", 147 [21] = "Port Remap support", 148 [22] = "QCN support", 149 [23] = "QP rate limiting support", 150 [24] = "Ethernet Flow control statistics support", 151 [25] = "Granular QoS per VF support", 152 [26] = "Port ETS Scheduler support", 153 [27] = "Port beacon support", 154 [28] = "RX-ALL support", 155 }; 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(fname); ++i) 159 if (fname[i] && (flags & (1LL << i))) 160 mlx4_dbg(dev, " %s\n", fname[i]); 161 } 162 163 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 u32 *inbox; 167 int err = 0; 168 169 #define MOD_STAT_CFG_IN_SIZE 0x100 170 171 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 172 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 173 174 mailbox = mlx4_alloc_cmd_mailbox(dev); 175 if (IS_ERR(mailbox)) 176 return PTR_ERR(mailbox); 177 inbox = mailbox->buf; 178 179 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 180 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 181 182 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 183 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 184 185 mlx4_free_cmd_mailbox(dev, mailbox); 186 return err; 187 } 188 189 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 190 { 191 struct mlx4_cmd_mailbox *mailbox; 192 u32 *outbox; 193 u8 in_modifier; 194 u8 field; 195 u16 field16; 196 int err; 197 198 #define QUERY_FUNC_BUS_OFFSET 0x00 199 #define QUERY_FUNC_DEVICE_OFFSET 0x01 200 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 201 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 202 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 203 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 204 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 205 206 mailbox = mlx4_alloc_cmd_mailbox(dev); 207 if (IS_ERR(mailbox)) 208 return PTR_ERR(mailbox); 209 outbox = mailbox->buf; 210 211 in_modifier = slave; 212 213 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 214 MLX4_CMD_QUERY_FUNC, 215 MLX4_CMD_TIME_CLASS_A, 216 MLX4_CMD_NATIVE); 217 if (err) 218 goto out; 219 220 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 221 func->bus = field & 0xf; 222 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 223 func->device = field & 0xf1; 224 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 225 func->function = field & 0x7; 226 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 227 func->physical_function = field & 0xf; 228 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 229 func->rsvd_eqs = field16 & 0xffff; 230 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 231 func->max_eq = field16 & 0xffff; 232 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 233 func->rsvd_uars = field & 0x0f; 234 235 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 236 func->bus, func->device, func->function, func->physical_function, 237 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 238 239 out: 240 mlx4_free_cmd_mailbox(dev, mailbox); 241 return err; 242 } 243 244 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 245 struct mlx4_vhcr *vhcr, 246 struct mlx4_cmd_mailbox *inbox, 247 struct mlx4_cmd_mailbox *outbox, 248 struct mlx4_cmd_info *cmd) 249 { 250 struct mlx4_priv *priv = mlx4_priv(dev); 251 u8 field, port; 252 u32 size, proxy_qp, qkey; 253 int err = 0; 254 struct mlx4_func func; 255 256 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 257 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 258 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 259 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 260 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 261 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 262 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 263 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 264 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 265 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 266 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 267 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 268 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 269 270 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 271 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 272 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 273 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 274 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 275 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 276 277 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 278 279 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 280 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 281 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 282 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 283 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 284 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 285 286 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 287 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 288 289 /* when opcode modifier = 1 */ 290 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 291 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 292 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 293 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 294 295 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 296 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 297 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 298 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 299 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 300 301 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 302 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 303 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 304 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 305 306 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 307 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 308 309 if (vhcr->op_modifier == 1) { 310 struct mlx4_active_ports actv_ports = 311 mlx4_get_active_ports(dev, slave); 312 int converted_port = mlx4_slave_convert_port( 313 dev, slave, vhcr->in_modifier); 314 315 if (converted_port < 0) 316 return -EINVAL; 317 318 vhcr->in_modifier = converted_port; 319 /* phys-port = logical-port */ 320 field = vhcr->in_modifier - 321 find_first_bit(actv_ports.ports, dev->caps.num_ports); 322 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 323 324 port = vhcr->in_modifier; 325 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 326 327 /* Set nic_info bit to mark new fields support */ 328 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 329 330 if (mlx4_vf_smi_enabled(dev, slave, port) && 331 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 332 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 333 MLX4_PUT(outbox->buf, qkey, 334 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 335 } 336 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 337 338 /* size is now the QP number */ 339 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 340 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 341 342 size += 2; 343 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 344 345 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 346 proxy_qp += 2; 347 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 348 349 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 350 QUERY_FUNC_CAP_PHYS_PORT_ID); 351 352 } else if (vhcr->op_modifier == 0) { 353 struct mlx4_active_ports actv_ports = 354 mlx4_get_active_ports(dev, slave); 355 /* enable rdma and ethernet interfaces, new quota locations, 356 * and reserved lkey 357 */ 358 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 359 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 360 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 361 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 362 363 field = min( 364 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 365 dev->caps.num_ports); 366 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 367 368 size = dev->caps.function_caps; /* set PF behaviours */ 369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 370 371 field = 0; /* protected FMR support not available as yet */ 372 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 373 374 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 375 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 376 size = dev->caps.num_qps; 377 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 378 379 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 380 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 381 size = dev->caps.num_srqs; 382 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 383 384 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 386 size = dev->caps.num_cqs; 387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 388 389 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 390 mlx4_QUERY_FUNC(dev, &func, slave)) { 391 size = vhcr->in_modifier & 392 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 393 dev->caps.num_eqs : 394 rounddown_pow_of_two(dev->caps.num_eqs); 395 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 396 size = dev->caps.reserved_eqs; 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 398 } else { 399 size = vhcr->in_modifier & 400 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 401 func.max_eq : 402 rounddown_pow_of_two(func.max_eq); 403 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 404 size = func.rsvd_eqs; 405 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 406 } 407 408 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 410 size = dev->caps.num_mpts; 411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 412 413 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 414 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 415 size = dev->caps.num_mtts; 416 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 417 418 size = dev->caps.num_mgms + dev->caps.num_amgms; 419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 420 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 421 422 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 423 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 424 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 425 426 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 427 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 428 } else 429 err = -EINVAL; 430 431 return err; 432 } 433 434 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 435 struct mlx4_func_cap *func_cap) 436 { 437 struct mlx4_cmd_mailbox *mailbox; 438 u32 *outbox; 439 u8 field, op_modifier; 440 u32 size, qkey; 441 int err = 0, quotas = 0; 442 u32 in_modifier; 443 444 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 445 in_modifier = op_modifier ? gen_or_port : 446 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 447 448 mailbox = mlx4_alloc_cmd_mailbox(dev); 449 if (IS_ERR(mailbox)) 450 return PTR_ERR(mailbox); 451 452 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 453 MLX4_CMD_QUERY_FUNC_CAP, 454 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 455 if (err) 456 goto out; 457 458 outbox = mailbox->buf; 459 460 if (!op_modifier) { 461 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 462 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 463 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 464 err = -EPROTONOSUPPORT; 465 goto out; 466 } 467 func_cap->flags = field; 468 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 469 470 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 471 func_cap->num_ports = field; 472 473 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 474 func_cap->pf_context_behaviour = size; 475 476 if (quotas) { 477 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 478 func_cap->qp_quota = size & 0xFFFFFF; 479 480 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 481 func_cap->srq_quota = size & 0xFFFFFF; 482 483 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 484 func_cap->cq_quota = size & 0xFFFFFF; 485 486 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 487 func_cap->mpt_quota = size & 0xFFFFFF; 488 489 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 490 func_cap->mtt_quota = size & 0xFFFFFF; 491 492 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 493 func_cap->mcg_quota = size & 0xFFFFFF; 494 495 } else { 496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 497 func_cap->qp_quota = size & 0xFFFFFF; 498 499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 500 func_cap->srq_quota = size & 0xFFFFFF; 501 502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 503 func_cap->cq_quota = size & 0xFFFFFF; 504 505 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 506 func_cap->mpt_quota = size & 0xFFFFFF; 507 508 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 509 func_cap->mtt_quota = size & 0xFFFFFF; 510 511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 512 func_cap->mcg_quota = size & 0xFFFFFF; 513 } 514 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 515 func_cap->max_eq = size & 0xFFFFFF; 516 517 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 518 func_cap->reserved_eq = size & 0xFFFFFF; 519 520 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 521 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 522 func_cap->reserved_lkey = size; 523 } else { 524 func_cap->reserved_lkey = 0; 525 } 526 527 func_cap->extra_flags = 0; 528 529 /* Mailbox data from 0x6c and onward should only be treated if 530 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 531 */ 532 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 533 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 534 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 535 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 536 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 537 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 538 } 539 540 goto out; 541 } 542 543 /* logical port query */ 544 if (gen_or_port > dev->caps.num_ports) { 545 err = -EINVAL; 546 goto out; 547 } 548 549 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 550 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 551 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 552 mlx4_err(dev, "VLAN is enforced on this port\n"); 553 err = -EPROTONOSUPPORT; 554 goto out; 555 } 556 557 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 558 mlx4_err(dev, "Force mac is enabled on this port\n"); 559 err = -EPROTONOSUPPORT; 560 goto out; 561 } 562 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 563 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 564 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 565 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 566 err = -EPROTONOSUPPORT; 567 goto out; 568 } 569 } 570 571 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 572 func_cap->physical_port = field; 573 if (func_cap->physical_port != gen_or_port) { 574 err = -ENOSYS; 575 goto out; 576 } 577 578 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 579 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 580 func_cap->qp0_qkey = qkey; 581 } else { 582 func_cap->qp0_qkey = 0; 583 } 584 585 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 586 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 587 588 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 589 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 590 591 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 592 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 593 594 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 595 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 596 597 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 598 MLX4_GET(func_cap->phys_port_id, outbox, 599 QUERY_FUNC_CAP_PHYS_PORT_ID); 600 601 /* All other resources are allocated by the master, but we still report 602 * 'num' and 'reserved' capabilities as follows: 603 * - num remains the maximum resource index 604 * - 'num - reserved' is the total available objects of a resource, but 605 * resource indices may be less than 'reserved' 606 * TODO: set per-resource quotas */ 607 608 out: 609 mlx4_free_cmd_mailbox(dev, mailbox); 610 611 return err; 612 } 613 614 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 615 { 616 struct mlx4_cmd_mailbox *mailbox; 617 u32 *outbox; 618 u8 field; 619 u32 field32, flags, ext_flags; 620 u16 size; 621 u16 stat_rate; 622 int err; 623 int i; 624 625 #define QUERY_DEV_CAP_OUT_SIZE 0x100 626 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 627 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 628 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 629 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 630 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 631 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 632 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 633 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 634 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 635 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 636 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 637 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 638 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 639 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 640 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 641 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 642 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 643 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 644 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 645 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 646 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 647 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 648 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 649 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 650 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 651 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 652 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 653 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 654 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 655 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 656 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 657 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 658 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 659 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 660 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 661 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 662 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 663 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 664 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 665 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 666 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 667 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 668 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 669 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 670 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 671 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 672 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 673 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 674 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 675 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 676 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 677 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 678 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 679 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 680 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 681 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 682 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 683 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 684 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 685 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 686 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 687 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 688 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 689 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 690 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 691 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 692 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 693 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 694 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 695 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 696 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 697 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 698 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 699 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 700 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 701 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 702 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 703 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 704 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 705 #define QUERY_DEV_CAP_VXLAN 0x9e 706 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 707 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 708 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 709 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 710 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 711 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 712 713 714 dev_cap->flags2 = 0; 715 mailbox = mlx4_alloc_cmd_mailbox(dev); 716 if (IS_ERR(mailbox)) 717 return PTR_ERR(mailbox); 718 outbox = mailbox->buf; 719 720 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 721 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 722 if (err) 723 goto out; 724 725 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 726 dev_cap->reserved_qps = 1 << (field & 0xf); 727 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 728 dev_cap->max_qps = 1 << (field & 0x1f); 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 730 dev_cap->reserved_srqs = 1 << (field >> 4); 731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 732 dev_cap->max_srqs = 1 << (field & 0x1f); 733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 734 dev_cap->max_cq_sz = 1 << field; 735 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 736 dev_cap->reserved_cqs = 1 << (field & 0xf); 737 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 738 dev_cap->max_cqs = 1 << (field & 0x1f); 739 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 740 dev_cap->max_mpts = 1 << (field & 0x3f); 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 742 dev_cap->reserved_eqs = 1 << (field & 0xf); 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 744 dev_cap->max_eqs = 1 << (field & 0xf); 745 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 746 dev_cap->reserved_mtts = 1 << (field >> 4); 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 748 dev_cap->max_mrw_sz = 1 << field; 749 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 750 dev_cap->reserved_mrws = 1 << (field & 0xf); 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 752 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 753 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 754 dev_cap->num_sys_eqs = size & 0xfff; 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 756 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 757 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 758 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 760 field &= 0x1f; 761 if (!field) 762 dev_cap->max_gso_sz = 0; 763 else 764 dev_cap->max_gso_sz = 1 << field; 765 766 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 767 if (field & 0x20) 768 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 769 if (field & 0x10) 770 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 771 field &= 0xf; 772 if (field) { 773 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 774 dev_cap->max_rss_tbl_sz = 1 << field; 775 } else 776 dev_cap->max_rss_tbl_sz = 0; 777 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 778 dev_cap->max_rdma_global = 1 << (field & 0x3f); 779 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 780 dev_cap->local_ca_ack_delay = field & 0x1f; 781 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 782 dev_cap->num_ports = field & 0xf; 783 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 784 dev_cap->max_msg_sz = 1 << (field & 0x1f); 785 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 786 if (field & 0x10) 787 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 788 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 789 if (field & 0x80) 790 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 791 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 792 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 793 if (field & 0x80) 794 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 795 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 796 if (field & 0x80) 797 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 798 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 799 dev_cap->fs_max_num_qp_per_entry = field; 800 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 801 if (field & 0x1) 802 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 803 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 804 dev_cap->stat_rate_support = stat_rate; 805 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 806 if (field & 0x80) 807 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 808 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 809 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 810 dev_cap->flags = flags | (u64)ext_flags << 32; 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 812 dev_cap->reserved_uars = field >> 4; 813 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 814 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 815 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 816 dev_cap->min_page_sz = 1 << field; 817 818 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 819 if (field & 0x80) { 820 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 821 dev_cap->bf_reg_size = 1 << (field & 0x1f); 822 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 823 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 824 field = 3; 825 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 826 } else { 827 dev_cap->bf_reg_size = 0; 828 } 829 830 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 831 dev_cap->max_sq_sg = field; 832 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 833 dev_cap->max_sq_desc_sz = size; 834 835 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 836 dev_cap->max_qp_per_mcg = 1 << field; 837 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 838 dev_cap->reserved_mgms = field & 0xf; 839 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 840 dev_cap->max_mcgs = 1 << field; 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 842 dev_cap->reserved_pds = field >> 4; 843 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 844 dev_cap->max_pds = 1 << (field & 0x3f); 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 846 dev_cap->reserved_xrcds = field >> 4; 847 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 848 dev_cap->max_xrcds = 1 << (field & 0x1f); 849 850 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 851 dev_cap->rdmarc_entry_sz = size; 852 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 853 dev_cap->qpc_entry_sz = size; 854 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 855 dev_cap->aux_entry_sz = size; 856 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 857 dev_cap->altc_entry_sz = size; 858 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 859 dev_cap->eqc_entry_sz = size; 860 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 861 dev_cap->cqc_entry_sz = size; 862 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 863 dev_cap->srq_entry_sz = size; 864 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 865 dev_cap->cmpt_entry_sz = size; 866 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 867 dev_cap->mtt_entry_sz = size; 868 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 869 dev_cap->dmpt_entry_sz = size; 870 871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 872 dev_cap->max_srq_sz = 1 << field; 873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 874 dev_cap->max_qp_sz = 1 << field; 875 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 876 dev_cap->resize_srq = field & 1; 877 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 878 dev_cap->max_rq_sg = field; 879 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 880 dev_cap->max_rq_desc_sz = size; 881 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 882 if (field & (1 << 4)) 883 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 884 if (field & (1 << 5)) 885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 886 if (field & (1 << 6)) 887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 888 if (field & (1 << 7)) 889 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 890 MLX4_GET(dev_cap->bmme_flags, outbox, 891 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 892 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 893 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 894 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 895 if (field & 0x20) 896 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 897 if (field & (1 << 2)) 898 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 899 MLX4_GET(dev_cap->reserved_lkey, outbox, 900 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 901 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 902 if (field32 & (1 << 0)) 903 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 904 if (field32 & (1 << 7)) 905 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 906 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 907 if (field & 1<<6) 908 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 909 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 910 if (field & 1<<3) 911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 912 if (field & (1 << 5)) 913 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 914 MLX4_GET(dev_cap->max_icm_sz, outbox, 915 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 916 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 917 MLX4_GET(dev_cap->max_counters, outbox, 918 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 919 920 MLX4_GET(field32, outbox, 921 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 922 if (field32 & (1 << 0)) 923 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 924 925 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 926 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 927 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 928 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 929 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 930 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 931 932 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 933 dev_cap->rl_caps.num_rates = size; 934 if (dev_cap->rl_caps.num_rates) { 935 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 936 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 937 dev_cap->rl_caps.max_val = size & 0xfff; 938 dev_cap->rl_caps.max_unit = size >> 14; 939 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 940 dev_cap->rl_caps.min_val = size & 0xfff; 941 dev_cap->rl_caps.min_unit = size >> 14; 942 } 943 944 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 945 if (field32 & (1 << 16)) 946 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 947 if (field32 & (1 << 26)) 948 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 949 if (field32 & (1 << 20)) 950 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 951 if (field32 & (1 << 21)) 952 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 953 954 for (i = 1; i <= dev_cap->num_ports; i++) { 955 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 956 if (err) 957 goto out; 958 } 959 960 /* 961 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 962 * we can't use any EQs whose doorbell falls on that page, 963 * even if the EQ itself isn't reserved. 964 */ 965 if (dev_cap->num_sys_eqs == 0) 966 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 967 dev_cap->reserved_eqs); 968 else 969 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 970 971 out: 972 mlx4_free_cmd_mailbox(dev, mailbox); 973 return err; 974 } 975 976 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 977 { 978 if (dev_cap->bf_reg_size > 0) 979 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 980 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 981 else 982 mlx4_dbg(dev, "BlueFlame not available\n"); 983 984 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 985 dev_cap->bmme_flags, dev_cap->reserved_lkey); 986 mlx4_dbg(dev, "Max ICM size %lld MB\n", 987 (unsigned long long) dev_cap->max_icm_sz >> 20); 988 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 989 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 990 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 991 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 992 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 993 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 994 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 995 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 996 dev_cap->eqc_entry_sz); 997 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 998 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 999 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1000 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1001 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1002 dev_cap->max_pds, dev_cap->reserved_mgms); 1003 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1004 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1005 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1006 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1007 dev_cap->port_cap[1].max_port_width); 1008 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1009 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1010 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1011 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1012 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1013 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1014 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1015 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1016 dev_cap->dmfs_high_rate_qpn_base); 1017 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1018 dev_cap->dmfs_high_rate_qpn_range); 1019 1020 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1021 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1022 1023 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1024 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1025 rl_caps->min_unit, rl_caps->min_val); 1026 } 1027 1028 dump_dev_cap_flags(dev, dev_cap->flags); 1029 dump_dev_cap_flags2(dev, dev_cap->flags2); 1030 } 1031 1032 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1033 { 1034 struct mlx4_cmd_mailbox *mailbox; 1035 u32 *outbox; 1036 u8 field; 1037 u32 field32; 1038 int err; 1039 1040 mailbox = mlx4_alloc_cmd_mailbox(dev); 1041 if (IS_ERR(mailbox)) 1042 return PTR_ERR(mailbox); 1043 outbox = mailbox->buf; 1044 1045 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1046 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1047 MLX4_CMD_TIME_CLASS_A, 1048 MLX4_CMD_NATIVE); 1049 1050 if (err) 1051 goto out; 1052 1053 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1054 port_cap->max_vl = field >> 4; 1055 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1056 port_cap->ib_mtu = field >> 4; 1057 port_cap->max_port_width = field & 0xf; 1058 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1059 port_cap->max_gids = 1 << (field & 0xf); 1060 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1061 port_cap->max_pkeys = 1 << (field & 0xf); 1062 } else { 1063 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1064 #define QUERY_PORT_MTU_OFFSET 0x01 1065 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1066 #define QUERY_PORT_WIDTH_OFFSET 0x06 1067 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1068 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1069 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1070 #define QUERY_PORT_MAC_OFFSET 0x10 1071 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1072 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1073 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1074 1075 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1076 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1077 if (err) 1078 goto out; 1079 1080 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1081 port_cap->supported_port_types = field & 3; 1082 port_cap->suggested_type = (field >> 3) & 1; 1083 port_cap->default_sense = (field >> 4) & 1; 1084 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1085 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1086 port_cap->ib_mtu = field & 0xf; 1087 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1088 port_cap->max_port_width = field & 0xf; 1089 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1090 port_cap->max_gids = 1 << (field >> 4); 1091 port_cap->max_pkeys = 1 << (field & 0xf); 1092 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1093 port_cap->max_vl = field & 0xf; 1094 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1095 port_cap->log_max_macs = field & 0xf; 1096 port_cap->log_max_vlans = field >> 4; 1097 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1098 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1099 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1100 port_cap->trans_type = field32 >> 24; 1101 port_cap->vendor_oui = field32 & 0xffffff; 1102 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1103 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1104 } 1105 1106 out: 1107 mlx4_free_cmd_mailbox(dev, mailbox); 1108 return err; 1109 } 1110 1111 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1112 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1113 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1114 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1115 1116 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1117 struct mlx4_vhcr *vhcr, 1118 struct mlx4_cmd_mailbox *inbox, 1119 struct mlx4_cmd_mailbox *outbox, 1120 struct mlx4_cmd_info *cmd) 1121 { 1122 u64 flags; 1123 int err = 0; 1124 u8 field; 1125 u16 field16; 1126 u32 bmme_flags, field32; 1127 int real_port; 1128 int slave_port; 1129 int first_port; 1130 struct mlx4_active_ports actv_ports; 1131 1132 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1133 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1134 if (err) 1135 return err; 1136 1137 /* add port mng change event capability and disable mw type 1 1138 * unconditionally to slaves 1139 */ 1140 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1141 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1142 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1143 actv_ports = mlx4_get_active_ports(dev, slave); 1144 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1145 for (slave_port = 0, real_port = first_port; 1146 real_port < first_port + 1147 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1148 ++real_port, ++slave_port) { 1149 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1150 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1151 else 1152 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1153 } 1154 for (; slave_port < dev->caps.num_ports; ++slave_port) 1155 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1156 1157 /* Not exposing RSS IP fragments to guests */ 1158 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1159 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1160 1161 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1162 field &= ~0x0F; 1163 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1164 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1165 1166 /* For guests, disable timestamp */ 1167 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1168 field &= 0x7f; 1169 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1170 1171 /* For guests, disable vxlan tunneling and QoS support */ 1172 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1173 field &= 0xd7; 1174 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1175 1176 /* For guests, disable port BEACON */ 1177 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1178 field &= 0x7f; 1179 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1180 1181 /* For guests, report Blueflame disabled */ 1182 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1183 field &= 0x7f; 1184 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1185 1186 /* For guests, disable mw type 2 and port remap*/ 1187 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1188 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1189 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1190 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1191 1192 /* turn off device-managed steering capability if not enabled */ 1193 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1194 MLX4_GET(field, outbox->buf, 1195 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1196 field &= 0x7f; 1197 MLX4_PUT(outbox->buf, field, 1198 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1199 } 1200 1201 /* turn off ipoib managed steering for guests */ 1202 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1203 field &= ~0x80; 1204 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1205 1206 /* turn off host side virt features (VST, FSM, etc) for guests */ 1207 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1208 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1209 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1210 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1211 1212 /* turn off QCN for guests */ 1213 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1214 field &= 0xfe; 1215 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1216 1217 /* turn off QP max-rate limiting for guests */ 1218 field16 = 0; 1219 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1220 1221 /* turn off QoS per VF support for guests */ 1222 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1223 field &= 0xef; 1224 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1225 1226 /* turn off ignore FCS feature for guests */ 1227 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1228 field &= 0xfb; 1229 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1230 1231 return 0; 1232 } 1233 1234 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1235 struct mlx4_vhcr *vhcr, 1236 struct mlx4_cmd_mailbox *inbox, 1237 struct mlx4_cmd_mailbox *outbox, 1238 struct mlx4_cmd_info *cmd) 1239 { 1240 struct mlx4_priv *priv = mlx4_priv(dev); 1241 u64 def_mac; 1242 u8 port_type; 1243 u16 short_field; 1244 int err; 1245 int admin_link_state; 1246 int port = mlx4_slave_convert_port(dev, slave, 1247 vhcr->in_modifier & 0xFF); 1248 1249 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1250 #define MLX4_PORT_LINK_UP_MASK 0x80 1251 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1252 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1253 1254 if (port < 0) 1255 return -EINVAL; 1256 1257 /* Protect against untrusted guests: enforce that this is the 1258 * QUERY_PORT general query. 1259 */ 1260 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1261 return -EINVAL; 1262 1263 vhcr->in_modifier = port; 1264 1265 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1266 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1267 MLX4_CMD_NATIVE); 1268 1269 if (!err && dev->caps.function != slave) { 1270 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1271 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1272 1273 /* get port type - currently only eth is enabled */ 1274 MLX4_GET(port_type, outbox->buf, 1275 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1276 1277 /* No link sensing allowed */ 1278 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1279 /* set port type to currently operating port type */ 1280 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1281 1282 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1283 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1284 port_type |= MLX4_PORT_LINK_UP_MASK; 1285 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1286 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1287 1288 MLX4_PUT(outbox->buf, port_type, 1289 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1290 1291 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1292 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1293 else 1294 short_field = 1; /* slave max gids */ 1295 MLX4_PUT(outbox->buf, short_field, 1296 QUERY_PORT_CUR_MAX_GID_OFFSET); 1297 1298 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1299 MLX4_PUT(outbox->buf, short_field, 1300 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1301 } 1302 1303 return err; 1304 } 1305 1306 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1307 int *gid_tbl_len, int *pkey_tbl_len) 1308 { 1309 struct mlx4_cmd_mailbox *mailbox; 1310 u32 *outbox; 1311 u16 field; 1312 int err; 1313 1314 mailbox = mlx4_alloc_cmd_mailbox(dev); 1315 if (IS_ERR(mailbox)) 1316 return PTR_ERR(mailbox); 1317 1318 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1319 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1320 MLX4_CMD_WRAPPED); 1321 if (err) 1322 goto out; 1323 1324 outbox = mailbox->buf; 1325 1326 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1327 *gid_tbl_len = field; 1328 1329 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1330 *pkey_tbl_len = field; 1331 1332 out: 1333 mlx4_free_cmd_mailbox(dev, mailbox); 1334 return err; 1335 } 1336 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1337 1338 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1339 { 1340 struct mlx4_cmd_mailbox *mailbox; 1341 struct mlx4_icm_iter iter; 1342 __be64 *pages; 1343 int lg; 1344 int nent = 0; 1345 int i; 1346 int err = 0; 1347 int ts = 0, tc = 0; 1348 1349 mailbox = mlx4_alloc_cmd_mailbox(dev); 1350 if (IS_ERR(mailbox)) 1351 return PTR_ERR(mailbox); 1352 pages = mailbox->buf; 1353 1354 for (mlx4_icm_first(icm, &iter); 1355 !mlx4_icm_last(&iter); 1356 mlx4_icm_next(&iter)) { 1357 /* 1358 * We have to pass pages that are aligned to their 1359 * size, so find the least significant 1 in the 1360 * address or size and use that as our log2 size. 1361 */ 1362 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1363 if (lg < MLX4_ICM_PAGE_SHIFT) { 1364 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1365 MLX4_ICM_PAGE_SIZE, 1366 (unsigned long long) mlx4_icm_addr(&iter), 1367 mlx4_icm_size(&iter)); 1368 err = -EINVAL; 1369 goto out; 1370 } 1371 1372 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1373 if (virt != -1) { 1374 pages[nent * 2] = cpu_to_be64(virt); 1375 virt += 1 << lg; 1376 } 1377 1378 pages[nent * 2 + 1] = 1379 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1380 (lg - MLX4_ICM_PAGE_SHIFT)); 1381 ts += 1 << (lg - 10); 1382 ++tc; 1383 1384 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1385 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1386 MLX4_CMD_TIME_CLASS_B, 1387 MLX4_CMD_NATIVE); 1388 if (err) 1389 goto out; 1390 nent = 0; 1391 } 1392 } 1393 } 1394 1395 if (nent) 1396 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1397 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1398 if (err) 1399 goto out; 1400 1401 switch (op) { 1402 case MLX4_CMD_MAP_FA: 1403 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1404 break; 1405 case MLX4_CMD_MAP_ICM_AUX: 1406 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1407 break; 1408 case MLX4_CMD_MAP_ICM: 1409 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1410 tc, ts, (unsigned long long) virt - (ts << 10)); 1411 break; 1412 } 1413 1414 out: 1415 mlx4_free_cmd_mailbox(dev, mailbox); 1416 return err; 1417 } 1418 1419 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1420 { 1421 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1422 } 1423 1424 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1425 { 1426 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1427 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1428 } 1429 1430 1431 int mlx4_RUN_FW(struct mlx4_dev *dev) 1432 { 1433 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1434 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1435 } 1436 1437 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1438 { 1439 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1440 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1441 struct mlx4_cmd_mailbox *mailbox; 1442 u32 *outbox; 1443 int err = 0; 1444 u64 fw_ver; 1445 u16 cmd_if_rev; 1446 u8 lg; 1447 1448 #define QUERY_FW_OUT_SIZE 0x100 1449 #define QUERY_FW_VER_OFFSET 0x00 1450 #define QUERY_FW_PPF_ID 0x09 1451 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1452 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1453 #define QUERY_FW_ERR_START_OFFSET 0x30 1454 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1455 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1456 1457 #define QUERY_FW_SIZE_OFFSET 0x00 1458 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1459 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1460 1461 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1462 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1463 1464 #define QUERY_FW_CLOCK_OFFSET 0x50 1465 #define QUERY_FW_CLOCK_BAR 0x58 1466 1467 mailbox = mlx4_alloc_cmd_mailbox(dev); 1468 if (IS_ERR(mailbox)) 1469 return PTR_ERR(mailbox); 1470 outbox = mailbox->buf; 1471 1472 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1473 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1474 if (err) 1475 goto out; 1476 1477 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1478 /* 1479 * FW subminor version is at more significant bits than minor 1480 * version, so swap here. 1481 */ 1482 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1483 ((fw_ver & 0xffff0000ull) >> 16) | 1484 ((fw_ver & 0x0000ffffull) << 16); 1485 1486 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1487 dev->caps.function = lg; 1488 1489 if (mlx4_is_slave(dev)) 1490 goto out; 1491 1492 1493 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1494 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1495 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1496 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1497 cmd_if_rev); 1498 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1499 (int) (dev->caps.fw_ver >> 32), 1500 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1501 (int) dev->caps.fw_ver & 0xffff); 1502 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1503 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1504 err = -ENODEV; 1505 goto out; 1506 } 1507 1508 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1509 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1510 1511 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1512 cmd->max_cmds = 1 << lg; 1513 1514 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1515 (int) (dev->caps.fw_ver >> 32), 1516 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1517 (int) dev->caps.fw_ver & 0xffff, 1518 cmd_if_rev, cmd->max_cmds); 1519 1520 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1521 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1522 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1523 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1524 1525 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1526 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1527 1528 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1529 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1530 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1531 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1532 1533 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1534 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1535 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1536 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1537 fw->comm_bar, fw->comm_base); 1538 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1539 1540 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1541 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1542 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1543 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1544 fw->clock_bar, fw->clock_offset); 1545 1546 /* 1547 * Round up number of system pages needed in case 1548 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1549 */ 1550 fw->fw_pages = 1551 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1552 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1553 1554 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1555 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1556 1557 out: 1558 mlx4_free_cmd_mailbox(dev, mailbox); 1559 return err; 1560 } 1561 1562 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1563 struct mlx4_vhcr *vhcr, 1564 struct mlx4_cmd_mailbox *inbox, 1565 struct mlx4_cmd_mailbox *outbox, 1566 struct mlx4_cmd_info *cmd) 1567 { 1568 u8 *outbuf; 1569 int err; 1570 1571 outbuf = outbox->buf; 1572 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1573 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1574 if (err) 1575 return err; 1576 1577 /* for slaves, set pci PPF ID to invalid and zero out everything 1578 * else except FW version */ 1579 outbuf[0] = outbuf[1] = 0; 1580 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1581 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1582 1583 return 0; 1584 } 1585 1586 static void get_board_id(void *vsd, char *board_id) 1587 { 1588 int i; 1589 1590 #define VSD_OFFSET_SIG1 0x00 1591 #define VSD_OFFSET_SIG2 0xde 1592 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1593 #define VSD_OFFSET_TS_BOARD_ID 0x20 1594 1595 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1596 1597 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1598 1599 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1600 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1601 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1602 } else { 1603 /* 1604 * The board ID is a string but the firmware byte 1605 * swaps each 4-byte word before passing it back to 1606 * us. Therefore we need to swab it before printing. 1607 */ 1608 for (i = 0; i < 4; ++i) 1609 ((u32 *) board_id)[i] = 1610 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1611 } 1612 } 1613 1614 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1615 { 1616 struct mlx4_cmd_mailbox *mailbox; 1617 u32 *outbox; 1618 int err; 1619 1620 #define QUERY_ADAPTER_OUT_SIZE 0x100 1621 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1622 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1623 1624 mailbox = mlx4_alloc_cmd_mailbox(dev); 1625 if (IS_ERR(mailbox)) 1626 return PTR_ERR(mailbox); 1627 outbox = mailbox->buf; 1628 1629 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1630 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1631 if (err) 1632 goto out; 1633 1634 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1635 1636 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1637 adapter->board_id); 1638 1639 out: 1640 mlx4_free_cmd_mailbox(dev, mailbox); 1641 return err; 1642 } 1643 1644 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1645 { 1646 struct mlx4_cmd_mailbox *mailbox; 1647 __be32 *inbox; 1648 int err; 1649 static const u8 a0_dmfs_hw_steering[] = { 1650 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1651 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1652 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1653 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1654 }; 1655 1656 #define INIT_HCA_IN_SIZE 0x200 1657 #define INIT_HCA_VERSION_OFFSET 0x000 1658 #define INIT_HCA_VERSION 2 1659 #define INIT_HCA_VXLAN_OFFSET 0x0c 1660 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1661 #define INIT_HCA_FLAGS_OFFSET 0x014 1662 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1663 #define INIT_HCA_QPC_OFFSET 0x020 1664 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1665 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1666 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1667 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1668 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1669 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1670 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1671 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1672 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1673 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1674 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1675 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1676 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1677 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1678 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1679 #define INIT_HCA_MCAST_OFFSET 0x0c0 1680 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1681 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1682 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1683 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1684 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1685 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1686 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1687 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1688 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1689 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1690 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1691 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1692 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1693 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1694 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1695 #define INIT_HCA_TPT_OFFSET 0x0f0 1696 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1697 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1698 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1699 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1700 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1701 #define INIT_HCA_UAR_OFFSET 0x120 1702 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1703 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1704 1705 mailbox = mlx4_alloc_cmd_mailbox(dev); 1706 if (IS_ERR(mailbox)) 1707 return PTR_ERR(mailbox); 1708 inbox = mailbox->buf; 1709 1710 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1711 1712 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1713 (ilog2(cache_line_size()) - 4) << 5; 1714 1715 #if defined(__LITTLE_ENDIAN) 1716 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1717 #elif defined(__BIG_ENDIAN) 1718 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1719 #else 1720 #error Host endianness not defined 1721 #endif 1722 /* Check port for UD address vector: */ 1723 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1724 1725 /* Enable IPoIB checksumming if we can: */ 1726 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1727 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1728 1729 /* Enable QoS support if module parameter set */ 1730 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1731 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1732 1733 /* enable counters */ 1734 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1735 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1736 1737 /* Enable RSS spread to fragmented IP packets when supported */ 1738 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1739 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1740 1741 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1742 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1743 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1744 dev->caps.eqe_size = 64; 1745 dev->caps.eqe_factor = 1; 1746 } else { 1747 dev->caps.eqe_size = 32; 1748 dev->caps.eqe_factor = 0; 1749 } 1750 1751 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1752 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1753 dev->caps.cqe_size = 64; 1754 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1755 } else { 1756 dev->caps.cqe_size = 32; 1757 } 1758 1759 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1760 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1761 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1762 dev->caps.eqe_size = cache_line_size(); 1763 dev->caps.cqe_size = cache_line_size(); 1764 dev->caps.eqe_factor = 0; 1765 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1766 (ilog2(dev->caps.eqe_size) - 5)), 1767 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1768 1769 /* User still need to know to support CQE > 32B */ 1770 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1771 } 1772 1773 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1774 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1775 1776 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1777 1778 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1779 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1780 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1781 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1782 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1783 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1784 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1785 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1786 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1787 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1788 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1789 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1790 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1791 1792 /* steering attributes */ 1793 if (dev->caps.steering_mode == 1794 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1795 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1796 cpu_to_be32(1 << 1797 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1798 1799 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1800 MLX4_PUT(inbox, param->log_mc_entry_sz, 1801 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1802 MLX4_PUT(inbox, param->log_mc_table_sz, 1803 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1804 /* Enable Ethernet flow steering 1805 * with udp unicast and tcp unicast 1806 */ 1807 if (dev->caps.dmfs_high_steer_mode != 1808 MLX4_STEERING_DMFS_A0_STATIC) 1809 MLX4_PUT(inbox, 1810 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1811 INIT_HCA_FS_ETH_BITS_OFFSET); 1812 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1813 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1814 /* Enable IPoIB flow steering 1815 * with udp unicast and tcp unicast 1816 */ 1817 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1818 INIT_HCA_FS_IB_BITS_OFFSET); 1819 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1820 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1821 1822 if (dev->caps.dmfs_high_steer_mode != 1823 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1824 MLX4_PUT(inbox, 1825 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1826 << 6)), 1827 INIT_HCA_FS_A0_OFFSET); 1828 } else { 1829 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1830 MLX4_PUT(inbox, param->log_mc_entry_sz, 1831 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1832 MLX4_PUT(inbox, param->log_mc_hash_sz, 1833 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1834 MLX4_PUT(inbox, param->log_mc_table_sz, 1835 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1836 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1837 MLX4_PUT(inbox, (u8) (1 << 3), 1838 INIT_HCA_UC_STEERING_OFFSET); 1839 } 1840 1841 /* TPT attributes */ 1842 1843 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1844 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1845 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1846 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1847 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1848 1849 /* UAR attributes */ 1850 1851 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1852 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1853 1854 /* set parser VXLAN attributes */ 1855 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1856 u8 parser_params = 0; 1857 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1858 } 1859 1860 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1861 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 1862 1863 if (err) 1864 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1865 1866 mlx4_free_cmd_mailbox(dev, mailbox); 1867 return err; 1868 } 1869 1870 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1871 struct mlx4_init_hca_param *param) 1872 { 1873 struct mlx4_cmd_mailbox *mailbox; 1874 __be32 *outbox; 1875 u32 dword_field; 1876 int err; 1877 u8 byte_field; 1878 static const u8 a0_dmfs_query_hw_steering[] = { 1879 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1880 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1881 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1882 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1883 }; 1884 1885 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1886 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1887 1888 mailbox = mlx4_alloc_cmd_mailbox(dev); 1889 if (IS_ERR(mailbox)) 1890 return PTR_ERR(mailbox); 1891 outbox = mailbox->buf; 1892 1893 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1894 MLX4_CMD_QUERY_HCA, 1895 MLX4_CMD_TIME_CLASS_B, 1896 !mlx4_is_slave(dev)); 1897 if (err) 1898 goto out; 1899 1900 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1901 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1902 1903 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1904 1905 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1906 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1907 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1908 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1909 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1910 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1911 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1912 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1913 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1914 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1915 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1916 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1917 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1918 1919 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1920 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1921 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1922 } else { 1923 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1924 if (byte_field & 0x8) 1925 param->steering_mode = MLX4_STEERING_MODE_B0; 1926 else 1927 param->steering_mode = MLX4_STEERING_MODE_A0; 1928 } 1929 1930 if (dword_field & (1 << 13)) 1931 param->rss_ip_frags = 1; 1932 1933 /* steering attributes */ 1934 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1935 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1936 MLX4_GET(param->log_mc_entry_sz, outbox, 1937 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1938 MLX4_GET(param->log_mc_table_sz, outbox, 1939 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1940 MLX4_GET(byte_field, outbox, 1941 INIT_HCA_FS_A0_OFFSET); 1942 param->dmfs_high_steer_mode = 1943 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 1944 } else { 1945 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1946 MLX4_GET(param->log_mc_entry_sz, outbox, 1947 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1948 MLX4_GET(param->log_mc_hash_sz, outbox, 1949 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1950 MLX4_GET(param->log_mc_table_sz, outbox, 1951 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1952 } 1953 1954 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1955 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1956 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1957 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1958 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1959 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1960 1961 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1962 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1963 if (byte_field) { 1964 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1965 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 1966 param->cqe_size = 1 << ((byte_field & 1967 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 1968 param->eqe_size = 1 << (((byte_field & 1969 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 1970 } 1971 1972 /* TPT attributes */ 1973 1974 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1975 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1976 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1977 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1978 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1979 1980 /* UAR attributes */ 1981 1982 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1983 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1984 1985 out: 1986 mlx4_free_cmd_mailbox(dev, mailbox); 1987 1988 return err; 1989 } 1990 1991 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 1992 { 1993 struct mlx4_cmd_mailbox *mailbox; 1994 __be32 *outbox; 1995 int err; 1996 1997 mailbox = mlx4_alloc_cmd_mailbox(dev); 1998 if (IS_ERR(mailbox)) { 1999 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2000 return PTR_ERR(mailbox); 2001 } 2002 outbox = mailbox->buf; 2003 2004 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2005 MLX4_CMD_QUERY_HCA, 2006 MLX4_CMD_TIME_CLASS_B, 2007 !mlx4_is_slave(dev)); 2008 if (err) { 2009 mlx4_warn(dev, "hca_core_clock update failed\n"); 2010 goto out; 2011 } 2012 2013 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2014 2015 out: 2016 mlx4_free_cmd_mailbox(dev, mailbox); 2017 2018 return err; 2019 } 2020 2021 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2022 * and real QP0 are active, so that the paravirtualized QP0 is ready 2023 * to operate */ 2024 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2025 { 2026 struct mlx4_priv *priv = mlx4_priv(dev); 2027 /* irrelevant if not infiniband */ 2028 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2029 priv->mfunc.master.qp0_state[port].qp0_active) 2030 return 1; 2031 return 0; 2032 } 2033 2034 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2035 struct mlx4_vhcr *vhcr, 2036 struct mlx4_cmd_mailbox *inbox, 2037 struct mlx4_cmd_mailbox *outbox, 2038 struct mlx4_cmd_info *cmd) 2039 { 2040 struct mlx4_priv *priv = mlx4_priv(dev); 2041 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2042 int err; 2043 2044 if (port < 0) 2045 return -EINVAL; 2046 2047 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2048 return 0; 2049 2050 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2051 /* Enable port only if it was previously disabled */ 2052 if (!priv->mfunc.master.init_port_ref[port]) { 2053 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2054 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2055 if (err) 2056 return err; 2057 } 2058 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2059 } else { 2060 if (slave == mlx4_master_func_num(dev)) { 2061 if (check_qp0_state(dev, slave, port) && 2062 !priv->mfunc.master.qp0_state[port].port_active) { 2063 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2064 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2065 if (err) 2066 return err; 2067 priv->mfunc.master.qp0_state[port].port_active = 1; 2068 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2069 } 2070 } else 2071 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2072 } 2073 ++priv->mfunc.master.init_port_ref[port]; 2074 return 0; 2075 } 2076 2077 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2078 { 2079 struct mlx4_cmd_mailbox *mailbox; 2080 u32 *inbox; 2081 int err; 2082 u32 flags; 2083 u16 field; 2084 2085 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2086 #define INIT_PORT_IN_SIZE 256 2087 #define INIT_PORT_FLAGS_OFFSET 0x00 2088 #define INIT_PORT_FLAG_SIG (1 << 18) 2089 #define INIT_PORT_FLAG_NG (1 << 17) 2090 #define INIT_PORT_FLAG_G0 (1 << 16) 2091 #define INIT_PORT_VL_SHIFT 4 2092 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2093 #define INIT_PORT_MTU_OFFSET 0x04 2094 #define INIT_PORT_MAX_GID_OFFSET 0x06 2095 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2096 #define INIT_PORT_GUID0_OFFSET 0x10 2097 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2098 #define INIT_PORT_SI_GUID_OFFSET 0x20 2099 2100 mailbox = mlx4_alloc_cmd_mailbox(dev); 2101 if (IS_ERR(mailbox)) 2102 return PTR_ERR(mailbox); 2103 inbox = mailbox->buf; 2104 2105 flags = 0; 2106 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2107 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2108 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2109 2110 field = 128 << dev->caps.ib_mtu_cap[port]; 2111 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2112 field = dev->caps.gid_table_len[port]; 2113 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2114 field = dev->caps.pkey_table_len[port]; 2115 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2116 2117 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2118 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2119 2120 mlx4_free_cmd_mailbox(dev, mailbox); 2121 } else 2122 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2123 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2124 2125 if (!err) 2126 mlx4_hca_core_clock_update(dev); 2127 2128 return err; 2129 } 2130 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2131 2132 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2133 struct mlx4_vhcr *vhcr, 2134 struct mlx4_cmd_mailbox *inbox, 2135 struct mlx4_cmd_mailbox *outbox, 2136 struct mlx4_cmd_info *cmd) 2137 { 2138 struct mlx4_priv *priv = mlx4_priv(dev); 2139 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2140 int err; 2141 2142 if (port < 0) 2143 return -EINVAL; 2144 2145 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2146 (1 << port))) 2147 return 0; 2148 2149 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2150 if (priv->mfunc.master.init_port_ref[port] == 1) { 2151 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2152 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2153 if (err) 2154 return err; 2155 } 2156 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2157 } else { 2158 /* infiniband port */ 2159 if (slave == mlx4_master_func_num(dev)) { 2160 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2161 priv->mfunc.master.qp0_state[port].port_active) { 2162 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2163 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2164 if (err) 2165 return err; 2166 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2167 priv->mfunc.master.qp0_state[port].port_active = 0; 2168 } 2169 } else 2170 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2171 } 2172 --priv->mfunc.master.init_port_ref[port]; 2173 return 0; 2174 } 2175 2176 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2177 { 2178 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2179 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2180 } 2181 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2182 2183 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2184 { 2185 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2186 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2187 } 2188 2189 struct mlx4_config_dev { 2190 __be32 update_flags; 2191 __be32 rsvd1[3]; 2192 __be16 vxlan_udp_dport; 2193 __be16 rsvd2; 2194 __be32 rsvd3; 2195 __be32 roce_flags; 2196 __be32 rsvd4[25]; 2197 __be16 rsvd5; 2198 u8 rsvd6; 2199 u8 rx_checksum_val; 2200 }; 2201 2202 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2203 #define MLX4_DISABLE_RX_PORT BIT(18) 2204 2205 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2206 { 2207 int err; 2208 struct mlx4_cmd_mailbox *mailbox; 2209 2210 mailbox = mlx4_alloc_cmd_mailbox(dev); 2211 if (IS_ERR(mailbox)) 2212 return PTR_ERR(mailbox); 2213 2214 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2215 2216 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2217 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2218 2219 mlx4_free_cmd_mailbox(dev, mailbox); 2220 return err; 2221 } 2222 2223 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2224 { 2225 int err; 2226 struct mlx4_cmd_mailbox *mailbox; 2227 2228 mailbox = mlx4_alloc_cmd_mailbox(dev); 2229 if (IS_ERR(mailbox)) 2230 return PTR_ERR(mailbox); 2231 2232 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2233 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2234 2235 if (!err) 2236 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2237 2238 mlx4_free_cmd_mailbox(dev, mailbox); 2239 return err; 2240 } 2241 2242 /* Conversion between the HW values and the actual functionality. 2243 * The value represented by the array index, 2244 * and the functionality determined by the flags. 2245 */ 2246 static const u8 config_dev_csum_flags[] = { 2247 [0] = 0, 2248 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2249 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2250 MLX4_RX_CSUM_MODE_L4, 2251 [3] = MLX4_RX_CSUM_MODE_L4 | 2252 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2253 MLX4_RX_CSUM_MODE_MULTI_VLAN 2254 }; 2255 2256 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2257 struct mlx4_config_dev_params *params) 2258 { 2259 struct mlx4_config_dev config_dev = {0}; 2260 int err; 2261 u8 csum_mask; 2262 2263 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2264 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2265 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2266 2267 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2268 return -ENOTSUPP; 2269 2270 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2271 if (err) 2272 return err; 2273 2274 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2275 CONFIG_DEV_RX_CSUM_MODE_MASK; 2276 2277 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2278 return -EINVAL; 2279 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2280 2281 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2282 CONFIG_DEV_RX_CSUM_MODE_MASK; 2283 2284 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2285 return -EINVAL; 2286 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2287 2288 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2289 2290 return 0; 2291 } 2292 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2293 2294 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2295 { 2296 struct mlx4_config_dev config_dev; 2297 2298 memset(&config_dev, 0, sizeof(config_dev)); 2299 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2300 config_dev.vxlan_udp_dport = udp_port; 2301 2302 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2303 } 2304 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2305 2306 #define CONFIG_DISABLE_RX_PORT BIT(15) 2307 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2308 { 2309 struct mlx4_config_dev config_dev; 2310 2311 memset(&config_dev, 0, sizeof(config_dev)); 2312 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2313 if (dis) 2314 config_dev.roce_flags = 2315 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2316 2317 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2318 } 2319 2320 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2321 { 2322 struct mlx4_cmd_mailbox *mailbox; 2323 struct { 2324 __be32 v_port1; 2325 __be32 v_port2; 2326 } *v2p; 2327 int err; 2328 2329 mailbox = mlx4_alloc_cmd_mailbox(dev); 2330 if (IS_ERR(mailbox)) 2331 return -ENOMEM; 2332 2333 v2p = mailbox->buf; 2334 v2p->v_port1 = cpu_to_be32(port1); 2335 v2p->v_port2 = cpu_to_be32(port2); 2336 2337 err = mlx4_cmd(dev, mailbox->dma, 0, 2338 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2339 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2340 2341 mlx4_free_cmd_mailbox(dev, mailbox); 2342 return err; 2343 } 2344 2345 2346 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2347 { 2348 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2349 MLX4_CMD_SET_ICM_SIZE, 2350 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2351 if (ret) 2352 return ret; 2353 2354 /* 2355 * Round up number of system pages needed in case 2356 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2357 */ 2358 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2359 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2360 2361 return 0; 2362 } 2363 2364 int mlx4_NOP(struct mlx4_dev *dev) 2365 { 2366 /* Input modifier of 0x1f means "finish as soon as possible." */ 2367 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2368 MLX4_CMD_NATIVE); 2369 } 2370 2371 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2372 { 2373 u8 port; 2374 u32 *outbox; 2375 struct mlx4_cmd_mailbox *mailbox; 2376 u32 in_mod; 2377 u32 guid_hi, guid_lo; 2378 int err, ret = 0; 2379 #define MOD_STAT_CFG_PORT_OFFSET 8 2380 #define MOD_STAT_CFG_GUID_H 0X14 2381 #define MOD_STAT_CFG_GUID_L 0X1c 2382 2383 mailbox = mlx4_alloc_cmd_mailbox(dev); 2384 if (IS_ERR(mailbox)) 2385 return PTR_ERR(mailbox); 2386 outbox = mailbox->buf; 2387 2388 for (port = 1; port <= dev->caps.num_ports; port++) { 2389 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2390 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2391 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2392 MLX4_CMD_NATIVE); 2393 if (err) { 2394 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2395 port); 2396 ret = err; 2397 } else { 2398 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2399 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2400 dev->caps.phys_port_id[port] = (u64)guid_lo | 2401 (u64)guid_hi << 32; 2402 } 2403 } 2404 mlx4_free_cmd_mailbox(dev, mailbox); 2405 return ret; 2406 } 2407 2408 #define MLX4_WOL_SETUP_MODE (5 << 28) 2409 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2410 { 2411 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2412 2413 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2414 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2415 MLX4_CMD_NATIVE); 2416 } 2417 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2418 2419 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2420 { 2421 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2422 2423 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2424 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2425 } 2426 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2427 2428 enum { 2429 ADD_TO_MCG = 0x26, 2430 }; 2431 2432 2433 void mlx4_opreq_action(struct work_struct *work) 2434 { 2435 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2436 opreq_task); 2437 struct mlx4_dev *dev = &priv->dev; 2438 int num_tasks = atomic_read(&priv->opreq_count); 2439 struct mlx4_cmd_mailbox *mailbox; 2440 struct mlx4_mgm *mgm; 2441 u32 *outbox; 2442 u32 modifier; 2443 u16 token; 2444 u16 type; 2445 int err; 2446 u32 num_qps; 2447 struct mlx4_qp qp; 2448 int i; 2449 u8 rem_mcg; 2450 u8 prot; 2451 2452 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2453 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2454 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2455 #define GET_OP_REQ_DATA_OFFSET 0x20 2456 2457 mailbox = mlx4_alloc_cmd_mailbox(dev); 2458 if (IS_ERR(mailbox)) { 2459 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2460 return; 2461 } 2462 outbox = mailbox->buf; 2463 2464 while (num_tasks) { 2465 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2466 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2467 MLX4_CMD_NATIVE); 2468 if (err) { 2469 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2470 err); 2471 return; 2472 } 2473 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2474 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2475 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2476 type &= 0xfff; 2477 2478 switch (type) { 2479 case ADD_TO_MCG: 2480 if (dev->caps.steering_mode == 2481 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2482 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2483 err = EPERM; 2484 break; 2485 } 2486 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2487 GET_OP_REQ_DATA_OFFSET); 2488 num_qps = be32_to_cpu(mgm->members_count) & 2489 MGM_QPN_MASK; 2490 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2491 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2492 2493 for (i = 0; i < num_qps; i++) { 2494 qp.qpn = be32_to_cpu(mgm->qp[i]); 2495 if (rem_mcg) 2496 err = mlx4_multicast_detach(dev, &qp, 2497 mgm->gid, 2498 prot, 0); 2499 else 2500 err = mlx4_multicast_attach(dev, &qp, 2501 mgm->gid, 2502 mgm->gid[5] 2503 , 0, prot, 2504 NULL); 2505 if (err) 2506 break; 2507 } 2508 break; 2509 default: 2510 mlx4_warn(dev, "Bad type for required operation\n"); 2511 err = EINVAL; 2512 break; 2513 } 2514 err = mlx4_cmd(dev, 0, ((u32) err | 2515 (__force u32)cpu_to_be32(token) << 16), 2516 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2517 MLX4_CMD_NATIVE); 2518 if (err) { 2519 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2520 err); 2521 goto out; 2522 } 2523 memset(outbox, 0, 0xffc); 2524 num_tasks = atomic_dec_return(&priv->opreq_count); 2525 } 2526 2527 out: 2528 mlx4_free_cmd_mailbox(dev, mailbox); 2529 } 2530 2531 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2532 struct mlx4_cmd_mailbox *mailbox) 2533 { 2534 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2535 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2536 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2537 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2538 2539 u32 set_attr_mask, getresp_attr_mask; 2540 u32 trap_attr_mask, traprepress_attr_mask; 2541 2542 MLX4_GET(set_attr_mask, mailbox->buf, 2543 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2544 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2545 set_attr_mask); 2546 2547 MLX4_GET(getresp_attr_mask, mailbox->buf, 2548 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2549 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2550 getresp_attr_mask); 2551 2552 MLX4_GET(trap_attr_mask, mailbox->buf, 2553 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2554 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2555 trap_attr_mask); 2556 2557 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2558 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2559 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2560 traprepress_attr_mask); 2561 2562 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2563 traprepress_attr_mask) 2564 return 1; 2565 2566 return 0; 2567 } 2568 2569 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2570 { 2571 struct mlx4_cmd_mailbox *mailbox; 2572 int secure_host_active; 2573 int err; 2574 2575 /* Check if mad_demux is supported */ 2576 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2577 return 0; 2578 2579 mailbox = mlx4_alloc_cmd_mailbox(dev); 2580 if (IS_ERR(mailbox)) { 2581 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2582 return -ENOMEM; 2583 } 2584 2585 /* Query mad_demux to find out which MADs are handled by internal sma */ 2586 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2587 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2588 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2589 if (err) { 2590 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2591 err); 2592 goto out; 2593 } 2594 2595 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2596 2597 /* Config mad_demux to handle all MADs returned by the query above */ 2598 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2599 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2600 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2601 if (err) { 2602 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2603 goto out; 2604 } 2605 2606 if (secure_host_active) 2607 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2608 out: 2609 mlx4_free_cmd_mailbox(dev, mailbox); 2610 return err; 2611 } 2612 2613 /* Access Reg commands */ 2614 enum mlx4_access_reg_masks { 2615 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2616 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2617 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2618 }; 2619 2620 struct mlx4_access_reg { 2621 __be16 constant1; 2622 u8 status; 2623 u8 resrvd1; 2624 __be16 reg_id; 2625 u8 method; 2626 u8 constant2; 2627 __be32 resrvd2[2]; 2628 __be16 len_const; 2629 __be16 resrvd3; 2630 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2631 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2632 } __attribute__((__packed__)); 2633 2634 /** 2635 * mlx4_ACCESS_REG - Generic access reg command. 2636 * @dev: mlx4_dev. 2637 * @reg_id: register ID to access. 2638 * @method: Access method Read/Write. 2639 * @reg_len: register length to Read/Write in bytes. 2640 * @reg_data: reg_data pointer to Read/Write From/To. 2641 * 2642 * Access ConnectX registers FW command. 2643 * Returns 0 on success and copies outbox mlx4_access_reg data 2644 * field into reg_data or a negative error code. 2645 */ 2646 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2647 enum mlx4_access_reg_method method, 2648 u16 reg_len, void *reg_data) 2649 { 2650 struct mlx4_cmd_mailbox *inbox, *outbox; 2651 struct mlx4_access_reg *inbuf, *outbuf; 2652 int err; 2653 2654 inbox = mlx4_alloc_cmd_mailbox(dev); 2655 if (IS_ERR(inbox)) 2656 return PTR_ERR(inbox); 2657 2658 outbox = mlx4_alloc_cmd_mailbox(dev); 2659 if (IS_ERR(outbox)) { 2660 mlx4_free_cmd_mailbox(dev, inbox); 2661 return PTR_ERR(outbox); 2662 } 2663 2664 inbuf = inbox->buf; 2665 outbuf = outbox->buf; 2666 2667 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2668 inbuf->constant2 = 0x1; 2669 inbuf->reg_id = cpu_to_be16(reg_id); 2670 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2671 2672 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2673 inbuf->len_const = 2674 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2675 ((0x3) << 12)); 2676 2677 memcpy(inbuf->reg_data, reg_data, reg_len); 2678 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2679 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2680 MLX4_CMD_WRAPPED); 2681 if (err) 2682 goto out; 2683 2684 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2685 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2686 mlx4_err(dev, 2687 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2688 reg_id, err); 2689 goto out; 2690 } 2691 2692 memcpy(reg_data, outbuf->reg_data, reg_len); 2693 out: 2694 mlx4_free_cmd_mailbox(dev, inbox); 2695 mlx4_free_cmd_mailbox(dev, outbox); 2696 return err; 2697 } 2698 2699 /* ConnectX registers IDs */ 2700 enum mlx4_reg_id { 2701 MLX4_REG_ID_PTYS = 0x5004, 2702 }; 2703 2704 /** 2705 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2706 * register 2707 * @dev: mlx4_dev. 2708 * @method: Access method Read/Write. 2709 * @ptys_reg: PTYS register data pointer. 2710 * 2711 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2712 * configuration 2713 * Returns 0 on success or a negative error code. 2714 */ 2715 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2716 enum mlx4_access_reg_method method, 2717 struct mlx4_ptys_reg *ptys_reg) 2718 { 2719 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2720 method, sizeof(*ptys_reg), ptys_reg); 2721 } 2722 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2723 2724 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2725 struct mlx4_vhcr *vhcr, 2726 struct mlx4_cmd_mailbox *inbox, 2727 struct mlx4_cmd_mailbox *outbox, 2728 struct mlx4_cmd_info *cmd) 2729 { 2730 struct mlx4_access_reg *inbuf = inbox->buf; 2731 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2732 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2733 2734 if (slave != mlx4_master_func_num(dev) && 2735 method == MLX4_ACCESS_REG_WRITE) 2736 return -EPERM; 2737 2738 if (reg_id == MLX4_REG_ID_PTYS) { 2739 struct mlx4_ptys_reg *ptys_reg = 2740 (struct mlx4_ptys_reg *)inbuf->reg_data; 2741 2742 ptys_reg->local_port = 2743 mlx4_slave_convert_port(dev, slave, 2744 ptys_reg->local_port); 2745 } 2746 2747 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2748 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2749 MLX4_CMD_NATIVE); 2750 } 2751