1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 4] = "reliable multicast", 88 [ 5] = "FCoIB support", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [10] = "VMM", 94 [12] = "Dual Port Different Protocol (DPDP) support", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [24] = "Demand paging support", 103 [25] = "Router support", 104 [30] = "IBoE support", 105 [32] = "Unicast loopback support", 106 [34] = "FCS header control", 107 [38] = "Wake On LAN support", 108 [40] = "UDP RSS support", 109 [41] = "Unicast VEP steering support", 110 [42] = "Multicast VEP steering support", 111 [48] = "Counters support", 112 [53] = "Port ETS Scheduler support", 113 [55] = "Port link type sensing support", 114 [59] = "Port management change event support", 115 [61] = "64 byte EQE support", 116 [62] = "64 byte CQE support", 117 }; 118 int i; 119 120 mlx4_dbg(dev, "DEV_CAP flags:\n"); 121 for (i = 0; i < ARRAY_SIZE(fname); ++i) 122 if (fname[i] && (flags & (1LL << i))) 123 mlx4_dbg(dev, " %s\n", fname[i]); 124 } 125 126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127 { 128 static const char * const fname[] = { 129 [0] = "RSS support", 130 [1] = "RSS Toeplitz Hash Function support", 131 [2] = "RSS XOR Hash Function support", 132 [3] = "Device manage flow steering support", 133 [4] = "Automatic MAC reassignment support", 134 [5] = "Time stamping support", 135 [6] = "VST (control vlan insertion/stripping) support", 136 [7] = "FSM (MAC anti-spoofing) support" 137 }; 138 int i; 139 140 for (i = 0; i < ARRAY_SIZE(fname); ++i) 141 if (fname[i] && (flags & (1LL << i))) 142 mlx4_dbg(dev, " %s\n", fname[i]); 143 } 144 145 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 146 { 147 struct mlx4_cmd_mailbox *mailbox; 148 u32 *inbox; 149 int err = 0; 150 151 #define MOD_STAT_CFG_IN_SIZE 0x100 152 153 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 154 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 155 156 mailbox = mlx4_alloc_cmd_mailbox(dev); 157 if (IS_ERR(mailbox)) 158 return PTR_ERR(mailbox); 159 inbox = mailbox->buf; 160 161 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); 162 163 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 164 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 165 166 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 167 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 168 169 mlx4_free_cmd_mailbox(dev, mailbox); 170 return err; 171 } 172 173 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 174 struct mlx4_vhcr *vhcr, 175 struct mlx4_cmd_mailbox *inbox, 176 struct mlx4_cmd_mailbox *outbox, 177 struct mlx4_cmd_info *cmd) 178 { 179 u8 field; 180 u32 size; 181 int err = 0; 182 183 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 184 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 185 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 186 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 187 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 188 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 189 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 190 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 191 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 192 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 193 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 194 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 195 196 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 197 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 198 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 199 200 /* when opcode modifier = 1 */ 201 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 202 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 203 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc 204 205 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 206 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 207 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 208 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 209 210 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 211 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 212 213 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 214 215 if (vhcr->op_modifier == 1) { 216 field = 0; 217 /* ensure force vlan and force mac bits are not set */ 218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 219 /* ensure that phy_wqe_gid bit is not set */ 220 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 221 222 field = vhcr->in_modifier; /* phys-port = logical-port */ 223 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 224 225 /* size is now the QP number */ 226 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; 227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 228 229 size += 2; 230 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 231 232 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; 233 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); 234 235 size += 2; 236 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); 237 238 } else if (vhcr->op_modifier == 0) { 239 /* enable rdma and ethernet interfaces */ 240 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); 241 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 242 243 field = dev->caps.num_ports; 244 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 245 246 size = dev->caps.function_caps; /* set PF behaviours */ 247 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 248 249 field = 0; /* protected FMR support not available as yet */ 250 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 251 252 size = dev->caps.num_qps; 253 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 254 255 size = dev->caps.num_srqs; 256 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 257 258 size = dev->caps.num_cqs; 259 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 260 261 size = dev->caps.num_eqs; 262 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 263 264 size = dev->caps.reserved_eqs; 265 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 266 267 size = dev->caps.num_mpts; 268 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 269 270 size = dev->caps.num_mtts; 271 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 272 273 size = dev->caps.num_mgms + dev->caps.num_amgms; 274 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 275 276 } else 277 err = -EINVAL; 278 279 return err; 280 } 281 282 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, 283 struct mlx4_func_cap *func_cap) 284 { 285 struct mlx4_cmd_mailbox *mailbox; 286 u32 *outbox; 287 u8 field, op_modifier; 288 u32 size; 289 int err = 0; 290 291 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 292 293 mailbox = mlx4_alloc_cmd_mailbox(dev); 294 if (IS_ERR(mailbox)) 295 return PTR_ERR(mailbox); 296 297 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, 298 MLX4_CMD_QUERY_FUNC_CAP, 299 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 300 if (err) 301 goto out; 302 303 outbox = mailbox->buf; 304 305 if (!op_modifier) { 306 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 307 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 308 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 309 err = -EPROTONOSUPPORT; 310 goto out; 311 } 312 func_cap->flags = field; 313 314 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 315 func_cap->num_ports = field; 316 317 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 318 func_cap->pf_context_behaviour = size; 319 320 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 321 func_cap->qp_quota = size & 0xFFFFFF; 322 323 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 324 func_cap->srq_quota = size & 0xFFFFFF; 325 326 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 327 func_cap->cq_quota = size & 0xFFFFFF; 328 329 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 330 func_cap->max_eq = size & 0xFFFFFF; 331 332 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 333 func_cap->reserved_eq = size & 0xFFFFFF; 334 335 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 336 func_cap->mpt_quota = size & 0xFFFFFF; 337 338 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 339 func_cap->mtt_quota = size & 0xFFFFFF; 340 341 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 342 func_cap->mcg_quota = size & 0xFFFFFF; 343 goto out; 344 } 345 346 /* logical port query */ 347 if (gen_or_port > dev->caps.num_ports) { 348 err = -EINVAL; 349 goto out; 350 } 351 352 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 353 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 354 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { 355 mlx4_err(dev, "VLAN is enforced on this port\n"); 356 err = -EPROTONOSUPPORT; 357 goto out; 358 } 359 360 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { 361 mlx4_err(dev, "Force mac is enabled on this port\n"); 362 err = -EPROTONOSUPPORT; 363 goto out; 364 } 365 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 366 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 367 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { 368 mlx4_err(dev, "phy_wqe_gid is " 369 "enforced on this ib port\n"); 370 err = -EPROTONOSUPPORT; 371 goto out; 372 } 373 } 374 375 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 376 func_cap->physical_port = field; 377 if (func_cap->physical_port != gen_or_port) { 378 err = -ENOSYS; 379 goto out; 380 } 381 382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 383 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 384 385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 386 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 387 388 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 389 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 390 391 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 392 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 393 394 /* All other resources are allocated by the master, but we still report 395 * 'num' and 'reserved' capabilities as follows: 396 * - num remains the maximum resource index 397 * - 'num - reserved' is the total available objects of a resource, but 398 * resource indices may be less than 'reserved' 399 * TODO: set per-resource quotas */ 400 401 out: 402 mlx4_free_cmd_mailbox(dev, mailbox); 403 404 return err; 405 } 406 407 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 408 { 409 struct mlx4_cmd_mailbox *mailbox; 410 u32 *outbox; 411 u8 field; 412 u32 field32, flags, ext_flags; 413 u16 size; 414 u16 stat_rate; 415 int err; 416 int i; 417 418 #define QUERY_DEV_CAP_OUT_SIZE 0x100 419 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 420 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 421 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 422 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 423 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 424 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 425 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 426 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 427 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 428 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 429 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 430 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 431 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 432 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 433 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 434 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 435 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 436 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 437 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 438 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 439 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 440 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 441 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 442 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 443 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 444 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 445 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 446 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 447 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 448 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 449 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 450 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 451 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 452 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 453 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 454 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 455 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 456 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 457 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 458 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 459 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 460 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 461 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 462 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 463 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 464 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 465 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 466 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 467 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 468 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 469 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 470 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 471 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 472 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 473 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 474 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 475 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 476 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 477 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 478 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 479 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 480 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 481 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 482 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 483 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 484 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 485 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 486 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 487 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 488 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 489 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 490 491 dev_cap->flags2 = 0; 492 mailbox = mlx4_alloc_cmd_mailbox(dev); 493 if (IS_ERR(mailbox)) 494 return PTR_ERR(mailbox); 495 outbox = mailbox->buf; 496 497 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 498 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 499 if (err) 500 goto out; 501 502 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 503 dev_cap->reserved_qps = 1 << (field & 0xf); 504 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 505 dev_cap->max_qps = 1 << (field & 0x1f); 506 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 507 dev_cap->reserved_srqs = 1 << (field >> 4); 508 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 509 dev_cap->max_srqs = 1 << (field & 0x1f); 510 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 511 dev_cap->max_cq_sz = 1 << field; 512 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 513 dev_cap->reserved_cqs = 1 << (field & 0xf); 514 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 515 dev_cap->max_cqs = 1 << (field & 0x1f); 516 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 517 dev_cap->max_mpts = 1 << (field & 0x3f); 518 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 519 dev_cap->reserved_eqs = field & 0xf; 520 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 521 dev_cap->max_eqs = 1 << (field & 0xf); 522 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 523 dev_cap->reserved_mtts = 1 << (field >> 4); 524 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 525 dev_cap->max_mrw_sz = 1 << field; 526 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 527 dev_cap->reserved_mrws = 1 << (field & 0xf); 528 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 529 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 530 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 531 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 532 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 533 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 534 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 535 field &= 0x1f; 536 if (!field) 537 dev_cap->max_gso_sz = 0; 538 else 539 dev_cap->max_gso_sz = 1 << field; 540 541 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 542 if (field & 0x20) 543 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 544 if (field & 0x10) 545 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 546 field &= 0xf; 547 if (field) { 548 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 549 dev_cap->max_rss_tbl_sz = 1 << field; 550 } else 551 dev_cap->max_rss_tbl_sz = 0; 552 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 553 dev_cap->max_rdma_global = 1 << (field & 0x3f); 554 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 555 dev_cap->local_ca_ack_delay = field & 0x1f; 556 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 557 dev_cap->num_ports = field & 0xf; 558 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 559 dev_cap->max_msg_sz = 1 << (field & 0x1f); 560 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 561 if (field & 0x80) 562 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 563 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 564 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 565 dev_cap->fs_max_num_qp_per_entry = field; 566 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 567 dev_cap->stat_rate_support = stat_rate; 568 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 569 if (field & 0x80) 570 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 571 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 572 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 573 dev_cap->flags = flags | (u64)ext_flags << 32; 574 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 575 dev_cap->reserved_uars = field >> 4; 576 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 577 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 578 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 579 dev_cap->min_page_sz = 1 << field; 580 581 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 582 if (field & 0x80) { 583 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 584 dev_cap->bf_reg_size = 1 << (field & 0x1f); 585 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 586 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 587 field = 3; 588 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 589 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 590 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 591 } else { 592 dev_cap->bf_reg_size = 0; 593 mlx4_dbg(dev, "BlueFlame not available\n"); 594 } 595 596 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 597 dev_cap->max_sq_sg = field; 598 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 599 dev_cap->max_sq_desc_sz = size; 600 601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 602 dev_cap->max_qp_per_mcg = 1 << field; 603 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 604 dev_cap->reserved_mgms = field & 0xf; 605 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 606 dev_cap->max_mcgs = 1 << field; 607 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 608 dev_cap->reserved_pds = field >> 4; 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 610 dev_cap->max_pds = 1 << (field & 0x3f); 611 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 612 dev_cap->reserved_xrcds = field >> 4; 613 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 614 dev_cap->max_xrcds = 1 << (field & 0x1f); 615 616 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 617 dev_cap->rdmarc_entry_sz = size; 618 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 619 dev_cap->qpc_entry_sz = size; 620 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 621 dev_cap->aux_entry_sz = size; 622 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 623 dev_cap->altc_entry_sz = size; 624 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 625 dev_cap->eqc_entry_sz = size; 626 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 627 dev_cap->cqc_entry_sz = size; 628 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 629 dev_cap->srq_entry_sz = size; 630 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 631 dev_cap->cmpt_entry_sz = size; 632 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 633 dev_cap->mtt_entry_sz = size; 634 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 635 dev_cap->dmpt_entry_sz = size; 636 637 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 638 dev_cap->max_srq_sz = 1 << field; 639 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 640 dev_cap->max_qp_sz = 1 << field; 641 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 642 dev_cap->resize_srq = field & 1; 643 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 644 dev_cap->max_rq_sg = field; 645 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 646 dev_cap->max_rq_desc_sz = size; 647 648 MLX4_GET(dev_cap->bmme_flags, outbox, 649 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 650 MLX4_GET(dev_cap->reserved_lkey, outbox, 651 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 652 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 653 if (field & 1<<6) 654 dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN; 655 MLX4_GET(dev_cap->max_icm_sz, outbox, 656 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 657 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 658 MLX4_GET(dev_cap->max_counters, outbox, 659 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 660 661 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 662 if (field32 & (1 << 26)) 663 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 664 if (field32 & (1 << 20)) 665 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 666 667 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 668 for (i = 1; i <= dev_cap->num_ports; ++i) { 669 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 670 dev_cap->max_vl[i] = field >> 4; 671 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 672 dev_cap->ib_mtu[i] = field >> 4; 673 dev_cap->max_port_width[i] = field & 0xf; 674 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 675 dev_cap->max_gids[i] = 1 << (field & 0xf); 676 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 677 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 678 } 679 } else { 680 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 681 #define QUERY_PORT_MTU_OFFSET 0x01 682 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 683 #define QUERY_PORT_WIDTH_OFFSET 0x06 684 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 685 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 686 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 687 #define QUERY_PORT_MAC_OFFSET 0x10 688 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 689 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 690 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 691 692 for (i = 1; i <= dev_cap->num_ports; ++i) { 693 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, 694 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 695 if (err) 696 goto out; 697 698 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 699 dev_cap->supported_port_types[i] = field & 3; 700 dev_cap->suggested_type[i] = (field >> 3) & 1; 701 dev_cap->default_sense[i] = (field >> 4) & 1; 702 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 703 dev_cap->ib_mtu[i] = field & 0xf; 704 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 705 dev_cap->max_port_width[i] = field & 0xf; 706 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 707 dev_cap->max_gids[i] = 1 << (field >> 4); 708 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 709 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 710 dev_cap->max_vl[i] = field & 0xf; 711 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 712 dev_cap->log_max_macs[i] = field & 0xf; 713 dev_cap->log_max_vlans[i] = field >> 4; 714 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); 715 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); 716 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 717 dev_cap->trans_type[i] = field32 >> 24; 718 dev_cap->vendor_oui[i] = field32 & 0xffffff; 719 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); 720 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); 721 } 722 } 723 724 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 725 dev_cap->bmme_flags, dev_cap->reserved_lkey); 726 727 /* 728 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 729 * we can't use any EQs whose doorbell falls on that page, 730 * even if the EQ itself isn't reserved. 731 */ 732 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 733 dev_cap->reserved_eqs); 734 735 mlx4_dbg(dev, "Max ICM size %lld MB\n", 736 (unsigned long long) dev_cap->max_icm_sz >> 20); 737 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 738 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 739 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 740 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 741 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 742 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 743 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 744 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); 745 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 746 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 747 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 748 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 749 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 750 dev_cap->max_pds, dev_cap->reserved_mgms); 751 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 752 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 753 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 754 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 755 dev_cap->max_port_width[1]); 756 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 757 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 758 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 759 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 760 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 761 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 762 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 763 764 dump_dev_cap_flags(dev, dev_cap->flags); 765 dump_dev_cap_flags2(dev, dev_cap->flags2); 766 767 out: 768 mlx4_free_cmd_mailbox(dev, mailbox); 769 return err; 770 } 771 772 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 773 struct mlx4_vhcr *vhcr, 774 struct mlx4_cmd_mailbox *inbox, 775 struct mlx4_cmd_mailbox *outbox, 776 struct mlx4_cmd_info *cmd) 777 { 778 u64 flags; 779 int err = 0; 780 u8 field; 781 u32 bmme_flags; 782 783 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 784 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 785 if (err) 786 return err; 787 788 /* add port mng change event capability and disable mw type 1 789 * unconditionally to slaves 790 */ 791 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 792 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 793 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 794 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 795 796 /* For guests, disable timestamp */ 797 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 798 field &= 0x7f; 799 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 800 801 /* For guests, report Blueflame disabled */ 802 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 803 field &= 0x7f; 804 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 805 806 /* For guests, disable mw type 2 */ 807 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 808 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 809 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 810 811 /* turn off device-managed steering capability if not enabled */ 812 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 813 MLX4_GET(field, outbox->buf, 814 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 815 field &= 0x7f; 816 MLX4_PUT(outbox->buf, field, 817 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 818 } 819 return 0; 820 } 821 822 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 823 struct mlx4_vhcr *vhcr, 824 struct mlx4_cmd_mailbox *inbox, 825 struct mlx4_cmd_mailbox *outbox, 826 struct mlx4_cmd_info *cmd) 827 { 828 struct mlx4_priv *priv = mlx4_priv(dev); 829 u64 def_mac; 830 u8 port_type; 831 u16 short_field; 832 int err; 833 834 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 835 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 836 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 837 838 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 839 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 840 MLX4_CMD_NATIVE); 841 842 if (!err && dev->caps.function != slave) { 843 /* if config MAC in DB use it */ 844 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac) 845 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 846 else { 847 /* set slave default_mac address */ 848 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); 849 def_mac += slave << 8; 850 priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac; 851 } 852 853 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 854 855 /* get port type - currently only eth is enabled */ 856 MLX4_GET(port_type, outbox->buf, 857 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 858 859 /* No link sensing allowed */ 860 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 861 /* set port type to currently operating port type */ 862 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 863 864 MLX4_PUT(outbox->buf, port_type, 865 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 866 867 short_field = 1; /* slave max gids */ 868 MLX4_PUT(outbox->buf, short_field, 869 QUERY_PORT_CUR_MAX_GID_OFFSET); 870 871 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 872 MLX4_PUT(outbox->buf, short_field, 873 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 874 } 875 876 return err; 877 } 878 879 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 880 int *gid_tbl_len, int *pkey_tbl_len) 881 { 882 struct mlx4_cmd_mailbox *mailbox; 883 u32 *outbox; 884 u16 field; 885 int err; 886 887 mailbox = mlx4_alloc_cmd_mailbox(dev); 888 if (IS_ERR(mailbox)) 889 return PTR_ERR(mailbox); 890 891 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 892 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 893 MLX4_CMD_WRAPPED); 894 if (err) 895 goto out; 896 897 outbox = mailbox->buf; 898 899 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 900 *gid_tbl_len = field; 901 902 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 903 *pkey_tbl_len = field; 904 905 out: 906 mlx4_free_cmd_mailbox(dev, mailbox); 907 return err; 908 } 909 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 910 911 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 912 { 913 struct mlx4_cmd_mailbox *mailbox; 914 struct mlx4_icm_iter iter; 915 __be64 *pages; 916 int lg; 917 int nent = 0; 918 int i; 919 int err = 0; 920 int ts = 0, tc = 0; 921 922 mailbox = mlx4_alloc_cmd_mailbox(dev); 923 if (IS_ERR(mailbox)) 924 return PTR_ERR(mailbox); 925 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 926 pages = mailbox->buf; 927 928 for (mlx4_icm_first(icm, &iter); 929 !mlx4_icm_last(&iter); 930 mlx4_icm_next(&iter)) { 931 /* 932 * We have to pass pages that are aligned to their 933 * size, so find the least significant 1 in the 934 * address or size and use that as our log2 size. 935 */ 936 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 937 if (lg < MLX4_ICM_PAGE_SHIFT) { 938 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 939 MLX4_ICM_PAGE_SIZE, 940 (unsigned long long) mlx4_icm_addr(&iter), 941 mlx4_icm_size(&iter)); 942 err = -EINVAL; 943 goto out; 944 } 945 946 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 947 if (virt != -1) { 948 pages[nent * 2] = cpu_to_be64(virt); 949 virt += 1 << lg; 950 } 951 952 pages[nent * 2 + 1] = 953 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 954 (lg - MLX4_ICM_PAGE_SHIFT)); 955 ts += 1 << (lg - 10); 956 ++tc; 957 958 if (++nent == MLX4_MAILBOX_SIZE / 16) { 959 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 960 MLX4_CMD_TIME_CLASS_B, 961 MLX4_CMD_NATIVE); 962 if (err) 963 goto out; 964 nent = 0; 965 } 966 } 967 } 968 969 if (nent) 970 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 971 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 972 if (err) 973 goto out; 974 975 switch (op) { 976 case MLX4_CMD_MAP_FA: 977 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 978 break; 979 case MLX4_CMD_MAP_ICM_AUX: 980 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 981 break; 982 case MLX4_CMD_MAP_ICM: 983 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 984 tc, ts, (unsigned long long) virt - (ts << 10)); 985 break; 986 } 987 988 out: 989 mlx4_free_cmd_mailbox(dev, mailbox); 990 return err; 991 } 992 993 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 994 { 995 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 996 } 997 998 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 999 { 1000 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1001 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1002 } 1003 1004 1005 int mlx4_RUN_FW(struct mlx4_dev *dev) 1006 { 1007 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1008 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1009 } 1010 1011 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1012 { 1013 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1014 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1015 struct mlx4_cmd_mailbox *mailbox; 1016 u32 *outbox; 1017 int err = 0; 1018 u64 fw_ver; 1019 u16 cmd_if_rev; 1020 u8 lg; 1021 1022 #define QUERY_FW_OUT_SIZE 0x100 1023 #define QUERY_FW_VER_OFFSET 0x00 1024 #define QUERY_FW_PPF_ID 0x09 1025 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1026 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1027 #define QUERY_FW_ERR_START_OFFSET 0x30 1028 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1029 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1030 1031 #define QUERY_FW_SIZE_OFFSET 0x00 1032 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1033 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1034 1035 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1036 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1037 1038 #define QUERY_FW_CLOCK_OFFSET 0x50 1039 #define QUERY_FW_CLOCK_BAR 0x58 1040 1041 mailbox = mlx4_alloc_cmd_mailbox(dev); 1042 if (IS_ERR(mailbox)) 1043 return PTR_ERR(mailbox); 1044 outbox = mailbox->buf; 1045 1046 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1047 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1048 if (err) 1049 goto out; 1050 1051 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1052 /* 1053 * FW subminor version is at more significant bits than minor 1054 * version, so swap here. 1055 */ 1056 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1057 ((fw_ver & 0xffff0000ull) >> 16) | 1058 ((fw_ver & 0x0000ffffull) << 16); 1059 1060 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1061 dev->caps.function = lg; 1062 1063 if (mlx4_is_slave(dev)) 1064 goto out; 1065 1066 1067 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1068 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1069 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1070 mlx4_err(dev, "Installed FW has unsupported " 1071 "command interface revision %d.\n", 1072 cmd_if_rev); 1073 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1074 (int) (dev->caps.fw_ver >> 32), 1075 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1076 (int) dev->caps.fw_ver & 0xffff); 1077 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", 1078 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1079 err = -ENODEV; 1080 goto out; 1081 } 1082 1083 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1084 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1085 1086 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1087 cmd->max_cmds = 1 << lg; 1088 1089 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1090 (int) (dev->caps.fw_ver >> 32), 1091 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1092 (int) dev->caps.fw_ver & 0xffff, 1093 cmd_if_rev, cmd->max_cmds); 1094 1095 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1096 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1097 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1098 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1099 1100 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1101 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1102 1103 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1104 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1105 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1106 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1107 1108 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1109 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1110 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1111 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1112 fw->comm_bar, fw->comm_base); 1113 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1114 1115 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1116 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1117 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1118 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1119 fw->clock_bar, fw->clock_offset); 1120 1121 /* 1122 * Round up number of system pages needed in case 1123 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1124 */ 1125 fw->fw_pages = 1126 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1127 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1128 1129 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1130 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1131 1132 out: 1133 mlx4_free_cmd_mailbox(dev, mailbox); 1134 return err; 1135 } 1136 1137 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1138 struct mlx4_vhcr *vhcr, 1139 struct mlx4_cmd_mailbox *inbox, 1140 struct mlx4_cmd_mailbox *outbox, 1141 struct mlx4_cmd_info *cmd) 1142 { 1143 u8 *outbuf; 1144 int err; 1145 1146 outbuf = outbox->buf; 1147 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1148 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1149 if (err) 1150 return err; 1151 1152 /* for slaves, set pci PPF ID to invalid and zero out everything 1153 * else except FW version */ 1154 outbuf[0] = outbuf[1] = 0; 1155 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1156 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1157 1158 return 0; 1159 } 1160 1161 static void get_board_id(void *vsd, char *board_id) 1162 { 1163 int i; 1164 1165 #define VSD_OFFSET_SIG1 0x00 1166 #define VSD_OFFSET_SIG2 0xde 1167 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1168 #define VSD_OFFSET_TS_BOARD_ID 0x20 1169 1170 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1171 1172 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1173 1174 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1175 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1176 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1177 } else { 1178 /* 1179 * The board ID is a string but the firmware byte 1180 * swaps each 4-byte word before passing it back to 1181 * us. Therefore we need to swab it before printing. 1182 */ 1183 for (i = 0; i < 4; ++i) 1184 ((u32 *) board_id)[i] = 1185 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1186 } 1187 } 1188 1189 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1190 { 1191 struct mlx4_cmd_mailbox *mailbox; 1192 u32 *outbox; 1193 int err; 1194 1195 #define QUERY_ADAPTER_OUT_SIZE 0x100 1196 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1197 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1198 1199 mailbox = mlx4_alloc_cmd_mailbox(dev); 1200 if (IS_ERR(mailbox)) 1201 return PTR_ERR(mailbox); 1202 outbox = mailbox->buf; 1203 1204 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1205 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1206 if (err) 1207 goto out; 1208 1209 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1210 1211 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1212 adapter->board_id); 1213 1214 out: 1215 mlx4_free_cmd_mailbox(dev, mailbox); 1216 return err; 1217 } 1218 1219 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1220 { 1221 struct mlx4_cmd_mailbox *mailbox; 1222 __be32 *inbox; 1223 int err; 1224 1225 #define INIT_HCA_IN_SIZE 0x200 1226 #define INIT_HCA_VERSION_OFFSET 0x000 1227 #define INIT_HCA_VERSION 2 1228 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1229 #define INIT_HCA_FLAGS_OFFSET 0x014 1230 #define INIT_HCA_QPC_OFFSET 0x020 1231 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1232 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1233 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1234 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1235 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1236 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1237 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1238 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1239 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1240 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1241 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1242 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1243 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1244 #define INIT_HCA_MCAST_OFFSET 0x0c0 1245 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1246 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1247 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1248 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1249 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1250 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1251 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1252 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1253 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1254 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1255 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1256 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1257 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1258 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1259 #define INIT_HCA_TPT_OFFSET 0x0f0 1260 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1261 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1262 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1263 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1264 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1265 #define INIT_HCA_UAR_OFFSET 0x120 1266 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1267 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1268 1269 mailbox = mlx4_alloc_cmd_mailbox(dev); 1270 if (IS_ERR(mailbox)) 1271 return PTR_ERR(mailbox); 1272 inbox = mailbox->buf; 1273 1274 memset(inbox, 0, INIT_HCA_IN_SIZE); 1275 1276 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1277 1278 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1279 (ilog2(cache_line_size()) - 4) << 5; 1280 1281 #if defined(__LITTLE_ENDIAN) 1282 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1283 #elif defined(__BIG_ENDIAN) 1284 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1285 #else 1286 #error Host endianness not defined 1287 #endif 1288 /* Check port for UD address vector: */ 1289 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1290 1291 /* Enable IPoIB checksumming if we can: */ 1292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1293 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1294 1295 /* Enable QoS support if module parameter set */ 1296 if (enable_qos) 1297 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1298 1299 /* enable counters */ 1300 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1301 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1302 1303 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1304 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1305 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1306 dev->caps.eqe_size = 64; 1307 dev->caps.eqe_factor = 1; 1308 } else { 1309 dev->caps.eqe_size = 32; 1310 dev->caps.eqe_factor = 0; 1311 } 1312 1313 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1314 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1315 dev->caps.cqe_size = 64; 1316 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 1317 } else { 1318 dev->caps.cqe_size = 32; 1319 } 1320 1321 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1322 1323 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1324 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1325 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1326 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1327 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1328 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1329 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1330 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1331 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1332 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1333 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1334 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1335 1336 /* steering attributes */ 1337 if (dev->caps.steering_mode == 1338 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1339 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1340 cpu_to_be32(1 << 1341 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1342 1343 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1344 MLX4_PUT(inbox, param->log_mc_entry_sz, 1345 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1346 MLX4_PUT(inbox, param->log_mc_table_sz, 1347 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1348 /* Enable Ethernet flow steering 1349 * with udp unicast and tcp unicast 1350 */ 1351 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1352 INIT_HCA_FS_ETH_BITS_OFFSET); 1353 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1354 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1355 /* Enable IPoIB flow steering 1356 * with udp unicast and tcp unicast 1357 */ 1358 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1359 INIT_HCA_FS_IB_BITS_OFFSET); 1360 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1361 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1362 } else { 1363 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1364 MLX4_PUT(inbox, param->log_mc_entry_sz, 1365 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1366 MLX4_PUT(inbox, param->log_mc_hash_sz, 1367 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1368 MLX4_PUT(inbox, param->log_mc_table_sz, 1369 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1370 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1371 MLX4_PUT(inbox, (u8) (1 << 3), 1372 INIT_HCA_UC_STEERING_OFFSET); 1373 } 1374 1375 /* TPT attributes */ 1376 1377 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1378 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1379 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1380 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1381 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1382 1383 /* UAR attributes */ 1384 1385 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1386 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1387 1388 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1389 MLX4_CMD_NATIVE); 1390 1391 if (err) 1392 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1393 1394 mlx4_free_cmd_mailbox(dev, mailbox); 1395 return err; 1396 } 1397 1398 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1399 struct mlx4_init_hca_param *param) 1400 { 1401 struct mlx4_cmd_mailbox *mailbox; 1402 __be32 *outbox; 1403 u32 dword_field; 1404 int err; 1405 u8 byte_field; 1406 1407 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1408 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1409 1410 mailbox = mlx4_alloc_cmd_mailbox(dev); 1411 if (IS_ERR(mailbox)) 1412 return PTR_ERR(mailbox); 1413 outbox = mailbox->buf; 1414 1415 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1416 MLX4_CMD_QUERY_HCA, 1417 MLX4_CMD_TIME_CLASS_B, 1418 !mlx4_is_slave(dev)); 1419 if (err) 1420 goto out; 1421 1422 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1423 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1424 1425 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1426 1427 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1428 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1429 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1430 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1431 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1432 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1433 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1434 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1435 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1436 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1437 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1438 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1439 1440 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1441 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1442 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1443 } else { 1444 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1445 if (byte_field & 0x8) 1446 param->steering_mode = MLX4_STEERING_MODE_B0; 1447 else 1448 param->steering_mode = MLX4_STEERING_MODE_A0; 1449 } 1450 /* steering attributes */ 1451 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1452 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1453 MLX4_GET(param->log_mc_entry_sz, outbox, 1454 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1455 MLX4_GET(param->log_mc_table_sz, outbox, 1456 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1457 } else { 1458 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1459 MLX4_GET(param->log_mc_entry_sz, outbox, 1460 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1461 MLX4_GET(param->log_mc_hash_sz, outbox, 1462 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1463 MLX4_GET(param->log_mc_table_sz, outbox, 1464 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1465 } 1466 1467 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1468 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1469 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1470 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1471 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1472 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1473 1474 /* TPT attributes */ 1475 1476 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1477 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1478 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1479 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1480 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1481 1482 /* UAR attributes */ 1483 1484 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1485 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1486 1487 out: 1488 mlx4_free_cmd_mailbox(dev, mailbox); 1489 1490 return err; 1491 } 1492 1493 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 1494 * and real QP0 are active, so that the paravirtualized QP0 is ready 1495 * to operate */ 1496 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 1497 { 1498 struct mlx4_priv *priv = mlx4_priv(dev); 1499 /* irrelevant if not infiniband */ 1500 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 1501 priv->mfunc.master.qp0_state[port].qp0_active) 1502 return 1; 1503 return 0; 1504 } 1505 1506 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1507 struct mlx4_vhcr *vhcr, 1508 struct mlx4_cmd_mailbox *inbox, 1509 struct mlx4_cmd_mailbox *outbox, 1510 struct mlx4_cmd_info *cmd) 1511 { 1512 struct mlx4_priv *priv = mlx4_priv(dev); 1513 int port = vhcr->in_modifier; 1514 int err; 1515 1516 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 1517 return 0; 1518 1519 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1520 /* Enable port only if it was previously disabled */ 1521 if (!priv->mfunc.master.init_port_ref[port]) { 1522 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1523 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1524 if (err) 1525 return err; 1526 } 1527 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1528 } else { 1529 if (slave == mlx4_master_func_num(dev)) { 1530 if (check_qp0_state(dev, slave, port) && 1531 !priv->mfunc.master.qp0_state[port].port_active) { 1532 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1533 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1534 if (err) 1535 return err; 1536 priv->mfunc.master.qp0_state[port].port_active = 1; 1537 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1538 } 1539 } else 1540 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1541 } 1542 ++priv->mfunc.master.init_port_ref[port]; 1543 return 0; 1544 } 1545 1546 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 1547 { 1548 struct mlx4_cmd_mailbox *mailbox; 1549 u32 *inbox; 1550 int err; 1551 u32 flags; 1552 u16 field; 1553 1554 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1555 #define INIT_PORT_IN_SIZE 256 1556 #define INIT_PORT_FLAGS_OFFSET 0x00 1557 #define INIT_PORT_FLAG_SIG (1 << 18) 1558 #define INIT_PORT_FLAG_NG (1 << 17) 1559 #define INIT_PORT_FLAG_G0 (1 << 16) 1560 #define INIT_PORT_VL_SHIFT 4 1561 #define INIT_PORT_PORT_WIDTH_SHIFT 8 1562 #define INIT_PORT_MTU_OFFSET 0x04 1563 #define INIT_PORT_MAX_GID_OFFSET 0x06 1564 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 1565 #define INIT_PORT_GUID0_OFFSET 0x10 1566 #define INIT_PORT_NODE_GUID_OFFSET 0x18 1567 #define INIT_PORT_SI_GUID_OFFSET 0x20 1568 1569 mailbox = mlx4_alloc_cmd_mailbox(dev); 1570 if (IS_ERR(mailbox)) 1571 return PTR_ERR(mailbox); 1572 inbox = mailbox->buf; 1573 1574 memset(inbox, 0, INIT_PORT_IN_SIZE); 1575 1576 flags = 0; 1577 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 1578 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 1579 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 1580 1581 field = 128 << dev->caps.ib_mtu_cap[port]; 1582 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 1583 field = dev->caps.gid_table_len[port]; 1584 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 1585 field = dev->caps.pkey_table_len[port]; 1586 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 1587 1588 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1589 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1590 1591 mlx4_free_cmd_mailbox(dev, mailbox); 1592 } else 1593 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1594 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1595 1596 return err; 1597 } 1598 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 1599 1600 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1601 struct mlx4_vhcr *vhcr, 1602 struct mlx4_cmd_mailbox *inbox, 1603 struct mlx4_cmd_mailbox *outbox, 1604 struct mlx4_cmd_info *cmd) 1605 { 1606 struct mlx4_priv *priv = mlx4_priv(dev); 1607 int port = vhcr->in_modifier; 1608 int err; 1609 1610 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 1611 (1 << port))) 1612 return 0; 1613 1614 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 1615 if (priv->mfunc.master.init_port_ref[port] == 1) { 1616 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1617 1000, MLX4_CMD_NATIVE); 1618 if (err) 1619 return err; 1620 } 1621 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1622 } else { 1623 /* infiniband port */ 1624 if (slave == mlx4_master_func_num(dev)) { 1625 if (!priv->mfunc.master.qp0_state[port].qp0_active && 1626 priv->mfunc.master.qp0_state[port].port_active) { 1627 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1628 1000, MLX4_CMD_NATIVE); 1629 if (err) 1630 return err; 1631 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1632 priv->mfunc.master.qp0_state[port].port_active = 0; 1633 } 1634 } else 1635 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1636 } 1637 --priv->mfunc.master.init_port_ref[port]; 1638 return 0; 1639 } 1640 1641 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 1642 { 1643 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1644 MLX4_CMD_WRAPPED); 1645 } 1646 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 1647 1648 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 1649 { 1650 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 1651 MLX4_CMD_NATIVE); 1652 } 1653 1654 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 1655 { 1656 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 1657 MLX4_CMD_SET_ICM_SIZE, 1658 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1659 if (ret) 1660 return ret; 1661 1662 /* 1663 * Round up number of system pages needed in case 1664 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1665 */ 1666 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1667 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1668 1669 return 0; 1670 } 1671 1672 int mlx4_NOP(struct mlx4_dev *dev) 1673 { 1674 /* Input modifier of 0x1f means "finish as soon as possible." */ 1675 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 1676 } 1677 1678 #define MLX4_WOL_SETUP_MODE (5 << 28) 1679 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 1680 { 1681 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1682 1683 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 1684 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1685 MLX4_CMD_NATIVE); 1686 } 1687 EXPORT_SYMBOL_GPL(mlx4_wol_read); 1688 1689 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 1690 { 1691 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1692 1693 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 1694 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1695 } 1696 EXPORT_SYMBOL_GPL(mlx4_wol_write); 1697