1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/init.h> 35 #include <linux/interrupt.h> 36 #include <linux/slab.h> 37 #include <linux/export.h> 38 #include <linux/mm.h> 39 #include <linux/dma-mapping.h> 40 41 #include <linux/mlx4/cmd.h> 42 #include <linux/cpu_rmap.h> 43 44 #include "mlx4.h" 45 #include "fw.h" 46 47 enum { 48 MLX4_IRQNAME_SIZE = 32 49 }; 50 51 enum { 52 MLX4_NUM_ASYNC_EQE = 0x100, 53 MLX4_NUM_SPARE_EQE = 0x80, 54 MLX4_EQ_ENTRY_SIZE = 0x20 55 }; 56 57 #define MLX4_EQ_STATUS_OK ( 0 << 28) 58 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 59 #define MLX4_EQ_OWNER_SW ( 0 << 24) 60 #define MLX4_EQ_OWNER_HW ( 1 << 24) 61 #define MLX4_EQ_FLAG_EC ( 1 << 18) 62 #define MLX4_EQ_FLAG_OI ( 1 << 17) 63 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 64 #define MLX4_EQ_STATE_FIRED (10 << 8) 65 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 66 67 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 81 (1ull << MLX4_EVENT_TYPE_CMD) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 92 return async_ev_mask; 93 } 94 95 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 96 { 97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 98 req_not << 31), 99 eq->doorbell); 100 /* We still want ordering, just not swabbing, so add a barrier */ 101 mb(); 102 } 103 104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor) 105 { 106 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor); 108 /* CX3 is capable of extending the EQE from 32 to 64 bytes. 109 * When this feature is enabled, the first (in the lower addresses) 110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 111 * contain the legacy EQE information. 112 */ 113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 114 } 115 116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor) 117 { 118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor); 119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 120 } 121 122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 123 { 124 struct mlx4_eqe *eqe = 125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 126 return (!!(eqe->owner & 0x80) ^ 127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 128 eqe : NULL; 129 } 130 131 void mlx4_gen_slave_eqe(struct work_struct *work) 132 { 133 struct mlx4_mfunc_master_ctx *master = 134 container_of(work, struct mlx4_mfunc_master_ctx, 135 slave_event_work); 136 struct mlx4_mfunc *mfunc = 137 container_of(master, struct mlx4_mfunc, master); 138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 139 struct mlx4_dev *dev = &priv->dev; 140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 141 struct mlx4_eqe *eqe; 142 u8 slave; 143 int i; 144 145 for (eqe = next_slave_event_eqe(slave_eq); eqe; 146 eqe = next_slave_event_eqe(slave_eq)) { 147 slave = eqe->slave_id; 148 149 /* All active slaves need to receive the event */ 150 if (slave == ALL_SLAVES) { 151 for (i = 0; i < dev->num_slaves; i++) { 152 if (i != dev->caps.function && 153 master->slave_state[i].active) 154 if (mlx4_GEN_EQE(dev, i, eqe)) 155 mlx4_warn(dev, "Failed to " 156 " generate event " 157 "for slave %d\n", i); 158 } 159 } else { 160 if (mlx4_GEN_EQE(dev, slave, eqe)) 161 mlx4_warn(dev, "Failed to generate event " 162 "for slave %d\n", slave); 163 } 164 ++slave_eq->cons; 165 } 166 } 167 168 169 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 170 { 171 struct mlx4_priv *priv = mlx4_priv(dev); 172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 173 struct mlx4_eqe *s_eqe; 174 unsigned long flags; 175 176 spin_lock_irqsave(&slave_eq->event_lock, flags); 177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 178 if ((!!(s_eqe->owner & 0x80)) ^ 179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. " 181 "No free EQE on slave events queue\n", slave); 182 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 183 return; 184 } 185 186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); 187 s_eqe->slave_id = slave; 188 /* ensure all information is written before setting the ownersip bit */ 189 wmb(); 190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 191 ++slave_eq->prod; 192 193 queue_work(priv->mfunc.master.comm_wq, 194 &priv->mfunc.master.slave_event_work); 195 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 196 } 197 198 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 199 struct mlx4_eqe *eqe) 200 { 201 struct mlx4_priv *priv = mlx4_priv(dev); 202 struct mlx4_slave_state *s_slave = 203 &priv->mfunc.master.slave_state[slave]; 204 205 if (!s_slave->active) { 206 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/ 207 return; 208 } 209 210 slave_event(dev, slave, eqe); 211 } 212 213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 214 { 215 struct mlx4_eqe eqe; 216 217 struct mlx4_priv *priv = mlx4_priv(dev); 218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 219 220 if (!s_slave->active) 221 return 0; 222 223 memset(&eqe, 0, sizeof eqe); 224 225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 227 eqe.event.port_mgmt_change.port = port; 228 229 return mlx4_GEN_EQE(dev, slave, &eqe); 230 } 231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 232 233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 234 { 235 struct mlx4_eqe eqe; 236 237 /*don't send if we don't have the that slave */ 238 if (dev->num_vfs < slave) 239 return 0; 240 memset(&eqe, 0, sizeof eqe); 241 242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 244 eqe.event.port_mgmt_change.port = port; 245 246 return mlx4_GEN_EQE(dev, slave, &eqe); 247 } 248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 249 250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 251 u8 port_subtype_change) 252 { 253 struct mlx4_eqe eqe; 254 255 /*don't send if we don't have the that slave */ 256 if (dev->num_vfs < slave) 257 return 0; 258 memset(&eqe, 0, sizeof eqe); 259 260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 261 eqe.subtype = port_subtype_change; 262 eqe.event.port_change.port = cpu_to_be32(port << 28); 263 264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 265 port_subtype_change, slave, port); 266 return mlx4_GEN_EQE(dev, slave, &eqe); 267 } 268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 269 270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 271 { 272 struct mlx4_priv *priv = mlx4_priv(dev); 273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 274 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) { 275 pr_err("%s: Error: asking for slave:%d, port:%d\n", 276 __func__, slave, port); 277 return SLAVE_PORT_DOWN; 278 } 279 return s_state[slave].port_state[port]; 280 } 281 EXPORT_SYMBOL(mlx4_get_slave_port_state); 282 283 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 284 enum slave_port_state state) 285 { 286 struct mlx4_priv *priv = mlx4_priv(dev); 287 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 288 289 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) { 290 pr_err("%s: Error: asking for slave:%d, port:%d\n", 291 __func__, slave, port); 292 return -1; 293 } 294 s_state[slave].port_state[port] = state; 295 296 return 0; 297 } 298 299 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 300 { 301 int i; 302 enum slave_port_gen_event gen_event; 303 304 for (i = 0; i < dev->num_slaves; i++) 305 set_and_calc_slave_port_state(dev, i, port, event, &gen_event); 306 } 307 /************************************************************************** 308 The function get as input the new event to that port, 309 and according to the prev state change the slave's port state. 310 The events are: 311 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 312 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 313 MLX4_PORT_STATE_IB_EVENT_GID_VALID 314 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 315 ***************************************************************************/ 316 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 317 u8 port, int event, 318 enum slave_port_gen_event *gen_event) 319 { 320 struct mlx4_priv *priv = mlx4_priv(dev); 321 struct mlx4_slave_state *ctx = NULL; 322 unsigned long flags; 323 int ret = -1; 324 enum slave_port_state cur_state = 325 mlx4_get_slave_port_state(dev, slave, port); 326 327 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 328 329 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) { 330 pr_err("%s: Error: asking for slave:%d, port:%d\n", 331 __func__, slave, port); 332 return ret; 333 } 334 335 ctx = &priv->mfunc.master.slave_state[slave]; 336 spin_lock_irqsave(&ctx->lock, flags); 337 338 switch (cur_state) { 339 case SLAVE_PORT_DOWN: 340 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 341 mlx4_set_slave_port_state(dev, slave, port, 342 SLAVE_PENDING_UP); 343 break; 344 case SLAVE_PENDING_UP: 345 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 346 mlx4_set_slave_port_state(dev, slave, port, 347 SLAVE_PORT_DOWN); 348 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 349 mlx4_set_slave_port_state(dev, slave, port, 350 SLAVE_PORT_UP); 351 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 352 } 353 break; 354 case SLAVE_PORT_UP: 355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 356 mlx4_set_slave_port_state(dev, slave, port, 357 SLAVE_PORT_DOWN); 358 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 359 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 360 event) { 361 mlx4_set_slave_port_state(dev, slave, port, 362 SLAVE_PENDING_UP); 363 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 364 } 365 break; 366 default: 367 pr_err("%s: BUG!!! UNKNOWN state: " 368 "slave:%d, port:%d\n", __func__, slave, port); 369 goto out; 370 } 371 ret = mlx4_get_slave_port_state(dev, slave, port); 372 373 out: 374 spin_unlock_irqrestore(&ctx->lock, flags); 375 return ret; 376 } 377 378 EXPORT_SYMBOL(set_and_calc_slave_port_state); 379 380 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 381 { 382 struct mlx4_eqe eqe; 383 384 memset(&eqe, 0, sizeof eqe); 385 386 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 387 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 388 eqe.event.port_mgmt_change.port = port; 389 eqe.event.port_mgmt_change.params.port_info.changed_attr = 390 cpu_to_be32((u32) attr); 391 392 slave_event(dev, ALL_SLAVES, &eqe); 393 return 0; 394 } 395 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 396 397 void mlx4_master_handle_slave_flr(struct work_struct *work) 398 { 399 struct mlx4_mfunc_master_ctx *master = 400 container_of(work, struct mlx4_mfunc_master_ctx, 401 slave_flr_event_work); 402 struct mlx4_mfunc *mfunc = 403 container_of(master, struct mlx4_mfunc, master); 404 struct mlx4_priv *priv = 405 container_of(mfunc, struct mlx4_priv, mfunc); 406 struct mlx4_dev *dev = &priv->dev; 407 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 408 int i; 409 int err; 410 unsigned long flags; 411 412 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 413 414 for (i = 0 ; i < dev->num_slaves; i++) { 415 416 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 417 mlx4_dbg(dev, "mlx4_handle_slave_flr: " 418 "clean slave: %d\n", i); 419 420 mlx4_delete_all_resources_for_slave(dev, i); 421 /*return the slave to running mode*/ 422 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 423 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 424 slave_state[i].is_slave_going_down = 0; 425 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 426 /*notify the FW:*/ 427 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 428 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 429 if (err) 430 mlx4_warn(dev, "Failed to notify FW on " 431 "FLR done (slave:%d)\n", i); 432 } 433 } 434 } 435 436 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 437 { 438 struct mlx4_priv *priv = mlx4_priv(dev); 439 struct mlx4_eqe *eqe; 440 int cqn; 441 int eqes_found = 0; 442 int set_ci = 0; 443 int port; 444 int slave = 0; 445 int ret; 446 u32 flr_slave; 447 u8 update_slave_state; 448 int i; 449 enum slave_port_gen_event gen_event; 450 unsigned long flags; 451 452 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) { 453 /* 454 * Make sure we read EQ entry contents after we've 455 * checked the ownership bit. 456 */ 457 rmb(); 458 459 switch (eqe->type) { 460 case MLX4_EVENT_TYPE_COMP: 461 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 462 mlx4_cq_completion(dev, cqn); 463 break; 464 465 case MLX4_EVENT_TYPE_PATH_MIG: 466 case MLX4_EVENT_TYPE_COMM_EST: 467 case MLX4_EVENT_TYPE_SQ_DRAINED: 468 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 469 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 470 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 471 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 472 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 473 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 474 if (mlx4_is_master(dev)) { 475 /* forward only to slave owning the QP */ 476 ret = mlx4_get_slave_from_resource_id(dev, 477 RES_QP, 478 be32_to_cpu(eqe->event.qp.qpn) 479 & 0xffffff, &slave); 480 if (ret && ret != -ENOENT) { 481 mlx4_dbg(dev, "QP event %02x(%02x) on " 482 "EQ %d at index %u: could " 483 "not get slave id (%d)\n", 484 eqe->type, eqe->subtype, 485 eq->eqn, eq->cons_index, ret); 486 break; 487 } 488 489 if (!ret && slave != dev->caps.function) { 490 mlx4_slave_event(dev, slave, eqe); 491 break; 492 } 493 494 } 495 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 496 0xffffff, eqe->type); 497 break; 498 499 case MLX4_EVENT_TYPE_SRQ_LIMIT: 500 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 501 __func__); 502 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 503 if (mlx4_is_master(dev)) { 504 /* forward only to slave owning the SRQ */ 505 ret = mlx4_get_slave_from_resource_id(dev, 506 RES_SRQ, 507 be32_to_cpu(eqe->event.srq.srqn) 508 & 0xffffff, 509 &slave); 510 if (ret && ret != -ENOENT) { 511 mlx4_warn(dev, "SRQ event %02x(%02x) " 512 "on EQ %d at index %u: could" 513 " not get slave id (%d)\n", 514 eqe->type, eqe->subtype, 515 eq->eqn, eq->cons_index, ret); 516 break; 517 } 518 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x," 519 " event: %02x(%02x)\n", __func__, 520 slave, 521 be32_to_cpu(eqe->event.srq.srqn), 522 eqe->type, eqe->subtype); 523 524 if (!ret && slave != dev->caps.function) { 525 mlx4_warn(dev, "%s: sending event " 526 "%02x(%02x) to slave:%d\n", 527 __func__, eqe->type, 528 eqe->subtype, slave); 529 mlx4_slave_event(dev, slave, eqe); 530 break; 531 } 532 } 533 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 534 0xffffff, eqe->type); 535 break; 536 537 case MLX4_EVENT_TYPE_CMD: 538 mlx4_cmd_event(dev, 539 be16_to_cpu(eqe->event.cmd.token), 540 eqe->event.cmd.status, 541 be64_to_cpu(eqe->event.cmd.out_param)); 542 break; 543 544 case MLX4_EVENT_TYPE_PORT_CHANGE: 545 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 546 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 547 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 548 port); 549 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 550 if (!mlx4_is_master(dev)) 551 break; 552 for (i = 0; i < dev->num_slaves; i++) { 553 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 554 if (i == mlx4_master_func_num(dev)) 555 continue; 556 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN" 557 " to slave: %d, port:%d\n", 558 __func__, i, port); 559 mlx4_slave_event(dev, i, eqe); 560 } else { /* IB port */ 561 set_and_calc_slave_port_state(dev, i, port, 562 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 563 &gen_event); 564 /*we can be in pending state, then do not send port_down event*/ 565 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 566 if (i == mlx4_master_func_num(dev)) 567 continue; 568 mlx4_slave_event(dev, i, eqe); 569 } 570 } 571 } 572 } else { 573 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 574 575 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 576 577 if (!mlx4_is_master(dev)) 578 break; 579 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 580 for (i = 0; i < dev->num_slaves; i++) { 581 if (i == mlx4_master_func_num(dev)) 582 continue; 583 mlx4_slave_event(dev, i, eqe); 584 } 585 else /* IB port */ 586 /* port-up event will be sent to a slave when the 587 * slave's alias-guid is set. This is done in alias_GUID.c 588 */ 589 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 590 } 591 break; 592 593 case MLX4_EVENT_TYPE_CQ_ERROR: 594 mlx4_warn(dev, "CQ %s on CQN %06x\n", 595 eqe->event.cq_err.syndrome == 1 ? 596 "overrun" : "access violation", 597 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 598 if (mlx4_is_master(dev)) { 599 ret = mlx4_get_slave_from_resource_id(dev, 600 RES_CQ, 601 be32_to_cpu(eqe->event.cq_err.cqn) 602 & 0xffffff, &slave); 603 if (ret && ret != -ENOENT) { 604 mlx4_dbg(dev, "CQ event %02x(%02x) on " 605 "EQ %d at index %u: could " 606 "not get slave id (%d)\n", 607 eqe->type, eqe->subtype, 608 eq->eqn, eq->cons_index, ret); 609 break; 610 } 611 612 if (!ret && slave != dev->caps.function) { 613 mlx4_slave_event(dev, slave, eqe); 614 break; 615 } 616 } 617 mlx4_cq_event(dev, 618 be32_to_cpu(eqe->event.cq_err.cqn) 619 & 0xffffff, 620 eqe->type); 621 break; 622 623 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 624 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 625 break; 626 627 case MLX4_EVENT_TYPE_COMM_CHANNEL: 628 if (!mlx4_is_master(dev)) { 629 mlx4_warn(dev, "Received comm channel event " 630 "for non master device\n"); 631 break; 632 } 633 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 634 eqe->event.comm_channel_arm.bit_vec, 635 sizeof eqe->event.comm_channel_arm.bit_vec); 636 queue_work(priv->mfunc.master.comm_wq, 637 &priv->mfunc.master.comm_work); 638 break; 639 640 case MLX4_EVENT_TYPE_FLR_EVENT: 641 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 642 if (!mlx4_is_master(dev)) { 643 mlx4_warn(dev, "Non-master function received" 644 "FLR event\n"); 645 break; 646 } 647 648 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 649 650 if (flr_slave >= dev->num_slaves) { 651 mlx4_warn(dev, 652 "Got FLR for unknown function: %d\n", 653 flr_slave); 654 update_slave_state = 0; 655 } else 656 update_slave_state = 1; 657 658 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 659 if (update_slave_state) { 660 priv->mfunc.master.slave_state[flr_slave].active = false; 661 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 662 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 663 } 664 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 665 queue_work(priv->mfunc.master.comm_wq, 666 &priv->mfunc.master.slave_flr_event_work); 667 break; 668 669 case MLX4_EVENT_TYPE_FATAL_WARNING: 670 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 671 if (mlx4_is_master(dev)) 672 for (i = 0; i < dev->num_slaves; i++) { 673 mlx4_dbg(dev, "%s: Sending " 674 "MLX4_FATAL_WARNING_SUBTYPE_WARMING" 675 " to slave: %d\n", __func__, i); 676 if (i == dev->caps.function) 677 continue; 678 mlx4_slave_event(dev, i, eqe); 679 } 680 mlx4_err(dev, "Temperature Threshold was reached! " 681 "Threshold: %d celsius degrees; " 682 "Current Temperature: %d\n", 683 be16_to_cpu(eqe->event.warming.warning_threshold), 684 be16_to_cpu(eqe->event.warming.current_temperature)); 685 } else 686 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), " 687 "subtype %02x on EQ %d at index %u. owner=%x, " 688 "nent=0x%x, slave=%x, ownership=%s\n", 689 eqe->type, eqe->subtype, eq->eqn, 690 eq->cons_index, eqe->owner, eq->nent, 691 eqe->slave_id, 692 !!(eqe->owner & 0x80) ^ 693 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 694 695 break; 696 697 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 698 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 699 (unsigned long) eqe); 700 break; 701 702 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 703 case MLX4_EVENT_TYPE_ECC_DETECT: 704 default: 705 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at " 706 "index %u. owner=%x, nent=0x%x, slave=%x, " 707 "ownership=%s\n", 708 eqe->type, eqe->subtype, eq->eqn, 709 eq->cons_index, eqe->owner, eq->nent, 710 eqe->slave_id, 711 !!(eqe->owner & 0x80) ^ 712 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 713 break; 714 }; 715 716 ++eq->cons_index; 717 eqes_found = 1; 718 ++set_ci; 719 720 /* 721 * The HCA will think the queue has overflowed if we 722 * don't tell it we've been processing events. We 723 * create our EQs with MLX4_NUM_SPARE_EQE extra 724 * entries, so we must update our consumer index at 725 * least that often. 726 */ 727 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 728 eq_set_ci(eq, 0); 729 set_ci = 0; 730 } 731 } 732 733 eq_set_ci(eq, 1); 734 735 return eqes_found; 736 } 737 738 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 739 { 740 struct mlx4_dev *dev = dev_ptr; 741 struct mlx4_priv *priv = mlx4_priv(dev); 742 int work = 0; 743 int i; 744 745 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 746 747 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 748 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 749 750 return IRQ_RETVAL(work); 751 } 752 753 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 754 { 755 struct mlx4_eq *eq = eq_ptr; 756 struct mlx4_dev *dev = eq->dev; 757 758 mlx4_eq_int(dev, eq); 759 760 /* MSI-X vectors always belong to us */ 761 return IRQ_HANDLED; 762 } 763 764 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 765 struct mlx4_vhcr *vhcr, 766 struct mlx4_cmd_mailbox *inbox, 767 struct mlx4_cmd_mailbox *outbox, 768 struct mlx4_cmd_info *cmd) 769 { 770 struct mlx4_priv *priv = mlx4_priv(dev); 771 struct mlx4_slave_event_eq_info *event_eq = 772 priv->mfunc.master.slave_state[slave].event_eq; 773 u32 in_modifier = vhcr->in_modifier; 774 u32 eqn = in_modifier & 0x3FF; 775 u64 in_param = vhcr->in_param; 776 int err = 0; 777 int i; 778 779 if (slave == dev->caps.function) 780 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 781 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 782 MLX4_CMD_NATIVE); 783 if (!err) 784 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 785 if (in_param & (1LL << i)) 786 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 787 788 return err; 789 } 790 791 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 792 int eq_num) 793 { 794 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 795 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 796 MLX4_CMD_WRAPPED); 797 } 798 799 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 800 int eq_num) 801 { 802 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 803 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 804 MLX4_CMD_WRAPPED); 805 } 806 807 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 808 int eq_num) 809 { 810 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 811 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A, 812 MLX4_CMD_WRAPPED); 813 } 814 815 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 816 { 817 /* 818 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 819 * we need to map, take the difference of highest index and 820 * the lowest index we'll use and add 1. 821 */ 822 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs + 823 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1; 824 } 825 826 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 827 { 828 struct mlx4_priv *priv = mlx4_priv(dev); 829 int index; 830 831 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 832 833 if (!priv->eq_table.uar_map[index]) { 834 priv->eq_table.uar_map[index] = 835 ioremap(pci_resource_start(dev->pdev, 2) + 836 ((eq->eqn / 4) << PAGE_SHIFT), 837 PAGE_SIZE); 838 if (!priv->eq_table.uar_map[index]) { 839 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 840 eq->eqn); 841 return NULL; 842 } 843 } 844 845 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 846 } 847 848 static void mlx4_unmap_uar(struct mlx4_dev *dev) 849 { 850 struct mlx4_priv *priv = mlx4_priv(dev); 851 int i; 852 853 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 854 if (priv->eq_table.uar_map[i]) { 855 iounmap(priv->eq_table.uar_map[i]); 856 priv->eq_table.uar_map[i] = NULL; 857 } 858 } 859 860 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 861 u8 intr, struct mlx4_eq *eq) 862 { 863 struct mlx4_priv *priv = mlx4_priv(dev); 864 struct mlx4_cmd_mailbox *mailbox; 865 struct mlx4_eq_context *eq_context; 866 int npages; 867 u64 *dma_list = NULL; 868 dma_addr_t t; 869 u64 mtt_addr; 870 int err = -ENOMEM; 871 int i; 872 873 eq->dev = dev; 874 eq->nent = roundup_pow_of_two(max(nent, 2)); 875 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 876 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE; 877 878 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 879 GFP_KERNEL); 880 if (!eq->page_list) 881 goto err_out; 882 883 for (i = 0; i < npages; ++i) 884 eq->page_list[i].buf = NULL; 885 886 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 887 if (!dma_list) 888 goto err_out_free; 889 890 mailbox = mlx4_alloc_cmd_mailbox(dev); 891 if (IS_ERR(mailbox)) 892 goto err_out_free; 893 eq_context = mailbox->buf; 894 895 for (i = 0; i < npages; ++i) { 896 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 897 PAGE_SIZE, &t, GFP_KERNEL); 898 if (!eq->page_list[i].buf) 899 goto err_out_free_pages; 900 901 dma_list[i] = t; 902 eq->page_list[i].map = t; 903 904 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 905 } 906 907 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 908 if (eq->eqn == -1) 909 goto err_out_free_pages; 910 911 eq->doorbell = mlx4_get_eq_uar(dev, eq); 912 if (!eq->doorbell) { 913 err = -ENOMEM; 914 goto err_out_free_eq; 915 } 916 917 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 918 if (err) 919 goto err_out_free_eq; 920 921 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 922 if (err) 923 goto err_out_free_mtt; 924 925 memset(eq_context, 0, sizeof *eq_context); 926 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 927 MLX4_EQ_STATE_ARMED); 928 eq_context->log_eq_size = ilog2(eq->nent); 929 eq_context->intr = intr; 930 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 931 932 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 933 eq_context->mtt_base_addr_h = mtt_addr >> 32; 934 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 935 936 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 937 if (err) { 938 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 939 goto err_out_free_mtt; 940 } 941 942 kfree(dma_list); 943 mlx4_free_cmd_mailbox(dev, mailbox); 944 945 eq->cons_index = 0; 946 947 return err; 948 949 err_out_free_mtt: 950 mlx4_mtt_cleanup(dev, &eq->mtt); 951 952 err_out_free_eq: 953 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn); 954 955 err_out_free_pages: 956 for (i = 0; i < npages; ++i) 957 if (eq->page_list[i].buf) 958 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 959 eq->page_list[i].buf, 960 eq->page_list[i].map); 961 962 mlx4_free_cmd_mailbox(dev, mailbox); 963 964 err_out_free: 965 kfree(eq->page_list); 966 kfree(dma_list); 967 968 err_out: 969 return err; 970 } 971 972 static void mlx4_free_eq(struct mlx4_dev *dev, 973 struct mlx4_eq *eq) 974 { 975 struct mlx4_priv *priv = mlx4_priv(dev); 976 struct mlx4_cmd_mailbox *mailbox; 977 int err; 978 int i; 979 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 980 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE; 981 982 mailbox = mlx4_alloc_cmd_mailbox(dev); 983 if (IS_ERR(mailbox)) 984 return; 985 986 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn); 987 if (err) 988 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 989 990 if (0) { 991 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 992 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) { 993 if (i % 4 == 0) 994 pr_cont("[%02x] ", i * 4); 995 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 996 if ((i + 1) % 4 == 0) 997 pr_cont("\n"); 998 } 999 } 1000 1001 mlx4_mtt_cleanup(dev, &eq->mtt); 1002 for (i = 0; i < npages; ++i) 1003 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 1004 eq->page_list[i].buf, 1005 eq->page_list[i].map); 1006 1007 kfree(eq->page_list); 1008 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn); 1009 mlx4_free_cmd_mailbox(dev, mailbox); 1010 } 1011 1012 static void mlx4_free_irqs(struct mlx4_dev *dev) 1013 { 1014 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1015 struct mlx4_priv *priv = mlx4_priv(dev); 1016 int i, vec; 1017 1018 if (eq_table->have_irq) 1019 free_irq(dev->pdev->irq, dev); 1020 1021 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1022 if (eq_table->eq[i].have_irq) { 1023 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1024 eq_table->eq[i].have_irq = 0; 1025 } 1026 1027 for (i = 0; i < dev->caps.comp_pool; i++) { 1028 /* 1029 * Freeing the assigned irq's 1030 * all bits should be 0, but we need to validate 1031 */ 1032 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1033 /* NO need protecting*/ 1034 vec = dev->caps.num_comp_vectors + 1 + i; 1035 free_irq(priv->eq_table.eq[vec].irq, 1036 &priv->eq_table.eq[vec]); 1037 } 1038 } 1039 1040 1041 kfree(eq_table->irq_names); 1042 } 1043 1044 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1045 { 1046 struct mlx4_priv *priv = mlx4_priv(dev); 1047 1048 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) + 1049 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1050 if (!priv->clr_base) { 1051 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n"); 1052 return -ENOMEM; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1059 { 1060 struct mlx4_priv *priv = mlx4_priv(dev); 1061 1062 iounmap(priv->clr_base); 1063 } 1064 1065 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1066 { 1067 struct mlx4_priv *priv = mlx4_priv(dev); 1068 1069 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1070 sizeof *priv->eq_table.eq, GFP_KERNEL); 1071 if (!priv->eq_table.eq) 1072 return -ENOMEM; 1073 1074 return 0; 1075 } 1076 1077 void mlx4_free_eq_table(struct mlx4_dev *dev) 1078 { 1079 kfree(mlx4_priv(dev)->eq_table.eq); 1080 } 1081 1082 int mlx4_init_eq_table(struct mlx4_dev *dev) 1083 { 1084 struct mlx4_priv *priv = mlx4_priv(dev); 1085 int err; 1086 int i; 1087 1088 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1089 sizeof *priv->eq_table.uar_map, 1090 GFP_KERNEL); 1091 if (!priv->eq_table.uar_map) { 1092 err = -ENOMEM; 1093 goto err_out_free; 1094 } 1095 1096 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs, 1097 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0); 1098 if (err) 1099 goto err_out_free; 1100 1101 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1102 priv->eq_table.uar_map[i] = NULL; 1103 1104 if (!mlx4_is_slave(dev)) { 1105 err = mlx4_map_clr_int(dev); 1106 if (err) 1107 goto err_out_bitmap; 1108 1109 priv->eq_table.clr_mask = 1110 swab32(1 << (priv->eq_table.inta_pin & 31)); 1111 priv->eq_table.clr_int = priv->clr_base + 1112 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1113 } 1114 1115 priv->eq_table.irq_names = 1116 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 + 1117 dev->caps.comp_pool), 1118 GFP_KERNEL); 1119 if (!priv->eq_table.irq_names) { 1120 err = -ENOMEM; 1121 goto err_out_bitmap; 1122 } 1123 1124 for (i = 0; i < dev->caps.num_comp_vectors; ++i) { 1125 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1126 dev->caps.reserved_cqs + 1127 MLX4_NUM_SPARE_EQE, 1128 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1129 &priv->eq_table.eq[i]); 1130 if (err) { 1131 --i; 1132 goto err_out_unmap; 1133 } 1134 } 1135 1136 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1137 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0, 1138 &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1139 if (err) 1140 goto err_out_comp; 1141 1142 /*if additional completion vectors poolsize is 0 this loop will not run*/ 1143 for (i = dev->caps.num_comp_vectors + 1; 1144 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) { 1145 1146 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1147 dev->caps.reserved_cqs + 1148 MLX4_NUM_SPARE_EQE, 1149 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1150 &priv->eq_table.eq[i]); 1151 if (err) { 1152 --i; 1153 goto err_out_unmap; 1154 } 1155 } 1156 1157 1158 if (dev->flags & MLX4_FLAG_MSI_X) { 1159 const char *eq_name; 1160 1161 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1162 if (i < dev->caps.num_comp_vectors) { 1163 snprintf(priv->eq_table.irq_names + 1164 i * MLX4_IRQNAME_SIZE, 1165 MLX4_IRQNAME_SIZE, 1166 "mlx4-comp-%d@pci:%s", i, 1167 pci_name(dev->pdev)); 1168 } else { 1169 snprintf(priv->eq_table.irq_names + 1170 i * MLX4_IRQNAME_SIZE, 1171 MLX4_IRQNAME_SIZE, 1172 "mlx4-async@pci:%s", 1173 pci_name(dev->pdev)); 1174 } 1175 1176 eq_name = priv->eq_table.irq_names + 1177 i * MLX4_IRQNAME_SIZE; 1178 err = request_irq(priv->eq_table.eq[i].irq, 1179 mlx4_msi_x_interrupt, 0, eq_name, 1180 priv->eq_table.eq + i); 1181 if (err) 1182 goto err_out_async; 1183 1184 priv->eq_table.eq[i].have_irq = 1; 1185 } 1186 } else { 1187 snprintf(priv->eq_table.irq_names, 1188 MLX4_IRQNAME_SIZE, 1189 DRV_NAME "@pci:%s", 1190 pci_name(dev->pdev)); 1191 err = request_irq(dev->pdev->irq, mlx4_interrupt, 1192 IRQF_SHARED, priv->eq_table.irq_names, dev); 1193 if (err) 1194 goto err_out_async; 1195 1196 priv->eq_table.have_irq = 1; 1197 } 1198 1199 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1200 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1201 if (err) 1202 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1203 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err); 1204 1205 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1206 eq_set_ci(&priv->eq_table.eq[i], 1); 1207 1208 return 0; 1209 1210 err_out_async: 1211 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1212 1213 err_out_comp: 1214 i = dev->caps.num_comp_vectors - 1; 1215 1216 err_out_unmap: 1217 while (i >= 0) { 1218 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1219 --i; 1220 } 1221 if (!mlx4_is_slave(dev)) 1222 mlx4_unmap_clr_int(dev); 1223 mlx4_free_irqs(dev); 1224 1225 err_out_bitmap: 1226 mlx4_unmap_uar(dev); 1227 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1228 1229 err_out_free: 1230 kfree(priv->eq_table.uar_map); 1231 1232 return err; 1233 } 1234 1235 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1236 { 1237 struct mlx4_priv *priv = mlx4_priv(dev); 1238 int i; 1239 1240 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1241 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1242 1243 mlx4_free_irqs(dev); 1244 1245 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) 1246 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1247 1248 if (!mlx4_is_slave(dev)) 1249 mlx4_unmap_clr_int(dev); 1250 1251 mlx4_unmap_uar(dev); 1252 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1253 1254 kfree(priv->eq_table.uar_map); 1255 } 1256 1257 /* A test that verifies that we can accept interrupts on all 1258 * the irq vectors of the device. 1259 * Interrupts are checked using the NOP command. 1260 */ 1261 int mlx4_test_interrupts(struct mlx4_dev *dev) 1262 { 1263 struct mlx4_priv *priv = mlx4_priv(dev); 1264 int i; 1265 int err; 1266 1267 err = mlx4_NOP(dev); 1268 /* When not in MSI_X, there is only one irq to check */ 1269 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1270 return err; 1271 1272 /* A loop over all completion vectors, for each vector we will check 1273 * whether it works by mapping command completions to that vector 1274 * and performing a NOP command 1275 */ 1276 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1277 /* Temporary use polling for command completions */ 1278 mlx4_cmd_use_polling(dev); 1279 1280 /* Map the new eq to handle all asynchronous events */ 1281 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1282 priv->eq_table.eq[i].eqn); 1283 if (err) { 1284 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1285 mlx4_cmd_use_events(dev); 1286 break; 1287 } 1288 1289 /* Go back to using events */ 1290 mlx4_cmd_use_events(dev); 1291 err = mlx4_NOP(dev); 1292 } 1293 1294 /* Return to default */ 1295 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1296 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1297 return err; 1298 } 1299 EXPORT_SYMBOL(mlx4_test_interrupts); 1300 1301 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1302 int *vector) 1303 { 1304 1305 struct mlx4_priv *priv = mlx4_priv(dev); 1306 int vec = 0, err = 0, i; 1307 1308 mutex_lock(&priv->msix_ctl.pool_lock); 1309 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1310 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1311 priv->msix_ctl.pool_bm |= 1ULL << i; 1312 vec = dev->caps.num_comp_vectors + 1 + i; 1313 snprintf(priv->eq_table.irq_names + 1314 vec * MLX4_IRQNAME_SIZE, 1315 MLX4_IRQNAME_SIZE, "%s", name); 1316 #ifdef CONFIG_RFS_ACCEL 1317 if (rmap) { 1318 err = irq_cpu_rmap_add(rmap, 1319 priv->eq_table.eq[vec].irq); 1320 if (err) 1321 mlx4_warn(dev, "Failed adding irq rmap\n"); 1322 } 1323 #endif 1324 err = request_irq(priv->eq_table.eq[vec].irq, 1325 mlx4_msi_x_interrupt, 0, 1326 &priv->eq_table.irq_names[vec<<5], 1327 priv->eq_table.eq + vec); 1328 if (err) { 1329 /*zero out bit by fliping it*/ 1330 priv->msix_ctl.pool_bm ^= 1 << i; 1331 vec = 0; 1332 continue; 1333 /*we dont want to break here*/ 1334 } 1335 eq_set_ci(&priv->eq_table.eq[vec], 1); 1336 } 1337 } 1338 mutex_unlock(&priv->msix_ctl.pool_lock); 1339 1340 if (vec) { 1341 *vector = vec; 1342 } else { 1343 *vector = 0; 1344 err = (i == dev->caps.comp_pool) ? -ENOSPC : err; 1345 } 1346 return err; 1347 } 1348 EXPORT_SYMBOL(mlx4_assign_eq); 1349 1350 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1351 { 1352 struct mlx4_priv *priv = mlx4_priv(dev); 1353 /*bm index*/ 1354 int i = vec - dev->caps.num_comp_vectors - 1; 1355 1356 if (likely(i >= 0)) { 1357 /*sanity check , making sure were not trying to free irq's 1358 Belonging to a legacy EQ*/ 1359 mutex_lock(&priv->msix_ctl.pool_lock); 1360 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1361 free_irq(priv->eq_table.eq[vec].irq, 1362 &priv->eq_table.eq[vec]); 1363 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1364 } 1365 mutex_unlock(&priv->msix_ctl.pool_lock); 1366 } 1367 1368 } 1369 EXPORT_SYMBOL(mlx4_release_eq); 1370 1371