1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/export.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/cpu_rmap.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 92 return async_ev_mask; 93 } 94 95 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 96 { 97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 98 req_not << 31), 99 eq->doorbell); 100 /* We still want ordering, just not swabbing, so add a barrier */ 101 mb(); 102 } 103 104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor) 105 { 106 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor); 108 /* CX3 is capable of extending the EQE from 32 to 64 bytes. 109 * When this feature is enabled, the first (in the lower addresses) 110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 111 * contain the legacy EQE information. 112 */ 113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 114 } 115 116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor) 117 { 118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor); 119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 120 } 121 122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 123 { 124 struct mlx4_eqe *eqe = 125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 126 return (!!(eqe->owner & 0x80) ^ 127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 128 eqe : NULL; 129 } 130 131 void mlx4_gen_slave_eqe(struct work_struct *work) 132 { 133 struct mlx4_mfunc_master_ctx *master = 134 container_of(work, struct mlx4_mfunc_master_ctx, 135 slave_event_work); 136 struct mlx4_mfunc *mfunc = 137 container_of(master, struct mlx4_mfunc, master); 138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 139 struct mlx4_dev *dev = &priv->dev; 140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 141 struct mlx4_eqe *eqe; 142 u8 slave; 143 int i; 144 145 for (eqe = next_slave_event_eqe(slave_eq); eqe; 146 eqe = next_slave_event_eqe(slave_eq)) { 147 slave = eqe->slave_id; 148 149 /* All active slaves need to receive the event */ 150 if (slave == ALL_SLAVES) { 151 for (i = 0; i < dev->num_slaves; i++) { 152 if (i != dev->caps.function && 153 master->slave_state[i].active) 154 if (mlx4_GEN_EQE(dev, i, eqe)) 155 mlx4_warn(dev, "Failed to " 156 " generate event " 157 "for slave %d\n", i); 158 } 159 } else { 160 if (mlx4_GEN_EQE(dev, slave, eqe)) 161 mlx4_warn(dev, "Failed to generate event " 162 "for slave %d\n", slave); 163 } 164 ++slave_eq->cons; 165 } 166 } 167 168 169 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 170 { 171 struct mlx4_priv *priv = mlx4_priv(dev); 172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 173 struct mlx4_eqe *s_eqe; 174 unsigned long flags; 175 176 spin_lock_irqsave(&slave_eq->event_lock, flags); 177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 178 if ((!!(s_eqe->owner & 0x80)) ^ 179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. " 181 "No free EQE on slave events queue\n", slave); 182 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 183 return; 184 } 185 186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); 187 s_eqe->slave_id = slave; 188 /* ensure all information is written before setting the ownersip bit */ 189 wmb(); 190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 191 ++slave_eq->prod; 192 193 queue_work(priv->mfunc.master.comm_wq, 194 &priv->mfunc.master.slave_event_work); 195 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 196 } 197 198 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 199 struct mlx4_eqe *eqe) 200 { 201 struct mlx4_priv *priv = mlx4_priv(dev); 202 struct mlx4_slave_state *s_slave = 203 &priv->mfunc.master.slave_state[slave]; 204 205 if (!s_slave->active) { 206 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/ 207 return; 208 } 209 210 slave_event(dev, slave, eqe); 211 } 212 213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 214 { 215 struct mlx4_eqe eqe; 216 217 struct mlx4_priv *priv = mlx4_priv(dev); 218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 219 220 if (!s_slave->active) 221 return 0; 222 223 memset(&eqe, 0, sizeof eqe); 224 225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 227 eqe.event.port_mgmt_change.port = port; 228 229 return mlx4_GEN_EQE(dev, slave, &eqe); 230 } 231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 232 233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 234 { 235 struct mlx4_eqe eqe; 236 237 /*don't send if we don't have the that slave */ 238 if (dev->num_vfs < slave) 239 return 0; 240 memset(&eqe, 0, sizeof eqe); 241 242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 244 eqe.event.port_mgmt_change.port = port; 245 246 return mlx4_GEN_EQE(dev, slave, &eqe); 247 } 248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 249 250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 251 u8 port_subtype_change) 252 { 253 struct mlx4_eqe eqe; 254 255 /*don't send if we don't have the that slave */ 256 if (dev->num_vfs < slave) 257 return 0; 258 memset(&eqe, 0, sizeof eqe); 259 260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 261 eqe.subtype = port_subtype_change; 262 eqe.event.port_change.port = cpu_to_be32(port << 28); 263 264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 265 port_subtype_change, slave, port); 266 return mlx4_GEN_EQE(dev, slave, &eqe); 267 } 268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 269 270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 271 { 272 struct mlx4_priv *priv = mlx4_priv(dev); 273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 274 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 275 276 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 277 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 278 pr_err("%s: Error: asking for slave:%d, port:%d\n", 279 __func__, slave, port); 280 return SLAVE_PORT_DOWN; 281 } 282 return s_state[slave].port_state[port]; 283 } 284 EXPORT_SYMBOL(mlx4_get_slave_port_state); 285 286 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 287 enum slave_port_state state) 288 { 289 struct mlx4_priv *priv = mlx4_priv(dev); 290 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 291 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 292 293 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 294 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 295 pr_err("%s: Error: asking for slave:%d, port:%d\n", 296 __func__, slave, port); 297 return -1; 298 } 299 s_state[slave].port_state[port] = state; 300 301 return 0; 302 } 303 304 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 305 { 306 int i; 307 enum slave_port_gen_event gen_event; 308 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 309 port); 310 311 for (i = 0; i < dev->num_vfs + 1; i++) 312 if (test_bit(i, slaves_pport.slaves)) 313 set_and_calc_slave_port_state(dev, i, port, 314 event, &gen_event); 315 } 316 /************************************************************************** 317 The function get as input the new event to that port, 318 and according to the prev state change the slave's port state. 319 The events are: 320 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 321 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 322 MLX4_PORT_STATE_IB_EVENT_GID_VALID 323 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 324 ***************************************************************************/ 325 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 326 u8 port, int event, 327 enum slave_port_gen_event *gen_event) 328 { 329 struct mlx4_priv *priv = mlx4_priv(dev); 330 struct mlx4_slave_state *ctx = NULL; 331 unsigned long flags; 332 int ret = -1; 333 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 334 enum slave_port_state cur_state = 335 mlx4_get_slave_port_state(dev, slave, port); 336 337 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 338 339 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 340 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 341 pr_err("%s: Error: asking for slave:%d, port:%d\n", 342 __func__, slave, port); 343 return ret; 344 } 345 346 ctx = &priv->mfunc.master.slave_state[slave]; 347 spin_lock_irqsave(&ctx->lock, flags); 348 349 switch (cur_state) { 350 case SLAVE_PORT_DOWN: 351 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 352 mlx4_set_slave_port_state(dev, slave, port, 353 SLAVE_PENDING_UP); 354 break; 355 case SLAVE_PENDING_UP: 356 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 357 mlx4_set_slave_port_state(dev, slave, port, 358 SLAVE_PORT_DOWN); 359 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 360 mlx4_set_slave_port_state(dev, slave, port, 361 SLAVE_PORT_UP); 362 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 363 } 364 break; 365 case SLAVE_PORT_UP: 366 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 367 mlx4_set_slave_port_state(dev, slave, port, 368 SLAVE_PORT_DOWN); 369 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 370 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 371 event) { 372 mlx4_set_slave_port_state(dev, slave, port, 373 SLAVE_PENDING_UP); 374 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 375 } 376 break; 377 default: 378 pr_err("%s: BUG!!! UNKNOWN state: " 379 "slave:%d, port:%d\n", __func__, slave, port); 380 goto out; 381 } 382 ret = mlx4_get_slave_port_state(dev, slave, port); 383 384 out: 385 spin_unlock_irqrestore(&ctx->lock, flags); 386 return ret; 387 } 388 389 EXPORT_SYMBOL(set_and_calc_slave_port_state); 390 391 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 392 { 393 struct mlx4_eqe eqe; 394 395 memset(&eqe, 0, sizeof eqe); 396 397 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 398 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 399 eqe.event.port_mgmt_change.port = port; 400 eqe.event.port_mgmt_change.params.port_info.changed_attr = 401 cpu_to_be32((u32) attr); 402 403 slave_event(dev, ALL_SLAVES, &eqe); 404 return 0; 405 } 406 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 407 408 void mlx4_master_handle_slave_flr(struct work_struct *work) 409 { 410 struct mlx4_mfunc_master_ctx *master = 411 container_of(work, struct mlx4_mfunc_master_ctx, 412 slave_flr_event_work); 413 struct mlx4_mfunc *mfunc = 414 container_of(master, struct mlx4_mfunc, master); 415 struct mlx4_priv *priv = 416 container_of(mfunc, struct mlx4_priv, mfunc); 417 struct mlx4_dev *dev = &priv->dev; 418 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 419 int i; 420 int err; 421 unsigned long flags; 422 423 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 424 425 for (i = 0 ; i < dev->num_slaves; i++) { 426 427 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 428 mlx4_dbg(dev, "mlx4_handle_slave_flr: " 429 "clean slave: %d\n", i); 430 431 mlx4_delete_all_resources_for_slave(dev, i); 432 /*return the slave to running mode*/ 433 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 434 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 435 slave_state[i].is_slave_going_down = 0; 436 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 437 /*notify the FW:*/ 438 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 440 if (err) 441 mlx4_warn(dev, "Failed to notify FW on " 442 "FLR done (slave:%d)\n", i); 443 } 444 } 445 } 446 447 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 448 { 449 struct mlx4_priv *priv = mlx4_priv(dev); 450 struct mlx4_eqe *eqe; 451 int cqn; 452 int eqes_found = 0; 453 int set_ci = 0; 454 int port; 455 int slave = 0; 456 int ret; 457 u32 flr_slave; 458 u8 update_slave_state; 459 int i; 460 enum slave_port_gen_event gen_event; 461 unsigned long flags; 462 struct mlx4_vport_state *s_info; 463 464 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) { 465 /* 466 * Make sure we read EQ entry contents after we've 467 * checked the ownership bit. 468 */ 469 rmb(); 470 471 switch (eqe->type) { 472 case MLX4_EVENT_TYPE_COMP: 473 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 474 mlx4_cq_completion(dev, cqn); 475 break; 476 477 case MLX4_EVENT_TYPE_PATH_MIG: 478 case MLX4_EVENT_TYPE_COMM_EST: 479 case MLX4_EVENT_TYPE_SQ_DRAINED: 480 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 481 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 482 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 483 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 484 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 485 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 486 if (mlx4_is_master(dev)) { 487 /* forward only to slave owning the QP */ 488 ret = mlx4_get_slave_from_resource_id(dev, 489 RES_QP, 490 be32_to_cpu(eqe->event.qp.qpn) 491 & 0xffffff, &slave); 492 if (ret && ret != -ENOENT) { 493 mlx4_dbg(dev, "QP event %02x(%02x) on " 494 "EQ %d at index %u: could " 495 "not get slave id (%d)\n", 496 eqe->type, eqe->subtype, 497 eq->eqn, eq->cons_index, ret); 498 break; 499 } 500 501 if (!ret && slave != dev->caps.function) { 502 mlx4_slave_event(dev, slave, eqe); 503 break; 504 } 505 506 } 507 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 508 0xffffff, eqe->type); 509 break; 510 511 case MLX4_EVENT_TYPE_SRQ_LIMIT: 512 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 513 __func__); 514 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 515 if (mlx4_is_master(dev)) { 516 /* forward only to slave owning the SRQ */ 517 ret = mlx4_get_slave_from_resource_id(dev, 518 RES_SRQ, 519 be32_to_cpu(eqe->event.srq.srqn) 520 & 0xffffff, 521 &slave); 522 if (ret && ret != -ENOENT) { 523 mlx4_warn(dev, "SRQ event %02x(%02x) " 524 "on EQ %d at index %u: could" 525 " not get slave id (%d)\n", 526 eqe->type, eqe->subtype, 527 eq->eqn, eq->cons_index, ret); 528 break; 529 } 530 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x," 531 " event: %02x(%02x)\n", __func__, 532 slave, 533 be32_to_cpu(eqe->event.srq.srqn), 534 eqe->type, eqe->subtype); 535 536 if (!ret && slave != dev->caps.function) { 537 mlx4_warn(dev, "%s: sending event " 538 "%02x(%02x) to slave:%d\n", 539 __func__, eqe->type, 540 eqe->subtype, slave); 541 mlx4_slave_event(dev, slave, eqe); 542 break; 543 } 544 } 545 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 546 0xffffff, eqe->type); 547 break; 548 549 case MLX4_EVENT_TYPE_CMD: 550 mlx4_cmd_event(dev, 551 be16_to_cpu(eqe->event.cmd.token), 552 eqe->event.cmd.status, 553 be64_to_cpu(eqe->event.cmd.out_param)); 554 break; 555 556 case MLX4_EVENT_TYPE_PORT_CHANGE: { 557 struct mlx4_slaves_pport slaves_port; 558 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 559 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 560 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 561 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 562 port); 563 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 564 if (!mlx4_is_master(dev)) 565 break; 566 for (i = 0; i < dev->num_vfs + 1; i++) { 567 if (!test_bit(i, slaves_port.slaves)) 568 continue; 569 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 570 if (i == mlx4_master_func_num(dev)) 571 continue; 572 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN" 573 " to slave: %d, port:%d\n", 574 __func__, i, port); 575 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 576 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 577 eqe->event.port_change.port = 578 cpu_to_be32( 579 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 580 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 581 mlx4_slave_event(dev, i, eqe); 582 } 583 } else { /* IB port */ 584 set_and_calc_slave_port_state(dev, i, port, 585 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 586 &gen_event); 587 /*we can be in pending state, then do not send port_down event*/ 588 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 589 if (i == mlx4_master_func_num(dev)) 590 continue; 591 mlx4_slave_event(dev, i, eqe); 592 } 593 } 594 } 595 } else { 596 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 597 598 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 599 600 if (!mlx4_is_master(dev)) 601 break; 602 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 603 for (i = 0; i < dev->num_vfs + 1; i++) { 604 if (!test_bit(i, slaves_port.slaves)) 605 continue; 606 if (i == mlx4_master_func_num(dev)) 607 continue; 608 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 609 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 610 eqe->event.port_change.port = 611 cpu_to_be32( 612 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 613 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 614 mlx4_slave_event(dev, i, eqe); 615 } 616 } 617 else /* IB port */ 618 /* port-up event will be sent to a slave when the 619 * slave's alias-guid is set. This is done in alias_GUID.c 620 */ 621 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 622 } 623 break; 624 } 625 626 case MLX4_EVENT_TYPE_CQ_ERROR: 627 mlx4_warn(dev, "CQ %s on CQN %06x\n", 628 eqe->event.cq_err.syndrome == 1 ? 629 "overrun" : "access violation", 630 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 631 if (mlx4_is_master(dev)) { 632 ret = mlx4_get_slave_from_resource_id(dev, 633 RES_CQ, 634 be32_to_cpu(eqe->event.cq_err.cqn) 635 & 0xffffff, &slave); 636 if (ret && ret != -ENOENT) { 637 mlx4_dbg(dev, "CQ event %02x(%02x) on " 638 "EQ %d at index %u: could " 639 "not get slave id (%d)\n", 640 eqe->type, eqe->subtype, 641 eq->eqn, eq->cons_index, ret); 642 break; 643 } 644 645 if (!ret && slave != dev->caps.function) { 646 mlx4_slave_event(dev, slave, eqe); 647 break; 648 } 649 } 650 mlx4_cq_event(dev, 651 be32_to_cpu(eqe->event.cq_err.cqn) 652 & 0xffffff, 653 eqe->type); 654 break; 655 656 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 657 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 658 break; 659 660 case MLX4_EVENT_TYPE_OP_REQUIRED: 661 atomic_inc(&priv->opreq_count); 662 /* FW commands can't be executed from interrupt context 663 * working in deferred task 664 */ 665 queue_work(mlx4_wq, &priv->opreq_task); 666 break; 667 668 case MLX4_EVENT_TYPE_COMM_CHANNEL: 669 if (!mlx4_is_master(dev)) { 670 mlx4_warn(dev, "Received comm channel event " 671 "for non master device\n"); 672 break; 673 } 674 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 675 eqe->event.comm_channel_arm.bit_vec, 676 sizeof eqe->event.comm_channel_arm.bit_vec); 677 queue_work(priv->mfunc.master.comm_wq, 678 &priv->mfunc.master.comm_work); 679 break; 680 681 case MLX4_EVENT_TYPE_FLR_EVENT: 682 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 683 if (!mlx4_is_master(dev)) { 684 mlx4_warn(dev, "Non-master function received" 685 "FLR event\n"); 686 break; 687 } 688 689 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 690 691 if (flr_slave >= dev->num_slaves) { 692 mlx4_warn(dev, 693 "Got FLR for unknown function: %d\n", 694 flr_slave); 695 update_slave_state = 0; 696 } else 697 update_slave_state = 1; 698 699 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 700 if (update_slave_state) { 701 priv->mfunc.master.slave_state[flr_slave].active = false; 702 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 703 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 704 } 705 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 706 queue_work(priv->mfunc.master.comm_wq, 707 &priv->mfunc.master.slave_flr_event_work); 708 break; 709 710 case MLX4_EVENT_TYPE_FATAL_WARNING: 711 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 712 if (mlx4_is_master(dev)) 713 for (i = 0; i < dev->num_slaves; i++) { 714 mlx4_dbg(dev, "%s: Sending " 715 "MLX4_FATAL_WARNING_SUBTYPE_WARMING" 716 " to slave: %d\n", __func__, i); 717 if (i == dev->caps.function) 718 continue; 719 mlx4_slave_event(dev, i, eqe); 720 } 721 mlx4_err(dev, "Temperature Threshold was reached! " 722 "Threshold: %d celsius degrees; " 723 "Current Temperature: %d\n", 724 be16_to_cpu(eqe->event.warming.warning_threshold), 725 be16_to_cpu(eqe->event.warming.current_temperature)); 726 } else 727 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), " 728 "subtype %02x on EQ %d at index %u. owner=%x, " 729 "nent=0x%x, slave=%x, ownership=%s\n", 730 eqe->type, eqe->subtype, eq->eqn, 731 eq->cons_index, eqe->owner, eq->nent, 732 eqe->slave_id, 733 !!(eqe->owner & 0x80) ^ 734 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 735 736 break; 737 738 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 739 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 740 (unsigned long) eqe); 741 break; 742 743 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 744 case MLX4_EVENT_TYPE_ECC_DETECT: 745 default: 746 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at " 747 "index %u. owner=%x, nent=0x%x, slave=%x, " 748 "ownership=%s\n", 749 eqe->type, eqe->subtype, eq->eqn, 750 eq->cons_index, eqe->owner, eq->nent, 751 eqe->slave_id, 752 !!(eqe->owner & 0x80) ^ 753 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 754 break; 755 }; 756 757 ++eq->cons_index; 758 eqes_found = 1; 759 ++set_ci; 760 761 /* 762 * The HCA will think the queue has overflowed if we 763 * don't tell it we've been processing events. We 764 * create our EQs with MLX4_NUM_SPARE_EQE extra 765 * entries, so we must update our consumer index at 766 * least that often. 767 */ 768 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 769 eq_set_ci(eq, 0); 770 set_ci = 0; 771 } 772 } 773 774 eq_set_ci(eq, 1); 775 776 return eqes_found; 777 } 778 779 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 780 { 781 struct mlx4_dev *dev = dev_ptr; 782 struct mlx4_priv *priv = mlx4_priv(dev); 783 int work = 0; 784 int i; 785 786 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 787 788 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 789 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 790 791 return IRQ_RETVAL(work); 792 } 793 794 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 795 { 796 struct mlx4_eq *eq = eq_ptr; 797 struct mlx4_dev *dev = eq->dev; 798 799 mlx4_eq_int(dev, eq); 800 801 /* MSI-X vectors always belong to us */ 802 return IRQ_HANDLED; 803 } 804 805 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 806 struct mlx4_vhcr *vhcr, 807 struct mlx4_cmd_mailbox *inbox, 808 struct mlx4_cmd_mailbox *outbox, 809 struct mlx4_cmd_info *cmd) 810 { 811 struct mlx4_priv *priv = mlx4_priv(dev); 812 struct mlx4_slave_event_eq_info *event_eq = 813 priv->mfunc.master.slave_state[slave].event_eq; 814 u32 in_modifier = vhcr->in_modifier; 815 u32 eqn = in_modifier & 0x3FF; 816 u64 in_param = vhcr->in_param; 817 int err = 0; 818 int i; 819 820 if (slave == dev->caps.function) 821 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 822 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 823 MLX4_CMD_NATIVE); 824 if (!err) 825 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 826 if (in_param & (1LL << i)) 827 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 828 829 return err; 830 } 831 832 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 833 int eq_num) 834 { 835 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 836 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 837 MLX4_CMD_WRAPPED); 838 } 839 840 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 841 int eq_num) 842 { 843 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 844 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 845 MLX4_CMD_WRAPPED); 846 } 847 848 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 849 int eq_num) 850 { 851 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 852 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A, 853 MLX4_CMD_WRAPPED); 854 } 855 856 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 857 { 858 /* 859 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 860 * we need to map, take the difference of highest index and 861 * the lowest index we'll use and add 1. 862 */ 863 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs + 864 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1; 865 } 866 867 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 868 { 869 struct mlx4_priv *priv = mlx4_priv(dev); 870 int index; 871 872 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 873 874 if (!priv->eq_table.uar_map[index]) { 875 priv->eq_table.uar_map[index] = 876 ioremap(pci_resource_start(dev->pdev, 2) + 877 ((eq->eqn / 4) << PAGE_SHIFT), 878 PAGE_SIZE); 879 if (!priv->eq_table.uar_map[index]) { 880 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 881 eq->eqn); 882 return NULL; 883 } 884 } 885 886 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 887 } 888 889 static void mlx4_unmap_uar(struct mlx4_dev *dev) 890 { 891 struct mlx4_priv *priv = mlx4_priv(dev); 892 int i; 893 894 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 895 if (priv->eq_table.uar_map[i]) { 896 iounmap(priv->eq_table.uar_map[i]); 897 priv->eq_table.uar_map[i] = NULL; 898 } 899 } 900 901 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 902 u8 intr, struct mlx4_eq *eq) 903 { 904 struct mlx4_priv *priv = mlx4_priv(dev); 905 struct mlx4_cmd_mailbox *mailbox; 906 struct mlx4_eq_context *eq_context; 907 int npages; 908 u64 *dma_list = NULL; 909 dma_addr_t t; 910 u64 mtt_addr; 911 int err = -ENOMEM; 912 int i; 913 914 eq->dev = dev; 915 eq->nent = roundup_pow_of_two(max(nent, 2)); 916 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 917 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE; 918 919 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 920 GFP_KERNEL); 921 if (!eq->page_list) 922 goto err_out; 923 924 for (i = 0; i < npages; ++i) 925 eq->page_list[i].buf = NULL; 926 927 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 928 if (!dma_list) 929 goto err_out_free; 930 931 mailbox = mlx4_alloc_cmd_mailbox(dev); 932 if (IS_ERR(mailbox)) 933 goto err_out_free; 934 eq_context = mailbox->buf; 935 936 for (i = 0; i < npages; ++i) { 937 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 938 PAGE_SIZE, &t, GFP_KERNEL); 939 if (!eq->page_list[i].buf) 940 goto err_out_free_pages; 941 942 dma_list[i] = t; 943 eq->page_list[i].map = t; 944 945 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 946 } 947 948 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 949 if (eq->eqn == -1) 950 goto err_out_free_pages; 951 952 eq->doorbell = mlx4_get_eq_uar(dev, eq); 953 if (!eq->doorbell) { 954 err = -ENOMEM; 955 goto err_out_free_eq; 956 } 957 958 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 959 if (err) 960 goto err_out_free_eq; 961 962 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 963 if (err) 964 goto err_out_free_mtt; 965 966 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 967 MLX4_EQ_STATE_ARMED); 968 eq_context->log_eq_size = ilog2(eq->nent); 969 eq_context->intr = intr; 970 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 971 972 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 973 eq_context->mtt_base_addr_h = mtt_addr >> 32; 974 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 975 976 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 977 if (err) { 978 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 979 goto err_out_free_mtt; 980 } 981 982 kfree(dma_list); 983 mlx4_free_cmd_mailbox(dev, mailbox); 984 985 eq->cons_index = 0; 986 987 return err; 988 989 err_out_free_mtt: 990 mlx4_mtt_cleanup(dev, &eq->mtt); 991 992 err_out_free_eq: 993 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 994 995 err_out_free_pages: 996 for (i = 0; i < npages; ++i) 997 if (eq->page_list[i].buf) 998 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 999 eq->page_list[i].buf, 1000 eq->page_list[i].map); 1001 1002 mlx4_free_cmd_mailbox(dev, mailbox); 1003 1004 err_out_free: 1005 kfree(eq->page_list); 1006 kfree(dma_list); 1007 1008 err_out: 1009 return err; 1010 } 1011 1012 static void mlx4_free_eq(struct mlx4_dev *dev, 1013 struct mlx4_eq *eq) 1014 { 1015 struct mlx4_priv *priv = mlx4_priv(dev); 1016 struct mlx4_cmd_mailbox *mailbox; 1017 int err; 1018 int i; 1019 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 1020 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE; 1021 1022 mailbox = mlx4_alloc_cmd_mailbox(dev); 1023 if (IS_ERR(mailbox)) 1024 return; 1025 1026 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn); 1027 if (err) 1028 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1029 1030 if (0) { 1031 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 1032 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) { 1033 if (i % 4 == 0) 1034 pr_cont("[%02x] ", i * 4); 1035 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 1036 if ((i + 1) % 4 == 0) 1037 pr_cont("\n"); 1038 } 1039 } 1040 1041 mlx4_mtt_cleanup(dev, &eq->mtt); 1042 for (i = 0; i < npages; ++i) 1043 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 1044 eq->page_list[i].buf, 1045 eq->page_list[i].map); 1046 1047 kfree(eq->page_list); 1048 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1049 mlx4_free_cmd_mailbox(dev, mailbox); 1050 } 1051 1052 static void mlx4_free_irqs(struct mlx4_dev *dev) 1053 { 1054 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1055 struct mlx4_priv *priv = mlx4_priv(dev); 1056 int i, vec; 1057 1058 if (eq_table->have_irq) 1059 free_irq(dev->pdev->irq, dev); 1060 1061 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1062 if (eq_table->eq[i].have_irq) { 1063 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1064 eq_table->eq[i].have_irq = 0; 1065 } 1066 1067 for (i = 0; i < dev->caps.comp_pool; i++) { 1068 /* 1069 * Freeing the assigned irq's 1070 * all bits should be 0, but we need to validate 1071 */ 1072 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1073 /* NO need protecting*/ 1074 vec = dev->caps.num_comp_vectors + 1 + i; 1075 free_irq(priv->eq_table.eq[vec].irq, 1076 &priv->eq_table.eq[vec]); 1077 } 1078 } 1079 1080 1081 kfree(eq_table->irq_names); 1082 } 1083 1084 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1085 { 1086 struct mlx4_priv *priv = mlx4_priv(dev); 1087 1088 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) + 1089 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1090 if (!priv->clr_base) { 1091 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n"); 1092 return -ENOMEM; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1099 { 1100 struct mlx4_priv *priv = mlx4_priv(dev); 1101 1102 iounmap(priv->clr_base); 1103 } 1104 1105 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1106 { 1107 struct mlx4_priv *priv = mlx4_priv(dev); 1108 1109 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1110 sizeof *priv->eq_table.eq, GFP_KERNEL); 1111 if (!priv->eq_table.eq) 1112 return -ENOMEM; 1113 1114 return 0; 1115 } 1116 1117 void mlx4_free_eq_table(struct mlx4_dev *dev) 1118 { 1119 kfree(mlx4_priv(dev)->eq_table.eq); 1120 } 1121 1122 int mlx4_init_eq_table(struct mlx4_dev *dev) 1123 { 1124 struct mlx4_priv *priv = mlx4_priv(dev); 1125 int err; 1126 int i; 1127 1128 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1129 sizeof *priv->eq_table.uar_map, 1130 GFP_KERNEL); 1131 if (!priv->eq_table.uar_map) { 1132 err = -ENOMEM; 1133 goto err_out_free; 1134 } 1135 1136 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs, 1137 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0); 1138 if (err) 1139 goto err_out_free; 1140 1141 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1142 priv->eq_table.uar_map[i] = NULL; 1143 1144 if (!mlx4_is_slave(dev)) { 1145 err = mlx4_map_clr_int(dev); 1146 if (err) 1147 goto err_out_bitmap; 1148 1149 priv->eq_table.clr_mask = 1150 swab32(1 << (priv->eq_table.inta_pin & 31)); 1151 priv->eq_table.clr_int = priv->clr_base + 1152 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1153 } 1154 1155 priv->eq_table.irq_names = 1156 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 + 1157 dev->caps.comp_pool), 1158 GFP_KERNEL); 1159 if (!priv->eq_table.irq_names) { 1160 err = -ENOMEM; 1161 goto err_out_bitmap; 1162 } 1163 1164 for (i = 0; i < dev->caps.num_comp_vectors; ++i) { 1165 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1166 dev->caps.reserved_cqs + 1167 MLX4_NUM_SPARE_EQE, 1168 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1169 &priv->eq_table.eq[i]); 1170 if (err) { 1171 --i; 1172 goto err_out_unmap; 1173 } 1174 } 1175 1176 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1177 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0, 1178 &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1179 if (err) 1180 goto err_out_comp; 1181 1182 /*if additional completion vectors poolsize is 0 this loop will not run*/ 1183 for (i = dev->caps.num_comp_vectors + 1; 1184 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) { 1185 1186 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1187 dev->caps.reserved_cqs + 1188 MLX4_NUM_SPARE_EQE, 1189 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1190 &priv->eq_table.eq[i]); 1191 if (err) { 1192 --i; 1193 goto err_out_unmap; 1194 } 1195 } 1196 1197 1198 if (dev->flags & MLX4_FLAG_MSI_X) { 1199 const char *eq_name; 1200 1201 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1202 if (i < dev->caps.num_comp_vectors) { 1203 snprintf(priv->eq_table.irq_names + 1204 i * MLX4_IRQNAME_SIZE, 1205 MLX4_IRQNAME_SIZE, 1206 "mlx4-comp-%d@pci:%s", i, 1207 pci_name(dev->pdev)); 1208 } else { 1209 snprintf(priv->eq_table.irq_names + 1210 i * MLX4_IRQNAME_SIZE, 1211 MLX4_IRQNAME_SIZE, 1212 "mlx4-async@pci:%s", 1213 pci_name(dev->pdev)); 1214 } 1215 1216 eq_name = priv->eq_table.irq_names + 1217 i * MLX4_IRQNAME_SIZE; 1218 err = request_irq(priv->eq_table.eq[i].irq, 1219 mlx4_msi_x_interrupt, 0, eq_name, 1220 priv->eq_table.eq + i); 1221 if (err) 1222 goto err_out_async; 1223 1224 priv->eq_table.eq[i].have_irq = 1; 1225 } 1226 } else { 1227 snprintf(priv->eq_table.irq_names, 1228 MLX4_IRQNAME_SIZE, 1229 DRV_NAME "@pci:%s", 1230 pci_name(dev->pdev)); 1231 err = request_irq(dev->pdev->irq, mlx4_interrupt, 1232 IRQF_SHARED, priv->eq_table.irq_names, dev); 1233 if (err) 1234 goto err_out_async; 1235 1236 priv->eq_table.have_irq = 1; 1237 } 1238 1239 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1240 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1241 if (err) 1242 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1243 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err); 1244 1245 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1246 eq_set_ci(&priv->eq_table.eq[i], 1); 1247 1248 return 0; 1249 1250 err_out_async: 1251 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1252 1253 err_out_comp: 1254 i = dev->caps.num_comp_vectors - 1; 1255 1256 err_out_unmap: 1257 while (i >= 0) { 1258 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1259 --i; 1260 } 1261 if (!mlx4_is_slave(dev)) 1262 mlx4_unmap_clr_int(dev); 1263 mlx4_free_irqs(dev); 1264 1265 err_out_bitmap: 1266 mlx4_unmap_uar(dev); 1267 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1268 1269 err_out_free: 1270 kfree(priv->eq_table.uar_map); 1271 1272 return err; 1273 } 1274 1275 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1276 { 1277 struct mlx4_priv *priv = mlx4_priv(dev); 1278 int i; 1279 1280 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1281 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1282 1283 mlx4_free_irqs(dev); 1284 1285 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) 1286 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1287 1288 if (!mlx4_is_slave(dev)) 1289 mlx4_unmap_clr_int(dev); 1290 1291 mlx4_unmap_uar(dev); 1292 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1293 1294 kfree(priv->eq_table.uar_map); 1295 } 1296 1297 /* A test that verifies that we can accept interrupts on all 1298 * the irq vectors of the device. 1299 * Interrupts are checked using the NOP command. 1300 */ 1301 int mlx4_test_interrupts(struct mlx4_dev *dev) 1302 { 1303 struct mlx4_priv *priv = mlx4_priv(dev); 1304 int i; 1305 int err; 1306 1307 err = mlx4_NOP(dev); 1308 /* When not in MSI_X, there is only one irq to check */ 1309 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1310 return err; 1311 1312 /* A loop over all completion vectors, for each vector we will check 1313 * whether it works by mapping command completions to that vector 1314 * and performing a NOP command 1315 */ 1316 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1317 /* Temporary use polling for command completions */ 1318 mlx4_cmd_use_polling(dev); 1319 1320 /* Map the new eq to handle all asynchronous events */ 1321 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1322 priv->eq_table.eq[i].eqn); 1323 if (err) { 1324 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1325 mlx4_cmd_use_events(dev); 1326 break; 1327 } 1328 1329 /* Go back to using events */ 1330 mlx4_cmd_use_events(dev); 1331 err = mlx4_NOP(dev); 1332 } 1333 1334 /* Return to default */ 1335 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1336 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1337 return err; 1338 } 1339 EXPORT_SYMBOL(mlx4_test_interrupts); 1340 1341 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1342 int *vector) 1343 { 1344 1345 struct mlx4_priv *priv = mlx4_priv(dev); 1346 int vec = 0, err = 0, i; 1347 1348 mutex_lock(&priv->msix_ctl.pool_lock); 1349 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1350 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1351 priv->msix_ctl.pool_bm |= 1ULL << i; 1352 vec = dev->caps.num_comp_vectors + 1 + i; 1353 snprintf(priv->eq_table.irq_names + 1354 vec * MLX4_IRQNAME_SIZE, 1355 MLX4_IRQNAME_SIZE, "%s", name); 1356 #ifdef CONFIG_RFS_ACCEL 1357 if (rmap) { 1358 err = irq_cpu_rmap_add(rmap, 1359 priv->eq_table.eq[vec].irq); 1360 if (err) 1361 mlx4_warn(dev, "Failed adding irq rmap\n"); 1362 } 1363 #endif 1364 err = request_irq(priv->eq_table.eq[vec].irq, 1365 mlx4_msi_x_interrupt, 0, 1366 &priv->eq_table.irq_names[vec<<5], 1367 priv->eq_table.eq + vec); 1368 if (err) { 1369 /*zero out bit by fliping it*/ 1370 priv->msix_ctl.pool_bm ^= 1 << i; 1371 vec = 0; 1372 continue; 1373 /*we dont want to break here*/ 1374 } 1375 eq_set_ci(&priv->eq_table.eq[vec], 1); 1376 } 1377 } 1378 mutex_unlock(&priv->msix_ctl.pool_lock); 1379 1380 if (vec) { 1381 *vector = vec; 1382 } else { 1383 *vector = 0; 1384 err = (i == dev->caps.comp_pool) ? -ENOSPC : err; 1385 } 1386 return err; 1387 } 1388 EXPORT_SYMBOL(mlx4_assign_eq); 1389 1390 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1391 { 1392 struct mlx4_priv *priv = mlx4_priv(dev); 1393 /*bm index*/ 1394 int i = vec - dev->caps.num_comp_vectors - 1; 1395 1396 if (likely(i >= 0)) { 1397 /*sanity check , making sure were not trying to free irq's 1398 Belonging to a legacy EQ*/ 1399 mutex_lock(&priv->msix_ctl.pool_lock); 1400 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1401 free_irq(priv->eq_table.eq[vec].irq, 1402 &priv->eq_table.eq[vec]); 1403 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1404 } 1405 mutex_unlock(&priv->msix_ctl.pool_lock); 1406 } 1407 1408 } 1409 EXPORT_SYMBOL(mlx4_release_eq); 1410 1411