1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/export.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/cpu_rmap.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT); 93 94 return async_ev_mask; 95 } 96 97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 98 { 99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 100 req_not << 31), 101 eq->doorbell); 102 /* We still want ordering, just not swabbing, so add a barrier */ 103 mb(); 104 } 105 106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, 107 u8 eqe_size) 108 { 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; 111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with 112 * strides of 64B,128B and 256B. 113 * When 64B EQE is used, the first (in the lower addresses) 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 115 * contain the legacy EQE information. 116 * In all other cases, the first 32B contains the legacy EQE info. 117 */ 118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 119 } 120 121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) 122 { 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 125 } 126 127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 128 { 129 struct mlx4_eqe *eqe = 130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 131 return (!!(eqe->owner & 0x80) ^ 132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 133 eqe : NULL; 134 } 135 136 void mlx4_gen_slave_eqe(struct work_struct *work) 137 { 138 struct mlx4_mfunc_master_ctx *master = 139 container_of(work, struct mlx4_mfunc_master_ctx, 140 slave_event_work); 141 struct mlx4_mfunc *mfunc = 142 container_of(master, struct mlx4_mfunc, master); 143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 144 struct mlx4_dev *dev = &priv->dev; 145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 146 struct mlx4_eqe *eqe; 147 u8 slave; 148 int i, phys_port, slave_port; 149 150 for (eqe = next_slave_event_eqe(slave_eq); eqe; 151 eqe = next_slave_event_eqe(slave_eq)) { 152 slave = eqe->slave_id; 153 154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE && 155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN && 156 mlx4_is_bonded(dev)) { 157 struct mlx4_port_cap port_cap; 158 159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state) 160 goto consume; 161 162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state) 163 goto consume; 164 } 165 /* All active slaves need to receive the event */ 166 if (slave == ALL_SLAVES) { 167 for (i = 0; i <= dev->persist->num_vfs; i++) { 168 phys_port = 0; 169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT && 170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) { 171 phys_port = eqe->event.port_mgmt_change.port; 172 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port); 173 if (slave_port < 0) /* VF doesn't have this port */ 174 continue; 175 eqe->event.port_mgmt_change.port = slave_port; 176 } 177 if (mlx4_GEN_EQE(dev, i, eqe)) 178 mlx4_warn(dev, "Failed to generate event for slave %d\n", 179 i); 180 if (phys_port) 181 eqe->event.port_mgmt_change.port = phys_port; 182 } 183 } else { 184 if (mlx4_GEN_EQE(dev, slave, eqe)) 185 mlx4_warn(dev, "Failed to generate event for slave %d\n", 186 slave); 187 } 188 consume: 189 ++slave_eq->cons; 190 } 191 } 192 193 194 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 195 { 196 struct mlx4_priv *priv = mlx4_priv(dev); 197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 198 struct mlx4_eqe *s_eqe; 199 unsigned long flags; 200 201 spin_lock_irqsave(&slave_eq->event_lock, flags); 202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 203 if ((!!(s_eqe->owner & 0x80)) ^ 204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 205 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 206 slave); 207 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 208 return; 209 } 210 211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1); 212 s_eqe->slave_id = slave; 213 /* ensure all information is written before setting the ownersip bit */ 214 dma_wmb(); 215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 216 ++slave_eq->prod; 217 218 queue_work(priv->mfunc.master.comm_wq, 219 &priv->mfunc.master.slave_event_work); 220 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 221 } 222 223 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 224 struct mlx4_eqe *eqe) 225 { 226 struct mlx4_priv *priv = mlx4_priv(dev); 227 228 if (slave < 0 || slave > dev->persist->num_vfs || 229 slave == dev->caps.function || 230 !priv->mfunc.master.slave_state[slave].active) 231 return; 232 233 slave_event(dev, slave, eqe); 234 } 235 236 #if defined(CONFIG_SMP) 237 static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec) 238 { 239 int hint_err; 240 struct mlx4_dev *dev = &priv->dev; 241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; 242 243 if (!eq->affinity_mask || cpumask_empty(eq->affinity_mask)) 244 return; 245 246 hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask); 247 if (hint_err) 248 mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err); 249 } 250 #endif 251 252 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 253 { 254 struct mlx4_eqe eqe; 255 256 struct mlx4_priv *priv = mlx4_priv(dev); 257 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 258 259 if (!s_slave->active) 260 return 0; 261 262 memset(&eqe, 0, sizeof eqe); 263 264 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 265 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 266 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 267 268 return mlx4_GEN_EQE(dev, slave, &eqe); 269 } 270 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 271 272 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 273 { 274 struct mlx4_eqe eqe; 275 276 /*don't send if we don't have the that slave */ 277 if (dev->persist->num_vfs < slave) 278 return 0; 279 memset(&eqe, 0, sizeof eqe); 280 281 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 282 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 283 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 284 285 return mlx4_GEN_EQE(dev, slave, &eqe); 286 } 287 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 288 289 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 290 u8 port_subtype_change) 291 { 292 struct mlx4_eqe eqe; 293 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port); 294 295 /*don't send if we don't have the that slave */ 296 if (dev->persist->num_vfs < slave) 297 return 0; 298 memset(&eqe, 0, sizeof eqe); 299 300 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 301 eqe.subtype = port_subtype_change; 302 eqe.event.port_change.port = cpu_to_be32(slave_port << 28); 303 304 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 305 port_subtype_change, slave, port); 306 return mlx4_GEN_EQE(dev, slave, &eqe); 307 } 308 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 309 310 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 311 { 312 struct mlx4_priv *priv = mlx4_priv(dev); 313 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 314 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 315 316 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 317 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 318 pr_err("%s: Error: asking for slave:%d, port:%d\n", 319 __func__, slave, port); 320 return SLAVE_PORT_DOWN; 321 } 322 return s_state[slave].port_state[port]; 323 } 324 EXPORT_SYMBOL(mlx4_get_slave_port_state); 325 326 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 327 enum slave_port_state state) 328 { 329 struct mlx4_priv *priv = mlx4_priv(dev); 330 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 331 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 332 333 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 334 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 335 pr_err("%s: Error: asking for slave:%d, port:%d\n", 336 __func__, slave, port); 337 return -1; 338 } 339 s_state[slave].port_state[port] = state; 340 341 return 0; 342 } 343 344 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 345 { 346 int i; 347 enum slave_port_gen_event gen_event; 348 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 349 port); 350 351 for (i = 0; i < dev->persist->num_vfs + 1; i++) 352 if (test_bit(i, slaves_pport.slaves)) 353 set_and_calc_slave_port_state(dev, i, port, 354 event, &gen_event); 355 } 356 /************************************************************************** 357 The function get as input the new event to that port, 358 and according to the prev state change the slave's port state. 359 The events are: 360 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 361 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 362 MLX4_PORT_STATE_IB_EVENT_GID_VALID 363 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 364 ***************************************************************************/ 365 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 366 u8 port, int event, 367 enum slave_port_gen_event *gen_event) 368 { 369 struct mlx4_priv *priv = mlx4_priv(dev); 370 struct mlx4_slave_state *ctx = NULL; 371 unsigned long flags; 372 int ret = -1; 373 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 374 enum slave_port_state cur_state = 375 mlx4_get_slave_port_state(dev, slave, port); 376 377 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 378 379 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 380 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 381 pr_err("%s: Error: asking for slave:%d, port:%d\n", 382 __func__, slave, port); 383 return ret; 384 } 385 386 ctx = &priv->mfunc.master.slave_state[slave]; 387 spin_lock_irqsave(&ctx->lock, flags); 388 389 switch (cur_state) { 390 case SLAVE_PORT_DOWN: 391 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 392 mlx4_set_slave_port_state(dev, slave, port, 393 SLAVE_PENDING_UP); 394 break; 395 case SLAVE_PENDING_UP: 396 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 397 mlx4_set_slave_port_state(dev, slave, port, 398 SLAVE_PORT_DOWN); 399 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 400 mlx4_set_slave_port_state(dev, slave, port, 401 SLAVE_PORT_UP); 402 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 403 } 404 break; 405 case SLAVE_PORT_UP: 406 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 407 mlx4_set_slave_port_state(dev, slave, port, 408 SLAVE_PORT_DOWN); 409 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 410 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 411 event) { 412 mlx4_set_slave_port_state(dev, slave, port, 413 SLAVE_PENDING_UP); 414 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 415 } 416 break; 417 default: 418 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 419 __func__, slave, port); 420 goto out; 421 } 422 ret = mlx4_get_slave_port_state(dev, slave, port); 423 424 out: 425 spin_unlock_irqrestore(&ctx->lock, flags); 426 return ret; 427 } 428 429 EXPORT_SYMBOL(set_and_calc_slave_port_state); 430 431 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 432 { 433 struct mlx4_eqe eqe; 434 435 memset(&eqe, 0, sizeof eqe); 436 437 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 438 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 439 eqe.event.port_mgmt_change.port = port; 440 eqe.event.port_mgmt_change.params.port_info.changed_attr = 441 cpu_to_be32((u32) attr); 442 443 slave_event(dev, ALL_SLAVES, &eqe); 444 return 0; 445 } 446 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 447 448 void mlx4_master_handle_slave_flr(struct work_struct *work) 449 { 450 struct mlx4_mfunc_master_ctx *master = 451 container_of(work, struct mlx4_mfunc_master_ctx, 452 slave_flr_event_work); 453 struct mlx4_mfunc *mfunc = 454 container_of(master, struct mlx4_mfunc, master); 455 struct mlx4_priv *priv = 456 container_of(mfunc, struct mlx4_priv, mfunc); 457 struct mlx4_dev *dev = &priv->dev; 458 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 459 int i; 460 int err; 461 unsigned long flags; 462 463 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 464 465 for (i = 0 ; i < dev->num_slaves; i++) { 466 467 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 468 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 469 i); 470 /* In case of 'Reset flow' FLR can be generated for 471 * a slave before mlx4_load_one is done. 472 * make sure interface is up before trying to delete 473 * slave resources which weren't allocated yet. 474 */ 475 if (dev->persist->interface_state & 476 MLX4_INTERFACE_STATE_UP) 477 mlx4_delete_all_resources_for_slave(dev, i); 478 /*return the slave to running mode*/ 479 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 480 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 481 slave_state[i].is_slave_going_down = 0; 482 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 483 /*notify the FW:*/ 484 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 485 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 486 if (err) 487 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 488 i); 489 } 490 } 491 } 492 493 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 494 { 495 struct mlx4_priv *priv = mlx4_priv(dev); 496 struct mlx4_eqe *eqe; 497 int cqn = -1; 498 int eqes_found = 0; 499 int set_ci = 0; 500 int port; 501 int slave = 0; 502 int ret; 503 u32 flr_slave; 504 u8 update_slave_state; 505 int i; 506 enum slave_port_gen_event gen_event; 507 unsigned long flags; 508 struct mlx4_vport_state *s_info; 509 int eqe_size = dev->caps.eqe_size; 510 511 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { 512 /* 513 * Make sure we read EQ entry contents after we've 514 * checked the ownership bit. 515 */ 516 dma_rmb(); 517 518 switch (eqe->type) { 519 case MLX4_EVENT_TYPE_COMP: 520 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 521 mlx4_cq_completion(dev, cqn); 522 break; 523 524 case MLX4_EVENT_TYPE_PATH_MIG: 525 case MLX4_EVENT_TYPE_COMM_EST: 526 case MLX4_EVENT_TYPE_SQ_DRAINED: 527 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 528 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 529 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 530 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 531 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 532 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 533 if (mlx4_is_master(dev)) { 534 /* forward only to slave owning the QP */ 535 ret = mlx4_get_slave_from_resource_id(dev, 536 RES_QP, 537 be32_to_cpu(eqe->event.qp.qpn) 538 & 0xffffff, &slave); 539 if (ret && ret != -ENOENT) { 540 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 541 eqe->type, eqe->subtype, 542 eq->eqn, eq->cons_index, ret); 543 break; 544 } 545 546 if (!ret && slave != dev->caps.function) { 547 mlx4_slave_event(dev, slave, eqe); 548 break; 549 } 550 551 } 552 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 553 0xffffff, eqe->type); 554 break; 555 556 case MLX4_EVENT_TYPE_SRQ_LIMIT: 557 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 558 __func__); 559 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 560 if (mlx4_is_master(dev)) { 561 /* forward only to slave owning the SRQ */ 562 ret = mlx4_get_slave_from_resource_id(dev, 563 RES_SRQ, 564 be32_to_cpu(eqe->event.srq.srqn) 565 & 0xffffff, 566 &slave); 567 if (ret && ret != -ENOENT) { 568 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 569 eqe->type, eqe->subtype, 570 eq->eqn, eq->cons_index, ret); 571 break; 572 } 573 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 574 __func__, slave, 575 be32_to_cpu(eqe->event.srq.srqn), 576 eqe->type, eqe->subtype); 577 578 if (!ret && slave != dev->caps.function) { 579 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 580 __func__, eqe->type, 581 eqe->subtype, slave); 582 mlx4_slave_event(dev, slave, eqe); 583 break; 584 } 585 } 586 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 587 0xffffff, eqe->type); 588 break; 589 590 case MLX4_EVENT_TYPE_CMD: 591 mlx4_cmd_event(dev, 592 be16_to_cpu(eqe->event.cmd.token), 593 eqe->event.cmd.status, 594 be64_to_cpu(eqe->event.cmd.out_param)); 595 break; 596 597 case MLX4_EVENT_TYPE_PORT_CHANGE: { 598 struct mlx4_slaves_pport slaves_port; 599 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 600 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 601 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 602 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 603 port); 604 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 605 if (!mlx4_is_master(dev)) 606 break; 607 for (i = 0; i < dev->persist->num_vfs + 1; 608 i++) { 609 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 610 611 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 612 continue; 613 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 614 if (i == mlx4_master_func_num(dev)) 615 continue; 616 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 617 __func__, i, port); 618 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; 619 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 620 eqe->event.port_change.port = 621 cpu_to_be32( 622 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 623 | (reported_port << 28)); 624 mlx4_slave_event(dev, i, eqe); 625 } 626 } else { /* IB port */ 627 set_and_calc_slave_port_state(dev, i, port, 628 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 629 &gen_event); 630 /*we can be in pending state, then do not send port_down event*/ 631 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 632 if (i == mlx4_master_func_num(dev)) 633 continue; 634 eqe->event.port_change.port = 635 cpu_to_be32( 636 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 637 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 638 mlx4_slave_event(dev, i, eqe); 639 } 640 } 641 } 642 } else { 643 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 644 645 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 646 647 if (!mlx4_is_master(dev)) 648 break; 649 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 650 for (i = 0; 651 i < dev->persist->num_vfs + 1; 652 i++) { 653 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 654 655 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 656 continue; 657 if (i == mlx4_master_func_num(dev)) 658 continue; 659 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; 660 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 661 eqe->event.port_change.port = 662 cpu_to_be32( 663 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 664 | (reported_port << 28)); 665 mlx4_slave_event(dev, i, eqe); 666 } 667 } 668 else /* IB port */ 669 /* port-up event will be sent to a slave when the 670 * slave's alias-guid is set. This is done in alias_GUID.c 671 */ 672 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 673 } 674 break; 675 } 676 677 case MLX4_EVENT_TYPE_CQ_ERROR: 678 mlx4_warn(dev, "CQ %s on CQN %06x\n", 679 eqe->event.cq_err.syndrome == 1 ? 680 "overrun" : "access violation", 681 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 682 if (mlx4_is_master(dev)) { 683 ret = mlx4_get_slave_from_resource_id(dev, 684 RES_CQ, 685 be32_to_cpu(eqe->event.cq_err.cqn) 686 & 0xffffff, &slave); 687 if (ret && ret != -ENOENT) { 688 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 689 eqe->type, eqe->subtype, 690 eq->eqn, eq->cons_index, ret); 691 break; 692 } 693 694 if (!ret && slave != dev->caps.function) { 695 mlx4_slave_event(dev, slave, eqe); 696 break; 697 } 698 } 699 mlx4_cq_event(dev, 700 be32_to_cpu(eqe->event.cq_err.cqn) 701 & 0xffffff, 702 eqe->type); 703 break; 704 705 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 706 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 707 break; 708 709 case MLX4_EVENT_TYPE_OP_REQUIRED: 710 atomic_inc(&priv->opreq_count); 711 /* FW commands can't be executed from interrupt context 712 * working in deferred task 713 */ 714 queue_work(mlx4_wq, &priv->opreq_task); 715 break; 716 717 case MLX4_EVENT_TYPE_COMM_CHANNEL: 718 if (!mlx4_is_master(dev)) { 719 mlx4_warn(dev, "Received comm channel event for non master device\n"); 720 break; 721 } 722 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 723 eqe->event.comm_channel_arm.bit_vec, 724 sizeof eqe->event.comm_channel_arm.bit_vec); 725 queue_work(priv->mfunc.master.comm_wq, 726 &priv->mfunc.master.comm_work); 727 break; 728 729 case MLX4_EVENT_TYPE_FLR_EVENT: 730 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 731 if (!mlx4_is_master(dev)) { 732 mlx4_warn(dev, "Non-master function received FLR event\n"); 733 break; 734 } 735 736 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 737 738 if (flr_slave >= dev->num_slaves) { 739 mlx4_warn(dev, 740 "Got FLR for unknown function: %d\n", 741 flr_slave); 742 update_slave_state = 0; 743 } else 744 update_slave_state = 1; 745 746 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 747 if (update_slave_state) { 748 priv->mfunc.master.slave_state[flr_slave].active = false; 749 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 750 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 751 } 752 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 753 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, 754 flr_slave); 755 queue_work(priv->mfunc.master.comm_wq, 756 &priv->mfunc.master.slave_flr_event_work); 757 break; 758 759 case MLX4_EVENT_TYPE_FATAL_WARNING: 760 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 761 if (mlx4_is_master(dev)) 762 for (i = 0; i < dev->num_slaves; i++) { 763 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 764 __func__, i); 765 if (i == dev->caps.function) 766 continue; 767 mlx4_slave_event(dev, i, eqe); 768 } 769 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 770 be16_to_cpu(eqe->event.warming.warning_threshold), 771 be16_to_cpu(eqe->event.warming.current_temperature)); 772 } else 773 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 774 eqe->type, eqe->subtype, eq->eqn, 775 eq->cons_index, eqe->owner, eq->nent, 776 eqe->slave_id, 777 !!(eqe->owner & 0x80) ^ 778 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 779 780 break; 781 782 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 783 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 784 (unsigned long) eqe); 785 break; 786 787 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT: 788 switch (eqe->subtype) { 789 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE: 790 mlx4_warn(dev, "Bad cable detected on port %u\n", 791 eqe->event.bad_cable.port); 792 break; 793 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE: 794 mlx4_warn(dev, "Unsupported cable detected\n"); 795 break; 796 default: 797 mlx4_dbg(dev, 798 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n", 799 eqe->type, eqe->subtype, eq->eqn, 800 eq->cons_index, eqe->owner, eq->nent, 801 !!(eqe->owner & 0x80) ^ 802 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 803 break; 804 } 805 break; 806 807 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 808 case MLX4_EVENT_TYPE_ECC_DETECT: 809 default: 810 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 811 eqe->type, eqe->subtype, eq->eqn, 812 eq->cons_index, eqe->owner, eq->nent, 813 eqe->slave_id, 814 !!(eqe->owner & 0x80) ^ 815 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 816 break; 817 }; 818 819 ++eq->cons_index; 820 eqes_found = 1; 821 ++set_ci; 822 823 /* 824 * The HCA will think the queue has overflowed if we 825 * don't tell it we've been processing events. We 826 * create our EQs with MLX4_NUM_SPARE_EQE extra 827 * entries, so we must update our consumer index at 828 * least that often. 829 */ 830 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 831 eq_set_ci(eq, 0); 832 set_ci = 0; 833 } 834 } 835 836 eq_set_ci(eq, 1); 837 838 /* cqn is 24bit wide but is initialized such that its higher bits 839 * are ones too. Thus, if we got any event, cqn's high bits should be off 840 * and we need to schedule the tasklet. 841 */ 842 if (!(cqn & ~0xffffff)) 843 tasklet_schedule(&eq->tasklet_ctx.task); 844 845 return eqes_found; 846 } 847 848 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 849 { 850 struct mlx4_dev *dev = dev_ptr; 851 struct mlx4_priv *priv = mlx4_priv(dev); 852 int work = 0; 853 int i; 854 855 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 856 857 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 858 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 859 860 return IRQ_RETVAL(work); 861 } 862 863 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 864 { 865 struct mlx4_eq *eq = eq_ptr; 866 struct mlx4_dev *dev = eq->dev; 867 868 mlx4_eq_int(dev, eq); 869 870 /* MSI-X vectors always belong to us */ 871 return IRQ_HANDLED; 872 } 873 874 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 875 struct mlx4_vhcr *vhcr, 876 struct mlx4_cmd_mailbox *inbox, 877 struct mlx4_cmd_mailbox *outbox, 878 struct mlx4_cmd_info *cmd) 879 { 880 struct mlx4_priv *priv = mlx4_priv(dev); 881 struct mlx4_slave_event_eq_info *event_eq = 882 priv->mfunc.master.slave_state[slave].event_eq; 883 u32 in_modifier = vhcr->in_modifier; 884 u32 eqn = in_modifier & 0x3FF; 885 u64 in_param = vhcr->in_param; 886 int err = 0; 887 int i; 888 889 if (slave == dev->caps.function) 890 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 891 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 892 MLX4_CMD_NATIVE); 893 if (!err) 894 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 895 if (in_param & (1LL << i)) 896 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 897 898 return err; 899 } 900 901 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 902 int eq_num) 903 { 904 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 905 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 906 MLX4_CMD_WRAPPED); 907 } 908 909 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 910 int eq_num) 911 { 912 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 913 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 914 MLX4_CMD_WRAPPED); 915 } 916 917 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num) 918 { 919 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ, 920 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 921 } 922 923 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 924 { 925 /* 926 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 927 * we need to map, take the difference of highest index and 928 * the lowest index we'll use and add 1. 929 */ 930 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 - 931 dev->caps.reserved_eqs / 4 + 1; 932 } 933 934 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 935 { 936 struct mlx4_priv *priv = mlx4_priv(dev); 937 int index; 938 939 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 940 941 if (!priv->eq_table.uar_map[index]) { 942 priv->eq_table.uar_map[index] = 943 ioremap(pci_resource_start(dev->persist->pdev, 2) + 944 ((eq->eqn / 4) << PAGE_SHIFT), 945 PAGE_SIZE); 946 if (!priv->eq_table.uar_map[index]) { 947 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 948 eq->eqn); 949 return NULL; 950 } 951 } 952 953 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 954 } 955 956 static void mlx4_unmap_uar(struct mlx4_dev *dev) 957 { 958 struct mlx4_priv *priv = mlx4_priv(dev); 959 int i; 960 961 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 962 if (priv->eq_table.uar_map[i]) { 963 iounmap(priv->eq_table.uar_map[i]); 964 priv->eq_table.uar_map[i] = NULL; 965 } 966 } 967 968 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 969 u8 intr, struct mlx4_eq *eq) 970 { 971 struct mlx4_priv *priv = mlx4_priv(dev); 972 struct mlx4_cmd_mailbox *mailbox; 973 struct mlx4_eq_context *eq_context; 974 int npages; 975 u64 *dma_list = NULL; 976 dma_addr_t t; 977 u64 mtt_addr; 978 int err = -ENOMEM; 979 int i; 980 981 eq->dev = dev; 982 eq->nent = roundup_pow_of_two(max(nent, 2)); 983 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 984 * strides of 64B,128B and 256B. 985 */ 986 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; 987 988 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 989 GFP_KERNEL); 990 if (!eq->page_list) 991 goto err_out; 992 993 for (i = 0; i < npages; ++i) 994 eq->page_list[i].buf = NULL; 995 996 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 997 if (!dma_list) 998 goto err_out_free; 999 1000 mailbox = mlx4_alloc_cmd_mailbox(dev); 1001 if (IS_ERR(mailbox)) 1002 goto err_out_free; 1003 eq_context = mailbox->buf; 1004 1005 for (i = 0; i < npages; ++i) { 1006 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> 1007 pdev->dev, 1008 PAGE_SIZE, &t, 1009 GFP_KERNEL); 1010 if (!eq->page_list[i].buf) 1011 goto err_out_free_pages; 1012 1013 dma_list[i] = t; 1014 eq->page_list[i].map = t; 1015 1016 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 1017 } 1018 1019 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 1020 if (eq->eqn == -1) 1021 goto err_out_free_pages; 1022 1023 eq->doorbell = mlx4_get_eq_uar(dev, eq); 1024 if (!eq->doorbell) { 1025 err = -ENOMEM; 1026 goto err_out_free_eq; 1027 } 1028 1029 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 1030 if (err) 1031 goto err_out_free_eq; 1032 1033 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 1034 if (err) 1035 goto err_out_free_mtt; 1036 1037 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 1038 MLX4_EQ_STATE_ARMED); 1039 eq_context->log_eq_size = ilog2(eq->nent); 1040 eq_context->intr = intr; 1041 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 1042 1043 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 1044 eq_context->mtt_base_addr_h = mtt_addr >> 32; 1045 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 1046 1047 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 1048 if (err) { 1049 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 1050 goto err_out_free_mtt; 1051 } 1052 1053 kfree(dma_list); 1054 mlx4_free_cmd_mailbox(dev, mailbox); 1055 1056 eq->cons_index = 0; 1057 1058 INIT_LIST_HEAD(&eq->tasklet_ctx.list); 1059 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list); 1060 spin_lock_init(&eq->tasklet_ctx.lock); 1061 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb, 1062 (unsigned long)&eq->tasklet_ctx); 1063 1064 return err; 1065 1066 err_out_free_mtt: 1067 mlx4_mtt_cleanup(dev, &eq->mtt); 1068 1069 err_out_free_eq: 1070 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1071 1072 err_out_free_pages: 1073 for (i = 0; i < npages; ++i) 1074 if (eq->page_list[i].buf) 1075 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1076 eq->page_list[i].buf, 1077 eq->page_list[i].map); 1078 1079 mlx4_free_cmd_mailbox(dev, mailbox); 1080 1081 err_out_free: 1082 kfree(eq->page_list); 1083 kfree(dma_list); 1084 1085 err_out: 1086 return err; 1087 } 1088 1089 static void mlx4_free_eq(struct mlx4_dev *dev, 1090 struct mlx4_eq *eq) 1091 { 1092 struct mlx4_priv *priv = mlx4_priv(dev); 1093 int err; 1094 int i; 1095 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 1096 * strides of 64B,128B and 256B 1097 */ 1098 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; 1099 1100 err = mlx4_HW2SW_EQ(dev, eq->eqn); 1101 if (err) 1102 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1103 1104 synchronize_irq(eq->irq); 1105 tasklet_disable(&eq->tasklet_ctx.task); 1106 1107 mlx4_mtt_cleanup(dev, &eq->mtt); 1108 for (i = 0; i < npages; ++i) 1109 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1110 eq->page_list[i].buf, 1111 eq->page_list[i].map); 1112 1113 kfree(eq->page_list); 1114 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1115 } 1116 1117 static void mlx4_free_irqs(struct mlx4_dev *dev) 1118 { 1119 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1120 int i; 1121 1122 if (eq_table->have_irq) 1123 free_irq(dev->persist->pdev->irq, dev); 1124 1125 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1126 if (eq_table->eq[i].have_irq) { 1127 free_cpumask_var(eq_table->eq[i].affinity_mask); 1128 #if defined(CONFIG_SMP) 1129 irq_set_affinity_hint(eq_table->eq[i].irq, NULL); 1130 #endif 1131 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1132 eq_table->eq[i].have_irq = 0; 1133 } 1134 1135 kfree(eq_table->irq_names); 1136 } 1137 1138 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1139 { 1140 struct mlx4_priv *priv = mlx4_priv(dev); 1141 1142 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, 1143 priv->fw.clr_int_bar) + 1144 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1145 if (!priv->clr_base) { 1146 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1147 return -ENOMEM; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1154 { 1155 struct mlx4_priv *priv = mlx4_priv(dev); 1156 1157 iounmap(priv->clr_base); 1158 } 1159 1160 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1161 { 1162 struct mlx4_priv *priv = mlx4_priv(dev); 1163 1164 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1165 sizeof *priv->eq_table.eq, GFP_KERNEL); 1166 if (!priv->eq_table.eq) 1167 return -ENOMEM; 1168 1169 return 0; 1170 } 1171 1172 void mlx4_free_eq_table(struct mlx4_dev *dev) 1173 { 1174 kfree(mlx4_priv(dev)->eq_table.eq); 1175 } 1176 1177 int mlx4_init_eq_table(struct mlx4_dev *dev) 1178 { 1179 struct mlx4_priv *priv = mlx4_priv(dev); 1180 int err; 1181 int i; 1182 1183 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1184 sizeof *priv->eq_table.uar_map, 1185 GFP_KERNEL); 1186 if (!priv->eq_table.uar_map) { 1187 err = -ENOMEM; 1188 goto err_out_free; 1189 } 1190 1191 err = mlx4_bitmap_init(&priv->eq_table.bitmap, 1192 roundup_pow_of_two(dev->caps.num_eqs), 1193 dev->caps.num_eqs - 1, 1194 dev->caps.reserved_eqs, 1195 roundup_pow_of_two(dev->caps.num_eqs) - 1196 dev->caps.num_eqs); 1197 if (err) 1198 goto err_out_free; 1199 1200 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1201 priv->eq_table.uar_map[i] = NULL; 1202 1203 if (!mlx4_is_slave(dev)) { 1204 err = mlx4_map_clr_int(dev); 1205 if (err) 1206 goto err_out_bitmap; 1207 1208 priv->eq_table.clr_mask = 1209 swab32(1 << (priv->eq_table.inta_pin & 31)); 1210 priv->eq_table.clr_int = priv->clr_base + 1211 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1212 } 1213 1214 priv->eq_table.irq_names = 1215 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1), 1216 GFP_KERNEL); 1217 if (!priv->eq_table.irq_names) { 1218 err = -ENOMEM; 1219 goto err_out_clr_int; 1220 } 1221 1222 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1223 if (i == MLX4_EQ_ASYNC) { 1224 err = mlx4_create_eq(dev, 1225 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1226 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]); 1227 } else { 1228 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1229 #ifdef CONFIG_RFS_ACCEL 1230 int port = find_first_bit(eq->actv_ports.ports, 1231 dev->caps.num_ports) + 1; 1232 1233 if (port <= dev->caps.num_ports) { 1234 struct mlx4_port_info *info = 1235 &mlx4_priv(dev)->port[port]; 1236 1237 if (!info->rmap) { 1238 info->rmap = alloc_irq_cpu_rmap( 1239 mlx4_get_eqs_per_port(dev, port)); 1240 if (!info->rmap) { 1241 mlx4_warn(dev, "Failed to allocate cpu rmap\n"); 1242 err = -ENOMEM; 1243 goto err_out_unmap; 1244 } 1245 } 1246 1247 err = irq_cpu_rmap_add( 1248 info->rmap, eq->irq); 1249 if (err) 1250 mlx4_warn(dev, "Failed adding irq rmap\n"); 1251 } 1252 #endif 1253 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1254 dev->caps.reserved_cqs + 1255 MLX4_NUM_SPARE_EQE, 1256 (dev->flags & MLX4_FLAG_MSI_X) ? 1257 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0, 1258 eq); 1259 } 1260 if (err) 1261 goto err_out_unmap; 1262 } 1263 1264 if (dev->flags & MLX4_FLAG_MSI_X) { 1265 const char *eq_name; 1266 1267 snprintf(priv->eq_table.irq_names + 1268 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, 1269 MLX4_IRQNAME_SIZE, 1270 "mlx4-async@pci:%s", 1271 pci_name(dev->persist->pdev)); 1272 eq_name = priv->eq_table.irq_names + 1273 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; 1274 1275 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, 1276 mlx4_msi_x_interrupt, 0, eq_name, 1277 priv->eq_table.eq + MLX4_EQ_ASYNC); 1278 if (err) 1279 goto err_out_unmap; 1280 1281 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; 1282 } else { 1283 snprintf(priv->eq_table.irq_names, 1284 MLX4_IRQNAME_SIZE, 1285 DRV_NAME "@pci:%s", 1286 pci_name(dev->persist->pdev)); 1287 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, 1288 IRQF_SHARED, priv->eq_table.irq_names, dev); 1289 if (err) 1290 goto err_out_unmap; 1291 1292 priv->eq_table.have_irq = 1; 1293 } 1294 1295 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1296 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1297 if (err) 1298 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1299 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); 1300 1301 /* arm ASYNC eq */ 1302 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1); 1303 1304 return 0; 1305 1306 err_out_unmap: 1307 while (i >= 0) 1308 mlx4_free_eq(dev, &priv->eq_table.eq[i--]); 1309 #ifdef CONFIG_RFS_ACCEL 1310 for (i = 1; i <= dev->caps.num_ports; i++) { 1311 if (mlx4_priv(dev)->port[i].rmap) { 1312 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1313 mlx4_priv(dev)->port[i].rmap = NULL; 1314 } 1315 } 1316 #endif 1317 mlx4_free_irqs(dev); 1318 1319 err_out_clr_int: 1320 if (!mlx4_is_slave(dev)) 1321 mlx4_unmap_clr_int(dev); 1322 1323 err_out_bitmap: 1324 mlx4_unmap_uar(dev); 1325 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1326 1327 err_out_free: 1328 kfree(priv->eq_table.uar_map); 1329 1330 return err; 1331 } 1332 1333 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1334 { 1335 struct mlx4_priv *priv = mlx4_priv(dev); 1336 int i; 1337 1338 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1339 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1340 1341 #ifdef CONFIG_RFS_ACCEL 1342 for (i = 1; i <= dev->caps.num_ports; i++) { 1343 if (mlx4_priv(dev)->port[i].rmap) { 1344 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1345 mlx4_priv(dev)->port[i].rmap = NULL; 1346 } 1347 } 1348 #endif 1349 mlx4_free_irqs(dev); 1350 1351 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1352 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1353 1354 if (!mlx4_is_slave(dev)) 1355 mlx4_unmap_clr_int(dev); 1356 1357 mlx4_unmap_uar(dev); 1358 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1359 1360 kfree(priv->eq_table.uar_map); 1361 } 1362 1363 /* A test that verifies that we can accept interrupts on all 1364 * the irq vectors of the device. 1365 * Interrupts are checked using the NOP command. 1366 */ 1367 int mlx4_test_interrupts(struct mlx4_dev *dev) 1368 { 1369 struct mlx4_priv *priv = mlx4_priv(dev); 1370 int i; 1371 int err; 1372 1373 err = mlx4_NOP(dev); 1374 /* When not in MSI_X, there is only one irq to check */ 1375 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1376 return err; 1377 1378 /* A loop over all completion vectors, for each vector we will check 1379 * whether it works by mapping command completions to that vector 1380 * and performing a NOP command 1381 */ 1382 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1383 /* Make sure request_irq was called */ 1384 if (!priv->eq_table.eq[i].have_irq) 1385 continue; 1386 1387 /* Temporary use polling for command completions */ 1388 mlx4_cmd_use_polling(dev); 1389 1390 /* Map the new eq to handle all asynchronous events */ 1391 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1392 priv->eq_table.eq[i].eqn); 1393 if (err) { 1394 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1395 mlx4_cmd_use_events(dev); 1396 break; 1397 } 1398 1399 /* Go back to using events */ 1400 mlx4_cmd_use_events(dev); 1401 err = mlx4_NOP(dev); 1402 } 1403 1404 /* Return to default */ 1405 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1406 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1407 return err; 1408 } 1409 EXPORT_SYMBOL(mlx4_test_interrupts); 1410 1411 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector) 1412 { 1413 struct mlx4_priv *priv = mlx4_priv(dev); 1414 1415 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1416 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) || 1417 (vector == MLX4_EQ_ASYNC)) 1418 return false; 1419 1420 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports); 1421 } 1422 EXPORT_SYMBOL(mlx4_is_eq_vector_valid); 1423 1424 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port) 1425 { 1426 struct mlx4_priv *priv = mlx4_priv(dev); 1427 unsigned int i; 1428 unsigned int sum = 0; 1429 1430 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) 1431 sum += !!test_bit(port - 1, 1432 priv->eq_table.eq[i].actv_ports.ports); 1433 1434 return sum; 1435 } 1436 EXPORT_SYMBOL(mlx4_get_eqs_per_port); 1437 1438 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector) 1439 { 1440 struct mlx4_priv *priv = mlx4_priv(dev); 1441 1442 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1443 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1)) 1444 return -EINVAL; 1445 1446 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports, 1447 dev->caps.num_ports) > 1); 1448 } 1449 EXPORT_SYMBOL(mlx4_is_eq_shared); 1450 1451 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port) 1452 { 1453 return mlx4_priv(dev)->port[port].rmap; 1454 } 1455 EXPORT_SYMBOL(mlx4_get_cpu_rmap); 1456 1457 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector) 1458 { 1459 struct mlx4_priv *priv = mlx4_priv(dev); 1460 int err = 0, i = 0; 1461 u32 min_ref_count_val = (u32)-1; 1462 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector); 1463 int *prequested_vector = NULL; 1464 1465 1466 mutex_lock(&priv->msix_ctl.pool_lock); 1467 if (requested_vector < (dev->caps.num_comp_vectors + 1) && 1468 (requested_vector >= 0) && 1469 (requested_vector != MLX4_EQ_ASYNC)) { 1470 if (test_bit(port - 1, 1471 priv->eq_table.eq[requested_vector].actv_ports.ports)) { 1472 prequested_vector = &requested_vector; 1473 } else { 1474 struct mlx4_eq *eq; 1475 1476 for (i = 1; i < port; 1477 requested_vector += mlx4_get_eqs_per_port(dev, i++)) 1478 ; 1479 1480 eq = &priv->eq_table.eq[requested_vector]; 1481 if (requested_vector < dev->caps.num_comp_vectors + 1 && 1482 test_bit(port - 1, eq->actv_ports.ports)) { 1483 prequested_vector = &requested_vector; 1484 } 1485 } 1486 } 1487 1488 if (!prequested_vector) { 1489 requested_vector = -1; 1490 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1; 1491 i++) { 1492 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1493 1494 if (min_ref_count_val > eq->ref_count && 1495 test_bit(port - 1, eq->actv_ports.ports)) { 1496 min_ref_count_val = eq->ref_count; 1497 requested_vector = i; 1498 } 1499 } 1500 1501 if (requested_vector < 0) { 1502 err = -ENOSPC; 1503 goto err_unlock; 1504 } 1505 1506 prequested_vector = &requested_vector; 1507 } 1508 1509 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && 1510 dev->flags & MLX4_FLAG_MSI_X) { 1511 set_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1512 snprintf(priv->eq_table.irq_names + 1513 *prequested_vector * MLX4_IRQNAME_SIZE, 1514 MLX4_IRQNAME_SIZE, "mlx4-%d@%s", 1515 *prequested_vector, dev_name(&dev->persist->pdev->dev)); 1516 1517 err = request_irq(priv->eq_table.eq[*prequested_vector].irq, 1518 mlx4_msi_x_interrupt, 0, 1519 &priv->eq_table.irq_names[*prequested_vector << 5], 1520 priv->eq_table.eq + *prequested_vector); 1521 1522 if (err) { 1523 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1524 *prequested_vector = -1; 1525 } else { 1526 #if defined(CONFIG_SMP) 1527 mlx4_set_eq_affinity_hint(priv, *prequested_vector); 1528 #endif 1529 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); 1530 priv->eq_table.eq[*prequested_vector].have_irq = 1; 1531 } 1532 } 1533 1534 if (!err && *prequested_vector >= 0) 1535 priv->eq_table.eq[*prequested_vector].ref_count++; 1536 1537 err_unlock: 1538 mutex_unlock(&priv->msix_ctl.pool_lock); 1539 1540 if (!err && *prequested_vector >= 0) 1541 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector); 1542 else 1543 *vector = 0; 1544 1545 return err; 1546 } 1547 EXPORT_SYMBOL(mlx4_assign_eq); 1548 1549 int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec) 1550 { 1551 struct mlx4_priv *priv = mlx4_priv(dev); 1552 1553 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq; 1554 } 1555 EXPORT_SYMBOL(mlx4_eq_get_irq); 1556 1557 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1558 { 1559 struct mlx4_priv *priv = mlx4_priv(dev); 1560 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec); 1561 1562 mutex_lock(&priv->msix_ctl.pool_lock); 1563 priv->eq_table.eq[eq_vec].ref_count--; 1564 1565 /* once we allocated EQ, we don't release it because it might be binded 1566 * to cpu_rmap. 1567 */ 1568 mutex_unlock(&priv->msix_ctl.pool_lock); 1569 } 1570 EXPORT_SYMBOL(mlx4_release_eq); 1571 1572