1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/export.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/cpu_rmap.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT); 93 94 return async_ev_mask; 95 } 96 97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 98 { 99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 100 req_not << 31), 101 eq->doorbell); 102 /* We still want ordering, just not swabbing, so add a barrier */ 103 mb(); 104 } 105 106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, 107 u8 eqe_size) 108 { 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; 111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with 112 * strides of 64B,128B and 256B. 113 * When 64B EQE is used, the first (in the lower addresses) 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 115 * contain the legacy EQE information. 116 * In all other cases, the first 32B contains the legacy EQE info. 117 */ 118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 119 } 120 121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) 122 { 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 125 } 126 127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 128 { 129 struct mlx4_eqe *eqe = 130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 131 return (!!(eqe->owner & 0x80) ^ 132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 133 eqe : NULL; 134 } 135 136 void mlx4_gen_slave_eqe(struct work_struct *work) 137 { 138 struct mlx4_mfunc_master_ctx *master = 139 container_of(work, struct mlx4_mfunc_master_ctx, 140 slave_event_work); 141 struct mlx4_mfunc *mfunc = 142 container_of(master, struct mlx4_mfunc, master); 143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 144 struct mlx4_dev *dev = &priv->dev; 145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 146 struct mlx4_eqe *eqe; 147 u8 slave; 148 int i; 149 150 for (eqe = next_slave_event_eqe(slave_eq); eqe; 151 eqe = next_slave_event_eqe(slave_eq)) { 152 slave = eqe->slave_id; 153 154 /* All active slaves need to receive the event */ 155 if (slave == ALL_SLAVES) { 156 for (i = 0; i < dev->num_slaves; i++) { 157 if (i != dev->caps.function && 158 master->slave_state[i].active) 159 if (mlx4_GEN_EQE(dev, i, eqe)) 160 mlx4_warn(dev, "Failed to generate event for slave %d\n", 161 i); 162 } 163 } else { 164 if (mlx4_GEN_EQE(dev, slave, eqe)) 165 mlx4_warn(dev, "Failed to generate event for slave %d\n", 166 slave); 167 } 168 ++slave_eq->cons; 169 } 170 } 171 172 173 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 174 { 175 struct mlx4_priv *priv = mlx4_priv(dev); 176 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 177 struct mlx4_eqe *s_eqe; 178 unsigned long flags; 179 180 spin_lock_irqsave(&slave_eq->event_lock, flags); 181 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 182 if ((!!(s_eqe->owner & 0x80)) ^ 183 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 184 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 185 slave); 186 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 187 return; 188 } 189 190 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); 191 s_eqe->slave_id = slave; 192 /* ensure all information is written before setting the ownersip bit */ 193 wmb(); 194 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 195 ++slave_eq->prod; 196 197 queue_work(priv->mfunc.master.comm_wq, 198 &priv->mfunc.master.slave_event_work); 199 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 200 } 201 202 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 203 struct mlx4_eqe *eqe) 204 { 205 struct mlx4_priv *priv = mlx4_priv(dev); 206 struct mlx4_slave_state *s_slave = 207 &priv->mfunc.master.slave_state[slave]; 208 209 if (!s_slave->active) { 210 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/ 211 return; 212 } 213 214 slave_event(dev, slave, eqe); 215 } 216 217 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 218 { 219 struct mlx4_eqe eqe; 220 221 struct mlx4_priv *priv = mlx4_priv(dev); 222 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 223 224 if (!s_slave->active) 225 return 0; 226 227 memset(&eqe, 0, sizeof eqe); 228 229 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 230 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 231 eqe.event.port_mgmt_change.port = port; 232 233 return mlx4_GEN_EQE(dev, slave, &eqe); 234 } 235 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 236 237 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 238 { 239 struct mlx4_eqe eqe; 240 241 /*don't send if we don't have the that slave */ 242 if (dev->persist->num_vfs < slave) 243 return 0; 244 memset(&eqe, 0, sizeof eqe); 245 246 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 247 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 248 eqe.event.port_mgmt_change.port = port; 249 250 return mlx4_GEN_EQE(dev, slave, &eqe); 251 } 252 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 253 254 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 255 u8 port_subtype_change) 256 { 257 struct mlx4_eqe eqe; 258 259 /*don't send if we don't have the that slave */ 260 if (dev->persist->num_vfs < slave) 261 return 0; 262 memset(&eqe, 0, sizeof eqe); 263 264 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 265 eqe.subtype = port_subtype_change; 266 eqe.event.port_change.port = cpu_to_be32(port << 28); 267 268 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 269 port_subtype_change, slave, port); 270 return mlx4_GEN_EQE(dev, slave, &eqe); 271 } 272 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 273 274 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 275 { 276 struct mlx4_priv *priv = mlx4_priv(dev); 277 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 278 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 279 280 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 281 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 282 pr_err("%s: Error: asking for slave:%d, port:%d\n", 283 __func__, slave, port); 284 return SLAVE_PORT_DOWN; 285 } 286 return s_state[slave].port_state[port]; 287 } 288 EXPORT_SYMBOL(mlx4_get_slave_port_state); 289 290 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 291 enum slave_port_state state) 292 { 293 struct mlx4_priv *priv = mlx4_priv(dev); 294 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 295 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 296 297 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 298 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 299 pr_err("%s: Error: asking for slave:%d, port:%d\n", 300 __func__, slave, port); 301 return -1; 302 } 303 s_state[slave].port_state[port] = state; 304 305 return 0; 306 } 307 308 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 309 { 310 int i; 311 enum slave_port_gen_event gen_event; 312 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 313 port); 314 315 for (i = 0; i < dev->persist->num_vfs + 1; i++) 316 if (test_bit(i, slaves_pport.slaves)) 317 set_and_calc_slave_port_state(dev, i, port, 318 event, &gen_event); 319 } 320 /************************************************************************** 321 The function get as input the new event to that port, 322 and according to the prev state change the slave's port state. 323 The events are: 324 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 325 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 326 MLX4_PORT_STATE_IB_EVENT_GID_VALID 327 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 328 ***************************************************************************/ 329 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 330 u8 port, int event, 331 enum slave_port_gen_event *gen_event) 332 { 333 struct mlx4_priv *priv = mlx4_priv(dev); 334 struct mlx4_slave_state *ctx = NULL; 335 unsigned long flags; 336 int ret = -1; 337 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 338 enum slave_port_state cur_state = 339 mlx4_get_slave_port_state(dev, slave, port); 340 341 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 342 343 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 344 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 345 pr_err("%s: Error: asking for slave:%d, port:%d\n", 346 __func__, slave, port); 347 return ret; 348 } 349 350 ctx = &priv->mfunc.master.slave_state[slave]; 351 spin_lock_irqsave(&ctx->lock, flags); 352 353 switch (cur_state) { 354 case SLAVE_PORT_DOWN: 355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 356 mlx4_set_slave_port_state(dev, slave, port, 357 SLAVE_PENDING_UP); 358 break; 359 case SLAVE_PENDING_UP: 360 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 361 mlx4_set_slave_port_state(dev, slave, port, 362 SLAVE_PORT_DOWN); 363 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 364 mlx4_set_slave_port_state(dev, slave, port, 365 SLAVE_PORT_UP); 366 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 367 } 368 break; 369 case SLAVE_PORT_UP: 370 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 371 mlx4_set_slave_port_state(dev, slave, port, 372 SLAVE_PORT_DOWN); 373 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 374 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 375 event) { 376 mlx4_set_slave_port_state(dev, slave, port, 377 SLAVE_PENDING_UP); 378 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 379 } 380 break; 381 default: 382 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 383 __func__, slave, port); 384 goto out; 385 } 386 ret = mlx4_get_slave_port_state(dev, slave, port); 387 388 out: 389 spin_unlock_irqrestore(&ctx->lock, flags); 390 return ret; 391 } 392 393 EXPORT_SYMBOL(set_and_calc_slave_port_state); 394 395 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 396 { 397 struct mlx4_eqe eqe; 398 399 memset(&eqe, 0, sizeof eqe); 400 401 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 402 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 403 eqe.event.port_mgmt_change.port = port; 404 eqe.event.port_mgmt_change.params.port_info.changed_attr = 405 cpu_to_be32((u32) attr); 406 407 slave_event(dev, ALL_SLAVES, &eqe); 408 return 0; 409 } 410 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 411 412 void mlx4_master_handle_slave_flr(struct work_struct *work) 413 { 414 struct mlx4_mfunc_master_ctx *master = 415 container_of(work, struct mlx4_mfunc_master_ctx, 416 slave_flr_event_work); 417 struct mlx4_mfunc *mfunc = 418 container_of(master, struct mlx4_mfunc, master); 419 struct mlx4_priv *priv = 420 container_of(mfunc, struct mlx4_priv, mfunc); 421 struct mlx4_dev *dev = &priv->dev; 422 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 423 int i; 424 int err; 425 unsigned long flags; 426 427 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 428 429 for (i = 0 ; i < dev->num_slaves; i++) { 430 431 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 432 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 433 i); 434 /* In case of 'Reset flow' FLR can be generated for 435 * a slave before mlx4_load_one is done. 436 * make sure interface is up before trying to delete 437 * slave resources which weren't allocated yet. 438 */ 439 if (dev->persist->interface_state & 440 MLX4_INTERFACE_STATE_UP) 441 mlx4_delete_all_resources_for_slave(dev, i); 442 /*return the slave to running mode*/ 443 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 444 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 445 slave_state[i].is_slave_going_down = 0; 446 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 447 /*notify the FW:*/ 448 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 449 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 450 if (err) 451 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 452 i); 453 } 454 } 455 } 456 457 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 458 { 459 struct mlx4_priv *priv = mlx4_priv(dev); 460 struct mlx4_eqe *eqe; 461 int cqn = -1; 462 int eqes_found = 0; 463 int set_ci = 0; 464 int port; 465 int slave = 0; 466 int ret; 467 u32 flr_slave; 468 u8 update_slave_state; 469 int i; 470 enum slave_port_gen_event gen_event; 471 unsigned long flags; 472 struct mlx4_vport_state *s_info; 473 int eqe_size = dev->caps.eqe_size; 474 475 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { 476 /* 477 * Make sure we read EQ entry contents after we've 478 * checked the ownership bit. 479 */ 480 rmb(); 481 482 switch (eqe->type) { 483 case MLX4_EVENT_TYPE_COMP: 484 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 485 mlx4_cq_completion(dev, cqn); 486 break; 487 488 case MLX4_EVENT_TYPE_PATH_MIG: 489 case MLX4_EVENT_TYPE_COMM_EST: 490 case MLX4_EVENT_TYPE_SQ_DRAINED: 491 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 492 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 493 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 494 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 495 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 496 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 497 if (mlx4_is_master(dev)) { 498 /* forward only to slave owning the QP */ 499 ret = mlx4_get_slave_from_resource_id(dev, 500 RES_QP, 501 be32_to_cpu(eqe->event.qp.qpn) 502 & 0xffffff, &slave); 503 if (ret && ret != -ENOENT) { 504 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 505 eqe->type, eqe->subtype, 506 eq->eqn, eq->cons_index, ret); 507 break; 508 } 509 510 if (!ret && slave != dev->caps.function) { 511 mlx4_slave_event(dev, slave, eqe); 512 break; 513 } 514 515 } 516 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 517 0xffffff, eqe->type); 518 break; 519 520 case MLX4_EVENT_TYPE_SRQ_LIMIT: 521 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 522 __func__); 523 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 524 if (mlx4_is_master(dev)) { 525 /* forward only to slave owning the SRQ */ 526 ret = mlx4_get_slave_from_resource_id(dev, 527 RES_SRQ, 528 be32_to_cpu(eqe->event.srq.srqn) 529 & 0xffffff, 530 &slave); 531 if (ret && ret != -ENOENT) { 532 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 533 eqe->type, eqe->subtype, 534 eq->eqn, eq->cons_index, ret); 535 break; 536 } 537 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 538 __func__, slave, 539 be32_to_cpu(eqe->event.srq.srqn), 540 eqe->type, eqe->subtype); 541 542 if (!ret && slave != dev->caps.function) { 543 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 544 __func__, eqe->type, 545 eqe->subtype, slave); 546 mlx4_slave_event(dev, slave, eqe); 547 break; 548 } 549 } 550 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 551 0xffffff, eqe->type); 552 break; 553 554 case MLX4_EVENT_TYPE_CMD: 555 mlx4_cmd_event(dev, 556 be16_to_cpu(eqe->event.cmd.token), 557 eqe->event.cmd.status, 558 be64_to_cpu(eqe->event.cmd.out_param)); 559 break; 560 561 case MLX4_EVENT_TYPE_PORT_CHANGE: { 562 struct mlx4_slaves_pport slaves_port; 563 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 564 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 565 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 566 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 567 port); 568 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 569 if (!mlx4_is_master(dev)) 570 break; 571 for (i = 0; i < dev->persist->num_vfs + 1; 572 i++) { 573 if (!test_bit(i, slaves_port.slaves)) 574 continue; 575 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 576 if (i == mlx4_master_func_num(dev)) 577 continue; 578 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 579 __func__, i, port); 580 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 581 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 582 eqe->event.port_change.port = 583 cpu_to_be32( 584 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 585 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 586 mlx4_slave_event(dev, i, eqe); 587 } 588 } else { /* IB port */ 589 set_and_calc_slave_port_state(dev, i, port, 590 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 591 &gen_event); 592 /*we can be in pending state, then do not send port_down event*/ 593 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 594 if (i == mlx4_master_func_num(dev)) 595 continue; 596 mlx4_slave_event(dev, i, eqe); 597 } 598 } 599 } 600 } else { 601 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 602 603 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 604 605 if (!mlx4_is_master(dev)) 606 break; 607 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 608 for (i = 0; 609 i < dev->persist->num_vfs + 1; 610 i++) { 611 if (!test_bit(i, slaves_port.slaves)) 612 continue; 613 if (i == mlx4_master_func_num(dev)) 614 continue; 615 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 616 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 617 eqe->event.port_change.port = 618 cpu_to_be32( 619 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 620 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 621 mlx4_slave_event(dev, i, eqe); 622 } 623 } 624 else /* IB port */ 625 /* port-up event will be sent to a slave when the 626 * slave's alias-guid is set. This is done in alias_GUID.c 627 */ 628 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 629 } 630 break; 631 } 632 633 case MLX4_EVENT_TYPE_CQ_ERROR: 634 mlx4_warn(dev, "CQ %s on CQN %06x\n", 635 eqe->event.cq_err.syndrome == 1 ? 636 "overrun" : "access violation", 637 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 638 if (mlx4_is_master(dev)) { 639 ret = mlx4_get_slave_from_resource_id(dev, 640 RES_CQ, 641 be32_to_cpu(eqe->event.cq_err.cqn) 642 & 0xffffff, &slave); 643 if (ret && ret != -ENOENT) { 644 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 645 eqe->type, eqe->subtype, 646 eq->eqn, eq->cons_index, ret); 647 break; 648 } 649 650 if (!ret && slave != dev->caps.function) { 651 mlx4_slave_event(dev, slave, eqe); 652 break; 653 } 654 } 655 mlx4_cq_event(dev, 656 be32_to_cpu(eqe->event.cq_err.cqn) 657 & 0xffffff, 658 eqe->type); 659 break; 660 661 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 662 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 663 break; 664 665 case MLX4_EVENT_TYPE_OP_REQUIRED: 666 atomic_inc(&priv->opreq_count); 667 /* FW commands can't be executed from interrupt context 668 * working in deferred task 669 */ 670 queue_work(mlx4_wq, &priv->opreq_task); 671 break; 672 673 case MLX4_EVENT_TYPE_COMM_CHANNEL: 674 if (!mlx4_is_master(dev)) { 675 mlx4_warn(dev, "Received comm channel event for non master device\n"); 676 break; 677 } 678 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 679 eqe->event.comm_channel_arm.bit_vec, 680 sizeof eqe->event.comm_channel_arm.bit_vec); 681 queue_work(priv->mfunc.master.comm_wq, 682 &priv->mfunc.master.comm_work); 683 break; 684 685 case MLX4_EVENT_TYPE_FLR_EVENT: 686 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 687 if (!mlx4_is_master(dev)) { 688 mlx4_warn(dev, "Non-master function received FLR event\n"); 689 break; 690 } 691 692 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 693 694 if (flr_slave >= dev->num_slaves) { 695 mlx4_warn(dev, 696 "Got FLR for unknown function: %d\n", 697 flr_slave); 698 update_slave_state = 0; 699 } else 700 update_slave_state = 1; 701 702 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 703 if (update_slave_state) { 704 priv->mfunc.master.slave_state[flr_slave].active = false; 705 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 706 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 707 } 708 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 709 queue_work(priv->mfunc.master.comm_wq, 710 &priv->mfunc.master.slave_flr_event_work); 711 break; 712 713 case MLX4_EVENT_TYPE_FATAL_WARNING: 714 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 715 if (mlx4_is_master(dev)) 716 for (i = 0; i < dev->num_slaves; i++) { 717 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 718 __func__, i); 719 if (i == dev->caps.function) 720 continue; 721 mlx4_slave_event(dev, i, eqe); 722 } 723 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 724 be16_to_cpu(eqe->event.warming.warning_threshold), 725 be16_to_cpu(eqe->event.warming.current_temperature)); 726 } else 727 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 728 eqe->type, eqe->subtype, eq->eqn, 729 eq->cons_index, eqe->owner, eq->nent, 730 eqe->slave_id, 731 !!(eqe->owner & 0x80) ^ 732 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 733 734 break; 735 736 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 737 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 738 (unsigned long) eqe); 739 break; 740 741 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT: 742 switch (eqe->subtype) { 743 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE: 744 mlx4_warn(dev, "Bad cable detected on port %u\n", 745 eqe->event.bad_cable.port); 746 break; 747 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE: 748 mlx4_warn(dev, "Unsupported cable detected\n"); 749 break; 750 default: 751 mlx4_dbg(dev, 752 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n", 753 eqe->type, eqe->subtype, eq->eqn, 754 eq->cons_index, eqe->owner, eq->nent, 755 !!(eqe->owner & 0x80) ^ 756 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 757 break; 758 } 759 break; 760 761 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 762 case MLX4_EVENT_TYPE_ECC_DETECT: 763 default: 764 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 765 eqe->type, eqe->subtype, eq->eqn, 766 eq->cons_index, eqe->owner, eq->nent, 767 eqe->slave_id, 768 !!(eqe->owner & 0x80) ^ 769 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 770 break; 771 }; 772 773 ++eq->cons_index; 774 eqes_found = 1; 775 ++set_ci; 776 777 /* 778 * The HCA will think the queue has overflowed if we 779 * don't tell it we've been processing events. We 780 * create our EQs with MLX4_NUM_SPARE_EQE extra 781 * entries, so we must update our consumer index at 782 * least that often. 783 */ 784 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 785 eq_set_ci(eq, 0); 786 set_ci = 0; 787 } 788 } 789 790 eq_set_ci(eq, 1); 791 792 /* cqn is 24bit wide but is initialized such that its higher bits 793 * are ones too. Thus, if we got any event, cqn's high bits should be off 794 * and we need to schedule the tasklet. 795 */ 796 if (!(cqn & ~0xffffff)) 797 tasklet_schedule(&eq->tasklet_ctx.task); 798 799 return eqes_found; 800 } 801 802 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 803 { 804 struct mlx4_dev *dev = dev_ptr; 805 struct mlx4_priv *priv = mlx4_priv(dev); 806 int work = 0; 807 int i; 808 809 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 810 811 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 812 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 813 814 return IRQ_RETVAL(work); 815 } 816 817 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 818 { 819 struct mlx4_eq *eq = eq_ptr; 820 struct mlx4_dev *dev = eq->dev; 821 822 mlx4_eq_int(dev, eq); 823 824 /* MSI-X vectors always belong to us */ 825 return IRQ_HANDLED; 826 } 827 828 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 829 struct mlx4_vhcr *vhcr, 830 struct mlx4_cmd_mailbox *inbox, 831 struct mlx4_cmd_mailbox *outbox, 832 struct mlx4_cmd_info *cmd) 833 { 834 struct mlx4_priv *priv = mlx4_priv(dev); 835 struct mlx4_slave_event_eq_info *event_eq = 836 priv->mfunc.master.slave_state[slave].event_eq; 837 u32 in_modifier = vhcr->in_modifier; 838 u32 eqn = in_modifier & 0x3FF; 839 u64 in_param = vhcr->in_param; 840 int err = 0; 841 int i; 842 843 if (slave == dev->caps.function) 844 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 845 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 846 MLX4_CMD_NATIVE); 847 if (!err) 848 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 849 if (in_param & (1LL << i)) 850 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 851 852 return err; 853 } 854 855 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 856 int eq_num) 857 { 858 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 859 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 860 MLX4_CMD_WRAPPED); 861 } 862 863 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 864 int eq_num) 865 { 866 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 867 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 868 MLX4_CMD_WRAPPED); 869 } 870 871 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num) 872 { 873 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ, 874 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 875 } 876 877 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 878 { 879 /* 880 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 881 * we need to map, take the difference of highest index and 882 * the lowest index we'll use and add 1. 883 */ 884 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs + 885 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1; 886 } 887 888 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 889 { 890 struct mlx4_priv *priv = mlx4_priv(dev); 891 int index; 892 893 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 894 895 if (!priv->eq_table.uar_map[index]) { 896 priv->eq_table.uar_map[index] = 897 ioremap(pci_resource_start(dev->persist->pdev, 2) + 898 ((eq->eqn / 4) << PAGE_SHIFT), 899 PAGE_SIZE); 900 if (!priv->eq_table.uar_map[index]) { 901 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 902 eq->eqn); 903 return NULL; 904 } 905 } 906 907 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 908 } 909 910 static void mlx4_unmap_uar(struct mlx4_dev *dev) 911 { 912 struct mlx4_priv *priv = mlx4_priv(dev); 913 int i; 914 915 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 916 if (priv->eq_table.uar_map[i]) { 917 iounmap(priv->eq_table.uar_map[i]); 918 priv->eq_table.uar_map[i] = NULL; 919 } 920 } 921 922 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 923 u8 intr, struct mlx4_eq *eq) 924 { 925 struct mlx4_priv *priv = mlx4_priv(dev); 926 struct mlx4_cmd_mailbox *mailbox; 927 struct mlx4_eq_context *eq_context; 928 int npages; 929 u64 *dma_list = NULL; 930 dma_addr_t t; 931 u64 mtt_addr; 932 int err = -ENOMEM; 933 int i; 934 935 eq->dev = dev; 936 eq->nent = roundup_pow_of_two(max(nent, 2)); 937 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 938 * strides of 64B,128B and 256B. 939 */ 940 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; 941 942 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 943 GFP_KERNEL); 944 if (!eq->page_list) 945 goto err_out; 946 947 for (i = 0; i < npages; ++i) 948 eq->page_list[i].buf = NULL; 949 950 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 951 if (!dma_list) 952 goto err_out_free; 953 954 mailbox = mlx4_alloc_cmd_mailbox(dev); 955 if (IS_ERR(mailbox)) 956 goto err_out_free; 957 eq_context = mailbox->buf; 958 959 for (i = 0; i < npages; ++i) { 960 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> 961 pdev->dev, 962 PAGE_SIZE, &t, 963 GFP_KERNEL); 964 if (!eq->page_list[i].buf) 965 goto err_out_free_pages; 966 967 dma_list[i] = t; 968 eq->page_list[i].map = t; 969 970 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 971 } 972 973 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 974 if (eq->eqn == -1) 975 goto err_out_free_pages; 976 977 eq->doorbell = mlx4_get_eq_uar(dev, eq); 978 if (!eq->doorbell) { 979 err = -ENOMEM; 980 goto err_out_free_eq; 981 } 982 983 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 984 if (err) 985 goto err_out_free_eq; 986 987 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 988 if (err) 989 goto err_out_free_mtt; 990 991 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 992 MLX4_EQ_STATE_ARMED); 993 eq_context->log_eq_size = ilog2(eq->nent); 994 eq_context->intr = intr; 995 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 996 997 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 998 eq_context->mtt_base_addr_h = mtt_addr >> 32; 999 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 1000 1001 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 1002 if (err) { 1003 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 1004 goto err_out_free_mtt; 1005 } 1006 1007 kfree(dma_list); 1008 mlx4_free_cmd_mailbox(dev, mailbox); 1009 1010 eq->cons_index = 0; 1011 1012 INIT_LIST_HEAD(&eq->tasklet_ctx.list); 1013 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list); 1014 spin_lock_init(&eq->tasklet_ctx.lock); 1015 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb, 1016 (unsigned long)&eq->tasklet_ctx); 1017 1018 return err; 1019 1020 err_out_free_mtt: 1021 mlx4_mtt_cleanup(dev, &eq->mtt); 1022 1023 err_out_free_eq: 1024 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1025 1026 err_out_free_pages: 1027 for (i = 0; i < npages; ++i) 1028 if (eq->page_list[i].buf) 1029 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1030 eq->page_list[i].buf, 1031 eq->page_list[i].map); 1032 1033 mlx4_free_cmd_mailbox(dev, mailbox); 1034 1035 err_out_free: 1036 kfree(eq->page_list); 1037 kfree(dma_list); 1038 1039 err_out: 1040 return err; 1041 } 1042 1043 static void mlx4_free_eq(struct mlx4_dev *dev, 1044 struct mlx4_eq *eq) 1045 { 1046 struct mlx4_priv *priv = mlx4_priv(dev); 1047 int err; 1048 int i; 1049 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 1050 * strides of 64B,128B and 256B 1051 */ 1052 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; 1053 1054 err = mlx4_HW2SW_EQ(dev, eq->eqn); 1055 if (err) 1056 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1057 1058 synchronize_irq(eq->irq); 1059 tasklet_disable(&eq->tasklet_ctx.task); 1060 1061 mlx4_mtt_cleanup(dev, &eq->mtt); 1062 for (i = 0; i < npages; ++i) 1063 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1064 eq->page_list[i].buf, 1065 eq->page_list[i].map); 1066 1067 kfree(eq->page_list); 1068 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1069 } 1070 1071 static void mlx4_free_irqs(struct mlx4_dev *dev) 1072 { 1073 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1074 struct mlx4_priv *priv = mlx4_priv(dev); 1075 int i, vec; 1076 1077 if (eq_table->have_irq) 1078 free_irq(dev->persist->pdev->irq, dev); 1079 1080 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1081 if (eq_table->eq[i].have_irq) { 1082 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1083 eq_table->eq[i].have_irq = 0; 1084 } 1085 1086 for (i = 0; i < dev->caps.comp_pool; i++) { 1087 /* 1088 * Freeing the assigned irq's 1089 * all bits should be 0, but we need to validate 1090 */ 1091 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1092 /* NO need protecting*/ 1093 vec = dev->caps.num_comp_vectors + 1 + i; 1094 free_irq(priv->eq_table.eq[vec].irq, 1095 &priv->eq_table.eq[vec]); 1096 } 1097 } 1098 1099 1100 kfree(eq_table->irq_names); 1101 } 1102 1103 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1104 { 1105 struct mlx4_priv *priv = mlx4_priv(dev); 1106 1107 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, 1108 priv->fw.clr_int_bar) + 1109 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1110 if (!priv->clr_base) { 1111 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1112 return -ENOMEM; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1119 { 1120 struct mlx4_priv *priv = mlx4_priv(dev); 1121 1122 iounmap(priv->clr_base); 1123 } 1124 1125 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1126 { 1127 struct mlx4_priv *priv = mlx4_priv(dev); 1128 1129 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1130 sizeof *priv->eq_table.eq, GFP_KERNEL); 1131 if (!priv->eq_table.eq) 1132 return -ENOMEM; 1133 1134 return 0; 1135 } 1136 1137 void mlx4_free_eq_table(struct mlx4_dev *dev) 1138 { 1139 kfree(mlx4_priv(dev)->eq_table.eq); 1140 } 1141 1142 int mlx4_init_eq_table(struct mlx4_dev *dev) 1143 { 1144 struct mlx4_priv *priv = mlx4_priv(dev); 1145 int err; 1146 int i; 1147 1148 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1149 sizeof *priv->eq_table.uar_map, 1150 GFP_KERNEL); 1151 if (!priv->eq_table.uar_map) { 1152 err = -ENOMEM; 1153 goto err_out_free; 1154 } 1155 1156 err = mlx4_bitmap_init(&priv->eq_table.bitmap, 1157 roundup_pow_of_two(dev->caps.num_eqs), 1158 dev->caps.num_eqs - 1, 1159 dev->caps.reserved_eqs, 1160 roundup_pow_of_two(dev->caps.num_eqs) - 1161 dev->caps.num_eqs); 1162 if (err) 1163 goto err_out_free; 1164 1165 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1166 priv->eq_table.uar_map[i] = NULL; 1167 1168 if (!mlx4_is_slave(dev)) { 1169 err = mlx4_map_clr_int(dev); 1170 if (err) 1171 goto err_out_bitmap; 1172 1173 priv->eq_table.clr_mask = 1174 swab32(1 << (priv->eq_table.inta_pin & 31)); 1175 priv->eq_table.clr_int = priv->clr_base + 1176 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1177 } 1178 1179 priv->eq_table.irq_names = 1180 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 + 1181 dev->caps.comp_pool), 1182 GFP_KERNEL); 1183 if (!priv->eq_table.irq_names) { 1184 err = -ENOMEM; 1185 goto err_out_bitmap; 1186 } 1187 1188 for (i = 0; i < dev->caps.num_comp_vectors; ++i) { 1189 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1190 dev->caps.reserved_cqs + 1191 MLX4_NUM_SPARE_EQE, 1192 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1193 &priv->eq_table.eq[i]); 1194 if (err) { 1195 --i; 1196 goto err_out_unmap; 1197 } 1198 } 1199 1200 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1201 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0, 1202 &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1203 if (err) 1204 goto err_out_comp; 1205 1206 /*if additional completion vectors poolsize is 0 this loop will not run*/ 1207 for (i = dev->caps.num_comp_vectors + 1; 1208 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) { 1209 1210 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1211 dev->caps.reserved_cqs + 1212 MLX4_NUM_SPARE_EQE, 1213 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1214 &priv->eq_table.eq[i]); 1215 if (err) { 1216 --i; 1217 goto err_out_unmap; 1218 } 1219 } 1220 1221 1222 if (dev->flags & MLX4_FLAG_MSI_X) { 1223 const char *eq_name; 1224 1225 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1226 if (i < dev->caps.num_comp_vectors) { 1227 snprintf(priv->eq_table.irq_names + 1228 i * MLX4_IRQNAME_SIZE, 1229 MLX4_IRQNAME_SIZE, 1230 "mlx4-comp-%d@pci:%s", i, 1231 pci_name(dev->persist->pdev)); 1232 } else { 1233 snprintf(priv->eq_table.irq_names + 1234 i * MLX4_IRQNAME_SIZE, 1235 MLX4_IRQNAME_SIZE, 1236 "mlx4-async@pci:%s", 1237 pci_name(dev->persist->pdev)); 1238 } 1239 1240 eq_name = priv->eq_table.irq_names + 1241 i * MLX4_IRQNAME_SIZE; 1242 err = request_irq(priv->eq_table.eq[i].irq, 1243 mlx4_msi_x_interrupt, 0, eq_name, 1244 priv->eq_table.eq + i); 1245 if (err) 1246 goto err_out_async; 1247 1248 priv->eq_table.eq[i].have_irq = 1; 1249 } 1250 } else { 1251 snprintf(priv->eq_table.irq_names, 1252 MLX4_IRQNAME_SIZE, 1253 DRV_NAME "@pci:%s", 1254 pci_name(dev->persist->pdev)); 1255 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, 1256 IRQF_SHARED, priv->eq_table.irq_names, dev); 1257 if (err) 1258 goto err_out_async; 1259 1260 priv->eq_table.have_irq = 1; 1261 } 1262 1263 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1264 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1265 if (err) 1266 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1267 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err); 1268 1269 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1270 eq_set_ci(&priv->eq_table.eq[i], 1); 1271 1272 return 0; 1273 1274 err_out_async: 1275 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1276 1277 err_out_comp: 1278 i = dev->caps.num_comp_vectors - 1; 1279 1280 err_out_unmap: 1281 while (i >= 0) { 1282 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1283 --i; 1284 } 1285 if (!mlx4_is_slave(dev)) 1286 mlx4_unmap_clr_int(dev); 1287 mlx4_free_irqs(dev); 1288 1289 err_out_bitmap: 1290 mlx4_unmap_uar(dev); 1291 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1292 1293 err_out_free: 1294 kfree(priv->eq_table.uar_map); 1295 1296 return err; 1297 } 1298 1299 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1300 { 1301 struct mlx4_priv *priv = mlx4_priv(dev); 1302 int i; 1303 1304 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1305 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1306 1307 mlx4_free_irqs(dev); 1308 1309 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) 1310 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1311 1312 if (!mlx4_is_slave(dev)) 1313 mlx4_unmap_clr_int(dev); 1314 1315 mlx4_unmap_uar(dev); 1316 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1317 1318 kfree(priv->eq_table.uar_map); 1319 } 1320 1321 /* A test that verifies that we can accept interrupts on all 1322 * the irq vectors of the device. 1323 * Interrupts are checked using the NOP command. 1324 */ 1325 int mlx4_test_interrupts(struct mlx4_dev *dev) 1326 { 1327 struct mlx4_priv *priv = mlx4_priv(dev); 1328 int i; 1329 int err; 1330 1331 err = mlx4_NOP(dev); 1332 /* When not in MSI_X, there is only one irq to check */ 1333 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1334 return err; 1335 1336 /* A loop over all completion vectors, for each vector we will check 1337 * whether it works by mapping command completions to that vector 1338 * and performing a NOP command 1339 */ 1340 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1341 /* Temporary use polling for command completions */ 1342 mlx4_cmd_use_polling(dev); 1343 1344 /* Map the new eq to handle all asynchronous events */ 1345 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1346 priv->eq_table.eq[i].eqn); 1347 if (err) { 1348 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1349 mlx4_cmd_use_events(dev); 1350 break; 1351 } 1352 1353 /* Go back to using events */ 1354 mlx4_cmd_use_events(dev); 1355 err = mlx4_NOP(dev); 1356 } 1357 1358 /* Return to default */ 1359 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1360 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1361 return err; 1362 } 1363 EXPORT_SYMBOL(mlx4_test_interrupts); 1364 1365 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1366 int *vector) 1367 { 1368 1369 struct mlx4_priv *priv = mlx4_priv(dev); 1370 int vec = 0, err = 0, i; 1371 1372 mutex_lock(&priv->msix_ctl.pool_lock); 1373 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1374 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1375 priv->msix_ctl.pool_bm |= 1ULL << i; 1376 vec = dev->caps.num_comp_vectors + 1 + i; 1377 snprintf(priv->eq_table.irq_names + 1378 vec * MLX4_IRQNAME_SIZE, 1379 MLX4_IRQNAME_SIZE, "%s", name); 1380 #ifdef CONFIG_RFS_ACCEL 1381 if (rmap) { 1382 err = irq_cpu_rmap_add(rmap, 1383 priv->eq_table.eq[vec].irq); 1384 if (err) 1385 mlx4_warn(dev, "Failed adding irq rmap\n"); 1386 } 1387 #endif 1388 err = request_irq(priv->eq_table.eq[vec].irq, 1389 mlx4_msi_x_interrupt, 0, 1390 &priv->eq_table.irq_names[vec<<5], 1391 priv->eq_table.eq + vec); 1392 if (err) { 1393 /*zero out bit by fliping it*/ 1394 priv->msix_ctl.pool_bm ^= 1 << i; 1395 vec = 0; 1396 continue; 1397 /*we dont want to break here*/ 1398 } 1399 1400 eq_set_ci(&priv->eq_table.eq[vec], 1); 1401 } 1402 } 1403 mutex_unlock(&priv->msix_ctl.pool_lock); 1404 1405 if (vec) { 1406 *vector = vec; 1407 } else { 1408 *vector = 0; 1409 err = (i == dev->caps.comp_pool) ? -ENOSPC : err; 1410 } 1411 return err; 1412 } 1413 EXPORT_SYMBOL(mlx4_assign_eq); 1414 1415 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec) 1416 { 1417 struct mlx4_priv *priv = mlx4_priv(dev); 1418 1419 return priv->eq_table.eq[vec].irq; 1420 } 1421 EXPORT_SYMBOL(mlx4_eq_get_irq); 1422 1423 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1424 { 1425 struct mlx4_priv *priv = mlx4_priv(dev); 1426 /*bm index*/ 1427 int i = vec - dev->caps.num_comp_vectors - 1; 1428 1429 if (likely(i >= 0)) { 1430 /*sanity check , making sure were not trying to free irq's 1431 Belonging to a legacy EQ*/ 1432 mutex_lock(&priv->msix_ctl.pool_lock); 1433 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1434 free_irq(priv->eq_table.eq[vec].irq, 1435 &priv->eq_table.eq[vec]); 1436 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1437 } 1438 mutex_unlock(&priv->msix_ctl.pool_lock); 1439 } 1440 1441 } 1442 EXPORT_SYMBOL(mlx4_release_eq); 1443 1444