1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/export.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/cpu_rmap.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT); 93 94 return async_ev_mask; 95 } 96 97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 98 { 99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 100 req_not << 31), 101 eq->doorbell); 102 /* We still want ordering, just not swabbing, so add a barrier */ 103 wmb(); 104 } 105 106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, 107 u8 eqe_size) 108 { 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; 111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with 112 * strides of 64B,128B and 256B. 113 * When 64B EQE is used, the first (in the lower addresses) 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 115 * contain the legacy EQE information. 116 * In all other cases, the first 32B contains the legacy EQE info. 117 */ 118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 119 } 120 121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) 122 { 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 125 } 126 127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 128 { 129 struct mlx4_eqe *eqe = 130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 131 return (!!(eqe->owner & 0x80) ^ 132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 133 eqe : NULL; 134 } 135 136 void mlx4_gen_slave_eqe(struct work_struct *work) 137 { 138 struct mlx4_mfunc_master_ctx *master = 139 container_of(work, struct mlx4_mfunc_master_ctx, 140 slave_event_work); 141 struct mlx4_mfunc *mfunc = 142 container_of(master, struct mlx4_mfunc, master); 143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 144 struct mlx4_dev *dev = &priv->dev; 145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 146 struct mlx4_eqe *eqe; 147 u8 slave; 148 int i, phys_port, slave_port; 149 150 for (eqe = next_slave_event_eqe(slave_eq); eqe; 151 eqe = next_slave_event_eqe(slave_eq)) { 152 slave = eqe->slave_id; 153 154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE && 155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN && 156 mlx4_is_bonded(dev)) { 157 struct mlx4_port_cap port_cap; 158 159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state) 160 goto consume; 161 162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state) 163 goto consume; 164 } 165 /* All active slaves need to receive the event */ 166 if (slave == ALL_SLAVES) { 167 for (i = 0; i <= dev->persist->num_vfs; i++) { 168 phys_port = 0; 169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT && 170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) { 171 phys_port = eqe->event.port_mgmt_change.port; 172 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port); 173 if (slave_port < 0) /* VF doesn't have this port */ 174 continue; 175 eqe->event.port_mgmt_change.port = slave_port; 176 } 177 if (mlx4_GEN_EQE(dev, i, eqe)) 178 mlx4_warn(dev, "Failed to generate event for slave %d\n", 179 i); 180 if (phys_port) 181 eqe->event.port_mgmt_change.port = phys_port; 182 } 183 } else { 184 if (mlx4_GEN_EQE(dev, slave, eqe)) 185 mlx4_warn(dev, "Failed to generate event for slave %d\n", 186 slave); 187 } 188 consume: 189 ++slave_eq->cons; 190 } 191 } 192 193 194 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 195 { 196 struct mlx4_priv *priv = mlx4_priv(dev); 197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 198 struct mlx4_eqe *s_eqe; 199 unsigned long flags; 200 201 spin_lock_irqsave(&slave_eq->event_lock, flags); 202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 203 if ((!!(s_eqe->owner & 0x80)) ^ 204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 205 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 206 slave); 207 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 208 return; 209 } 210 211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1); 212 s_eqe->slave_id = slave; 213 /* ensure all information is written before setting the ownersip bit */ 214 dma_wmb(); 215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 216 ++slave_eq->prod; 217 218 queue_work(priv->mfunc.master.comm_wq, 219 &priv->mfunc.master.slave_event_work); 220 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 221 } 222 223 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 224 struct mlx4_eqe *eqe) 225 { 226 struct mlx4_priv *priv = mlx4_priv(dev); 227 228 if (slave < 0 || slave > dev->persist->num_vfs || 229 slave == dev->caps.function || 230 !priv->mfunc.master.slave_state[slave].active) 231 return; 232 233 slave_event(dev, slave, eqe); 234 } 235 236 #if defined(CONFIG_SMP) 237 static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec) 238 { 239 int hint_err; 240 struct mlx4_dev *dev = &priv->dev; 241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; 242 243 if (!cpumask_available(eq->affinity_mask) || 244 cpumask_empty(eq->affinity_mask)) 245 return; 246 247 hint_err = irq_update_affinity_hint(eq->irq, eq->affinity_mask); 248 if (hint_err) 249 mlx4_warn(dev, "irq_update_affinity_hint failed, err %d\n", hint_err); 250 } 251 #endif 252 253 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 254 { 255 struct mlx4_eqe eqe; 256 257 struct mlx4_priv *priv = mlx4_priv(dev); 258 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 259 260 if (!s_slave->active) 261 return 0; 262 263 memset(&eqe, 0, sizeof(eqe)); 264 265 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 266 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 267 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 268 269 return mlx4_GEN_EQE(dev, slave, &eqe); 270 } 271 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 272 273 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 274 { 275 struct mlx4_eqe eqe; 276 277 /*don't send if we don't have the that slave */ 278 if (dev->persist->num_vfs < slave) 279 return 0; 280 memset(&eqe, 0, sizeof(eqe)); 281 282 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 283 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 284 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 285 286 return mlx4_GEN_EQE(dev, slave, &eqe); 287 } 288 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 289 290 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 291 u8 port_subtype_change) 292 { 293 struct mlx4_eqe eqe; 294 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port); 295 296 /*don't send if we don't have the that slave */ 297 if (dev->persist->num_vfs < slave) 298 return 0; 299 memset(&eqe, 0, sizeof(eqe)); 300 301 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 302 eqe.subtype = port_subtype_change; 303 eqe.event.port_change.port = cpu_to_be32(slave_port << 28); 304 305 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 306 port_subtype_change, slave, port); 307 return mlx4_GEN_EQE(dev, slave, &eqe); 308 } 309 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 310 311 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 312 { 313 struct mlx4_priv *priv = mlx4_priv(dev); 314 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 315 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 316 317 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 318 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 319 pr_err("%s: Error: asking for slave:%d, port:%d\n", 320 __func__, slave, port); 321 return SLAVE_PORT_DOWN; 322 } 323 return s_state[slave].port_state[port]; 324 } 325 EXPORT_SYMBOL(mlx4_get_slave_port_state); 326 327 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 328 enum slave_port_state state) 329 { 330 struct mlx4_priv *priv = mlx4_priv(dev); 331 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 332 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 333 334 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 335 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 336 pr_err("%s: Error: asking for slave:%d, port:%d\n", 337 __func__, slave, port); 338 return -1; 339 } 340 s_state[slave].port_state[port] = state; 341 342 return 0; 343 } 344 345 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 346 { 347 int i; 348 enum slave_port_gen_event gen_event; 349 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 350 port); 351 352 for (i = 0; i < dev->persist->num_vfs + 1; i++) 353 if (test_bit(i, slaves_pport.slaves)) 354 set_and_calc_slave_port_state(dev, i, port, 355 event, &gen_event); 356 } 357 /************************************************************************** 358 The function get as input the new event to that port, 359 and according to the prev state change the slave's port state. 360 The events are: 361 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 362 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 363 MLX4_PORT_STATE_IB_EVENT_GID_VALID 364 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 365 ***************************************************************************/ 366 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 367 u8 port, int event, 368 enum slave_port_gen_event *gen_event) 369 { 370 struct mlx4_priv *priv = mlx4_priv(dev); 371 struct mlx4_slave_state *ctx = NULL; 372 unsigned long flags; 373 int ret = -1; 374 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 375 enum slave_port_state cur_state = 376 mlx4_get_slave_port_state(dev, slave, port); 377 378 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 379 380 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 381 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 382 pr_err("%s: Error: asking for slave:%d, port:%d\n", 383 __func__, slave, port); 384 return ret; 385 } 386 387 ctx = &priv->mfunc.master.slave_state[slave]; 388 spin_lock_irqsave(&ctx->lock, flags); 389 390 switch (cur_state) { 391 case SLAVE_PORT_DOWN: 392 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 393 mlx4_set_slave_port_state(dev, slave, port, 394 SLAVE_PENDING_UP); 395 break; 396 case SLAVE_PENDING_UP: 397 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 398 mlx4_set_slave_port_state(dev, slave, port, 399 SLAVE_PORT_DOWN); 400 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 401 mlx4_set_slave_port_state(dev, slave, port, 402 SLAVE_PORT_UP); 403 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 404 } 405 break; 406 case SLAVE_PORT_UP: 407 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 408 mlx4_set_slave_port_state(dev, slave, port, 409 SLAVE_PORT_DOWN); 410 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 411 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 412 event) { 413 mlx4_set_slave_port_state(dev, slave, port, 414 SLAVE_PENDING_UP); 415 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 416 } 417 break; 418 default: 419 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 420 __func__, slave, port); 421 goto out; 422 } 423 ret = mlx4_get_slave_port_state(dev, slave, port); 424 425 out: 426 spin_unlock_irqrestore(&ctx->lock, flags); 427 return ret; 428 } 429 430 EXPORT_SYMBOL(set_and_calc_slave_port_state); 431 432 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 433 { 434 struct mlx4_eqe eqe; 435 436 memset(&eqe, 0, sizeof(eqe)); 437 438 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 439 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 440 eqe.event.port_mgmt_change.port = port; 441 eqe.event.port_mgmt_change.params.port_info.changed_attr = 442 cpu_to_be32((u32) attr); 443 444 slave_event(dev, ALL_SLAVES, &eqe); 445 return 0; 446 } 447 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 448 449 void mlx4_master_handle_slave_flr(struct work_struct *work) 450 { 451 struct mlx4_mfunc_master_ctx *master = 452 container_of(work, struct mlx4_mfunc_master_ctx, 453 slave_flr_event_work); 454 struct mlx4_mfunc *mfunc = 455 container_of(master, struct mlx4_mfunc, master); 456 struct mlx4_priv *priv = 457 container_of(mfunc, struct mlx4_priv, mfunc); 458 struct mlx4_dev *dev = &priv->dev; 459 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 460 int i; 461 int err; 462 unsigned long flags; 463 464 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 465 466 for (i = 0 ; i < dev->num_slaves; i++) { 467 468 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 469 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 470 i); 471 /* In case of 'Reset flow' FLR can be generated for 472 * a slave before mlx4_load_one is done. 473 * make sure interface is up before trying to delete 474 * slave resources which weren't allocated yet. 475 */ 476 if (dev->persist->interface_state & 477 MLX4_INTERFACE_STATE_UP) 478 mlx4_delete_all_resources_for_slave(dev, i); 479 /*return the slave to running mode*/ 480 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 481 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 482 slave_state[i].is_slave_going_down = 0; 483 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 484 /*notify the FW:*/ 485 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 486 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 487 if (err) 488 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 489 i); 490 } 491 } 492 } 493 494 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 495 { 496 struct mlx4_priv *priv = mlx4_priv(dev); 497 struct mlx4_eqe *eqe; 498 int cqn; 499 int eqes_found = 0; 500 int set_ci = 0; 501 int port; 502 int slave = 0; 503 int ret; 504 u32 flr_slave; 505 u8 update_slave_state; 506 int i; 507 enum slave_port_gen_event gen_event; 508 unsigned long flags; 509 struct mlx4_vport_state *s_info; 510 int eqe_size = dev->caps.eqe_size; 511 512 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { 513 /* 514 * Make sure we read EQ entry contents after we've 515 * checked the ownership bit. 516 */ 517 dma_rmb(); 518 519 switch (eqe->type) { 520 case MLX4_EVENT_TYPE_COMP: 521 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 522 mlx4_cq_completion(dev, cqn); 523 break; 524 525 case MLX4_EVENT_TYPE_PATH_MIG: 526 case MLX4_EVENT_TYPE_COMM_EST: 527 case MLX4_EVENT_TYPE_SQ_DRAINED: 528 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 529 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 530 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 531 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 532 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 533 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 534 if (mlx4_is_master(dev)) { 535 /* forward only to slave owning the QP */ 536 ret = mlx4_get_slave_from_resource_id(dev, 537 RES_QP, 538 be32_to_cpu(eqe->event.qp.qpn) 539 & 0xffffff, &slave); 540 if (ret && ret != -ENOENT) { 541 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 542 eqe->type, eqe->subtype, 543 eq->eqn, eq->cons_index, ret); 544 break; 545 } 546 547 if (!ret && slave != dev->caps.function) { 548 mlx4_slave_event(dev, slave, eqe); 549 break; 550 } 551 552 } 553 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 554 0xffffff, eqe->type); 555 break; 556 557 case MLX4_EVENT_TYPE_SRQ_LIMIT: 558 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n", 559 __func__, be32_to_cpu(eqe->event.srq.srqn), 560 eq->eqn); 561 fallthrough; 562 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 563 if (mlx4_is_master(dev)) { 564 /* forward only to slave owning the SRQ */ 565 ret = mlx4_get_slave_from_resource_id(dev, 566 RES_SRQ, 567 be32_to_cpu(eqe->event.srq.srqn) 568 & 0xffffff, 569 &slave); 570 if (ret && ret != -ENOENT) { 571 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 572 eqe->type, eqe->subtype, 573 eq->eqn, eq->cons_index, ret); 574 break; 575 } 576 if (eqe->type == 577 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) 578 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 579 __func__, slave, 580 be32_to_cpu(eqe->event.srq.srqn), 581 eqe->type, eqe->subtype); 582 583 if (!ret && slave != dev->caps.function) { 584 if (eqe->type == 585 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) 586 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 587 __func__, eqe->type, 588 eqe->subtype, slave); 589 mlx4_slave_event(dev, slave, eqe); 590 break; 591 } 592 } 593 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 594 0xffffff, eqe->type); 595 break; 596 597 case MLX4_EVENT_TYPE_CMD: 598 mlx4_cmd_event(dev, 599 be16_to_cpu(eqe->event.cmd.token), 600 eqe->event.cmd.status, 601 be64_to_cpu(eqe->event.cmd.out_param)); 602 break; 603 604 case MLX4_EVENT_TYPE_PORT_CHANGE: { 605 struct mlx4_slaves_pport slaves_port; 606 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 607 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 608 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 609 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 610 port); 611 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 612 if (!mlx4_is_master(dev)) 613 break; 614 for (i = 0; i < dev->persist->num_vfs + 1; 615 i++) { 616 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 617 618 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 619 continue; 620 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 621 if (i == mlx4_master_func_num(dev)) 622 continue; 623 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 624 __func__, i, port); 625 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; 626 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 627 eqe->event.port_change.port = 628 cpu_to_be32( 629 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 630 | (reported_port << 28)); 631 mlx4_slave_event(dev, i, eqe); 632 } 633 } else { /* IB port */ 634 set_and_calc_slave_port_state(dev, i, port, 635 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 636 &gen_event); 637 /*we can be in pending state, then do not send port_down event*/ 638 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 639 if (i == mlx4_master_func_num(dev)) 640 continue; 641 eqe->event.port_change.port = 642 cpu_to_be32( 643 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 644 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 645 mlx4_slave_event(dev, i, eqe); 646 } 647 } 648 } 649 } else { 650 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 651 652 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 653 654 if (!mlx4_is_master(dev)) 655 break; 656 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 657 for (i = 0; 658 i < dev->persist->num_vfs + 1; 659 i++) { 660 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 661 662 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 663 continue; 664 if (i == mlx4_master_func_num(dev)) 665 continue; 666 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state; 667 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 668 eqe->event.port_change.port = 669 cpu_to_be32( 670 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 671 | (reported_port << 28)); 672 mlx4_slave_event(dev, i, eqe); 673 } 674 } 675 else /* IB port */ 676 /* port-up event will be sent to a slave when the 677 * slave's alias-guid is set. This is done in alias_GUID.c 678 */ 679 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 680 } 681 break; 682 } 683 684 case MLX4_EVENT_TYPE_CQ_ERROR: 685 mlx4_warn(dev, "CQ %s on CQN %06x\n", 686 eqe->event.cq_err.syndrome == 1 ? 687 "overrun" : "access violation", 688 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 689 if (mlx4_is_master(dev)) { 690 ret = mlx4_get_slave_from_resource_id(dev, 691 RES_CQ, 692 be32_to_cpu(eqe->event.cq_err.cqn) 693 & 0xffffff, &slave); 694 if (ret && ret != -ENOENT) { 695 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 696 eqe->type, eqe->subtype, 697 eq->eqn, eq->cons_index, ret); 698 break; 699 } 700 701 if (!ret && slave != dev->caps.function) { 702 mlx4_slave_event(dev, slave, eqe); 703 break; 704 } 705 } 706 mlx4_cq_event(dev, 707 be32_to_cpu(eqe->event.cq_err.cqn) 708 & 0xffffff, 709 eqe->type); 710 break; 711 712 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 713 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 714 break; 715 716 case MLX4_EVENT_TYPE_OP_REQUIRED: 717 atomic_inc(&priv->opreq_count); 718 /* FW commands can't be executed from interrupt context 719 * working in deferred task 720 */ 721 queue_work(mlx4_wq, &priv->opreq_task); 722 break; 723 724 case MLX4_EVENT_TYPE_COMM_CHANNEL: 725 if (!mlx4_is_master(dev)) { 726 mlx4_warn(dev, "Received comm channel event for non master device\n"); 727 break; 728 } 729 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 730 eqe->event.comm_channel_arm.bit_vec, 731 sizeof(eqe->event.comm_channel_arm.bit_vec)); 732 queue_work(priv->mfunc.master.comm_wq, 733 &priv->mfunc.master.comm_work); 734 break; 735 736 case MLX4_EVENT_TYPE_FLR_EVENT: 737 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 738 if (!mlx4_is_master(dev)) { 739 mlx4_warn(dev, "Non-master function received FLR event\n"); 740 break; 741 } 742 743 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 744 745 if (flr_slave >= dev->num_slaves) { 746 mlx4_warn(dev, 747 "Got FLR for unknown function: %d\n", 748 flr_slave); 749 update_slave_state = 0; 750 } else 751 update_slave_state = 1; 752 753 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 754 if (update_slave_state) { 755 priv->mfunc.master.slave_state[flr_slave].active = false; 756 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 757 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 758 } 759 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 760 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, 761 flr_slave); 762 queue_work(priv->mfunc.master.comm_wq, 763 &priv->mfunc.master.slave_flr_event_work); 764 break; 765 766 case MLX4_EVENT_TYPE_FATAL_WARNING: 767 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 768 if (mlx4_is_master(dev)) 769 for (i = 0; i < dev->num_slaves; i++) { 770 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 771 __func__, i); 772 if (i == dev->caps.function) 773 continue; 774 mlx4_slave_event(dev, i, eqe); 775 } 776 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 777 be16_to_cpu(eqe->event.warming.warning_threshold), 778 be16_to_cpu(eqe->event.warming.current_temperature)); 779 } else 780 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 781 eqe->type, eqe->subtype, eq->eqn, 782 eq->cons_index, eqe->owner, eq->nent, 783 eqe->slave_id, 784 !!(eqe->owner & 0x80) ^ 785 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 786 787 break; 788 789 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 790 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 791 (unsigned long) eqe); 792 break; 793 794 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT: 795 switch (eqe->subtype) { 796 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE: 797 mlx4_warn(dev, "Bad cable detected on port %u\n", 798 eqe->event.bad_cable.port); 799 break; 800 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE: 801 mlx4_warn(dev, "Unsupported cable detected\n"); 802 break; 803 default: 804 mlx4_dbg(dev, 805 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n", 806 eqe->type, eqe->subtype, eq->eqn, 807 eq->cons_index, eqe->owner, eq->nent, 808 !!(eqe->owner & 0x80) ^ 809 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 810 break; 811 } 812 break; 813 814 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 815 case MLX4_EVENT_TYPE_ECC_DETECT: 816 default: 817 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 818 eqe->type, eqe->subtype, eq->eqn, 819 eq->cons_index, eqe->owner, eq->nent, 820 eqe->slave_id, 821 !!(eqe->owner & 0x80) ^ 822 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 823 break; 824 } 825 826 ++eq->cons_index; 827 eqes_found = 1; 828 ++set_ci; 829 830 /* 831 * The HCA will think the queue has overflowed if we 832 * don't tell it we've been processing events. We 833 * create our EQs with MLX4_NUM_SPARE_EQE extra 834 * entries, so we must update our consumer index at 835 * least that often. 836 */ 837 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 838 eq_set_ci(eq, 0); 839 set_ci = 0; 840 } 841 } 842 843 eq_set_ci(eq, 1); 844 845 return eqes_found; 846 } 847 848 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 849 { 850 struct mlx4_dev *dev = dev_ptr; 851 struct mlx4_priv *priv = mlx4_priv(dev); 852 int work = 0; 853 int i; 854 855 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 856 857 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 858 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 859 860 return IRQ_RETVAL(work); 861 } 862 863 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 864 { 865 struct mlx4_eq *eq = eq_ptr; 866 struct mlx4_dev *dev = eq->dev; 867 868 mlx4_eq_int(dev, eq); 869 870 /* MSI-X vectors always belong to us */ 871 return IRQ_HANDLED; 872 } 873 874 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 875 struct mlx4_vhcr *vhcr, 876 struct mlx4_cmd_mailbox *inbox, 877 struct mlx4_cmd_mailbox *outbox, 878 struct mlx4_cmd_info *cmd) 879 { 880 struct mlx4_priv *priv = mlx4_priv(dev); 881 struct mlx4_slave_event_eq_info *event_eq = 882 priv->mfunc.master.slave_state[slave].event_eq; 883 u32 in_modifier = vhcr->in_modifier; 884 u32 eqn = in_modifier & 0x3FF; 885 u64 in_param = vhcr->in_param; 886 int err = 0; 887 int i; 888 889 if (slave == dev->caps.function) 890 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 891 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 892 MLX4_CMD_NATIVE); 893 if (!err) 894 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 895 if (in_param & (1LL << i)) 896 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 897 898 return err; 899 } 900 901 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 902 int eq_num) 903 { 904 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 905 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 906 MLX4_CMD_WRAPPED); 907 } 908 909 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 910 int eq_num) 911 { 912 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 913 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 914 MLX4_CMD_WRAPPED); 915 } 916 917 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num) 918 { 919 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ, 920 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 921 } 922 923 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 924 { 925 /* 926 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 927 * we need to map, take the difference of highest index and 928 * the lowest index we'll use and add 1. 929 */ 930 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 - 931 dev->caps.reserved_eqs / 4 + 1; 932 } 933 934 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 935 { 936 struct mlx4_priv *priv = mlx4_priv(dev); 937 int index; 938 939 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 940 941 if (!priv->eq_table.uar_map[index]) { 942 priv->eq_table.uar_map[index] = 943 ioremap( 944 pci_resource_start(dev->persist->pdev, 2) + 945 ((eq->eqn / 4) << (dev->uar_page_shift)), 946 (1 << (dev->uar_page_shift))); 947 if (!priv->eq_table.uar_map[index]) { 948 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 949 eq->eqn); 950 return NULL; 951 } 952 } 953 954 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 955 } 956 957 static void mlx4_unmap_uar(struct mlx4_dev *dev) 958 { 959 struct mlx4_priv *priv = mlx4_priv(dev); 960 int i; 961 962 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 963 if (priv->eq_table.uar_map[i]) { 964 iounmap(priv->eq_table.uar_map[i]); 965 priv->eq_table.uar_map[i] = NULL; 966 } 967 } 968 969 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 970 u8 intr, struct mlx4_eq *eq) 971 { 972 struct mlx4_priv *priv = mlx4_priv(dev); 973 struct mlx4_cmd_mailbox *mailbox; 974 struct mlx4_eq_context *eq_context; 975 int npages; 976 u64 *dma_list = NULL; 977 dma_addr_t t; 978 u64 mtt_addr; 979 int err = -ENOMEM; 980 int i; 981 982 eq->dev = dev; 983 eq->nent = roundup_pow_of_two(max(nent, 2)); 984 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 985 * strides of 64B,128B and 256B. 986 */ 987 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; 988 989 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list), 990 GFP_KERNEL); 991 if (!eq->page_list) 992 goto err_out; 993 994 for (i = 0; i < npages; ++i) 995 eq->page_list[i].buf = NULL; 996 997 dma_list = kmalloc_array(npages, sizeof(*dma_list), GFP_KERNEL); 998 if (!dma_list) 999 goto err_out_free; 1000 1001 mailbox = mlx4_alloc_cmd_mailbox(dev); 1002 if (IS_ERR(mailbox)) 1003 goto err_out_free; 1004 eq_context = mailbox->buf; 1005 1006 for (i = 0; i < npages; ++i) { 1007 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> 1008 pdev->dev, 1009 PAGE_SIZE, &t, 1010 GFP_KERNEL); 1011 if (!eq->page_list[i].buf) 1012 goto err_out_free_pages; 1013 1014 dma_list[i] = t; 1015 eq->page_list[i].map = t; 1016 } 1017 1018 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 1019 if (eq->eqn == -1) 1020 goto err_out_free_pages; 1021 1022 eq->doorbell = mlx4_get_eq_uar(dev, eq); 1023 if (!eq->doorbell) { 1024 err = -ENOMEM; 1025 goto err_out_free_eq; 1026 } 1027 1028 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 1029 if (err) 1030 goto err_out_free_eq; 1031 1032 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 1033 if (err) 1034 goto err_out_free_mtt; 1035 1036 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 1037 MLX4_EQ_STATE_ARMED); 1038 eq_context->log_eq_size = ilog2(eq->nent); 1039 eq_context->intr = intr; 1040 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 1041 1042 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 1043 eq_context->mtt_base_addr_h = mtt_addr >> 32; 1044 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 1045 1046 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 1047 if (err) { 1048 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 1049 goto err_out_free_mtt; 1050 } 1051 1052 kfree(dma_list); 1053 mlx4_free_cmd_mailbox(dev, mailbox); 1054 1055 eq->cons_index = 0; 1056 1057 INIT_LIST_HEAD(&eq->tasklet_ctx.list); 1058 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list); 1059 spin_lock_init(&eq->tasklet_ctx.lock); 1060 tasklet_setup(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb); 1061 1062 return err; 1063 1064 err_out_free_mtt: 1065 mlx4_mtt_cleanup(dev, &eq->mtt); 1066 1067 err_out_free_eq: 1068 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1069 1070 err_out_free_pages: 1071 for (i = 0; i < npages; ++i) 1072 if (eq->page_list[i].buf) 1073 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1074 eq->page_list[i].buf, 1075 eq->page_list[i].map); 1076 1077 mlx4_free_cmd_mailbox(dev, mailbox); 1078 1079 err_out_free: 1080 kfree(eq->page_list); 1081 kfree(dma_list); 1082 1083 err_out: 1084 return err; 1085 } 1086 1087 static void mlx4_free_eq(struct mlx4_dev *dev, 1088 struct mlx4_eq *eq) 1089 { 1090 struct mlx4_priv *priv = mlx4_priv(dev); 1091 int err; 1092 int i; 1093 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 1094 * strides of 64B,128B and 256B 1095 */ 1096 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; 1097 1098 err = mlx4_HW2SW_EQ(dev, eq->eqn); 1099 if (err) 1100 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1101 1102 synchronize_irq(eq->irq); 1103 tasklet_disable(&eq->tasklet_ctx.task); 1104 1105 mlx4_mtt_cleanup(dev, &eq->mtt); 1106 for (i = 0; i < npages; ++i) 1107 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1108 eq->page_list[i].buf, 1109 eq->page_list[i].map); 1110 1111 kfree(eq->page_list); 1112 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1113 } 1114 1115 static void mlx4_free_irqs(struct mlx4_dev *dev) 1116 { 1117 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1118 int i; 1119 1120 if (eq_table->have_irq) 1121 free_irq(dev->persist->pdev->irq, dev); 1122 1123 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1124 if (eq_table->eq[i].have_irq) { 1125 free_cpumask_var(eq_table->eq[i].affinity_mask); 1126 irq_update_affinity_hint(eq_table->eq[i].irq, NULL); 1127 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1128 eq_table->eq[i].have_irq = 0; 1129 } 1130 1131 kfree(eq_table->irq_names); 1132 } 1133 1134 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1135 { 1136 struct mlx4_priv *priv = mlx4_priv(dev); 1137 1138 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, 1139 priv->fw.clr_int_bar) + 1140 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1141 if (!priv->clr_base) { 1142 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1143 return -ENOMEM; 1144 } 1145 1146 return 0; 1147 } 1148 1149 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1150 { 1151 struct mlx4_priv *priv = mlx4_priv(dev); 1152 1153 iounmap(priv->clr_base); 1154 } 1155 1156 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1157 { 1158 struct mlx4_priv *priv = mlx4_priv(dev); 1159 1160 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1161 sizeof(*priv->eq_table.eq), GFP_KERNEL); 1162 if (!priv->eq_table.eq) 1163 return -ENOMEM; 1164 1165 return 0; 1166 } 1167 1168 void mlx4_free_eq_table(struct mlx4_dev *dev) 1169 { 1170 kfree(mlx4_priv(dev)->eq_table.eq); 1171 } 1172 1173 int mlx4_init_eq_table(struct mlx4_dev *dev) 1174 { 1175 struct mlx4_priv *priv = mlx4_priv(dev); 1176 int err; 1177 int i; 1178 1179 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1180 sizeof(*priv->eq_table.uar_map), 1181 GFP_KERNEL); 1182 if (!priv->eq_table.uar_map) { 1183 err = -ENOMEM; 1184 goto err_out_free; 1185 } 1186 1187 err = mlx4_bitmap_init(&priv->eq_table.bitmap, 1188 roundup_pow_of_two(dev->caps.num_eqs), 1189 dev->caps.num_eqs - 1, 1190 dev->caps.reserved_eqs, 1191 roundup_pow_of_two(dev->caps.num_eqs) - 1192 dev->caps.num_eqs); 1193 if (err) 1194 goto err_out_free; 1195 1196 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1197 priv->eq_table.uar_map[i] = NULL; 1198 1199 if (!mlx4_is_slave(dev)) { 1200 err = mlx4_map_clr_int(dev); 1201 if (err) 1202 goto err_out_bitmap; 1203 1204 priv->eq_table.clr_mask = 1205 swab32(1 << (priv->eq_table.inta_pin & 31)); 1206 priv->eq_table.clr_int = priv->clr_base + 1207 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1208 } 1209 1210 priv->eq_table.irq_names = 1211 kmalloc_array(MLX4_IRQNAME_SIZE, 1212 (dev->caps.num_comp_vectors + 1), 1213 GFP_KERNEL); 1214 if (!priv->eq_table.irq_names) { 1215 err = -ENOMEM; 1216 goto err_out_clr_int; 1217 } 1218 1219 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1220 if (i == MLX4_EQ_ASYNC) { 1221 err = mlx4_create_eq(dev, 1222 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1223 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]); 1224 } else { 1225 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1226 #ifdef CONFIG_RFS_ACCEL 1227 int port = find_first_bit(eq->actv_ports.ports, 1228 dev->caps.num_ports) + 1; 1229 1230 if (port <= dev->caps.num_ports) { 1231 struct mlx4_port_info *info = 1232 &mlx4_priv(dev)->port[port]; 1233 1234 if (!info->rmap) { 1235 info->rmap = alloc_irq_cpu_rmap( 1236 mlx4_get_eqs_per_port(dev, port)); 1237 if (!info->rmap) { 1238 mlx4_warn(dev, "Failed to allocate cpu rmap\n"); 1239 err = -ENOMEM; 1240 goto err_out_unmap; 1241 } 1242 } 1243 1244 err = irq_cpu_rmap_add( 1245 info->rmap, eq->irq); 1246 if (err) 1247 mlx4_warn(dev, "Failed adding irq rmap\n"); 1248 } 1249 #endif 1250 err = mlx4_create_eq(dev, dev->quotas.cq + 1251 MLX4_NUM_SPARE_EQE, 1252 (dev->flags & MLX4_FLAG_MSI_X) ? 1253 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0, 1254 eq); 1255 } 1256 if (err) 1257 goto err_out_unmap; 1258 } 1259 1260 if (dev->flags & MLX4_FLAG_MSI_X) { 1261 const char *eq_name; 1262 1263 snprintf(priv->eq_table.irq_names + 1264 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, 1265 MLX4_IRQNAME_SIZE, 1266 "mlx4-async@pci:%s", 1267 pci_name(dev->persist->pdev)); 1268 eq_name = priv->eq_table.irq_names + 1269 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; 1270 1271 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, 1272 mlx4_msi_x_interrupt, 0, eq_name, 1273 priv->eq_table.eq + MLX4_EQ_ASYNC); 1274 if (err) 1275 goto err_out_unmap; 1276 1277 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; 1278 } else { 1279 snprintf(priv->eq_table.irq_names, 1280 MLX4_IRQNAME_SIZE, 1281 DRV_NAME "@pci:%s", 1282 pci_name(dev->persist->pdev)); 1283 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, 1284 IRQF_SHARED, priv->eq_table.irq_names, dev); 1285 if (err) 1286 goto err_out_unmap; 1287 1288 priv->eq_table.have_irq = 1; 1289 } 1290 1291 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1292 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1293 if (err) 1294 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1295 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); 1296 1297 /* arm ASYNC eq */ 1298 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1); 1299 1300 return 0; 1301 1302 err_out_unmap: 1303 while (i > 0) 1304 mlx4_free_eq(dev, &priv->eq_table.eq[--i]); 1305 #ifdef CONFIG_RFS_ACCEL 1306 for (i = 1; i <= dev->caps.num_ports; i++) { 1307 if (mlx4_priv(dev)->port[i].rmap) { 1308 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1309 mlx4_priv(dev)->port[i].rmap = NULL; 1310 } 1311 } 1312 #endif 1313 mlx4_free_irqs(dev); 1314 1315 err_out_clr_int: 1316 if (!mlx4_is_slave(dev)) 1317 mlx4_unmap_clr_int(dev); 1318 1319 err_out_bitmap: 1320 mlx4_unmap_uar(dev); 1321 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1322 1323 err_out_free: 1324 kfree(priv->eq_table.uar_map); 1325 1326 return err; 1327 } 1328 1329 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1330 { 1331 struct mlx4_priv *priv = mlx4_priv(dev); 1332 int i; 1333 1334 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1335 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1336 1337 #ifdef CONFIG_RFS_ACCEL 1338 for (i = 1; i <= dev->caps.num_ports; i++) { 1339 if (mlx4_priv(dev)->port[i].rmap) { 1340 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1341 mlx4_priv(dev)->port[i].rmap = NULL; 1342 } 1343 } 1344 #endif 1345 mlx4_free_irqs(dev); 1346 1347 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1348 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1349 1350 if (!mlx4_is_slave(dev)) 1351 mlx4_unmap_clr_int(dev); 1352 1353 mlx4_unmap_uar(dev); 1354 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1355 1356 kfree(priv->eq_table.uar_map); 1357 } 1358 1359 /* A test that verifies that we can accept interrupts 1360 * on the vector allocated for asynchronous events 1361 */ 1362 int mlx4_test_async(struct mlx4_dev *dev) 1363 { 1364 return mlx4_NOP(dev); 1365 } 1366 EXPORT_SYMBOL(mlx4_test_async); 1367 1368 /* A test that verifies that we can accept interrupts 1369 * on the given irq vector of the tested port. 1370 * Interrupts are checked using the NOP command. 1371 */ 1372 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector) 1373 { 1374 struct mlx4_priv *priv = mlx4_priv(dev); 1375 int err; 1376 1377 /* Temporary use polling for command completions */ 1378 mlx4_cmd_use_polling(dev); 1379 1380 /* Map the new eq to handle all asynchronous events */ 1381 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1382 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn); 1383 if (err) { 1384 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1385 goto out; 1386 } 1387 1388 /* Go back to using events */ 1389 mlx4_cmd_use_events(dev); 1390 err = mlx4_NOP(dev); 1391 1392 /* Return to default */ 1393 mlx4_cmd_use_polling(dev); 1394 out: 1395 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1396 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1397 mlx4_cmd_use_events(dev); 1398 1399 return err; 1400 } 1401 EXPORT_SYMBOL(mlx4_test_interrupt); 1402 1403 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector) 1404 { 1405 struct mlx4_priv *priv = mlx4_priv(dev); 1406 1407 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1408 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) || 1409 (vector == MLX4_EQ_ASYNC)) 1410 return false; 1411 1412 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports); 1413 } 1414 EXPORT_SYMBOL(mlx4_is_eq_vector_valid); 1415 1416 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port) 1417 { 1418 struct mlx4_priv *priv = mlx4_priv(dev); 1419 unsigned int i; 1420 unsigned int sum = 0; 1421 1422 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) 1423 sum += !!test_bit(port - 1, 1424 priv->eq_table.eq[i].actv_ports.ports); 1425 1426 return sum; 1427 } 1428 EXPORT_SYMBOL(mlx4_get_eqs_per_port); 1429 1430 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector) 1431 { 1432 struct mlx4_priv *priv = mlx4_priv(dev); 1433 1434 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1435 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1)) 1436 return -EINVAL; 1437 1438 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports, 1439 dev->caps.num_ports) > 1); 1440 } 1441 EXPORT_SYMBOL(mlx4_is_eq_shared); 1442 1443 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port) 1444 { 1445 return mlx4_priv(dev)->port[port].rmap; 1446 } 1447 EXPORT_SYMBOL(mlx4_get_cpu_rmap); 1448 1449 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector) 1450 { 1451 struct mlx4_priv *priv = mlx4_priv(dev); 1452 int err = 0, i = 0; 1453 u32 min_ref_count_val = (u32)-1; 1454 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector); 1455 int *prequested_vector = NULL; 1456 1457 1458 mutex_lock(&priv->msix_ctl.pool_lock); 1459 if (requested_vector < (dev->caps.num_comp_vectors + 1) && 1460 (requested_vector >= 0) && 1461 (requested_vector != MLX4_EQ_ASYNC)) { 1462 if (test_bit(port - 1, 1463 priv->eq_table.eq[requested_vector].actv_ports.ports)) { 1464 prequested_vector = &requested_vector; 1465 } else { 1466 struct mlx4_eq *eq; 1467 1468 for (i = 1; i < port; 1469 requested_vector += mlx4_get_eqs_per_port(dev, i++)) 1470 ; 1471 1472 eq = &priv->eq_table.eq[requested_vector]; 1473 if (requested_vector < dev->caps.num_comp_vectors + 1 && 1474 test_bit(port - 1, eq->actv_ports.ports)) { 1475 prequested_vector = &requested_vector; 1476 } 1477 } 1478 } 1479 1480 if (!prequested_vector) { 1481 requested_vector = -1; 1482 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1; 1483 i++) { 1484 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1485 1486 if (min_ref_count_val > eq->ref_count && 1487 test_bit(port - 1, eq->actv_ports.ports)) { 1488 min_ref_count_val = eq->ref_count; 1489 requested_vector = i; 1490 } 1491 } 1492 1493 if (requested_vector < 0) { 1494 err = -ENOSPC; 1495 goto err_unlock; 1496 } 1497 1498 prequested_vector = &requested_vector; 1499 } 1500 1501 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && 1502 dev->flags & MLX4_FLAG_MSI_X) { 1503 set_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1504 snprintf(priv->eq_table.irq_names + 1505 *prequested_vector * MLX4_IRQNAME_SIZE, 1506 MLX4_IRQNAME_SIZE, "mlx4-%d@%s", 1507 *prequested_vector, dev_name(&dev->persist->pdev->dev)); 1508 1509 err = request_irq(priv->eq_table.eq[*prequested_vector].irq, 1510 mlx4_msi_x_interrupt, 0, 1511 &priv->eq_table.irq_names[*prequested_vector << 5], 1512 priv->eq_table.eq + *prequested_vector); 1513 1514 if (err) { 1515 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1516 *prequested_vector = -1; 1517 } else { 1518 #if defined(CONFIG_SMP) 1519 mlx4_set_eq_affinity_hint(priv, *prequested_vector); 1520 #endif 1521 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); 1522 priv->eq_table.eq[*prequested_vector].have_irq = 1; 1523 } 1524 } 1525 1526 if (!err && *prequested_vector >= 0) 1527 priv->eq_table.eq[*prequested_vector].ref_count++; 1528 1529 err_unlock: 1530 mutex_unlock(&priv->msix_ctl.pool_lock); 1531 1532 if (!err && *prequested_vector >= 0) 1533 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector); 1534 else 1535 *vector = 0; 1536 1537 return err; 1538 } 1539 EXPORT_SYMBOL(mlx4_assign_eq); 1540 1541 int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec) 1542 { 1543 struct mlx4_priv *priv = mlx4_priv(dev); 1544 1545 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq; 1546 } 1547 EXPORT_SYMBOL(mlx4_eq_get_irq); 1548 1549 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1550 { 1551 struct mlx4_priv *priv = mlx4_priv(dev); 1552 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec); 1553 1554 mutex_lock(&priv->msix_ctl.pool_lock); 1555 priv->eq_table.eq[eq_vec].ref_count--; 1556 1557 /* once we allocated EQ, we don't release it because it might be binded 1558 * to cpu_rmap. 1559 */ 1560 mutex_unlock(&priv->msix_ctl.pool_lock); 1561 } 1562 EXPORT_SYMBOL(mlx4_release_eq); 1563 1564