1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/vmalloc.h> 41 #include <linux/tcp.h> 42 #include <linux/moduleparam.h> 43 44 #include "mlx4_en.h" 45 46 enum { 47 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 48 MAX_BF = 256, 49 }; 50 51 static int inline_thold __read_mostly = MAX_INLINE; 52 53 module_param_named(inline_thold, inline_thold, int, 0444); 54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); 55 56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 57 struct mlx4_en_tx_ring *ring, int qpn, u32 size, 58 u16 stride) 59 { 60 struct mlx4_en_dev *mdev = priv->mdev; 61 int tmp; 62 int err; 63 64 ring->size = size; 65 ring->size_mask = size - 1; 66 ring->stride = stride; 67 68 inline_thold = min(inline_thold, MAX_INLINE); 69 70 tmp = size * sizeof(struct mlx4_en_tx_info); 71 ring->tx_info = vmalloc(tmp); 72 if (!ring->tx_info) 73 return -ENOMEM; 74 75 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 76 ring->tx_info, tmp); 77 78 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 79 if (!ring->bounce_buf) { 80 err = -ENOMEM; 81 goto err_tx; 82 } 83 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 84 85 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 86 2 * PAGE_SIZE); 87 if (err) { 88 en_err(priv, "Failed allocating hwq resources\n"); 89 goto err_bounce; 90 } 91 92 err = mlx4_en_map_buffer(&ring->wqres.buf); 93 if (err) { 94 en_err(priv, "Failed to map TX buffer\n"); 95 goto err_hwq_res; 96 } 97 98 ring->buf = ring->wqres.buf.direct.buf; 99 100 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " 101 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, 102 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); 103 104 ring->qpn = qpn; 105 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); 106 if (err) { 107 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 108 goto err_map; 109 } 110 ring->qp.event = mlx4_en_sqp_event; 111 112 err = mlx4_bf_alloc(mdev->dev, &ring->bf); 113 if (err) { 114 en_dbg(DRV, priv, "working without blueflame (%d)", err); 115 ring->bf.uar = &mdev->priv_uar; 116 ring->bf.uar->map = mdev->uar_map; 117 ring->bf_enabled = false; 118 } else 119 ring->bf_enabled = true; 120 121 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 122 123 return 0; 124 125 err_map: 126 mlx4_en_unmap_buffer(&ring->wqres.buf); 127 err_hwq_res: 128 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 129 err_bounce: 130 kfree(ring->bounce_buf); 131 ring->bounce_buf = NULL; 132 err_tx: 133 vfree(ring->tx_info); 134 ring->tx_info = NULL; 135 return err; 136 } 137 138 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 139 struct mlx4_en_tx_ring *ring) 140 { 141 struct mlx4_en_dev *mdev = priv->mdev; 142 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 143 144 if (ring->bf_enabled) 145 mlx4_bf_free(mdev->dev, &ring->bf); 146 mlx4_qp_remove(mdev->dev, &ring->qp); 147 mlx4_qp_free(mdev->dev, &ring->qp); 148 mlx4_en_unmap_buffer(&ring->wqres.buf); 149 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 150 kfree(ring->bounce_buf); 151 ring->bounce_buf = NULL; 152 vfree(ring->tx_info); 153 ring->tx_info = NULL; 154 } 155 156 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 157 struct mlx4_en_tx_ring *ring, 158 int cq, int user_prio) 159 { 160 struct mlx4_en_dev *mdev = priv->mdev; 161 int err; 162 163 ring->cqn = cq; 164 ring->prod = 0; 165 ring->cons = 0xffffffff; 166 ring->last_nr_txbb = 1; 167 ring->poll_cnt = 0; 168 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 169 memset(ring->buf, 0, ring->buf_size); 170 171 ring->qp_state = MLX4_QP_STATE_RST; 172 ring->doorbell_qpn = ring->qp.qpn << 8; 173 174 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 175 ring->cqn, user_prio, &ring->context); 176 if (ring->bf_enabled) 177 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); 178 179 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 180 &ring->qp, &ring->qp_state); 181 182 return err; 183 } 184 185 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 186 struct mlx4_en_tx_ring *ring) 187 { 188 struct mlx4_en_dev *mdev = priv->mdev; 189 190 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 191 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 192 } 193 194 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 195 struct mlx4_en_tx_ring *ring, int index, 196 u8 owner) 197 { 198 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 199 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 200 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 201 void *end = ring->buf + ring->buf_size; 202 __be32 *ptr = (__be32 *)tx_desc; 203 int i; 204 205 /* Optimize the common case when there are no wraparounds */ 206 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 207 /* Stamp the freed descriptor */ 208 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 209 i += STAMP_STRIDE) { 210 *ptr = stamp; 211 ptr += STAMP_DWORDS; 212 } 213 } else { 214 /* Stamp the freed descriptor */ 215 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 216 i += STAMP_STRIDE) { 217 *ptr = stamp; 218 ptr += STAMP_DWORDS; 219 if ((void *)ptr >= end) { 220 ptr = ring->buf; 221 stamp ^= cpu_to_be32(0x80000000); 222 } 223 } 224 } 225 } 226 227 228 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 229 struct mlx4_en_tx_ring *ring, 230 int index, u8 owner, u64 timestamp) 231 { 232 struct mlx4_en_dev *mdev = priv->mdev; 233 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 234 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 235 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 236 struct sk_buff *skb = tx_info->skb; 237 struct skb_frag_struct *frag; 238 void *end = ring->buf + ring->buf_size; 239 int frags = skb_shinfo(skb)->nr_frags; 240 int i; 241 struct skb_shared_hwtstamps hwts; 242 243 if (timestamp) { 244 mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp); 245 skb_tstamp_tx(skb, &hwts); 246 } 247 248 /* Optimize the common case when there are no wraparounds */ 249 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 250 if (!tx_info->inl) { 251 if (tx_info->linear) { 252 dma_unmap_single(priv->ddev, 253 (dma_addr_t) be64_to_cpu(data->addr), 254 be32_to_cpu(data->byte_count), 255 PCI_DMA_TODEVICE); 256 ++data; 257 } 258 259 for (i = 0; i < frags; i++) { 260 frag = &skb_shinfo(skb)->frags[i]; 261 dma_unmap_page(priv->ddev, 262 (dma_addr_t) be64_to_cpu(data[i].addr), 263 skb_frag_size(frag), PCI_DMA_TODEVICE); 264 } 265 } 266 } else { 267 if (!tx_info->inl) { 268 if ((void *) data >= end) { 269 data = ring->buf + ((void *)data - end); 270 } 271 272 if (tx_info->linear) { 273 dma_unmap_single(priv->ddev, 274 (dma_addr_t) be64_to_cpu(data->addr), 275 be32_to_cpu(data->byte_count), 276 PCI_DMA_TODEVICE); 277 ++data; 278 } 279 280 for (i = 0; i < frags; i++) { 281 /* Check for wraparound before unmapping */ 282 if ((void *) data >= end) 283 data = ring->buf; 284 frag = &skb_shinfo(skb)->frags[i]; 285 dma_unmap_page(priv->ddev, 286 (dma_addr_t) be64_to_cpu(data->addr), 287 skb_frag_size(frag), PCI_DMA_TODEVICE); 288 ++data; 289 } 290 } 291 } 292 dev_kfree_skb_any(skb); 293 return tx_info->nr_txbb; 294 } 295 296 297 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 298 { 299 struct mlx4_en_priv *priv = netdev_priv(dev); 300 int cnt = 0; 301 302 /* Skip last polled descriptor */ 303 ring->cons += ring->last_nr_txbb; 304 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 305 ring->cons, ring->prod); 306 307 if ((u32) (ring->prod - ring->cons) > ring->size) { 308 if (netif_msg_tx_err(priv)) 309 en_warn(priv, "Tx consumer passed producer!\n"); 310 return 0; 311 } 312 313 while (ring->cons != ring->prod) { 314 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 315 ring->cons & ring->size_mask, 316 !!(ring->cons & ring->size), 0); 317 ring->cons += ring->last_nr_txbb; 318 cnt++; 319 } 320 321 netdev_tx_reset_queue(ring->tx_queue); 322 323 if (cnt) 324 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 325 326 return cnt; 327 } 328 329 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) 330 { 331 struct mlx4_en_priv *priv = netdev_priv(dev); 332 struct mlx4_cq *mcq = &cq->mcq; 333 struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; 334 struct mlx4_cqe *cqe; 335 u16 index; 336 u16 new_index, ring_index, stamp_index; 337 u32 txbbs_skipped = 0; 338 u32 txbbs_stamp = 0; 339 u32 cons_index = mcq->cons_index; 340 int size = cq->size; 341 u32 size_mask = ring->size_mask; 342 struct mlx4_cqe *buf = cq->buf; 343 u32 packets = 0; 344 u32 bytes = 0; 345 int factor = priv->cqe_factor; 346 u64 timestamp = 0; 347 348 if (!priv->port_up) 349 return; 350 351 index = cons_index & size_mask; 352 cqe = &buf[(index << factor) + factor]; 353 ring_index = ring->cons & size_mask; 354 stamp_index = ring_index; 355 356 /* Process all completed CQEs */ 357 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 358 cons_index & size)) { 359 /* 360 * make sure we read the CQE after we read the 361 * ownership bit 362 */ 363 rmb(); 364 365 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 366 MLX4_CQE_OPCODE_ERROR)) { 367 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 368 369 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 370 cqe_err->vendor_err_syndrome, 371 cqe_err->syndrome); 372 } 373 374 /* Skip over last polled CQE */ 375 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 376 377 do { 378 txbbs_skipped += ring->last_nr_txbb; 379 ring_index = (ring_index + ring->last_nr_txbb) & size_mask; 380 if (ring->tx_info[ring_index].ts_requested) 381 timestamp = mlx4_en_get_cqe_ts(cqe); 382 383 /* free next descriptor */ 384 ring->last_nr_txbb = mlx4_en_free_tx_desc( 385 priv, ring, ring_index, 386 !!((ring->cons + txbbs_skipped) & 387 ring->size), timestamp); 388 389 mlx4_en_stamp_wqe(priv, ring, stamp_index, 390 !!((ring->cons + txbbs_stamp) & 391 ring->size)); 392 stamp_index = ring_index; 393 txbbs_stamp = txbbs_skipped; 394 packets++; 395 bytes += ring->tx_info[ring_index].nr_bytes; 396 } while (ring_index != new_index); 397 398 ++cons_index; 399 index = cons_index & size_mask; 400 cqe = &buf[(index << factor) + factor]; 401 } 402 403 404 /* 405 * To prevent CQ overflow we first update CQ consumer and only then 406 * the ring consumer. 407 */ 408 mcq->cons_index = cons_index; 409 mlx4_cq_set_ci(mcq); 410 wmb(); 411 ring->cons += txbbs_skipped; 412 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 413 414 /* 415 * Wakeup Tx queue if this stopped, and at least 1 packet 416 * was completed 417 */ 418 if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { 419 netif_tx_wake_queue(ring->tx_queue); 420 priv->port_stats.wake_queue++; 421 } 422 } 423 424 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 425 { 426 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 427 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 428 429 mlx4_en_process_tx_cq(cq->dev, cq); 430 mlx4_en_arm_cq(priv, cq); 431 } 432 433 434 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 435 struct mlx4_en_tx_ring *ring, 436 u32 index, 437 unsigned int desc_size) 438 { 439 u32 copy = (ring->size - index) * TXBB_SIZE; 440 int i; 441 442 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 443 if ((i & (TXBB_SIZE - 1)) == 0) 444 wmb(); 445 446 *((u32 *) (ring->buf + i)) = 447 *((u32 *) (ring->bounce_buf + copy + i)); 448 } 449 450 for (i = copy - 4; i >= 4 ; i -= 4) { 451 if ((i & (TXBB_SIZE - 1)) == 0) 452 wmb(); 453 454 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 455 *((u32 *) (ring->bounce_buf + i)); 456 } 457 458 /* Return real descriptor location */ 459 return ring->buf + index * TXBB_SIZE; 460 } 461 462 static int is_inline(struct sk_buff *skb, void **pfrag) 463 { 464 void *ptr; 465 466 if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { 467 if (skb_shinfo(skb)->nr_frags == 1) { 468 ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); 469 if (unlikely(!ptr)) 470 return 0; 471 472 if (pfrag) 473 *pfrag = ptr; 474 475 return 1; 476 } else if (unlikely(skb_shinfo(skb)->nr_frags)) 477 return 0; 478 else 479 return 1; 480 } 481 482 return 0; 483 } 484 485 static int inline_size(struct sk_buff *skb) 486 { 487 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 488 <= MLX4_INLINE_ALIGN) 489 return ALIGN(skb->len + CTRL_SIZE + 490 sizeof(struct mlx4_wqe_inline_seg), 16); 491 else 492 return ALIGN(skb->len + CTRL_SIZE + 2 * 493 sizeof(struct mlx4_wqe_inline_seg), 16); 494 } 495 496 static int get_real_size(struct sk_buff *skb, struct net_device *dev, 497 int *lso_header_size) 498 { 499 struct mlx4_en_priv *priv = netdev_priv(dev); 500 int real_size; 501 502 if (skb_is_gso(skb)) { 503 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 504 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + 505 ALIGN(*lso_header_size + 4, DS_SIZE); 506 if (unlikely(*lso_header_size != skb_headlen(skb))) { 507 /* We add a segment for the skb linear buffer only if 508 * it contains data */ 509 if (*lso_header_size < skb_headlen(skb)) 510 real_size += DS_SIZE; 511 else { 512 if (netif_msg_tx_err(priv)) 513 en_warn(priv, "Non-linear headers\n"); 514 return 0; 515 } 516 } 517 } else { 518 *lso_header_size = 0; 519 if (!is_inline(skb, NULL)) 520 real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; 521 else 522 real_size = inline_size(skb); 523 } 524 525 return real_size; 526 } 527 528 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, 529 int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) 530 { 531 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 532 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 533 534 if (skb->len <= spc) { 535 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 536 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 537 if (skb_shinfo(skb)->nr_frags) 538 memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, 539 skb_frag_size(&skb_shinfo(skb)->frags[0])); 540 541 } else { 542 inl->byte_count = cpu_to_be32(1 << 31 | spc); 543 if (skb_headlen(skb) <= spc) { 544 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 545 if (skb_headlen(skb) < spc) { 546 memcpy(((void *)(inl + 1)) + skb_headlen(skb), 547 fragptr, spc - skb_headlen(skb)); 548 fragptr += spc - skb_headlen(skb); 549 } 550 inl = (void *) (inl + 1) + spc; 551 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 552 } else { 553 skb_copy_from_linear_data(skb, inl + 1, spc); 554 inl = (void *) (inl + 1) + spc; 555 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 556 skb_headlen(skb) - spc); 557 if (skb_shinfo(skb)->nr_frags) 558 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, 559 fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); 560 } 561 562 wmb(); 563 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 564 } 565 } 566 567 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) 568 { 569 struct mlx4_en_priv *priv = netdev_priv(dev); 570 u16 rings_p_up = priv->num_tx_rings_p_up; 571 u8 up = 0; 572 573 if (dev->num_tc) 574 return skb_tx_hash(dev, skb); 575 576 if (vlan_tx_tag_present(skb)) 577 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; 578 579 return __netdev_pick_tx(dev, skb) % rings_p_up + up * rings_p_up; 580 } 581 582 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt) 583 { 584 __iowrite64_copy(dst, src, bytecnt / 8); 585 } 586 587 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 588 { 589 struct mlx4_en_priv *priv = netdev_priv(dev); 590 struct mlx4_en_dev *mdev = priv->mdev; 591 struct device *ddev = priv->ddev; 592 struct mlx4_en_tx_ring *ring; 593 struct mlx4_en_tx_desc *tx_desc; 594 struct mlx4_wqe_data_seg *data; 595 struct mlx4_en_tx_info *tx_info; 596 int tx_ind = 0; 597 int nr_txbb; 598 int desc_size; 599 int real_size; 600 u32 index, bf_index; 601 __be32 op_own; 602 u16 vlan_tag = 0; 603 int i; 604 int lso_header_size; 605 void *fragptr; 606 bool bounce = false; 607 608 if (!priv->port_up) 609 goto tx_drop; 610 611 real_size = get_real_size(skb, dev, &lso_header_size); 612 if (unlikely(!real_size)) 613 goto tx_drop; 614 615 /* Align descriptor to TXBB size */ 616 desc_size = ALIGN(real_size, TXBB_SIZE); 617 nr_txbb = desc_size / TXBB_SIZE; 618 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 619 if (netif_msg_tx_err(priv)) 620 en_warn(priv, "Oversized header or SG list\n"); 621 goto tx_drop; 622 } 623 624 tx_ind = skb->queue_mapping; 625 ring = &priv->tx_ring[tx_ind]; 626 if (vlan_tx_tag_present(skb)) 627 vlan_tag = vlan_tx_tag_get(skb); 628 629 /* Check available TXBBs And 2K spare for prefetch */ 630 if (unlikely(((int)(ring->prod - ring->cons)) > 631 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 632 /* every full Tx ring stops queue */ 633 netif_tx_stop_queue(ring->tx_queue); 634 priv->port_stats.queue_stopped++; 635 636 /* If queue was emptied after the if, and before the 637 * stop_queue - need to wake the queue, or else it will remain 638 * stopped forever. 639 * Need a memory barrier to make sure ring->cons was not 640 * updated before queue was stopped. 641 */ 642 wmb(); 643 644 if (unlikely(((int)(ring->prod - ring->cons)) <= 645 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 646 netif_tx_wake_queue(ring->tx_queue); 647 priv->port_stats.wake_queue++; 648 } else { 649 return NETDEV_TX_BUSY; 650 } 651 } 652 653 /* Track current inflight packets for performance analysis */ 654 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 655 (u32) (ring->prod - ring->cons - 1)); 656 657 /* Packet is good - grab an index and transmit it */ 658 index = ring->prod & ring->size_mask; 659 bf_index = ring->prod; 660 661 /* See if we have enough space for whole descriptor TXBB for setting 662 * SW ownership on next descriptor; if not, use a bounce buffer. */ 663 if (likely(index + nr_txbb <= ring->size)) 664 tx_desc = ring->buf + index * TXBB_SIZE; 665 else { 666 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 667 bounce = true; 668 } 669 670 /* Save skb in tx_info ring */ 671 tx_info = &ring->tx_info[index]; 672 tx_info->skb = skb; 673 tx_info->nr_txbb = nr_txbb; 674 675 if (lso_header_size) 676 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 677 DS_SIZE)); 678 else 679 data = &tx_desc->data; 680 681 /* valid only for none inline segments */ 682 tx_info->data_offset = (void *)data - (void *)tx_desc; 683 684 tx_info->linear = (lso_header_size < skb_headlen(skb) && 685 !is_inline(skb, NULL)) ? 1 : 0; 686 687 data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; 688 689 if (is_inline(skb, &fragptr)) { 690 tx_info->inl = 1; 691 } else { 692 /* Map fragments */ 693 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { 694 struct skb_frag_struct *frag; 695 dma_addr_t dma; 696 697 frag = &skb_shinfo(skb)->frags[i]; 698 dma = skb_frag_dma_map(ddev, frag, 699 0, skb_frag_size(frag), 700 DMA_TO_DEVICE); 701 if (dma_mapping_error(ddev, dma)) 702 goto tx_drop_unmap; 703 704 data->addr = cpu_to_be64(dma); 705 data->lkey = cpu_to_be32(mdev->mr.key); 706 wmb(); 707 data->byte_count = cpu_to_be32(skb_frag_size(frag)); 708 --data; 709 } 710 711 /* Map linear part */ 712 if (tx_info->linear) { 713 u32 byte_count = skb_headlen(skb) - lso_header_size; 714 dma_addr_t dma; 715 716 dma = dma_map_single(ddev, skb->data + 717 lso_header_size, byte_count, 718 PCI_DMA_TODEVICE); 719 if (dma_mapping_error(ddev, dma)) 720 goto tx_drop_unmap; 721 722 data->addr = cpu_to_be64(dma); 723 data->lkey = cpu_to_be32(mdev->mr.key); 724 wmb(); 725 data->byte_count = cpu_to_be32(byte_count); 726 } 727 tx_info->inl = 0; 728 } 729 730 /* 731 * For timestamping add flag to skb_shinfo and 732 * set flag for further reference 733 */ 734 if (ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 735 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 736 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 737 tx_info->ts_requested = 1; 738 } 739 740 /* Prepare ctrl segement apart opcode+ownership, which depends on 741 * whether LSO is used */ 742 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); 743 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * 744 !!vlan_tx_tag_present(skb); 745 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; 746 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 747 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 748 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 749 MLX4_WQE_CTRL_TCP_UDP_CSUM); 750 ring->tx_csum++; 751 } 752 753 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 754 struct ethhdr *ethh; 755 756 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 757 * so that VFs and PF can communicate with each other 758 */ 759 ethh = (struct ethhdr *)skb->data; 760 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 761 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 762 } 763 764 /* Handle LSO (TSO) packets */ 765 if (lso_header_size) { 766 /* Mark opcode as LSO */ 767 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 768 ((ring->prod & ring->size) ? 769 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 770 771 /* Fill in the LSO prefix */ 772 tx_desc->lso.mss_hdr_size = cpu_to_be32( 773 skb_shinfo(skb)->gso_size << 16 | lso_header_size); 774 775 /* Copy headers; 776 * note that we already verified that it is linear */ 777 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 778 779 priv->port_stats.tso_packets++; 780 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + 781 !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); 782 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 783 ring->packets += i; 784 } else { 785 /* Normal (Non LSO) packet */ 786 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 787 ((ring->prod & ring->size) ? 788 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 789 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 790 ring->packets++; 791 792 } 793 ring->bytes += tx_info->nr_bytes; 794 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 795 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 796 797 if (tx_info->inl) { 798 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); 799 tx_info->inl = 1; 800 } 801 802 ring->prod += nr_txbb; 803 804 /* If we used a bounce buffer then copy descriptor back into place */ 805 if (bounce) 806 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 807 808 skb_tx_timestamp(skb); 809 810 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) { 811 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn); 812 op_own |= htonl((bf_index & 0xffff) << 8); 813 /* Ensure new descirptor hits memory 814 * before setting ownership of this descriptor to HW */ 815 wmb(); 816 tx_desc->ctrl.owner_opcode = op_own; 817 818 wmb(); 819 820 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, 821 desc_size); 822 823 wmb(); 824 825 ring->bf.offset ^= ring->bf.buf_size; 826 } else { 827 /* Ensure new descirptor hits memory 828 * before setting ownership of this descriptor to HW */ 829 wmb(); 830 tx_desc->ctrl.owner_opcode = op_own; 831 wmb(); 832 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); 833 } 834 835 return NETDEV_TX_OK; 836 837 tx_drop_unmap: 838 en_err(priv, "DMA mapping error\n"); 839 840 for (i++; i < skb_shinfo(skb)->nr_frags; i++) { 841 data++; 842 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 843 be32_to_cpu(data->byte_count), 844 PCI_DMA_TODEVICE); 845 } 846 847 tx_drop: 848 dev_kfree_skb_any(skb); 849 priv->stats.tx_dropped++; 850 return NETDEV_TX_OK; 851 } 852 853