1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/vmalloc.h> 41 #include <linux/tcp.h> 42 #include <linux/ip.h> 43 #include <linux/moduleparam.h> 44 45 #include "mlx4_en.h" 46 47 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 48 struct mlx4_en_tx_ring **pring, int qpn, u32 size, 49 u16 stride, int node, int queue_index) 50 { 51 struct mlx4_en_dev *mdev = priv->mdev; 52 struct mlx4_en_tx_ring *ring; 53 int tmp; 54 int err; 55 56 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 57 if (!ring) { 58 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 59 if (!ring) { 60 en_err(priv, "Failed allocating TX ring\n"); 61 return -ENOMEM; 62 } 63 } 64 65 ring->size = size; 66 ring->size_mask = size - 1; 67 ring->stride = stride; 68 ring->inline_thold = priv->prof->inline_thold; 69 70 tmp = size * sizeof(struct mlx4_en_tx_info); 71 ring->tx_info = vmalloc_node(tmp, node); 72 if (!ring->tx_info) { 73 ring->tx_info = vmalloc(tmp); 74 if (!ring->tx_info) { 75 err = -ENOMEM; 76 goto err_ring; 77 } 78 } 79 80 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 81 ring->tx_info, tmp); 82 83 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 84 if (!ring->bounce_buf) { 85 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 86 if (!ring->bounce_buf) { 87 err = -ENOMEM; 88 goto err_info; 89 } 90 } 91 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 92 93 /* Allocate HW buffers on provided NUMA node */ 94 set_dev_node(&mdev->dev->pdev->dev, node); 95 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 96 2 * PAGE_SIZE); 97 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 98 if (err) { 99 en_err(priv, "Failed allocating hwq resources\n"); 100 goto err_bounce; 101 } 102 103 err = mlx4_en_map_buffer(&ring->wqres.buf); 104 if (err) { 105 en_err(priv, "Failed to map TX buffer\n"); 106 goto err_hwq_res; 107 } 108 109 ring->buf = ring->wqres.buf.direct.buf; 110 111 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 112 ring, ring->buf, ring->size, ring->buf_size, 113 (unsigned long long) ring->wqres.buf.direct.map); 114 115 ring->qpn = qpn; 116 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); 117 if (err) { 118 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 119 goto err_map; 120 } 121 ring->qp.event = mlx4_en_sqp_event; 122 123 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 124 if (err) { 125 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 126 ring->bf.uar = &mdev->priv_uar; 127 ring->bf.uar->map = mdev->uar_map; 128 ring->bf_enabled = false; 129 } else 130 ring->bf_enabled = true; 131 132 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 133 ring->queue_index = queue_index; 134 135 if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) 136 cpumask_set_cpu(queue_index, &ring->affinity_mask); 137 138 *pring = ring; 139 return 0; 140 141 err_map: 142 mlx4_en_unmap_buffer(&ring->wqres.buf); 143 err_hwq_res: 144 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 145 err_bounce: 146 kfree(ring->bounce_buf); 147 ring->bounce_buf = NULL; 148 err_info: 149 vfree(ring->tx_info); 150 ring->tx_info = NULL; 151 err_ring: 152 kfree(ring); 153 *pring = NULL; 154 return err; 155 } 156 157 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 158 struct mlx4_en_tx_ring **pring) 159 { 160 struct mlx4_en_dev *mdev = priv->mdev; 161 struct mlx4_en_tx_ring *ring = *pring; 162 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 163 164 if (ring->bf_enabled) 165 mlx4_bf_free(mdev->dev, &ring->bf); 166 mlx4_qp_remove(mdev->dev, &ring->qp); 167 mlx4_qp_free(mdev->dev, &ring->qp); 168 mlx4_en_unmap_buffer(&ring->wqres.buf); 169 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 170 kfree(ring->bounce_buf); 171 ring->bounce_buf = NULL; 172 vfree(ring->tx_info); 173 ring->tx_info = NULL; 174 kfree(ring); 175 *pring = NULL; 176 } 177 178 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 179 struct mlx4_en_tx_ring *ring, 180 int cq, int user_prio) 181 { 182 struct mlx4_en_dev *mdev = priv->mdev; 183 int err; 184 185 ring->cqn = cq; 186 ring->prod = 0; 187 ring->cons = 0xffffffff; 188 ring->last_nr_txbb = 1; 189 ring->poll_cnt = 0; 190 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 191 memset(ring->buf, 0, ring->buf_size); 192 193 ring->qp_state = MLX4_QP_STATE_RST; 194 ring->doorbell_qpn = ring->qp.qpn << 8; 195 196 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 197 ring->cqn, user_prio, &ring->context); 198 if (ring->bf_enabled) 199 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); 200 201 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 202 &ring->qp, &ring->qp_state); 203 if (!user_prio && cpu_online(ring->queue_index)) 204 netif_set_xps_queue(priv->dev, &ring->affinity_mask, 205 ring->queue_index); 206 207 return err; 208 } 209 210 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 211 struct mlx4_en_tx_ring *ring) 212 { 213 struct mlx4_en_dev *mdev = priv->mdev; 214 215 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 216 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 217 } 218 219 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 220 struct mlx4_en_tx_ring *ring, int index, 221 u8 owner) 222 { 223 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 224 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 225 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 226 void *end = ring->buf + ring->buf_size; 227 __be32 *ptr = (__be32 *)tx_desc; 228 int i; 229 230 /* Optimize the common case when there are no wraparounds */ 231 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 232 /* Stamp the freed descriptor */ 233 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 234 i += STAMP_STRIDE) { 235 *ptr = stamp; 236 ptr += STAMP_DWORDS; 237 } 238 } else { 239 /* Stamp the freed descriptor */ 240 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 241 i += STAMP_STRIDE) { 242 *ptr = stamp; 243 ptr += STAMP_DWORDS; 244 if ((void *)ptr >= end) { 245 ptr = ring->buf; 246 stamp ^= cpu_to_be32(0x80000000); 247 } 248 } 249 } 250 } 251 252 253 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 254 struct mlx4_en_tx_ring *ring, 255 int index, u8 owner, u64 timestamp) 256 { 257 struct mlx4_en_dev *mdev = priv->mdev; 258 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 259 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 260 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 261 struct sk_buff *skb = tx_info->skb; 262 struct skb_frag_struct *frag; 263 void *end = ring->buf + ring->buf_size; 264 int frags = skb_shinfo(skb)->nr_frags; 265 int i; 266 struct skb_shared_hwtstamps hwts; 267 268 if (timestamp) { 269 mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp); 270 skb_tstamp_tx(skb, &hwts); 271 } 272 273 /* Optimize the common case when there are no wraparounds */ 274 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 275 if (!tx_info->inl) { 276 if (tx_info->linear) { 277 dma_unmap_single(priv->ddev, 278 (dma_addr_t) be64_to_cpu(data->addr), 279 be32_to_cpu(data->byte_count), 280 PCI_DMA_TODEVICE); 281 ++data; 282 } 283 284 for (i = 0; i < frags; i++) { 285 frag = &skb_shinfo(skb)->frags[i]; 286 dma_unmap_page(priv->ddev, 287 (dma_addr_t) be64_to_cpu(data[i].addr), 288 skb_frag_size(frag), PCI_DMA_TODEVICE); 289 } 290 } 291 } else { 292 if (!tx_info->inl) { 293 if ((void *) data >= end) { 294 data = ring->buf + ((void *)data - end); 295 } 296 297 if (tx_info->linear) { 298 dma_unmap_single(priv->ddev, 299 (dma_addr_t) be64_to_cpu(data->addr), 300 be32_to_cpu(data->byte_count), 301 PCI_DMA_TODEVICE); 302 ++data; 303 } 304 305 for (i = 0; i < frags; i++) { 306 /* Check for wraparound before unmapping */ 307 if ((void *) data >= end) 308 data = ring->buf; 309 frag = &skb_shinfo(skb)->frags[i]; 310 dma_unmap_page(priv->ddev, 311 (dma_addr_t) be64_to_cpu(data->addr), 312 skb_frag_size(frag), PCI_DMA_TODEVICE); 313 ++data; 314 } 315 } 316 } 317 dev_kfree_skb_any(skb); 318 return tx_info->nr_txbb; 319 } 320 321 322 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 323 { 324 struct mlx4_en_priv *priv = netdev_priv(dev); 325 int cnt = 0; 326 327 /* Skip last polled descriptor */ 328 ring->cons += ring->last_nr_txbb; 329 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 330 ring->cons, ring->prod); 331 332 if ((u32) (ring->prod - ring->cons) > ring->size) { 333 if (netif_msg_tx_err(priv)) 334 en_warn(priv, "Tx consumer passed producer!\n"); 335 return 0; 336 } 337 338 while (ring->cons != ring->prod) { 339 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 340 ring->cons & ring->size_mask, 341 !!(ring->cons & ring->size), 0); 342 ring->cons += ring->last_nr_txbb; 343 cnt++; 344 } 345 346 netdev_tx_reset_queue(ring->tx_queue); 347 348 if (cnt) 349 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 350 351 return cnt; 352 } 353 354 static int mlx4_en_process_tx_cq(struct net_device *dev, 355 struct mlx4_en_cq *cq, 356 int budget) 357 { 358 struct mlx4_en_priv *priv = netdev_priv(dev); 359 struct mlx4_cq *mcq = &cq->mcq; 360 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 361 struct mlx4_cqe *cqe; 362 u16 index; 363 u16 new_index, ring_index, stamp_index; 364 u32 txbbs_skipped = 0; 365 u32 txbbs_stamp = 0; 366 u32 cons_index = mcq->cons_index; 367 int size = cq->size; 368 u32 size_mask = ring->size_mask; 369 struct mlx4_cqe *buf = cq->buf; 370 u32 packets = 0; 371 u32 bytes = 0; 372 int factor = priv->cqe_factor; 373 u64 timestamp = 0; 374 int done = 0; 375 376 if (!priv->port_up) 377 return 0; 378 379 index = cons_index & size_mask; 380 cqe = &buf[(index << factor) + factor]; 381 ring_index = ring->cons & size_mask; 382 stamp_index = ring_index; 383 384 /* Process all completed CQEs */ 385 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 386 cons_index & size) && (done < budget)) { 387 /* 388 * make sure we read the CQE after we read the 389 * ownership bit 390 */ 391 rmb(); 392 393 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 394 MLX4_CQE_OPCODE_ERROR)) { 395 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 396 397 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 398 cqe_err->vendor_err_syndrome, 399 cqe_err->syndrome); 400 } 401 402 /* Skip over last polled CQE */ 403 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 404 405 do { 406 txbbs_skipped += ring->last_nr_txbb; 407 ring_index = (ring_index + ring->last_nr_txbb) & size_mask; 408 if (ring->tx_info[ring_index].ts_requested) 409 timestamp = mlx4_en_get_cqe_ts(cqe); 410 411 /* free next descriptor */ 412 ring->last_nr_txbb = mlx4_en_free_tx_desc( 413 priv, ring, ring_index, 414 !!((ring->cons + txbbs_skipped) & 415 ring->size), timestamp); 416 417 mlx4_en_stamp_wqe(priv, ring, stamp_index, 418 !!((ring->cons + txbbs_stamp) & 419 ring->size)); 420 stamp_index = ring_index; 421 txbbs_stamp = txbbs_skipped; 422 packets++; 423 bytes += ring->tx_info[ring_index].nr_bytes; 424 } while ((++done < budget) && (ring_index != new_index)); 425 426 ++cons_index; 427 index = cons_index & size_mask; 428 cqe = &buf[(index << factor) + factor]; 429 } 430 431 432 /* 433 * To prevent CQ overflow we first update CQ consumer and only then 434 * the ring consumer. 435 */ 436 mcq->cons_index = cons_index; 437 mlx4_cq_set_ci(mcq); 438 wmb(); 439 ring->cons += txbbs_skipped; 440 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 441 442 /* 443 * Wakeup Tx queue if this stopped, and at least 1 packet 444 * was completed 445 */ 446 if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { 447 netif_tx_wake_queue(ring->tx_queue); 448 ring->wake_queue++; 449 } 450 return done; 451 } 452 453 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 454 { 455 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 456 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 457 458 if (priv->port_up) 459 napi_schedule(&cq->napi); 460 else 461 mlx4_en_arm_cq(priv, cq); 462 } 463 464 /* TX CQ polling - called by NAPI */ 465 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 466 { 467 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 468 struct net_device *dev = cq->dev; 469 struct mlx4_en_priv *priv = netdev_priv(dev); 470 int done; 471 472 done = mlx4_en_process_tx_cq(dev, cq, budget); 473 474 /* If we used up all the quota - we're probably not done yet... */ 475 if (done < budget) { 476 /* Done for now */ 477 cq->mcq.irq_affinity_change = false; 478 napi_complete(napi); 479 mlx4_en_arm_cq(priv, cq); 480 return done; 481 } else if (unlikely(cq->mcq.irq_affinity_change)) { 482 cq->mcq.irq_affinity_change = false; 483 napi_complete(napi); 484 mlx4_en_arm_cq(priv, cq); 485 return 0; 486 } 487 return budget; 488 } 489 490 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 491 struct mlx4_en_tx_ring *ring, 492 u32 index, 493 unsigned int desc_size) 494 { 495 u32 copy = (ring->size - index) * TXBB_SIZE; 496 int i; 497 498 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 499 if ((i & (TXBB_SIZE - 1)) == 0) 500 wmb(); 501 502 *((u32 *) (ring->buf + i)) = 503 *((u32 *) (ring->bounce_buf + copy + i)); 504 } 505 506 for (i = copy - 4; i >= 4 ; i -= 4) { 507 if ((i & (TXBB_SIZE - 1)) == 0) 508 wmb(); 509 510 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 511 *((u32 *) (ring->bounce_buf + i)); 512 } 513 514 /* Return real descriptor location */ 515 return ring->buf + index * TXBB_SIZE; 516 } 517 518 static int is_inline(int inline_thold, struct sk_buff *skb, void **pfrag) 519 { 520 void *ptr; 521 522 if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { 523 if (skb_shinfo(skb)->nr_frags == 1) { 524 ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); 525 if (unlikely(!ptr)) 526 return 0; 527 528 if (pfrag) 529 *pfrag = ptr; 530 531 return 1; 532 } else if (unlikely(skb_shinfo(skb)->nr_frags)) 533 return 0; 534 else 535 return 1; 536 } 537 538 return 0; 539 } 540 541 static int inline_size(struct sk_buff *skb) 542 { 543 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 544 <= MLX4_INLINE_ALIGN) 545 return ALIGN(skb->len + CTRL_SIZE + 546 sizeof(struct mlx4_wqe_inline_seg), 16); 547 else 548 return ALIGN(skb->len + CTRL_SIZE + 2 * 549 sizeof(struct mlx4_wqe_inline_seg), 16); 550 } 551 552 static int get_real_size(struct sk_buff *skb, struct net_device *dev, 553 int *lso_header_size) 554 { 555 struct mlx4_en_priv *priv = netdev_priv(dev); 556 int real_size; 557 558 if (skb_is_gso(skb)) { 559 if (skb->encapsulation) 560 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 561 else 562 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 563 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + 564 ALIGN(*lso_header_size + 4, DS_SIZE); 565 if (unlikely(*lso_header_size != skb_headlen(skb))) { 566 /* We add a segment for the skb linear buffer only if 567 * it contains data */ 568 if (*lso_header_size < skb_headlen(skb)) 569 real_size += DS_SIZE; 570 else { 571 if (netif_msg_tx_err(priv)) 572 en_warn(priv, "Non-linear headers\n"); 573 return 0; 574 } 575 } 576 } else { 577 *lso_header_size = 0; 578 if (!is_inline(priv->prof->inline_thold, skb, NULL)) 579 real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; 580 else 581 real_size = inline_size(skb); 582 } 583 584 return real_size; 585 } 586 587 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, 588 int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) 589 { 590 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 591 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 592 593 if (skb->len <= spc) { 594 if (likely(skb->len >= MIN_PKT_LEN)) { 595 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 596 } else { 597 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 598 memset(((void *)(inl + 1)) + skb->len, 0, 599 MIN_PKT_LEN - skb->len); 600 } 601 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 602 if (skb_shinfo(skb)->nr_frags) 603 memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, 604 skb_frag_size(&skb_shinfo(skb)->frags[0])); 605 606 } else { 607 inl->byte_count = cpu_to_be32(1 << 31 | spc); 608 if (skb_headlen(skb) <= spc) { 609 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 610 if (skb_headlen(skb) < spc) { 611 memcpy(((void *)(inl + 1)) + skb_headlen(skb), 612 fragptr, spc - skb_headlen(skb)); 613 fragptr += spc - skb_headlen(skb); 614 } 615 inl = (void *) (inl + 1) + spc; 616 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 617 } else { 618 skb_copy_from_linear_data(skb, inl + 1, spc); 619 inl = (void *) (inl + 1) + spc; 620 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 621 skb_headlen(skb) - spc); 622 if (skb_shinfo(skb)->nr_frags) 623 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, 624 fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); 625 } 626 627 wmb(); 628 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 629 } 630 } 631 632 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 633 void *accel_priv, select_queue_fallback_t fallback) 634 { 635 struct mlx4_en_priv *priv = netdev_priv(dev); 636 u16 rings_p_up = priv->num_tx_rings_p_up; 637 u8 up = 0; 638 639 if (dev->num_tc) 640 return skb_tx_hash(dev, skb); 641 642 if (vlan_tx_tag_present(skb)) 643 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; 644 645 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 646 } 647 648 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt) 649 { 650 __iowrite64_copy(dst, src, bytecnt / 8); 651 } 652 653 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 654 { 655 struct mlx4_en_priv *priv = netdev_priv(dev); 656 struct mlx4_en_dev *mdev = priv->mdev; 657 struct device *ddev = priv->ddev; 658 struct mlx4_en_tx_ring *ring; 659 struct mlx4_en_tx_desc *tx_desc; 660 struct mlx4_wqe_data_seg *data; 661 struct mlx4_en_tx_info *tx_info; 662 int tx_ind = 0; 663 int nr_txbb; 664 int desc_size; 665 int real_size; 666 u32 index, bf_index; 667 __be32 op_own; 668 u16 vlan_tag = 0; 669 int i; 670 int lso_header_size; 671 void *fragptr; 672 bool bounce = false; 673 674 if (!priv->port_up) 675 goto tx_drop; 676 677 real_size = get_real_size(skb, dev, &lso_header_size); 678 if (unlikely(!real_size)) 679 goto tx_drop; 680 681 /* Align descriptor to TXBB size */ 682 desc_size = ALIGN(real_size, TXBB_SIZE); 683 nr_txbb = desc_size / TXBB_SIZE; 684 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 685 if (netif_msg_tx_err(priv)) 686 en_warn(priv, "Oversized header or SG list\n"); 687 goto tx_drop; 688 } 689 690 tx_ind = skb->queue_mapping; 691 ring = priv->tx_ring[tx_ind]; 692 if (vlan_tx_tag_present(skb)) 693 vlan_tag = vlan_tx_tag_get(skb); 694 695 /* Check available TXBBs And 2K spare for prefetch */ 696 if (unlikely(((int)(ring->prod - ring->cons)) > 697 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 698 /* every full Tx ring stops queue */ 699 netif_tx_stop_queue(ring->tx_queue); 700 ring->queue_stopped++; 701 702 /* If queue was emptied after the if, and before the 703 * stop_queue - need to wake the queue, or else it will remain 704 * stopped forever. 705 * Need a memory barrier to make sure ring->cons was not 706 * updated before queue was stopped. 707 */ 708 wmb(); 709 710 if (unlikely(((int)(ring->prod - ring->cons)) <= 711 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 712 netif_tx_wake_queue(ring->tx_queue); 713 ring->wake_queue++; 714 } else { 715 return NETDEV_TX_BUSY; 716 } 717 } 718 719 /* Track current inflight packets for performance analysis */ 720 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 721 (u32) (ring->prod - ring->cons - 1)); 722 723 /* Packet is good - grab an index and transmit it */ 724 index = ring->prod & ring->size_mask; 725 bf_index = ring->prod; 726 727 /* See if we have enough space for whole descriptor TXBB for setting 728 * SW ownership on next descriptor; if not, use a bounce buffer. */ 729 if (likely(index + nr_txbb <= ring->size)) 730 tx_desc = ring->buf + index * TXBB_SIZE; 731 else { 732 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 733 bounce = true; 734 } 735 736 /* Save skb in tx_info ring */ 737 tx_info = &ring->tx_info[index]; 738 tx_info->skb = skb; 739 tx_info->nr_txbb = nr_txbb; 740 741 if (lso_header_size) 742 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 743 DS_SIZE)); 744 else 745 data = &tx_desc->data; 746 747 /* valid only for none inline segments */ 748 tx_info->data_offset = (void *)data - (void *)tx_desc; 749 750 tx_info->linear = (lso_header_size < skb_headlen(skb) && 751 !is_inline(ring->inline_thold, skb, NULL)) ? 1 : 0; 752 753 data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; 754 755 if (is_inline(ring->inline_thold, skb, &fragptr)) { 756 tx_info->inl = 1; 757 } else { 758 /* Map fragments */ 759 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { 760 struct skb_frag_struct *frag; 761 dma_addr_t dma; 762 763 frag = &skb_shinfo(skb)->frags[i]; 764 dma = skb_frag_dma_map(ddev, frag, 765 0, skb_frag_size(frag), 766 DMA_TO_DEVICE); 767 if (dma_mapping_error(ddev, dma)) 768 goto tx_drop_unmap; 769 770 data->addr = cpu_to_be64(dma); 771 data->lkey = cpu_to_be32(mdev->mr.key); 772 wmb(); 773 data->byte_count = cpu_to_be32(skb_frag_size(frag)); 774 --data; 775 } 776 777 /* Map linear part */ 778 if (tx_info->linear) { 779 u32 byte_count = skb_headlen(skb) - lso_header_size; 780 dma_addr_t dma; 781 782 dma = dma_map_single(ddev, skb->data + 783 lso_header_size, byte_count, 784 PCI_DMA_TODEVICE); 785 if (dma_mapping_error(ddev, dma)) 786 goto tx_drop_unmap; 787 788 data->addr = cpu_to_be64(dma); 789 data->lkey = cpu_to_be32(mdev->mr.key); 790 wmb(); 791 data->byte_count = cpu_to_be32(byte_count); 792 } 793 tx_info->inl = 0; 794 } 795 796 /* 797 * For timestamping add flag to skb_shinfo and 798 * set flag for further reference 799 */ 800 if (ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 801 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 802 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 803 tx_info->ts_requested = 1; 804 } 805 806 /* Prepare ctrl segement apart opcode+ownership, which depends on 807 * whether LSO is used */ 808 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); 809 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * 810 !!vlan_tx_tag_present(skb); 811 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; 812 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 813 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 814 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 815 MLX4_WQE_CTRL_TCP_UDP_CSUM); 816 ring->tx_csum++; 817 } 818 819 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 820 struct ethhdr *ethh; 821 822 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 823 * so that VFs and PF can communicate with each other 824 */ 825 ethh = (struct ethhdr *)skb->data; 826 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 827 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 828 } 829 830 /* Handle LSO (TSO) packets */ 831 if (lso_header_size) { 832 /* Mark opcode as LSO */ 833 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 834 ((ring->prod & ring->size) ? 835 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 836 837 /* Fill in the LSO prefix */ 838 tx_desc->lso.mss_hdr_size = cpu_to_be32( 839 skb_shinfo(skb)->gso_size << 16 | lso_header_size); 840 841 /* Copy headers; 842 * note that we already verified that it is linear */ 843 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 844 845 priv->port_stats.tso_packets++; 846 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + 847 !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); 848 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 849 ring->packets += i; 850 } else { 851 /* Normal (Non LSO) packet */ 852 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 853 ((ring->prod & ring->size) ? 854 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 855 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 856 ring->packets++; 857 858 } 859 ring->bytes += tx_info->nr_bytes; 860 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 861 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 862 863 if (tx_info->inl) { 864 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); 865 tx_info->inl = 1; 866 } 867 868 if (skb->encapsulation) { 869 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); 870 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) 871 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 872 else 873 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 874 } 875 876 ring->prod += nr_txbb; 877 878 /* If we used a bounce buffer then copy descriptor back into place */ 879 if (bounce) 880 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 881 882 skb_tx_timestamp(skb); 883 884 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) { 885 tx_desc->ctrl.bf_qpn |= cpu_to_be32(ring->doorbell_qpn); 886 887 op_own |= htonl((bf_index & 0xffff) << 8); 888 /* Ensure new descirptor hits memory 889 * before setting ownership of this descriptor to HW */ 890 wmb(); 891 tx_desc->ctrl.owner_opcode = op_own; 892 893 wmb(); 894 895 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, 896 desc_size); 897 898 wmb(); 899 900 ring->bf.offset ^= ring->bf.buf_size; 901 } else { 902 /* Ensure new descirptor hits memory 903 * before setting ownership of this descriptor to HW */ 904 wmb(); 905 tx_desc->ctrl.owner_opcode = op_own; 906 wmb(); 907 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); 908 } 909 910 return NETDEV_TX_OK; 911 912 tx_drop_unmap: 913 en_err(priv, "DMA mapping error\n"); 914 915 for (i++; i < skb_shinfo(skb)->nr_frags; i++) { 916 data++; 917 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 918 be32_to_cpu(data->byte_count), 919 PCI_DMA_TODEVICE); 920 } 921 922 tx_drop: 923 dev_kfree_skb_any(skb); 924 priv->stats.tx_dropped++; 925 return NETDEV_TX_OK; 926 } 927 928