1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 61 if (!ring) { 62 en_err(priv, "Failed allocating TX ring\n"); 63 return -ENOMEM; 64 } 65 } 66 67 ring->size = size; 68 ring->size_mask = size - 1; 69 ring->sp_stride = stride; 70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 71 72 tmp = size * sizeof(struct mlx4_en_tx_info); 73 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); 74 if (!ring->tx_info) { 75 err = -ENOMEM; 76 goto err_ring; 77 } 78 79 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 80 ring->tx_info, tmp); 81 82 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 83 if (!ring->bounce_buf) { 84 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 85 if (!ring->bounce_buf) { 86 err = -ENOMEM; 87 goto err_info; 88 } 89 } 90 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 91 92 /* Allocate HW buffers on provided NUMA node */ 93 set_dev_node(&mdev->dev->persist->pdev->dev, node); 94 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 95 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 96 if (err) { 97 en_err(priv, "Failed allocating hwq resources\n"); 98 goto err_bounce; 99 } 100 101 ring->buf = ring->sp_wqres.buf.direct.buf; 102 103 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 104 ring, ring->buf, ring->size, ring->buf_size, 105 (unsigned long long) ring->sp_wqres.buf.direct.map); 106 107 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 108 MLX4_RESERVE_ETH_BF_QP); 109 if (err) { 110 en_err(priv, "failed reserving qp for TX ring\n"); 111 goto err_hwq_res; 112 } 113 114 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp, GFP_KERNEL); 115 if (err) { 116 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 117 goto err_reserve; 118 } 119 ring->sp_qp.event = mlx4_en_sqp_event; 120 121 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 122 if (err) { 123 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 124 ring->bf.uar = &mdev->priv_uar; 125 ring->bf.uar->map = mdev->uar_map; 126 ring->bf_enabled = false; 127 ring->bf_alloced = false; 128 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 129 } else { 130 ring->bf_alloced = true; 131 ring->bf_enabled = !!(priv->pflags & 132 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 133 } 134 135 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 136 ring->queue_index = queue_index; 137 138 if (queue_index < priv->num_tx_rings_p_up) 139 cpumask_set_cpu(cpumask_local_spread(queue_index, 140 priv->mdev->dev->numa_node), 141 &ring->sp_affinity_mask); 142 143 *pring = ring; 144 return 0; 145 146 err_reserve: 147 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 148 err_hwq_res: 149 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 150 err_bounce: 151 kfree(ring->bounce_buf); 152 ring->bounce_buf = NULL; 153 err_info: 154 kvfree(ring->tx_info); 155 ring->tx_info = NULL; 156 err_ring: 157 kfree(ring); 158 *pring = NULL; 159 return err; 160 } 161 162 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 163 struct mlx4_en_tx_ring **pring) 164 { 165 struct mlx4_en_dev *mdev = priv->mdev; 166 struct mlx4_en_tx_ring *ring = *pring; 167 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 168 169 if (ring->bf_alloced) 170 mlx4_bf_free(mdev->dev, &ring->bf); 171 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 172 mlx4_qp_free(mdev->dev, &ring->sp_qp); 173 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 174 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 175 kfree(ring->bounce_buf); 176 ring->bounce_buf = NULL; 177 kvfree(ring->tx_info); 178 ring->tx_info = NULL; 179 kfree(ring); 180 *pring = NULL; 181 } 182 183 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 184 struct mlx4_en_tx_ring *ring, 185 int cq, int user_prio) 186 { 187 struct mlx4_en_dev *mdev = priv->mdev; 188 int err; 189 190 ring->sp_cqn = cq; 191 ring->prod = 0; 192 ring->cons = 0xffffffff; 193 ring->last_nr_txbb = 1; 194 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 195 memset(ring->buf, 0, ring->buf_size); 196 ring->free_tx_desc = mlx4_en_free_tx_desc; 197 198 ring->sp_qp_state = MLX4_QP_STATE_RST; 199 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 200 ring->mr_key = cpu_to_be32(mdev->mr.key); 201 202 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 203 ring->sp_cqn, user_prio, &ring->sp_context); 204 if (ring->bf_alloced) 205 ring->sp_context.usr_page = 206 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 207 ring->bf.uar->index)); 208 209 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 210 &ring->sp_qp, &ring->sp_qp_state); 211 if (!cpumask_empty(&ring->sp_affinity_mask)) 212 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 213 ring->queue_index); 214 215 return err; 216 } 217 218 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 219 struct mlx4_en_tx_ring *ring) 220 { 221 struct mlx4_en_dev *mdev = priv->mdev; 222 223 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 224 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 225 } 226 227 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 228 { 229 return ring->prod - ring->cons > ring->full_size; 230 } 231 232 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 233 struct mlx4_en_tx_ring *ring, int index, 234 u8 owner) 235 { 236 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 237 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 238 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 239 void *end = ring->buf + ring->buf_size; 240 __be32 *ptr = (__be32 *)tx_desc; 241 int i; 242 243 /* Optimize the common case when there are no wraparounds */ 244 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 245 /* Stamp the freed descriptor */ 246 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 247 i += STAMP_STRIDE) { 248 *ptr = stamp; 249 ptr += STAMP_DWORDS; 250 } 251 } else { 252 /* Stamp the freed descriptor */ 253 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 254 i += STAMP_STRIDE) { 255 *ptr = stamp; 256 ptr += STAMP_DWORDS; 257 if ((void *)ptr >= end) { 258 ptr = ring->buf; 259 stamp ^= cpu_to_be32(0x80000000); 260 } 261 } 262 } 263 } 264 265 266 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 267 struct mlx4_en_tx_ring *ring, 268 int index, u8 owner, u64 timestamp, 269 int napi_mode) 270 { 271 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 272 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 273 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 274 void *end = ring->buf + ring->buf_size; 275 struct sk_buff *skb = tx_info->skb; 276 int nr_maps = tx_info->nr_maps; 277 int i; 278 279 /* We do not touch skb here, so prefetch skb->users location 280 * to speedup consume_skb() 281 */ 282 prefetchw(&skb->users); 283 284 if (unlikely(timestamp)) { 285 struct skb_shared_hwtstamps hwts; 286 287 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 288 skb_tstamp_tx(skb, &hwts); 289 } 290 291 /* Optimize the common case when there are no wraparounds */ 292 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 293 if (!tx_info->inl) { 294 if (tx_info->linear) 295 dma_unmap_single(priv->ddev, 296 tx_info->map0_dma, 297 tx_info->map0_byte_count, 298 PCI_DMA_TODEVICE); 299 else 300 dma_unmap_page(priv->ddev, 301 tx_info->map0_dma, 302 tx_info->map0_byte_count, 303 PCI_DMA_TODEVICE); 304 for (i = 1; i < nr_maps; i++) { 305 data++; 306 dma_unmap_page(priv->ddev, 307 (dma_addr_t)be64_to_cpu(data->addr), 308 be32_to_cpu(data->byte_count), 309 PCI_DMA_TODEVICE); 310 } 311 } 312 } else { 313 if (!tx_info->inl) { 314 if ((void *) data >= end) { 315 data = ring->buf + ((void *)data - end); 316 } 317 318 if (tx_info->linear) 319 dma_unmap_single(priv->ddev, 320 tx_info->map0_dma, 321 tx_info->map0_byte_count, 322 PCI_DMA_TODEVICE); 323 else 324 dma_unmap_page(priv->ddev, 325 tx_info->map0_dma, 326 tx_info->map0_byte_count, 327 PCI_DMA_TODEVICE); 328 for (i = 1; i < nr_maps; i++) { 329 data++; 330 /* Check for wraparound before unmapping */ 331 if ((void *) data >= end) 332 data = ring->buf; 333 dma_unmap_page(priv->ddev, 334 (dma_addr_t)be64_to_cpu(data->addr), 335 be32_to_cpu(data->byte_count), 336 PCI_DMA_TODEVICE); 337 } 338 } 339 } 340 napi_consume_skb(skb, napi_mode); 341 342 return tx_info->nr_txbb; 343 } 344 345 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 346 struct mlx4_en_tx_ring *ring, 347 int index, u8 owner, u64 timestamp, 348 int napi_mode) 349 { 350 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 351 struct mlx4_en_rx_alloc frame = { 352 .page = tx_info->page, 353 .dma = tx_info->map0_dma, 354 }; 355 356 if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 357 dma_unmap_page(priv->ddev, tx_info->map0_dma, 358 PAGE_SIZE, priv->dma_dir); 359 put_page(tx_info->page); 360 } 361 362 return tx_info->nr_txbb; 363 } 364 365 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 366 { 367 struct mlx4_en_priv *priv = netdev_priv(dev); 368 int cnt = 0; 369 370 /* Skip last polled descriptor */ 371 ring->cons += ring->last_nr_txbb; 372 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 373 ring->cons, ring->prod); 374 375 if ((u32) (ring->prod - ring->cons) > ring->size) { 376 if (netif_msg_tx_err(priv)) 377 en_warn(priv, "Tx consumer passed producer!\n"); 378 return 0; 379 } 380 381 while (ring->cons != ring->prod) { 382 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 383 ring->cons & ring->size_mask, 384 !!(ring->cons & ring->size), 0, 385 0 /* Non-NAPI caller */); 386 ring->cons += ring->last_nr_txbb; 387 cnt++; 388 } 389 390 if (ring->tx_queue) 391 netdev_tx_reset_queue(ring->tx_queue); 392 393 if (cnt) 394 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 395 396 return cnt; 397 } 398 399 static bool mlx4_en_process_tx_cq(struct net_device *dev, 400 struct mlx4_en_cq *cq, int napi_budget) 401 { 402 struct mlx4_en_priv *priv = netdev_priv(dev); 403 struct mlx4_cq *mcq = &cq->mcq; 404 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 405 struct mlx4_cqe *cqe; 406 u16 index; 407 u16 new_index, ring_index, stamp_index; 408 u32 txbbs_skipped = 0; 409 u32 txbbs_stamp = 0; 410 u32 cons_index = mcq->cons_index; 411 int size = cq->size; 412 u32 size_mask = ring->size_mask; 413 struct mlx4_cqe *buf = cq->buf; 414 u32 packets = 0; 415 u32 bytes = 0; 416 int factor = priv->cqe_factor; 417 int done = 0; 418 int budget = priv->tx_work_limit; 419 u32 last_nr_txbb; 420 u32 ring_cons; 421 422 if (!priv->port_up) 423 return true; 424 425 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 426 427 index = cons_index & size_mask; 428 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 429 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 430 ring_cons = ACCESS_ONCE(ring->cons); 431 ring_index = ring_cons & size_mask; 432 stamp_index = ring_index; 433 434 /* Process all completed CQEs */ 435 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 436 cons_index & size) && (done < budget)) { 437 /* 438 * make sure we read the CQE after we read the 439 * ownership bit 440 */ 441 dma_rmb(); 442 443 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 444 MLX4_CQE_OPCODE_ERROR)) { 445 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 446 447 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 448 cqe_err->vendor_err_syndrome, 449 cqe_err->syndrome); 450 } 451 452 /* Skip over last polled CQE */ 453 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 454 455 do { 456 u64 timestamp = 0; 457 458 txbbs_skipped += last_nr_txbb; 459 ring_index = (ring_index + last_nr_txbb) & size_mask; 460 461 if (unlikely(ring->tx_info[ring_index].ts_requested)) 462 timestamp = mlx4_en_get_cqe_ts(cqe); 463 464 /* free next descriptor */ 465 last_nr_txbb = ring->free_tx_desc( 466 priv, ring, ring_index, 467 !!((ring_cons + txbbs_skipped) & 468 ring->size), timestamp, napi_budget); 469 470 mlx4_en_stamp_wqe(priv, ring, stamp_index, 471 !!((ring_cons + txbbs_stamp) & 472 ring->size)); 473 stamp_index = ring_index; 474 txbbs_stamp = txbbs_skipped; 475 packets++; 476 bytes += ring->tx_info[ring_index].nr_bytes; 477 } while ((++done < budget) && (ring_index != new_index)); 478 479 ++cons_index; 480 index = cons_index & size_mask; 481 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 482 } 483 484 485 /* 486 * To prevent CQ overflow we first update CQ consumer and only then 487 * the ring consumer. 488 */ 489 mcq->cons_index = cons_index; 490 mlx4_cq_set_ci(mcq); 491 wmb(); 492 493 /* we want to dirty this cache line once */ 494 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 495 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 496 497 if (ring->free_tx_desc == mlx4_en_recycle_tx_desc) 498 return done < budget; 499 500 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 501 502 /* Wakeup Tx queue if this stopped, and ring is not full. 503 */ 504 if (netif_tx_queue_stopped(ring->tx_queue) && 505 !mlx4_en_is_tx_ring_full(ring)) { 506 netif_tx_wake_queue(ring->tx_queue); 507 ring->wake_queue++; 508 } 509 return done < budget; 510 } 511 512 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 513 { 514 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 515 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 516 517 if (likely(priv->port_up)) 518 napi_schedule_irqoff(&cq->napi); 519 else 520 mlx4_en_arm_cq(priv, cq); 521 } 522 523 /* TX CQ polling - called by NAPI */ 524 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 525 { 526 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 527 struct net_device *dev = cq->dev; 528 struct mlx4_en_priv *priv = netdev_priv(dev); 529 int clean_complete; 530 531 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 532 if (!clean_complete) 533 return budget; 534 535 napi_complete(napi); 536 mlx4_en_arm_cq(priv, cq); 537 538 return 0; 539 } 540 541 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 542 struct mlx4_en_tx_ring *ring, 543 u32 index, 544 unsigned int desc_size) 545 { 546 u32 copy = (ring->size - index) * TXBB_SIZE; 547 int i; 548 549 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 550 if ((i & (TXBB_SIZE - 1)) == 0) 551 wmb(); 552 553 *((u32 *) (ring->buf + i)) = 554 *((u32 *) (ring->bounce_buf + copy + i)); 555 } 556 557 for (i = copy - 4; i >= 4 ; i -= 4) { 558 if ((i & (TXBB_SIZE - 1)) == 0) 559 wmb(); 560 561 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 562 *((u32 *) (ring->bounce_buf + i)); 563 } 564 565 /* Return real descriptor location */ 566 return ring->buf + index * TXBB_SIZE; 567 } 568 569 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 570 * 571 * It seems strange we do not simply use skb_copy_bits(). 572 * This would allow to inline all skbs iff skb->len <= inline_thold 573 * 574 * Note that caller already checked skb was not a gso packet 575 */ 576 static bool is_inline(int inline_thold, const struct sk_buff *skb, 577 const struct skb_shared_info *shinfo, 578 void **pfrag) 579 { 580 void *ptr; 581 582 if (skb->len > inline_thold || !inline_thold) 583 return false; 584 585 if (shinfo->nr_frags == 1) { 586 ptr = skb_frag_address_safe(&shinfo->frags[0]); 587 if (unlikely(!ptr)) 588 return false; 589 *pfrag = ptr; 590 return true; 591 } 592 if (shinfo->nr_frags) 593 return false; 594 return true; 595 } 596 597 static int inline_size(const struct sk_buff *skb) 598 { 599 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 600 <= MLX4_INLINE_ALIGN) 601 return ALIGN(skb->len + CTRL_SIZE + 602 sizeof(struct mlx4_wqe_inline_seg), 16); 603 else 604 return ALIGN(skb->len + CTRL_SIZE + 2 * 605 sizeof(struct mlx4_wqe_inline_seg), 16); 606 } 607 608 static int get_real_size(const struct sk_buff *skb, 609 const struct skb_shared_info *shinfo, 610 struct net_device *dev, 611 int *lso_header_size, 612 bool *inline_ok, 613 void **pfrag) 614 { 615 struct mlx4_en_priv *priv = netdev_priv(dev); 616 int real_size; 617 618 if (shinfo->gso_size) { 619 *inline_ok = false; 620 if (skb->encapsulation) 621 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 622 else 623 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 624 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 625 ALIGN(*lso_header_size + 4, DS_SIZE); 626 if (unlikely(*lso_header_size != skb_headlen(skb))) { 627 /* We add a segment for the skb linear buffer only if 628 * it contains data */ 629 if (*lso_header_size < skb_headlen(skb)) 630 real_size += DS_SIZE; 631 else { 632 if (netif_msg_tx_err(priv)) 633 en_warn(priv, "Non-linear headers\n"); 634 return 0; 635 } 636 } 637 } else { 638 *lso_header_size = 0; 639 *inline_ok = is_inline(priv->prof->inline_thold, skb, 640 shinfo, pfrag); 641 642 if (*inline_ok) 643 real_size = inline_size(skb); 644 else 645 real_size = CTRL_SIZE + 646 (shinfo->nr_frags + 1) * DS_SIZE; 647 } 648 649 return real_size; 650 } 651 652 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 653 const struct sk_buff *skb, 654 const struct skb_shared_info *shinfo, 655 void *fragptr) 656 { 657 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 658 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 659 unsigned int hlen = skb_headlen(skb); 660 661 if (skb->len <= spc) { 662 if (likely(skb->len >= MIN_PKT_LEN)) { 663 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 664 } else { 665 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 666 memset(((void *)(inl + 1)) + skb->len, 0, 667 MIN_PKT_LEN - skb->len); 668 } 669 skb_copy_from_linear_data(skb, inl + 1, hlen); 670 if (shinfo->nr_frags) 671 memcpy(((void *)(inl + 1)) + hlen, fragptr, 672 skb_frag_size(&shinfo->frags[0])); 673 674 } else { 675 inl->byte_count = cpu_to_be32(1 << 31 | spc); 676 if (hlen <= spc) { 677 skb_copy_from_linear_data(skb, inl + 1, hlen); 678 if (hlen < spc) { 679 memcpy(((void *)(inl + 1)) + hlen, 680 fragptr, spc - hlen); 681 fragptr += spc - hlen; 682 } 683 inl = (void *) (inl + 1) + spc; 684 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 685 } else { 686 skb_copy_from_linear_data(skb, inl + 1, spc); 687 inl = (void *) (inl + 1) + spc; 688 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 689 hlen - spc); 690 if (shinfo->nr_frags) 691 memcpy(((void *)(inl + 1)) + hlen - spc, 692 fragptr, 693 skb_frag_size(&shinfo->frags[0])); 694 } 695 696 dma_wmb(); 697 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 698 } 699 } 700 701 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 702 void *accel_priv, select_queue_fallback_t fallback) 703 { 704 struct mlx4_en_priv *priv = netdev_priv(dev); 705 u16 rings_p_up = priv->num_tx_rings_p_up; 706 u8 up = 0; 707 708 if (netdev_get_num_tc(dev)) 709 return skb_tx_hash(dev, skb); 710 711 if (skb_vlan_tag_present(skb)) 712 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; 713 714 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 715 } 716 717 static void mlx4_bf_copy(void __iomem *dst, const void *src, 718 unsigned int bytecnt) 719 { 720 __iowrite64_copy(dst, src, bytecnt / 8); 721 } 722 723 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 724 { 725 wmb(); 726 /* Since there is no iowrite*_native() that writes the 727 * value as is, without byteswapping - using the one 728 * the doesn't do byteswapping in the relevant arch 729 * endianness. 730 */ 731 #if defined(__LITTLE_ENDIAN) 732 iowrite32( 733 #else 734 iowrite32be( 735 #endif 736 ring->doorbell_qpn, 737 ring->bf.uar->map + MLX4_SEND_DOORBELL); 738 } 739 740 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 741 struct mlx4_en_tx_desc *tx_desc, 742 union mlx4_wqe_qpn_vlan qpn_vlan, 743 int desc_size, int bf_index, 744 __be32 op_own, bool bf_ok, 745 bool send_doorbell) 746 { 747 tx_desc->ctrl.qpn_vlan = qpn_vlan; 748 749 if (bf_ok) { 750 op_own |= htonl((bf_index & 0xffff) << 8); 751 /* Ensure new descriptor hits memory 752 * before setting ownership of this descriptor to HW 753 */ 754 dma_wmb(); 755 tx_desc->ctrl.owner_opcode = op_own; 756 757 wmb(); 758 759 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 760 desc_size); 761 762 wmb(); 763 764 ring->bf.offset ^= ring->bf.buf_size; 765 } else { 766 /* Ensure new descriptor hits memory 767 * before setting ownership of this descriptor to HW 768 */ 769 dma_wmb(); 770 tx_desc->ctrl.owner_opcode = op_own; 771 if (send_doorbell) 772 mlx4_en_xmit_doorbell(ring); 773 else 774 ring->xmit_more++; 775 } 776 } 777 778 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 779 { 780 struct skb_shared_info *shinfo = skb_shinfo(skb); 781 struct mlx4_en_priv *priv = netdev_priv(dev); 782 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 783 struct device *ddev = priv->ddev; 784 struct mlx4_en_tx_ring *ring; 785 struct mlx4_en_tx_desc *tx_desc; 786 struct mlx4_wqe_data_seg *data; 787 struct mlx4_en_tx_info *tx_info; 788 int tx_ind = 0; 789 int nr_txbb; 790 int desc_size; 791 int real_size; 792 u32 index, bf_index; 793 __be32 op_own; 794 u16 vlan_proto = 0; 795 int i_frag; 796 int lso_header_size; 797 void *fragptr = NULL; 798 bool bounce = false; 799 bool send_doorbell; 800 bool stop_queue; 801 bool inline_ok; 802 u32 ring_cons; 803 bool bf_ok; 804 805 tx_ind = skb_get_queue_mapping(skb); 806 ring = priv->tx_ring[TX][tx_ind]; 807 808 if (!priv->port_up) 809 goto tx_drop; 810 811 /* fetch ring->cons far ahead before needing it to avoid stall */ 812 ring_cons = ACCESS_ONCE(ring->cons); 813 814 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 815 &inline_ok, &fragptr); 816 if (unlikely(!real_size)) 817 goto tx_drop_count; 818 819 /* Align descriptor to TXBB size */ 820 desc_size = ALIGN(real_size, TXBB_SIZE); 821 nr_txbb = desc_size / TXBB_SIZE; 822 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 823 if (netif_msg_tx_err(priv)) 824 en_warn(priv, "Oversized header or SG list\n"); 825 goto tx_drop_count; 826 } 827 828 bf_ok = ring->bf_enabled; 829 if (skb_vlan_tag_present(skb)) { 830 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 831 vlan_proto = be16_to_cpu(skb->vlan_proto); 832 if (vlan_proto == ETH_P_8021AD) 833 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 834 else if (vlan_proto == ETH_P_8021Q) 835 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 836 else 837 qpn_vlan.ins_vlan = 0; 838 bf_ok = false; 839 } 840 841 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 842 843 /* Track current inflight packets for performance analysis */ 844 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 845 (u32)(ring->prod - ring_cons - 1)); 846 847 /* Packet is good - grab an index and transmit it */ 848 index = ring->prod & ring->size_mask; 849 bf_index = ring->prod; 850 851 /* See if we have enough space for whole descriptor TXBB for setting 852 * SW ownership on next descriptor; if not, use a bounce buffer. */ 853 if (likely(index + nr_txbb <= ring->size)) 854 tx_desc = ring->buf + index * TXBB_SIZE; 855 else { 856 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 857 bounce = true; 858 bf_ok = false; 859 } 860 861 /* Save skb in tx_info ring */ 862 tx_info = &ring->tx_info[index]; 863 tx_info->skb = skb; 864 tx_info->nr_txbb = nr_txbb; 865 866 data = &tx_desc->data; 867 if (lso_header_size) 868 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 869 DS_SIZE)); 870 871 /* valid only for none inline segments */ 872 tx_info->data_offset = (void *)data - (void *)tx_desc; 873 874 tx_info->inl = inline_ok; 875 876 tx_info->linear = (lso_header_size < skb_headlen(skb) && 877 !inline_ok) ? 1 : 0; 878 879 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 880 data += tx_info->nr_maps - 1; 881 882 if (!tx_info->inl) { 883 dma_addr_t dma = 0; 884 u32 byte_count = 0; 885 886 /* Map fragments if any */ 887 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 888 const struct skb_frag_struct *frag; 889 890 frag = &shinfo->frags[i_frag]; 891 byte_count = skb_frag_size(frag); 892 dma = skb_frag_dma_map(ddev, frag, 893 0, byte_count, 894 DMA_TO_DEVICE); 895 if (dma_mapping_error(ddev, dma)) 896 goto tx_drop_unmap; 897 898 data->addr = cpu_to_be64(dma); 899 data->lkey = ring->mr_key; 900 dma_wmb(); 901 data->byte_count = cpu_to_be32(byte_count); 902 --data; 903 } 904 905 /* Map linear part if needed */ 906 if (tx_info->linear) { 907 byte_count = skb_headlen(skb) - lso_header_size; 908 909 dma = dma_map_single(ddev, skb->data + 910 lso_header_size, byte_count, 911 PCI_DMA_TODEVICE); 912 if (dma_mapping_error(ddev, dma)) 913 goto tx_drop_unmap; 914 915 data->addr = cpu_to_be64(dma); 916 data->lkey = ring->mr_key; 917 dma_wmb(); 918 data->byte_count = cpu_to_be32(byte_count); 919 } 920 /* tx completion can avoid cache line miss for common cases */ 921 tx_info->map0_dma = dma; 922 tx_info->map0_byte_count = byte_count; 923 } 924 925 /* 926 * For timestamping add flag to skb_shinfo and 927 * set flag for further reference 928 */ 929 tx_info->ts_requested = 0; 930 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 931 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 932 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 933 tx_info->ts_requested = 1; 934 } 935 936 /* Prepare ctrl segement apart opcode+ownership, which depends on 937 * whether LSO is used */ 938 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 939 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 940 if (!skb->encapsulation) 941 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 942 MLX4_WQE_CTRL_TCP_UDP_CSUM); 943 else 944 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 945 ring->tx_csum++; 946 } 947 948 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 949 struct ethhdr *ethh; 950 951 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 952 * so that VFs and PF can communicate with each other 953 */ 954 ethh = (struct ethhdr *)skb->data; 955 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 956 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 957 } 958 959 /* Handle LSO (TSO) packets */ 960 if (lso_header_size) { 961 int i; 962 963 /* Mark opcode as LSO */ 964 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 965 ((ring->prod & ring->size) ? 966 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 967 968 /* Fill in the LSO prefix */ 969 tx_desc->lso.mss_hdr_size = cpu_to_be32( 970 shinfo->gso_size << 16 | lso_header_size); 971 972 /* Copy headers; 973 * note that we already verified that it is linear */ 974 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 975 976 ring->tso_packets++; 977 978 i = shinfo->gso_segs; 979 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 980 ring->packets += i; 981 } else { 982 /* Normal (Non LSO) packet */ 983 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 984 ((ring->prod & ring->size) ? 985 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 986 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 987 ring->packets++; 988 } 989 ring->bytes += tx_info->nr_bytes; 990 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 991 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 992 993 if (tx_info->inl) 994 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 995 996 if (skb->encapsulation) { 997 union { 998 struct iphdr *v4; 999 struct ipv6hdr *v6; 1000 unsigned char *hdr; 1001 } ip; 1002 u8 proto; 1003 1004 ip.hdr = skb_inner_network_header(skb); 1005 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1006 ip.v6->nexthdr; 1007 1008 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1009 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1010 else 1011 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1012 } 1013 1014 ring->prod += nr_txbb; 1015 1016 /* If we used a bounce buffer then copy descriptor back into place */ 1017 if (unlikely(bounce)) 1018 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1019 1020 skb_tx_timestamp(skb); 1021 1022 /* Check available TXBBs And 2K spare for prefetch */ 1023 stop_queue = mlx4_en_is_tx_ring_full(ring); 1024 if (unlikely(stop_queue)) { 1025 netif_tx_stop_queue(ring->tx_queue); 1026 ring->queue_stopped++; 1027 } 1028 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 1029 1030 real_size = (real_size / 16) & 0x3f; 1031 1032 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1033 1034 if (bf_ok) 1035 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1036 else 1037 qpn_vlan.fence_size = real_size; 1038 1039 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1040 op_own, bf_ok, send_doorbell); 1041 1042 if (unlikely(stop_queue)) { 1043 /* If queue was emptied after the if (stop_queue) , and before 1044 * the netif_tx_stop_queue() - need to wake the queue, 1045 * or else it will remain stopped forever. 1046 * Need a memory barrier to make sure ring->cons was not 1047 * updated before queue was stopped. 1048 */ 1049 smp_rmb(); 1050 1051 ring_cons = ACCESS_ONCE(ring->cons); 1052 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1053 netif_tx_wake_queue(ring->tx_queue); 1054 ring->wake_queue++; 1055 } 1056 } 1057 return NETDEV_TX_OK; 1058 1059 tx_drop_unmap: 1060 en_err(priv, "DMA mapping error\n"); 1061 1062 while (++i_frag < shinfo->nr_frags) { 1063 ++data; 1064 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 1065 be32_to_cpu(data->byte_count), 1066 PCI_DMA_TODEVICE); 1067 } 1068 1069 tx_drop_count: 1070 ring->tx_dropped++; 1071 tx_drop: 1072 dev_kfree_skb_any(skb); 1073 return NETDEV_TX_OK; 1074 } 1075 1076 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1077 struct mlx4_en_rx_alloc *frame, 1078 struct net_device *dev, unsigned int length, 1079 int tx_ind, int *doorbell_pending) 1080 { 1081 struct mlx4_en_priv *priv = netdev_priv(dev); 1082 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 1083 struct mlx4_en_tx_ring *ring; 1084 struct mlx4_en_tx_desc *tx_desc; 1085 struct mlx4_wqe_data_seg *data; 1086 struct mlx4_en_tx_info *tx_info; 1087 int index, bf_index; 1088 bool send_doorbell; 1089 int nr_txbb = 1; 1090 bool stop_queue; 1091 dma_addr_t dma; 1092 int real_size; 1093 __be32 op_own; 1094 u32 ring_cons; 1095 bool bf_ok; 1096 1097 BUILD_BUG_ON_MSG(ALIGN(CTRL_SIZE + DS_SIZE, TXBB_SIZE) != TXBB_SIZE, 1098 "mlx4_en_xmit_frame requires minimum size tx desc"); 1099 1100 ring = priv->tx_ring[TX_XDP][tx_ind]; 1101 1102 if (!priv->port_up) 1103 goto tx_drop; 1104 1105 if (mlx4_en_is_tx_ring_full(ring)) 1106 goto tx_drop_count; 1107 1108 /* fetch ring->cons far ahead before needing it to avoid stall */ 1109 ring_cons = READ_ONCE(ring->cons); 1110 1111 index = ring->prod & ring->size_mask; 1112 tx_info = &ring->tx_info[index]; 1113 1114 bf_ok = ring->bf_enabled; 1115 1116 /* Track current inflight packets for performance analysis */ 1117 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1118 (u32)(ring->prod - ring_cons - 1)); 1119 1120 bf_index = ring->prod; 1121 tx_desc = ring->buf + index * TXBB_SIZE; 1122 data = &tx_desc->data; 1123 1124 dma = frame->dma; 1125 1126 tx_info->page = frame->page; 1127 frame->page = NULL; 1128 tx_info->map0_dma = dma; 1129 tx_info->map0_byte_count = PAGE_SIZE; 1130 tx_info->nr_txbb = nr_txbb; 1131 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1132 tx_info->data_offset = (void *)data - (void *)tx_desc; 1133 tx_info->ts_requested = 0; 1134 tx_info->nr_maps = 1; 1135 tx_info->linear = 1; 1136 tx_info->inl = 0; 1137 1138 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1139 length, PCI_DMA_TODEVICE); 1140 1141 data->addr = cpu_to_be64(dma + frame->page_offset); 1142 data->lkey = ring->mr_key; 1143 dma_wmb(); 1144 data->byte_count = cpu_to_be32(length); 1145 1146 /* tx completion can avoid cache line miss for common cases */ 1147 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1148 1149 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1150 ((ring->prod & ring->size) ? 1151 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1152 1153 rx_ring->xdp_tx++; 1154 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1155 1156 ring->prod += nr_txbb; 1157 1158 stop_queue = mlx4_en_is_tx_ring_full(ring); 1159 send_doorbell = stop_queue || 1160 *doorbell_pending > MLX4_EN_DOORBELL_BUDGET; 1161 bf_ok &= send_doorbell; 1162 1163 real_size = ((CTRL_SIZE + nr_txbb * DS_SIZE) / 16) & 0x3f; 1164 1165 if (bf_ok) 1166 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1167 else 1168 qpn_vlan.fence_size = real_size; 1169 1170 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, bf_index, 1171 op_own, bf_ok, send_doorbell); 1172 *doorbell_pending = send_doorbell ? 0 : *doorbell_pending + 1; 1173 1174 return NETDEV_TX_OK; 1175 1176 tx_drop_count: 1177 rx_ring->xdp_tx_full++; 1178 tx_drop: 1179 return NETDEV_TX_BUSY; 1180 } 1181