1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 en_err(priv, "Failed allocating TX ring\n"); 61 return -ENOMEM; 62 } 63 64 ring->size = size; 65 ring->size_mask = size - 1; 66 ring->sp_stride = stride; 67 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 68 69 tmp = size * sizeof(struct mlx4_en_tx_info); 70 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); 71 if (!ring->tx_info) { 72 err = -ENOMEM; 73 goto err_ring; 74 } 75 76 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 77 ring->tx_info, tmp); 78 79 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 80 if (!ring->bounce_buf) { 81 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 82 if (!ring->bounce_buf) { 83 err = -ENOMEM; 84 goto err_info; 85 } 86 } 87 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 88 89 /* Allocate HW buffers on provided NUMA node */ 90 set_dev_node(&mdev->dev->persist->pdev->dev, node); 91 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 92 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 93 if (err) { 94 en_err(priv, "Failed allocating hwq resources\n"); 95 goto err_bounce; 96 } 97 98 ring->buf = ring->sp_wqres.buf.direct.buf; 99 100 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 101 ring, ring->buf, ring->size, ring->buf_size, 102 (unsigned long long) ring->sp_wqres.buf.direct.map); 103 104 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 105 MLX4_RESERVE_ETH_BF_QP, 106 MLX4_RES_USAGE_DRIVER); 107 if (err) { 108 en_err(priv, "failed reserving qp for TX ring\n"); 109 goto err_hwq_res; 110 } 111 112 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); 113 if (err) { 114 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 115 goto err_reserve; 116 } 117 ring->sp_qp.event = mlx4_en_sqp_event; 118 119 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 120 if (err) { 121 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 122 ring->bf.uar = &mdev->priv_uar; 123 ring->bf.uar->map = mdev->uar_map; 124 ring->bf_enabled = false; 125 ring->bf_alloced = false; 126 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 127 } else { 128 ring->bf_alloced = true; 129 ring->bf_enabled = !!(priv->pflags & 130 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 131 } 132 133 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 134 ring->queue_index = queue_index; 135 136 if (queue_index < priv->num_tx_rings_p_up) 137 cpumask_set_cpu(cpumask_local_spread(queue_index, 138 priv->mdev->dev->numa_node), 139 &ring->sp_affinity_mask); 140 141 *pring = ring; 142 return 0; 143 144 err_reserve: 145 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 146 err_hwq_res: 147 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 148 err_bounce: 149 kfree(ring->bounce_buf); 150 ring->bounce_buf = NULL; 151 err_info: 152 kvfree(ring->tx_info); 153 ring->tx_info = NULL; 154 err_ring: 155 kfree(ring); 156 *pring = NULL; 157 return err; 158 } 159 160 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 161 struct mlx4_en_tx_ring **pring) 162 { 163 struct mlx4_en_dev *mdev = priv->mdev; 164 struct mlx4_en_tx_ring *ring = *pring; 165 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 166 167 if (ring->bf_alloced) 168 mlx4_bf_free(mdev->dev, &ring->bf); 169 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 170 mlx4_qp_free(mdev->dev, &ring->sp_qp); 171 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 172 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 173 kfree(ring->bounce_buf); 174 ring->bounce_buf = NULL; 175 kvfree(ring->tx_info); 176 ring->tx_info = NULL; 177 kfree(ring); 178 *pring = NULL; 179 } 180 181 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 182 struct mlx4_en_tx_ring *ring, 183 int cq, int user_prio) 184 { 185 struct mlx4_en_dev *mdev = priv->mdev; 186 int err; 187 188 ring->sp_cqn = cq; 189 ring->prod = 0; 190 ring->cons = 0xffffffff; 191 ring->last_nr_txbb = 1; 192 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 193 memset(ring->buf, 0, ring->buf_size); 194 ring->free_tx_desc = mlx4_en_free_tx_desc; 195 196 ring->sp_qp_state = MLX4_QP_STATE_RST; 197 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 198 ring->mr_key = cpu_to_be32(mdev->mr.key); 199 200 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 201 ring->sp_cqn, user_prio, &ring->sp_context); 202 if (ring->bf_alloced) 203 ring->sp_context.usr_page = 204 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 205 ring->bf.uar->index)); 206 207 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 208 &ring->sp_qp, &ring->sp_qp_state); 209 if (!cpumask_empty(&ring->sp_affinity_mask)) 210 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 211 ring->queue_index); 212 213 return err; 214 } 215 216 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 217 struct mlx4_en_tx_ring *ring) 218 { 219 struct mlx4_en_dev *mdev = priv->mdev; 220 221 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 222 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 223 } 224 225 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 226 { 227 return ring->prod - ring->cons > ring->full_size; 228 } 229 230 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 231 struct mlx4_en_tx_ring *ring, int index, 232 u8 owner) 233 { 234 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 235 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 236 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 237 void *end = ring->buf + ring->buf_size; 238 __be32 *ptr = (__be32 *)tx_desc; 239 int i; 240 241 /* Optimize the common case when there are no wraparounds */ 242 if (likely((void *)tx_desc + 243 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 244 /* Stamp the freed descriptor */ 245 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 246 i += STAMP_STRIDE) { 247 *ptr = stamp; 248 ptr += STAMP_DWORDS; 249 } 250 } else { 251 /* Stamp the freed descriptor */ 252 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 253 i += STAMP_STRIDE) { 254 *ptr = stamp; 255 ptr += STAMP_DWORDS; 256 if ((void *)ptr >= end) { 257 ptr = ring->buf; 258 stamp ^= cpu_to_be32(0x80000000); 259 } 260 } 261 } 262 } 263 264 265 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 266 struct mlx4_en_tx_ring *ring, 267 int index, u64 timestamp, 268 int napi_mode) 269 { 270 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 271 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 272 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 273 void *end = ring->buf + ring->buf_size; 274 struct sk_buff *skb = tx_info->skb; 275 int nr_maps = tx_info->nr_maps; 276 int i; 277 278 /* We do not touch skb here, so prefetch skb->users location 279 * to speedup consume_skb() 280 */ 281 prefetchw(&skb->users); 282 283 if (unlikely(timestamp)) { 284 struct skb_shared_hwtstamps hwts; 285 286 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 287 skb_tstamp_tx(skb, &hwts); 288 } 289 290 if (!tx_info->inl) { 291 if (tx_info->linear) 292 dma_unmap_single(priv->ddev, 293 tx_info->map0_dma, 294 tx_info->map0_byte_count, 295 PCI_DMA_TODEVICE); 296 else 297 dma_unmap_page(priv->ddev, 298 tx_info->map0_dma, 299 tx_info->map0_byte_count, 300 PCI_DMA_TODEVICE); 301 /* Optimize the common case when there are no wraparounds */ 302 if (likely((void *)tx_desc + 303 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 304 for (i = 1; i < nr_maps; i++) { 305 data++; 306 dma_unmap_page(priv->ddev, 307 (dma_addr_t)be64_to_cpu(data->addr), 308 be32_to_cpu(data->byte_count), 309 PCI_DMA_TODEVICE); 310 } 311 } else { 312 if ((void *)data >= end) 313 data = ring->buf + ((void *)data - end); 314 315 for (i = 1; i < nr_maps; i++) { 316 data++; 317 /* Check for wraparound before unmapping */ 318 if ((void *) data >= end) 319 data = ring->buf; 320 dma_unmap_page(priv->ddev, 321 (dma_addr_t)be64_to_cpu(data->addr), 322 be32_to_cpu(data->byte_count), 323 PCI_DMA_TODEVICE); 324 } 325 } 326 } 327 napi_consume_skb(skb, napi_mode); 328 329 return tx_info->nr_txbb; 330 } 331 332 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 333 struct mlx4_en_tx_ring *ring, 334 int index, u64 timestamp, 335 int napi_mode) 336 { 337 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 338 struct mlx4_en_rx_alloc frame = { 339 .page = tx_info->page, 340 .dma = tx_info->map0_dma, 341 }; 342 343 if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 344 dma_unmap_page(priv->ddev, tx_info->map0_dma, 345 PAGE_SIZE, priv->dma_dir); 346 put_page(tx_info->page); 347 } 348 349 return tx_info->nr_txbb; 350 } 351 352 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 353 { 354 struct mlx4_en_priv *priv = netdev_priv(dev); 355 int cnt = 0; 356 357 /* Skip last polled descriptor */ 358 ring->cons += ring->last_nr_txbb; 359 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 360 ring->cons, ring->prod); 361 362 if ((u32) (ring->prod - ring->cons) > ring->size) { 363 if (netif_msg_tx_err(priv)) 364 en_warn(priv, "Tx consumer passed producer!\n"); 365 return 0; 366 } 367 368 while (ring->cons != ring->prod) { 369 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 370 ring->cons & ring->size_mask, 371 0, 0 /* Non-NAPI caller */); 372 ring->cons += ring->last_nr_txbb; 373 cnt++; 374 } 375 376 if (ring->tx_queue) 377 netdev_tx_reset_queue(ring->tx_queue); 378 379 if (cnt) 380 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 381 382 return cnt; 383 } 384 385 bool mlx4_en_process_tx_cq(struct net_device *dev, 386 struct mlx4_en_cq *cq, int napi_budget) 387 { 388 struct mlx4_en_priv *priv = netdev_priv(dev); 389 struct mlx4_cq *mcq = &cq->mcq; 390 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 391 struct mlx4_cqe *cqe; 392 u16 index, ring_index, stamp_index; 393 u32 txbbs_skipped = 0; 394 u32 txbbs_stamp = 0; 395 u32 cons_index = mcq->cons_index; 396 int size = cq->size; 397 u32 size_mask = ring->size_mask; 398 struct mlx4_cqe *buf = cq->buf; 399 u32 packets = 0; 400 u32 bytes = 0; 401 int factor = priv->cqe_factor; 402 int done = 0; 403 int budget = priv->tx_work_limit; 404 u32 last_nr_txbb; 405 u32 ring_cons; 406 407 if (unlikely(!priv->port_up)) 408 return true; 409 410 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 411 412 index = cons_index & size_mask; 413 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 414 last_nr_txbb = READ_ONCE(ring->last_nr_txbb); 415 ring_cons = READ_ONCE(ring->cons); 416 ring_index = ring_cons & size_mask; 417 stamp_index = ring_index; 418 419 /* Process all completed CQEs */ 420 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 421 cons_index & size) && (done < budget)) { 422 u16 new_index; 423 424 /* 425 * make sure we read the CQE after we read the 426 * ownership bit 427 */ 428 dma_rmb(); 429 430 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 431 MLX4_CQE_OPCODE_ERROR)) { 432 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 433 434 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 435 cqe_err->vendor_err_syndrome, 436 cqe_err->syndrome); 437 } 438 439 /* Skip over last polled CQE */ 440 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 441 442 do { 443 u64 timestamp = 0; 444 445 txbbs_skipped += last_nr_txbb; 446 ring_index = (ring_index + last_nr_txbb) & size_mask; 447 448 if (unlikely(ring->tx_info[ring_index].ts_requested)) 449 timestamp = mlx4_en_get_cqe_ts(cqe); 450 451 /* free next descriptor */ 452 last_nr_txbb = ring->free_tx_desc( 453 priv, ring, ring_index, 454 timestamp, napi_budget); 455 456 mlx4_en_stamp_wqe(priv, ring, stamp_index, 457 !!((ring_cons + txbbs_stamp) & 458 ring->size)); 459 stamp_index = ring_index; 460 txbbs_stamp = txbbs_skipped; 461 packets++; 462 bytes += ring->tx_info[ring_index].nr_bytes; 463 } while ((++done < budget) && (ring_index != new_index)); 464 465 ++cons_index; 466 index = cons_index & size_mask; 467 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 468 } 469 470 /* 471 * To prevent CQ overflow we first update CQ consumer and only then 472 * the ring consumer. 473 */ 474 mcq->cons_index = cons_index; 475 mlx4_cq_set_ci(mcq); 476 wmb(); 477 478 /* we want to dirty this cache line once */ 479 WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); 480 WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); 481 482 if (cq->type == TX_XDP) 483 return done < budget; 484 485 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 486 487 /* Wakeup Tx queue if this stopped, and ring is not full. 488 */ 489 if (netif_tx_queue_stopped(ring->tx_queue) && 490 !mlx4_en_is_tx_ring_full(ring)) { 491 netif_tx_wake_queue(ring->tx_queue); 492 ring->wake_queue++; 493 } 494 495 return done < budget; 496 } 497 498 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 499 { 500 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 501 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 502 503 if (likely(priv->port_up)) 504 napi_schedule_irqoff(&cq->napi); 505 else 506 mlx4_en_arm_cq(priv, cq); 507 } 508 509 /* TX CQ polling - called by NAPI */ 510 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 511 { 512 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 513 struct net_device *dev = cq->dev; 514 struct mlx4_en_priv *priv = netdev_priv(dev); 515 bool clean_complete; 516 517 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 518 if (!clean_complete) 519 return budget; 520 521 napi_complete(napi); 522 mlx4_en_arm_cq(priv, cq); 523 524 return 0; 525 } 526 527 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 528 struct mlx4_en_tx_ring *ring, 529 u32 index, 530 unsigned int desc_size) 531 { 532 u32 copy = (ring->size - index) << LOG_TXBB_SIZE; 533 int i; 534 535 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 536 if ((i & (TXBB_SIZE - 1)) == 0) 537 wmb(); 538 539 *((u32 *) (ring->buf + i)) = 540 *((u32 *) (ring->bounce_buf + copy + i)); 541 } 542 543 for (i = copy - 4; i >= 4 ; i -= 4) { 544 if ((i & (TXBB_SIZE - 1)) == 0) 545 wmb(); 546 547 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = 548 *((u32 *) (ring->bounce_buf + i)); 549 } 550 551 /* Return real descriptor location */ 552 return ring->buf + (index << LOG_TXBB_SIZE); 553 } 554 555 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 556 * 557 * It seems strange we do not simply use skb_copy_bits(). 558 * This would allow to inline all skbs iff skb->len <= inline_thold 559 * 560 * Note that caller already checked skb was not a gso packet 561 */ 562 static bool is_inline(int inline_thold, const struct sk_buff *skb, 563 const struct skb_shared_info *shinfo, 564 void **pfrag) 565 { 566 void *ptr; 567 568 if (skb->len > inline_thold || !inline_thold) 569 return false; 570 571 if (shinfo->nr_frags == 1) { 572 ptr = skb_frag_address_safe(&shinfo->frags[0]); 573 if (unlikely(!ptr)) 574 return false; 575 *pfrag = ptr; 576 return true; 577 } 578 if (shinfo->nr_frags) 579 return false; 580 return true; 581 } 582 583 static int inline_size(const struct sk_buff *skb) 584 { 585 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 586 <= MLX4_INLINE_ALIGN) 587 return ALIGN(skb->len + CTRL_SIZE + 588 sizeof(struct mlx4_wqe_inline_seg), 16); 589 else 590 return ALIGN(skb->len + CTRL_SIZE + 2 * 591 sizeof(struct mlx4_wqe_inline_seg), 16); 592 } 593 594 static int get_real_size(const struct sk_buff *skb, 595 const struct skb_shared_info *shinfo, 596 struct net_device *dev, 597 int *lso_header_size, 598 bool *inline_ok, 599 void **pfrag) 600 { 601 struct mlx4_en_priv *priv = netdev_priv(dev); 602 int real_size; 603 604 if (shinfo->gso_size) { 605 *inline_ok = false; 606 if (skb->encapsulation) 607 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 608 else 609 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 610 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 611 ALIGN(*lso_header_size + 4, DS_SIZE); 612 if (unlikely(*lso_header_size != skb_headlen(skb))) { 613 /* We add a segment for the skb linear buffer only if 614 * it contains data */ 615 if (*lso_header_size < skb_headlen(skb)) 616 real_size += DS_SIZE; 617 else { 618 if (netif_msg_tx_err(priv)) 619 en_warn(priv, "Non-linear headers\n"); 620 return 0; 621 } 622 } 623 } else { 624 *lso_header_size = 0; 625 *inline_ok = is_inline(priv->prof->inline_thold, skb, 626 shinfo, pfrag); 627 628 if (*inline_ok) 629 real_size = inline_size(skb); 630 else 631 real_size = CTRL_SIZE + 632 (shinfo->nr_frags + 1) * DS_SIZE; 633 } 634 635 return real_size; 636 } 637 638 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 639 const struct sk_buff *skb, 640 const struct skb_shared_info *shinfo, 641 void *fragptr) 642 { 643 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 644 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); 645 unsigned int hlen = skb_headlen(skb); 646 647 if (skb->len <= spc) { 648 if (likely(skb->len >= MIN_PKT_LEN)) { 649 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 650 } else { 651 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 652 memset(((void *)(inl + 1)) + skb->len, 0, 653 MIN_PKT_LEN - skb->len); 654 } 655 skb_copy_from_linear_data(skb, inl + 1, hlen); 656 if (shinfo->nr_frags) 657 memcpy(((void *)(inl + 1)) + hlen, fragptr, 658 skb_frag_size(&shinfo->frags[0])); 659 660 } else { 661 inl->byte_count = cpu_to_be32(1 << 31 | spc); 662 if (hlen <= spc) { 663 skb_copy_from_linear_data(skb, inl + 1, hlen); 664 if (hlen < spc) { 665 memcpy(((void *)(inl + 1)) + hlen, 666 fragptr, spc - hlen); 667 fragptr += spc - hlen; 668 } 669 inl = (void *) (inl + 1) + spc; 670 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 671 } else { 672 skb_copy_from_linear_data(skb, inl + 1, spc); 673 inl = (void *) (inl + 1) + spc; 674 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 675 hlen - spc); 676 if (shinfo->nr_frags) 677 memcpy(((void *)(inl + 1)) + hlen - spc, 678 fragptr, 679 skb_frag_size(&shinfo->frags[0])); 680 } 681 682 dma_wmb(); 683 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 684 } 685 } 686 687 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 688 struct net_device *sb_dev) 689 { 690 struct mlx4_en_priv *priv = netdev_priv(dev); 691 u16 rings_p_up = priv->num_tx_rings_p_up; 692 693 if (netdev_get_num_tc(dev)) 694 return netdev_pick_tx(dev, skb, NULL); 695 696 return netdev_pick_tx(dev, skb, NULL) % rings_p_up; 697 } 698 699 static void mlx4_bf_copy(void __iomem *dst, const void *src, 700 unsigned int bytecnt) 701 { 702 __iowrite64_copy(dst, src, bytecnt / 8); 703 } 704 705 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 706 { 707 wmb(); 708 /* Since there is no iowrite*_native() that writes the 709 * value as is, without byteswapping - using the one 710 * the doesn't do byteswapping in the relevant arch 711 * endianness. 712 */ 713 #if defined(__LITTLE_ENDIAN) 714 iowrite32( 715 #else 716 iowrite32be( 717 #endif 718 (__force u32)ring->doorbell_qpn, 719 ring->bf.uar->map + MLX4_SEND_DOORBELL); 720 } 721 722 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 723 struct mlx4_en_tx_desc *tx_desc, 724 union mlx4_wqe_qpn_vlan qpn_vlan, 725 int desc_size, int bf_index, 726 __be32 op_own, bool bf_ok, 727 bool send_doorbell) 728 { 729 tx_desc->ctrl.qpn_vlan = qpn_vlan; 730 731 if (bf_ok) { 732 op_own |= htonl((bf_index & 0xffff) << 8); 733 /* Ensure new descriptor hits memory 734 * before setting ownership of this descriptor to HW 735 */ 736 dma_wmb(); 737 tx_desc->ctrl.owner_opcode = op_own; 738 739 wmb(); 740 741 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 742 desc_size); 743 744 wmb(); 745 746 ring->bf.offset ^= ring->bf.buf_size; 747 } else { 748 /* Ensure new descriptor hits memory 749 * before setting ownership of this descriptor to HW 750 */ 751 dma_wmb(); 752 tx_desc->ctrl.owner_opcode = op_own; 753 if (send_doorbell) 754 mlx4_en_xmit_doorbell(ring); 755 else 756 ring->xmit_more++; 757 } 758 } 759 760 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, 761 struct skb_shared_info *shinfo, 762 struct mlx4_wqe_data_seg *data, 763 struct sk_buff *skb, 764 int lso_header_size, 765 __be32 mr_key, 766 struct mlx4_en_tx_info *tx_info) 767 { 768 struct device *ddev = priv->ddev; 769 dma_addr_t dma = 0; 770 u32 byte_count = 0; 771 int i_frag; 772 773 /* Map fragments if any */ 774 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 775 const struct skb_frag_struct *frag; 776 777 frag = &shinfo->frags[i_frag]; 778 byte_count = skb_frag_size(frag); 779 dma = skb_frag_dma_map(ddev, frag, 780 0, byte_count, 781 DMA_TO_DEVICE); 782 if (dma_mapping_error(ddev, dma)) 783 goto tx_drop_unmap; 784 785 data->addr = cpu_to_be64(dma); 786 data->lkey = mr_key; 787 dma_wmb(); 788 data->byte_count = cpu_to_be32(byte_count); 789 --data; 790 } 791 792 /* Map linear part if needed */ 793 if (tx_info->linear) { 794 byte_count = skb_headlen(skb) - lso_header_size; 795 796 dma = dma_map_single(ddev, skb->data + 797 lso_header_size, byte_count, 798 PCI_DMA_TODEVICE); 799 if (dma_mapping_error(ddev, dma)) 800 goto tx_drop_unmap; 801 802 data->addr = cpu_to_be64(dma); 803 data->lkey = mr_key; 804 dma_wmb(); 805 data->byte_count = cpu_to_be32(byte_count); 806 } 807 /* tx completion can avoid cache line miss for common cases */ 808 tx_info->map0_dma = dma; 809 tx_info->map0_byte_count = byte_count; 810 811 return true; 812 813 tx_drop_unmap: 814 en_err(priv, "DMA mapping error\n"); 815 816 while (++i_frag < shinfo->nr_frags) { 817 ++data; 818 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), 819 be32_to_cpu(data->byte_count), 820 PCI_DMA_TODEVICE); 821 } 822 823 return false; 824 } 825 826 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 827 { 828 struct skb_shared_info *shinfo = skb_shinfo(skb); 829 struct mlx4_en_priv *priv = netdev_priv(dev); 830 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 831 struct mlx4_en_tx_ring *ring; 832 struct mlx4_en_tx_desc *tx_desc; 833 struct mlx4_wqe_data_seg *data; 834 struct mlx4_en_tx_info *tx_info; 835 int tx_ind; 836 int nr_txbb; 837 int desc_size; 838 int real_size; 839 u32 index, bf_index; 840 __be32 op_own; 841 int lso_header_size; 842 void *fragptr = NULL; 843 bool bounce = false; 844 bool send_doorbell; 845 bool stop_queue; 846 bool inline_ok; 847 u8 data_offset; 848 u32 ring_cons; 849 bool bf_ok; 850 851 tx_ind = skb_get_queue_mapping(skb); 852 ring = priv->tx_ring[TX][tx_ind]; 853 854 if (unlikely(!priv->port_up)) 855 goto tx_drop; 856 857 /* fetch ring->cons far ahead before needing it to avoid stall */ 858 ring_cons = READ_ONCE(ring->cons); 859 860 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 861 &inline_ok, &fragptr); 862 if (unlikely(!real_size)) 863 goto tx_drop_count; 864 865 /* Align descriptor to TXBB size */ 866 desc_size = ALIGN(real_size, TXBB_SIZE); 867 nr_txbb = desc_size >> LOG_TXBB_SIZE; 868 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 869 if (netif_msg_tx_err(priv)) 870 en_warn(priv, "Oversized header or SG list\n"); 871 goto tx_drop_count; 872 } 873 874 bf_ok = ring->bf_enabled; 875 if (skb_vlan_tag_present(skb)) { 876 u16 vlan_proto; 877 878 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 879 vlan_proto = be16_to_cpu(skb->vlan_proto); 880 if (vlan_proto == ETH_P_8021AD) 881 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 882 else if (vlan_proto == ETH_P_8021Q) 883 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 884 else 885 qpn_vlan.ins_vlan = 0; 886 bf_ok = false; 887 } 888 889 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 890 891 /* Track current inflight packets for performance analysis */ 892 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 893 (u32)(ring->prod - ring_cons - 1)); 894 895 /* Packet is good - grab an index and transmit it */ 896 index = ring->prod & ring->size_mask; 897 bf_index = ring->prod; 898 899 /* See if we have enough space for whole descriptor TXBB for setting 900 * SW ownership on next descriptor; if not, use a bounce buffer. */ 901 if (likely(index + nr_txbb <= ring->size)) 902 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 903 else { 904 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 905 bounce = true; 906 bf_ok = false; 907 } 908 909 /* Save skb in tx_info ring */ 910 tx_info = &ring->tx_info[index]; 911 tx_info->skb = skb; 912 tx_info->nr_txbb = nr_txbb; 913 914 if (!lso_header_size) { 915 data = &tx_desc->data; 916 data_offset = offsetof(struct mlx4_en_tx_desc, data); 917 } else { 918 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE); 919 920 data = (void *)&tx_desc->lso + lso_align; 921 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; 922 } 923 924 /* valid only for none inline segments */ 925 tx_info->data_offset = data_offset; 926 927 tx_info->inl = inline_ok; 928 929 tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; 930 931 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 932 data += tx_info->nr_maps - 1; 933 934 if (!tx_info->inl) 935 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, 936 lso_header_size, ring->mr_key, 937 tx_info)) 938 goto tx_drop_count; 939 940 /* 941 * For timestamping add flag to skb_shinfo and 942 * set flag for further reference 943 */ 944 tx_info->ts_requested = 0; 945 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 946 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 947 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 948 tx_info->ts_requested = 1; 949 } 950 951 /* Prepare ctrl segement apart opcode+ownership, which depends on 952 * whether LSO is used */ 953 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 954 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 955 if (!skb->encapsulation) 956 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 957 MLX4_WQE_CTRL_TCP_UDP_CSUM); 958 else 959 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 960 ring->tx_csum++; 961 } 962 963 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 964 struct ethhdr *ethh; 965 966 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 967 * so that VFs and PF can communicate with each other 968 */ 969 ethh = (struct ethhdr *)skb->data; 970 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 971 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 972 } 973 974 /* Handle LSO (TSO) packets */ 975 if (lso_header_size) { 976 int i; 977 978 /* Mark opcode as LSO */ 979 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 980 ((ring->prod & ring->size) ? 981 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 982 983 /* Fill in the LSO prefix */ 984 tx_desc->lso.mss_hdr_size = cpu_to_be32( 985 shinfo->gso_size << 16 | lso_header_size); 986 987 /* Copy headers; 988 * note that we already verified that it is linear */ 989 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 990 991 ring->tso_packets++; 992 993 i = shinfo->gso_segs; 994 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 995 ring->packets += i; 996 } else { 997 /* Normal (Non LSO) packet */ 998 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 999 ((ring->prod & ring->size) ? 1000 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1001 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 1002 ring->packets++; 1003 } 1004 ring->bytes += tx_info->nr_bytes; 1005 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 1006 1007 if (tx_info->inl) 1008 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 1009 1010 if (skb->encapsulation) { 1011 union { 1012 struct iphdr *v4; 1013 struct ipv6hdr *v6; 1014 unsigned char *hdr; 1015 } ip; 1016 u8 proto; 1017 1018 ip.hdr = skb_inner_network_header(skb); 1019 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1020 ip.v6->nexthdr; 1021 1022 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1023 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1024 else 1025 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1026 } 1027 1028 ring->prod += nr_txbb; 1029 1030 /* If we used a bounce buffer then copy descriptor back into place */ 1031 if (unlikely(bounce)) 1032 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1033 1034 skb_tx_timestamp(skb); 1035 1036 /* Check available TXBBs And 2K spare for prefetch */ 1037 stop_queue = mlx4_en_is_tx_ring_full(ring); 1038 if (unlikely(stop_queue)) { 1039 netif_tx_stop_queue(ring->tx_queue); 1040 ring->queue_stopped++; 1041 } 1042 1043 send_doorbell = __netdev_tx_sent_queue(ring->tx_queue, 1044 tx_info->nr_bytes, 1045 netdev_xmit_more()); 1046 1047 real_size = (real_size / 16) & 0x3f; 1048 1049 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1050 1051 if (bf_ok) 1052 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1053 else 1054 qpn_vlan.fence_size = real_size; 1055 1056 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1057 op_own, bf_ok, send_doorbell); 1058 1059 if (unlikely(stop_queue)) { 1060 /* If queue was emptied after the if (stop_queue) , and before 1061 * the netif_tx_stop_queue() - need to wake the queue, 1062 * or else it will remain stopped forever. 1063 * Need a memory barrier to make sure ring->cons was not 1064 * updated before queue was stopped. 1065 */ 1066 smp_rmb(); 1067 1068 ring_cons = READ_ONCE(ring->cons); 1069 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1070 netif_tx_wake_queue(ring->tx_queue); 1071 ring->wake_queue++; 1072 } 1073 } 1074 return NETDEV_TX_OK; 1075 1076 tx_drop_count: 1077 ring->tx_dropped++; 1078 tx_drop: 1079 dev_kfree_skb_any(skb); 1080 return NETDEV_TX_OK; 1081 } 1082 1083 #define MLX4_EN_XDP_TX_NRTXBB 1 1084 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ 1085 / 16) & 0x3f) 1086 1087 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 1088 struct mlx4_en_tx_ring *ring) 1089 { 1090 int i; 1091 1092 for (i = 0; i < ring->size; i++) { 1093 struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; 1094 struct mlx4_en_tx_desc *tx_desc = ring->buf + 1095 (i << LOG_TXBB_SIZE); 1096 1097 tx_info->map0_byte_count = PAGE_SIZE; 1098 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; 1099 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); 1100 tx_info->ts_requested = 0; 1101 tx_info->nr_maps = 1; 1102 tx_info->linear = 1; 1103 tx_info->inl = 0; 1104 1105 tx_desc->data.lkey = ring->mr_key; 1106 tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; 1107 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1108 } 1109 } 1110 1111 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1112 struct mlx4_en_rx_alloc *frame, 1113 struct mlx4_en_priv *priv, unsigned int length, 1114 int tx_ind, bool *doorbell_pending) 1115 { 1116 struct mlx4_en_tx_desc *tx_desc; 1117 struct mlx4_en_tx_info *tx_info; 1118 struct mlx4_wqe_data_seg *data; 1119 struct mlx4_en_tx_ring *ring; 1120 dma_addr_t dma; 1121 __be32 op_own; 1122 int index; 1123 1124 if (unlikely(!priv->port_up)) 1125 goto tx_drop; 1126 1127 ring = priv->tx_ring[TX_XDP][tx_ind]; 1128 1129 if (unlikely(mlx4_en_is_tx_ring_full(ring))) 1130 goto tx_drop_count; 1131 1132 index = ring->prod & ring->size_mask; 1133 tx_info = &ring->tx_info[index]; 1134 1135 /* Track current inflight packets for performance analysis */ 1136 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1137 (u32)(ring->prod - READ_ONCE(ring->cons) - 1)); 1138 1139 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 1140 data = &tx_desc->data; 1141 1142 dma = frame->dma; 1143 1144 tx_info->page = frame->page; 1145 frame->page = NULL; 1146 tx_info->map0_dma = dma; 1147 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1148 1149 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1150 length, PCI_DMA_TODEVICE); 1151 1152 data->addr = cpu_to_be64(dma + frame->page_offset); 1153 dma_wmb(); 1154 data->byte_count = cpu_to_be32(length); 1155 1156 /* tx completion can avoid cache line miss for common cases */ 1157 1158 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1159 ((ring->prod & ring->size) ? 1160 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1161 1162 rx_ring->xdp_tx++; 1163 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1164 1165 ring->prod += MLX4_EN_XDP_TX_NRTXBB; 1166 1167 /* Ensure new descriptor hits memory 1168 * before setting ownership of this descriptor to HW 1169 */ 1170 dma_wmb(); 1171 tx_desc->ctrl.owner_opcode = op_own; 1172 ring->xmit_more++; 1173 1174 *doorbell_pending = true; 1175 1176 return NETDEV_TX_OK; 1177 1178 tx_drop_count: 1179 rx_ring->xdp_tx_full++; 1180 *doorbell_pending = true; 1181 tx_drop: 1182 return NETDEV_TX_BUSY; 1183 } 1184