1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/vmalloc.h> 41 #include <linux/tcp.h> 42 #include <linux/moduleparam.h> 43 44 #include "mlx4_en.h" 45 46 enum { 47 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 48 MAX_BF = 256, 49 }; 50 51 static int inline_thold __read_mostly = MAX_INLINE; 52 53 module_param_named(inline_thold, inline_thold, int, 0444); 54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); 55 56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 57 struct mlx4_en_tx_ring **pring, int qpn, u32 size, 58 u16 stride, int node) 59 { 60 struct mlx4_en_dev *mdev = priv->mdev; 61 struct mlx4_en_tx_ring *ring; 62 int tmp; 63 int err; 64 65 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 66 if (!ring) { 67 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 68 if (!ring) { 69 en_err(priv, "Failed allocating TX ring\n"); 70 return -ENOMEM; 71 } 72 } 73 74 ring->size = size; 75 ring->size_mask = size - 1; 76 ring->stride = stride; 77 78 inline_thold = min(inline_thold, MAX_INLINE); 79 80 tmp = size * sizeof(struct mlx4_en_tx_info); 81 ring->tx_info = vmalloc_node(tmp, node); 82 if (!ring->tx_info) { 83 ring->tx_info = vmalloc(tmp); 84 if (!ring->tx_info) { 85 err = -ENOMEM; 86 goto err_ring; 87 } 88 } 89 90 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 91 ring->tx_info, tmp); 92 93 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 94 if (!ring->bounce_buf) { 95 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 96 if (!ring->bounce_buf) { 97 err = -ENOMEM; 98 goto err_info; 99 } 100 } 101 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 102 103 /* Allocate HW buffers on provided NUMA node */ 104 set_dev_node(&mdev->dev->pdev->dev, node); 105 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 106 2 * PAGE_SIZE); 107 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 108 if (err) { 109 en_err(priv, "Failed allocating hwq resources\n"); 110 goto err_bounce; 111 } 112 113 err = mlx4_en_map_buffer(&ring->wqres.buf); 114 if (err) { 115 en_err(priv, "Failed to map TX buffer\n"); 116 goto err_hwq_res; 117 } 118 119 ring->buf = ring->wqres.buf.direct.buf; 120 121 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " 122 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, 123 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); 124 125 ring->qpn = qpn; 126 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); 127 if (err) { 128 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 129 goto err_map; 130 } 131 ring->qp.event = mlx4_en_sqp_event; 132 133 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 134 if (err) { 135 en_dbg(DRV, priv, "working without blueflame (%d)", err); 136 ring->bf.uar = &mdev->priv_uar; 137 ring->bf.uar->map = mdev->uar_map; 138 ring->bf_enabled = false; 139 } else 140 ring->bf_enabled = true; 141 142 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 143 144 *pring = ring; 145 return 0; 146 147 err_map: 148 mlx4_en_unmap_buffer(&ring->wqres.buf); 149 err_hwq_res: 150 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 151 err_bounce: 152 kfree(ring->bounce_buf); 153 ring->bounce_buf = NULL; 154 err_info: 155 vfree(ring->tx_info); 156 ring->tx_info = NULL; 157 err_ring: 158 kfree(ring); 159 *pring = NULL; 160 return err; 161 } 162 163 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 164 struct mlx4_en_tx_ring **pring) 165 { 166 struct mlx4_en_dev *mdev = priv->mdev; 167 struct mlx4_en_tx_ring *ring = *pring; 168 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 169 170 if (ring->bf_enabled) 171 mlx4_bf_free(mdev->dev, &ring->bf); 172 mlx4_qp_remove(mdev->dev, &ring->qp); 173 mlx4_qp_free(mdev->dev, &ring->qp); 174 mlx4_en_unmap_buffer(&ring->wqres.buf); 175 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 176 kfree(ring->bounce_buf); 177 ring->bounce_buf = NULL; 178 vfree(ring->tx_info); 179 ring->tx_info = NULL; 180 kfree(ring); 181 *pring = NULL; 182 } 183 184 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 185 struct mlx4_en_tx_ring *ring, 186 int cq, int user_prio) 187 { 188 struct mlx4_en_dev *mdev = priv->mdev; 189 int err; 190 191 ring->cqn = cq; 192 ring->prod = 0; 193 ring->cons = 0xffffffff; 194 ring->last_nr_txbb = 1; 195 ring->poll_cnt = 0; 196 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 197 memset(ring->buf, 0, ring->buf_size); 198 199 ring->qp_state = MLX4_QP_STATE_RST; 200 ring->doorbell_qpn = ring->qp.qpn << 8; 201 202 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 203 ring->cqn, user_prio, &ring->context); 204 if (ring->bf_enabled) 205 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); 206 207 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 208 &ring->qp, &ring->qp_state); 209 210 return err; 211 } 212 213 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 214 struct mlx4_en_tx_ring *ring) 215 { 216 struct mlx4_en_dev *mdev = priv->mdev; 217 218 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 219 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 220 } 221 222 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 223 struct mlx4_en_tx_ring *ring, int index, 224 u8 owner) 225 { 226 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 227 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 228 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 229 void *end = ring->buf + ring->buf_size; 230 __be32 *ptr = (__be32 *)tx_desc; 231 int i; 232 233 /* Optimize the common case when there are no wraparounds */ 234 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 235 /* Stamp the freed descriptor */ 236 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 237 i += STAMP_STRIDE) { 238 *ptr = stamp; 239 ptr += STAMP_DWORDS; 240 } 241 } else { 242 /* Stamp the freed descriptor */ 243 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 244 i += STAMP_STRIDE) { 245 *ptr = stamp; 246 ptr += STAMP_DWORDS; 247 if ((void *)ptr >= end) { 248 ptr = ring->buf; 249 stamp ^= cpu_to_be32(0x80000000); 250 } 251 } 252 } 253 } 254 255 256 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 257 struct mlx4_en_tx_ring *ring, 258 int index, u8 owner, u64 timestamp) 259 { 260 struct mlx4_en_dev *mdev = priv->mdev; 261 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 262 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 263 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 264 struct sk_buff *skb = tx_info->skb; 265 struct skb_frag_struct *frag; 266 void *end = ring->buf + ring->buf_size; 267 int frags = skb_shinfo(skb)->nr_frags; 268 int i; 269 struct skb_shared_hwtstamps hwts; 270 271 if (timestamp) { 272 mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp); 273 skb_tstamp_tx(skb, &hwts); 274 } 275 276 /* Optimize the common case when there are no wraparounds */ 277 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 278 if (!tx_info->inl) { 279 if (tx_info->linear) { 280 dma_unmap_single(priv->ddev, 281 (dma_addr_t) be64_to_cpu(data->addr), 282 be32_to_cpu(data->byte_count), 283 PCI_DMA_TODEVICE); 284 ++data; 285 } 286 287 for (i = 0; i < frags; i++) { 288 frag = &skb_shinfo(skb)->frags[i]; 289 dma_unmap_page(priv->ddev, 290 (dma_addr_t) be64_to_cpu(data[i].addr), 291 skb_frag_size(frag), PCI_DMA_TODEVICE); 292 } 293 } 294 } else { 295 if (!tx_info->inl) { 296 if ((void *) data >= end) { 297 data = ring->buf + ((void *)data - end); 298 } 299 300 if (tx_info->linear) { 301 dma_unmap_single(priv->ddev, 302 (dma_addr_t) be64_to_cpu(data->addr), 303 be32_to_cpu(data->byte_count), 304 PCI_DMA_TODEVICE); 305 ++data; 306 } 307 308 for (i = 0; i < frags; i++) { 309 /* Check for wraparound before unmapping */ 310 if ((void *) data >= end) 311 data = ring->buf; 312 frag = &skb_shinfo(skb)->frags[i]; 313 dma_unmap_page(priv->ddev, 314 (dma_addr_t) be64_to_cpu(data->addr), 315 skb_frag_size(frag), PCI_DMA_TODEVICE); 316 ++data; 317 } 318 } 319 } 320 dev_kfree_skb_any(skb); 321 return tx_info->nr_txbb; 322 } 323 324 325 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 326 { 327 struct mlx4_en_priv *priv = netdev_priv(dev); 328 int cnt = 0; 329 330 /* Skip last polled descriptor */ 331 ring->cons += ring->last_nr_txbb; 332 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 333 ring->cons, ring->prod); 334 335 if ((u32) (ring->prod - ring->cons) > ring->size) { 336 if (netif_msg_tx_err(priv)) 337 en_warn(priv, "Tx consumer passed producer!\n"); 338 return 0; 339 } 340 341 while (ring->cons != ring->prod) { 342 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 343 ring->cons & ring->size_mask, 344 !!(ring->cons & ring->size), 0); 345 ring->cons += ring->last_nr_txbb; 346 cnt++; 347 } 348 349 netdev_tx_reset_queue(ring->tx_queue); 350 351 if (cnt) 352 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 353 354 return cnt; 355 } 356 357 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) 358 { 359 struct mlx4_en_priv *priv = netdev_priv(dev); 360 struct mlx4_cq *mcq = &cq->mcq; 361 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 362 struct mlx4_cqe *cqe; 363 u16 index; 364 u16 new_index, ring_index, stamp_index; 365 u32 txbbs_skipped = 0; 366 u32 txbbs_stamp = 0; 367 u32 cons_index = mcq->cons_index; 368 int size = cq->size; 369 u32 size_mask = ring->size_mask; 370 struct mlx4_cqe *buf = cq->buf; 371 u32 packets = 0; 372 u32 bytes = 0; 373 int factor = priv->cqe_factor; 374 u64 timestamp = 0; 375 376 if (!priv->port_up) 377 return; 378 379 index = cons_index & size_mask; 380 cqe = &buf[(index << factor) + factor]; 381 ring_index = ring->cons & size_mask; 382 stamp_index = ring_index; 383 384 /* Process all completed CQEs */ 385 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 386 cons_index & size)) { 387 /* 388 * make sure we read the CQE after we read the 389 * ownership bit 390 */ 391 rmb(); 392 393 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 394 MLX4_CQE_OPCODE_ERROR)) { 395 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 396 397 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 398 cqe_err->vendor_err_syndrome, 399 cqe_err->syndrome); 400 } 401 402 /* Skip over last polled CQE */ 403 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 404 405 do { 406 txbbs_skipped += ring->last_nr_txbb; 407 ring_index = (ring_index + ring->last_nr_txbb) & size_mask; 408 if (ring->tx_info[ring_index].ts_requested) 409 timestamp = mlx4_en_get_cqe_ts(cqe); 410 411 /* free next descriptor */ 412 ring->last_nr_txbb = mlx4_en_free_tx_desc( 413 priv, ring, ring_index, 414 !!((ring->cons + txbbs_skipped) & 415 ring->size), timestamp); 416 417 mlx4_en_stamp_wqe(priv, ring, stamp_index, 418 !!((ring->cons + txbbs_stamp) & 419 ring->size)); 420 stamp_index = ring_index; 421 txbbs_stamp = txbbs_skipped; 422 packets++; 423 bytes += ring->tx_info[ring_index].nr_bytes; 424 } while (ring_index != new_index); 425 426 ++cons_index; 427 index = cons_index & size_mask; 428 cqe = &buf[(index << factor) + factor]; 429 } 430 431 432 /* 433 * To prevent CQ overflow we first update CQ consumer and only then 434 * the ring consumer. 435 */ 436 mcq->cons_index = cons_index; 437 mlx4_cq_set_ci(mcq); 438 wmb(); 439 ring->cons += txbbs_skipped; 440 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 441 442 /* 443 * Wakeup Tx queue if this stopped, and at least 1 packet 444 * was completed 445 */ 446 if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { 447 netif_tx_wake_queue(ring->tx_queue); 448 priv->port_stats.wake_queue++; 449 } 450 } 451 452 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 453 { 454 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 455 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 456 457 mlx4_en_process_tx_cq(cq->dev, cq); 458 mlx4_en_arm_cq(priv, cq); 459 } 460 461 462 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 463 struct mlx4_en_tx_ring *ring, 464 u32 index, 465 unsigned int desc_size) 466 { 467 u32 copy = (ring->size - index) * TXBB_SIZE; 468 int i; 469 470 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 471 if ((i & (TXBB_SIZE - 1)) == 0) 472 wmb(); 473 474 *((u32 *) (ring->buf + i)) = 475 *((u32 *) (ring->bounce_buf + copy + i)); 476 } 477 478 for (i = copy - 4; i >= 4 ; i -= 4) { 479 if ((i & (TXBB_SIZE - 1)) == 0) 480 wmb(); 481 482 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 483 *((u32 *) (ring->bounce_buf + i)); 484 } 485 486 /* Return real descriptor location */ 487 return ring->buf + index * TXBB_SIZE; 488 } 489 490 static int is_inline(struct sk_buff *skb, void **pfrag) 491 { 492 void *ptr; 493 494 if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { 495 if (skb_shinfo(skb)->nr_frags == 1) { 496 ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); 497 if (unlikely(!ptr)) 498 return 0; 499 500 if (pfrag) 501 *pfrag = ptr; 502 503 return 1; 504 } else if (unlikely(skb_shinfo(skb)->nr_frags)) 505 return 0; 506 else 507 return 1; 508 } 509 510 return 0; 511 } 512 513 static int inline_size(struct sk_buff *skb) 514 { 515 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 516 <= MLX4_INLINE_ALIGN) 517 return ALIGN(skb->len + CTRL_SIZE + 518 sizeof(struct mlx4_wqe_inline_seg), 16); 519 else 520 return ALIGN(skb->len + CTRL_SIZE + 2 * 521 sizeof(struct mlx4_wqe_inline_seg), 16); 522 } 523 524 static int get_real_size(struct sk_buff *skb, struct net_device *dev, 525 int *lso_header_size) 526 { 527 struct mlx4_en_priv *priv = netdev_priv(dev); 528 int real_size; 529 530 if (skb_is_gso(skb)) { 531 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 532 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + 533 ALIGN(*lso_header_size + 4, DS_SIZE); 534 if (unlikely(*lso_header_size != skb_headlen(skb))) { 535 /* We add a segment for the skb linear buffer only if 536 * it contains data */ 537 if (*lso_header_size < skb_headlen(skb)) 538 real_size += DS_SIZE; 539 else { 540 if (netif_msg_tx_err(priv)) 541 en_warn(priv, "Non-linear headers\n"); 542 return 0; 543 } 544 } 545 } else { 546 *lso_header_size = 0; 547 if (!is_inline(skb, NULL)) 548 real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; 549 else 550 real_size = inline_size(skb); 551 } 552 553 return real_size; 554 } 555 556 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, 557 int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) 558 { 559 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 560 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 561 562 if (skb->len <= spc) { 563 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 564 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 565 if (skb_shinfo(skb)->nr_frags) 566 memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, 567 skb_frag_size(&skb_shinfo(skb)->frags[0])); 568 569 } else { 570 inl->byte_count = cpu_to_be32(1 << 31 | spc); 571 if (skb_headlen(skb) <= spc) { 572 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); 573 if (skb_headlen(skb) < spc) { 574 memcpy(((void *)(inl + 1)) + skb_headlen(skb), 575 fragptr, spc - skb_headlen(skb)); 576 fragptr += spc - skb_headlen(skb); 577 } 578 inl = (void *) (inl + 1) + spc; 579 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 580 } else { 581 skb_copy_from_linear_data(skb, inl + 1, spc); 582 inl = (void *) (inl + 1) + spc; 583 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 584 skb_headlen(skb) - spc); 585 if (skb_shinfo(skb)->nr_frags) 586 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, 587 fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); 588 } 589 590 wmb(); 591 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 592 } 593 } 594 595 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 596 void *accel_priv) 597 { 598 struct mlx4_en_priv *priv = netdev_priv(dev); 599 u16 rings_p_up = priv->num_tx_rings_p_up; 600 u8 up = 0; 601 602 if (dev->num_tc) 603 return skb_tx_hash(dev, skb); 604 605 if (vlan_tx_tag_present(skb)) 606 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; 607 608 return __netdev_pick_tx(dev, skb) % rings_p_up + up * rings_p_up; 609 } 610 611 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt) 612 { 613 __iowrite64_copy(dst, src, bytecnt / 8); 614 } 615 616 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 617 { 618 struct mlx4_en_priv *priv = netdev_priv(dev); 619 struct mlx4_en_dev *mdev = priv->mdev; 620 struct device *ddev = priv->ddev; 621 struct mlx4_en_tx_ring *ring; 622 struct mlx4_en_tx_desc *tx_desc; 623 struct mlx4_wqe_data_seg *data; 624 struct mlx4_en_tx_info *tx_info; 625 int tx_ind = 0; 626 int nr_txbb; 627 int desc_size; 628 int real_size; 629 u32 index, bf_index; 630 __be32 op_own; 631 u16 vlan_tag = 0; 632 int i; 633 int lso_header_size; 634 void *fragptr; 635 bool bounce = false; 636 637 if (!priv->port_up) 638 goto tx_drop; 639 640 real_size = get_real_size(skb, dev, &lso_header_size); 641 if (unlikely(!real_size)) 642 goto tx_drop; 643 644 /* Align descriptor to TXBB size */ 645 desc_size = ALIGN(real_size, TXBB_SIZE); 646 nr_txbb = desc_size / TXBB_SIZE; 647 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 648 if (netif_msg_tx_err(priv)) 649 en_warn(priv, "Oversized header or SG list\n"); 650 goto tx_drop; 651 } 652 653 tx_ind = skb->queue_mapping; 654 ring = priv->tx_ring[tx_ind]; 655 if (vlan_tx_tag_present(skb)) 656 vlan_tag = vlan_tx_tag_get(skb); 657 658 /* Check available TXBBs And 2K spare for prefetch */ 659 if (unlikely(((int)(ring->prod - ring->cons)) > 660 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 661 /* every full Tx ring stops queue */ 662 netif_tx_stop_queue(ring->tx_queue); 663 priv->port_stats.queue_stopped++; 664 665 /* If queue was emptied after the if, and before the 666 * stop_queue - need to wake the queue, or else it will remain 667 * stopped forever. 668 * Need a memory barrier to make sure ring->cons was not 669 * updated before queue was stopped. 670 */ 671 wmb(); 672 673 if (unlikely(((int)(ring->prod - ring->cons)) <= 674 ring->size - HEADROOM - MAX_DESC_TXBBS)) { 675 netif_tx_wake_queue(ring->tx_queue); 676 priv->port_stats.wake_queue++; 677 } else { 678 return NETDEV_TX_BUSY; 679 } 680 } 681 682 /* Track current inflight packets for performance analysis */ 683 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 684 (u32) (ring->prod - ring->cons - 1)); 685 686 /* Packet is good - grab an index and transmit it */ 687 index = ring->prod & ring->size_mask; 688 bf_index = ring->prod; 689 690 /* See if we have enough space for whole descriptor TXBB for setting 691 * SW ownership on next descriptor; if not, use a bounce buffer. */ 692 if (likely(index + nr_txbb <= ring->size)) 693 tx_desc = ring->buf + index * TXBB_SIZE; 694 else { 695 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 696 bounce = true; 697 } 698 699 /* Save skb in tx_info ring */ 700 tx_info = &ring->tx_info[index]; 701 tx_info->skb = skb; 702 tx_info->nr_txbb = nr_txbb; 703 704 if (lso_header_size) 705 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 706 DS_SIZE)); 707 else 708 data = &tx_desc->data; 709 710 /* valid only for none inline segments */ 711 tx_info->data_offset = (void *)data - (void *)tx_desc; 712 713 tx_info->linear = (lso_header_size < skb_headlen(skb) && 714 !is_inline(skb, NULL)) ? 1 : 0; 715 716 data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; 717 718 if (is_inline(skb, &fragptr)) { 719 tx_info->inl = 1; 720 } else { 721 /* Map fragments */ 722 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { 723 struct skb_frag_struct *frag; 724 dma_addr_t dma; 725 726 frag = &skb_shinfo(skb)->frags[i]; 727 dma = skb_frag_dma_map(ddev, frag, 728 0, skb_frag_size(frag), 729 DMA_TO_DEVICE); 730 if (dma_mapping_error(ddev, dma)) 731 goto tx_drop_unmap; 732 733 data->addr = cpu_to_be64(dma); 734 data->lkey = cpu_to_be32(mdev->mr.key); 735 wmb(); 736 data->byte_count = cpu_to_be32(skb_frag_size(frag)); 737 --data; 738 } 739 740 /* Map linear part */ 741 if (tx_info->linear) { 742 u32 byte_count = skb_headlen(skb) - lso_header_size; 743 dma_addr_t dma; 744 745 dma = dma_map_single(ddev, skb->data + 746 lso_header_size, byte_count, 747 PCI_DMA_TODEVICE); 748 if (dma_mapping_error(ddev, dma)) 749 goto tx_drop_unmap; 750 751 data->addr = cpu_to_be64(dma); 752 data->lkey = cpu_to_be32(mdev->mr.key); 753 wmb(); 754 data->byte_count = cpu_to_be32(byte_count); 755 } 756 tx_info->inl = 0; 757 } 758 759 /* 760 * For timestamping add flag to skb_shinfo and 761 * set flag for further reference 762 */ 763 if (ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 764 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 765 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 766 tx_info->ts_requested = 1; 767 } 768 769 /* Prepare ctrl segement apart opcode+ownership, which depends on 770 * whether LSO is used */ 771 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); 772 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * 773 !!vlan_tx_tag_present(skb); 774 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; 775 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 776 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 777 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 778 MLX4_WQE_CTRL_TCP_UDP_CSUM); 779 ring->tx_csum++; 780 } 781 782 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 783 struct ethhdr *ethh; 784 785 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 786 * so that VFs and PF can communicate with each other 787 */ 788 ethh = (struct ethhdr *)skb->data; 789 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 790 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 791 } 792 793 /* Handle LSO (TSO) packets */ 794 if (lso_header_size) { 795 /* Mark opcode as LSO */ 796 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 797 ((ring->prod & ring->size) ? 798 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 799 800 /* Fill in the LSO prefix */ 801 tx_desc->lso.mss_hdr_size = cpu_to_be32( 802 skb_shinfo(skb)->gso_size << 16 | lso_header_size); 803 804 /* Copy headers; 805 * note that we already verified that it is linear */ 806 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 807 808 priv->port_stats.tso_packets++; 809 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + 810 !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); 811 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 812 ring->packets += i; 813 } else { 814 /* Normal (Non LSO) packet */ 815 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 816 ((ring->prod & ring->size) ? 817 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 818 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 819 ring->packets++; 820 821 } 822 ring->bytes += tx_info->nr_bytes; 823 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 824 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 825 826 if (tx_info->inl) { 827 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); 828 tx_info->inl = 1; 829 } 830 831 ring->prod += nr_txbb; 832 833 /* If we used a bounce buffer then copy descriptor back into place */ 834 if (bounce) 835 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 836 837 skb_tx_timestamp(skb); 838 839 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) { 840 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn); 841 op_own |= htonl((bf_index & 0xffff) << 8); 842 /* Ensure new descirptor hits memory 843 * before setting ownership of this descriptor to HW */ 844 wmb(); 845 tx_desc->ctrl.owner_opcode = op_own; 846 847 wmb(); 848 849 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, 850 desc_size); 851 852 wmb(); 853 854 ring->bf.offset ^= ring->bf.buf_size; 855 } else { 856 /* Ensure new descirptor hits memory 857 * before setting ownership of this descriptor to HW */ 858 wmb(); 859 tx_desc->ctrl.owner_opcode = op_own; 860 wmb(); 861 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); 862 } 863 864 return NETDEV_TX_OK; 865 866 tx_drop_unmap: 867 en_err(priv, "DMA mapping error\n"); 868 869 for (i++; i < skb_shinfo(skb)->nr_frags; i++) { 870 data++; 871 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 872 be32_to_cpu(data->byte_count), 873 PCI_DMA_TODEVICE); 874 } 875 876 tx_drop: 877 dev_kfree_skb_any(skb); 878 priv->stats.tx_dropped++; 879 return NETDEV_TX_OK; 880 } 881 882