1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 #include <linux/indirect_call_wrapper.h> 47 48 #include "mlx4_en.h" 49 50 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 51 struct mlx4_en_tx_ring **pring, u32 size, 52 u16 stride, int node, int queue_index) 53 { 54 struct mlx4_en_dev *mdev = priv->mdev; 55 struct mlx4_en_tx_ring *ring; 56 int tmp; 57 int err; 58 59 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 60 if (!ring) { 61 en_err(priv, "Failed allocating TX ring\n"); 62 return -ENOMEM; 63 } 64 65 ring->size = size; 66 ring->size_mask = size - 1; 67 ring->sp_stride = stride; 68 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 69 70 tmp = size * sizeof(struct mlx4_en_tx_info); 71 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); 72 if (!ring->tx_info) { 73 err = -ENOMEM; 74 goto err_ring; 75 } 76 77 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 78 ring->tx_info, tmp); 79 80 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 81 if (!ring->bounce_buf) { 82 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 83 if (!ring->bounce_buf) { 84 err = -ENOMEM; 85 goto err_info; 86 } 87 } 88 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 89 90 /* Allocate HW buffers on provided NUMA node */ 91 set_dev_node(&mdev->dev->persist->pdev->dev, node); 92 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 93 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 94 if (err) { 95 en_err(priv, "Failed allocating hwq resources\n"); 96 goto err_bounce; 97 } 98 99 ring->buf = ring->sp_wqres.buf.direct.buf; 100 101 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 102 ring, ring->buf, ring->size, ring->buf_size, 103 (unsigned long long) ring->sp_wqres.buf.direct.map); 104 105 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 106 MLX4_RESERVE_ETH_BF_QP, 107 MLX4_RES_USAGE_DRIVER); 108 if (err) { 109 en_err(priv, "failed reserving qp for TX ring\n"); 110 goto err_hwq_res; 111 } 112 113 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); 114 if (err) { 115 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 116 goto err_reserve; 117 } 118 ring->sp_qp.event = mlx4_en_sqp_event; 119 120 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 121 if (err) { 122 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 123 ring->bf.uar = &mdev->priv_uar; 124 ring->bf.uar->map = mdev->uar_map; 125 ring->bf_enabled = false; 126 ring->bf_alloced = false; 127 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 128 } else { 129 ring->bf_alloced = true; 130 ring->bf_enabled = !!(priv->pflags & 131 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 132 } 133 ring->doorbell_address = ring->bf.uar->map + MLX4_SEND_DOORBELL; 134 135 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 136 ring->queue_index = queue_index; 137 138 if (queue_index < priv->num_tx_rings_p_up) 139 cpumask_set_cpu(cpumask_local_spread(queue_index, 140 priv->mdev->dev->numa_node), 141 &ring->sp_affinity_mask); 142 143 *pring = ring; 144 return 0; 145 146 err_reserve: 147 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 148 err_hwq_res: 149 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 150 err_bounce: 151 kfree(ring->bounce_buf); 152 ring->bounce_buf = NULL; 153 err_info: 154 kvfree(ring->tx_info); 155 ring->tx_info = NULL; 156 err_ring: 157 kfree(ring); 158 *pring = NULL; 159 return err; 160 } 161 162 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 163 struct mlx4_en_tx_ring **pring) 164 { 165 struct mlx4_en_dev *mdev = priv->mdev; 166 struct mlx4_en_tx_ring *ring = *pring; 167 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 168 169 if (ring->bf_alloced) 170 mlx4_bf_free(mdev->dev, &ring->bf); 171 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 172 mlx4_qp_free(mdev->dev, &ring->sp_qp); 173 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 174 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 175 kfree(ring->bounce_buf); 176 ring->bounce_buf = NULL; 177 kvfree(ring->tx_info); 178 ring->tx_info = NULL; 179 kfree(ring); 180 *pring = NULL; 181 } 182 183 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 184 struct mlx4_en_tx_ring *ring, 185 int cq, int user_prio) 186 { 187 struct mlx4_en_dev *mdev = priv->mdev; 188 int err; 189 190 ring->sp_cqn = cq; 191 ring->prod = 0; 192 ring->cons = 0xffffffff; 193 ring->last_nr_txbb = 1; 194 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 195 memset(ring->buf, 0, ring->buf_size); 196 ring->free_tx_desc = mlx4_en_free_tx_desc; 197 198 ring->sp_qp_state = MLX4_QP_STATE_RST; 199 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 200 ring->mr_key = cpu_to_be32(mdev->mr.key); 201 202 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 203 ring->sp_cqn, user_prio, &ring->sp_context); 204 if (ring->bf_alloced) 205 ring->sp_context.usr_page = 206 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 207 ring->bf.uar->index)); 208 209 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 210 &ring->sp_qp, &ring->sp_qp_state); 211 if (!cpumask_empty(&ring->sp_affinity_mask)) 212 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 213 ring->queue_index); 214 215 return err; 216 } 217 218 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 219 struct mlx4_en_tx_ring *ring) 220 { 221 struct mlx4_en_dev *mdev = priv->mdev; 222 223 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 224 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 225 } 226 227 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 228 { 229 return ring->prod - ring->cons > ring->full_size; 230 } 231 232 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 233 struct mlx4_en_tx_ring *ring, int index, 234 u8 owner) 235 { 236 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 237 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 238 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 239 void *end = ring->buf + ring->buf_size; 240 __be32 *ptr = (__be32 *)tx_desc; 241 int i; 242 243 /* Optimize the common case when there are no wraparounds */ 244 if (likely((void *)tx_desc + 245 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 246 /* Stamp the freed descriptor */ 247 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 248 i += STAMP_STRIDE) { 249 *ptr = stamp; 250 ptr += STAMP_DWORDS; 251 } 252 } else { 253 /* Stamp the freed descriptor */ 254 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 255 i += STAMP_STRIDE) { 256 *ptr = stamp; 257 ptr += STAMP_DWORDS; 258 if ((void *)ptr >= end) { 259 ptr = ring->buf; 260 stamp ^= cpu_to_be32(0x80000000); 261 } 262 } 263 } 264 } 265 266 INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 267 struct mlx4_en_tx_ring *ring, 268 int index, u64 timestamp, 269 int napi_mode)); 270 271 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 272 struct mlx4_en_tx_ring *ring, 273 int index, u64 timestamp, 274 int napi_mode) 275 { 276 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 277 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 278 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 279 void *end = ring->buf + ring->buf_size; 280 struct sk_buff *skb = tx_info->skb; 281 int nr_maps = tx_info->nr_maps; 282 int i; 283 284 /* We do not touch skb here, so prefetch skb->users location 285 * to speedup consume_skb() 286 */ 287 prefetchw(&skb->users); 288 289 if (unlikely(timestamp)) { 290 struct skb_shared_hwtstamps hwts; 291 292 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 293 skb_tstamp_tx(skb, &hwts); 294 } 295 296 if (!tx_info->inl) { 297 if (tx_info->linear) 298 dma_unmap_single(priv->ddev, 299 tx_info->map0_dma, 300 tx_info->map0_byte_count, 301 DMA_TO_DEVICE); 302 else 303 dma_unmap_page(priv->ddev, 304 tx_info->map0_dma, 305 tx_info->map0_byte_count, 306 DMA_TO_DEVICE); 307 /* Optimize the common case when there are no wraparounds */ 308 if (likely((void *)tx_desc + 309 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 310 for (i = 1; i < nr_maps; i++) { 311 data++; 312 dma_unmap_page(priv->ddev, 313 (dma_addr_t)be64_to_cpu(data->addr), 314 be32_to_cpu(data->byte_count), 315 DMA_TO_DEVICE); 316 } 317 } else { 318 if ((void *)data >= end) 319 data = ring->buf + ((void *)data - end); 320 321 for (i = 1; i < nr_maps; i++) { 322 data++; 323 /* Check for wraparound before unmapping */ 324 if ((void *) data >= end) 325 data = ring->buf; 326 dma_unmap_page(priv->ddev, 327 (dma_addr_t)be64_to_cpu(data->addr), 328 be32_to_cpu(data->byte_count), 329 DMA_TO_DEVICE); 330 } 331 } 332 } 333 napi_consume_skb(skb, napi_mode); 334 335 return tx_info->nr_txbb; 336 } 337 338 INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 339 struct mlx4_en_tx_ring *ring, 340 int index, u64 timestamp, 341 int napi_mode)); 342 343 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 344 struct mlx4_en_tx_ring *ring, 345 int index, u64 timestamp, 346 int napi_mode) 347 { 348 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 349 struct mlx4_en_rx_alloc frame = { 350 .page = tx_info->page, 351 .dma = tx_info->map0_dma, 352 }; 353 354 if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 355 dma_unmap_page(priv->ddev, tx_info->map0_dma, 356 PAGE_SIZE, priv->dma_dir); 357 put_page(tx_info->page); 358 } 359 360 return tx_info->nr_txbb; 361 } 362 363 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 364 { 365 struct mlx4_en_priv *priv = netdev_priv(dev); 366 int cnt = 0; 367 368 /* Skip last polled descriptor */ 369 ring->cons += ring->last_nr_txbb; 370 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 371 ring->cons, ring->prod); 372 373 if ((u32) (ring->prod - ring->cons) > ring->size) { 374 if (netif_msg_tx_err(priv)) 375 en_warn(priv, "Tx consumer passed producer!\n"); 376 return 0; 377 } 378 379 while (ring->cons != ring->prod) { 380 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 381 ring->cons & ring->size_mask, 382 0, 0 /* Non-NAPI caller */); 383 ring->cons += ring->last_nr_txbb; 384 cnt++; 385 } 386 387 if (ring->tx_queue) 388 netdev_tx_reset_queue(ring->tx_queue); 389 390 if (cnt) 391 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 392 393 return cnt; 394 } 395 396 static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe, 397 u16 cqe_index, struct mlx4_en_tx_ring *ring) 398 { 399 struct mlx4_en_dev *mdev = priv->mdev; 400 struct mlx4_en_tx_info *tx_info; 401 struct mlx4_en_tx_desc *tx_desc; 402 u16 wqe_index; 403 int desc_size; 404 405 en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n", 406 ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome); 407 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe), 408 false); 409 410 wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask; 411 tx_info = &ring->tx_info[wqe_index]; 412 desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE; 413 en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn, 414 wqe_index, desc_size); 415 tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE); 416 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false); 417 418 if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state)) 419 return; 420 421 en_err(priv, "Scheduling port restart\n"); 422 queue_work(mdev->workqueue, &priv->restart_task); 423 } 424 425 int mlx4_en_process_tx_cq(struct net_device *dev, 426 struct mlx4_en_cq *cq, int napi_budget) 427 { 428 struct mlx4_en_priv *priv = netdev_priv(dev); 429 struct mlx4_cq *mcq = &cq->mcq; 430 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 431 struct mlx4_cqe *cqe; 432 u16 index, ring_index, stamp_index; 433 u32 txbbs_skipped = 0; 434 u32 txbbs_stamp = 0; 435 u32 cons_index = mcq->cons_index; 436 int size = cq->size; 437 u32 size_mask = ring->size_mask; 438 struct mlx4_cqe *buf = cq->buf; 439 u32 packets = 0; 440 u32 bytes = 0; 441 int factor = priv->cqe_factor; 442 int done = 0; 443 int budget = priv->tx_work_limit; 444 u32 last_nr_txbb; 445 u32 ring_cons; 446 447 if (unlikely(!priv->port_up)) 448 return 0; 449 450 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 451 452 index = cons_index & size_mask; 453 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 454 last_nr_txbb = READ_ONCE(ring->last_nr_txbb); 455 ring_cons = READ_ONCE(ring->cons); 456 ring_index = ring_cons & size_mask; 457 stamp_index = ring_index; 458 459 /* Process all completed CQEs */ 460 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 461 cons_index & size) && (done < budget)) { 462 u16 new_index; 463 464 /* 465 * make sure we read the CQE after we read the 466 * ownership bit 467 */ 468 dma_rmb(); 469 470 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 471 MLX4_CQE_OPCODE_ERROR)) 472 if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state)) 473 mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index, 474 ring); 475 476 /* Skip over last polled CQE */ 477 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 478 479 do { 480 u64 timestamp = 0; 481 482 txbbs_skipped += last_nr_txbb; 483 ring_index = (ring_index + last_nr_txbb) & size_mask; 484 485 if (unlikely(ring->tx_info[ring_index].ts_requested)) 486 timestamp = mlx4_en_get_cqe_ts(cqe); 487 488 /* free next descriptor */ 489 last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc, 490 mlx4_en_free_tx_desc, 491 mlx4_en_recycle_tx_desc, 492 priv, ring, ring_index, 493 timestamp, napi_budget); 494 495 mlx4_en_stamp_wqe(priv, ring, stamp_index, 496 !!((ring_cons + txbbs_stamp) & 497 ring->size)); 498 stamp_index = ring_index; 499 txbbs_stamp = txbbs_skipped; 500 packets++; 501 bytes += ring->tx_info[ring_index].nr_bytes; 502 } while ((++done < budget) && (ring_index != new_index)); 503 504 ++cons_index; 505 index = cons_index & size_mask; 506 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 507 } 508 509 /* 510 * To prevent CQ overflow we first update CQ consumer and only then 511 * the ring consumer. 512 */ 513 mcq->cons_index = cons_index; 514 mlx4_cq_set_ci(mcq); 515 wmb(); 516 517 /* we want to dirty this cache line once */ 518 WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); 519 WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); 520 521 if (cq->type == TX_XDP) 522 return done; 523 524 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 525 526 /* Wakeup Tx queue if this stopped, and ring is not full. 527 */ 528 if (netif_tx_queue_stopped(ring->tx_queue) && 529 !mlx4_en_is_tx_ring_full(ring)) { 530 netif_tx_wake_queue(ring->tx_queue); 531 ring->wake_queue++; 532 } 533 534 return done; 535 } 536 537 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 538 { 539 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 540 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 541 542 if (likely(priv->port_up)) 543 napi_schedule_irqoff(&cq->napi); 544 else 545 mlx4_en_arm_cq(priv, cq); 546 } 547 548 /* TX CQ polling - called by NAPI */ 549 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 550 { 551 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 552 struct net_device *dev = cq->dev; 553 struct mlx4_en_priv *priv = netdev_priv(dev); 554 int work_done; 555 556 work_done = mlx4_en_process_tx_cq(dev, cq, budget); 557 if (work_done >= budget) 558 return budget; 559 560 if (napi_complete_done(napi, work_done)) 561 mlx4_en_arm_cq(priv, cq); 562 563 return 0; 564 } 565 566 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 567 struct mlx4_en_tx_ring *ring, 568 u32 index, 569 unsigned int desc_size) 570 { 571 u32 copy = (ring->size - index) << LOG_TXBB_SIZE; 572 int i; 573 574 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 575 if ((i & (TXBB_SIZE - 1)) == 0) 576 wmb(); 577 578 *((u32 *) (ring->buf + i)) = 579 *((u32 *) (ring->bounce_buf + copy + i)); 580 } 581 582 for (i = copy - 4; i >= 4 ; i -= 4) { 583 if ((i & (TXBB_SIZE - 1)) == 0) 584 wmb(); 585 586 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = 587 *((u32 *) (ring->bounce_buf + i)); 588 } 589 590 /* Return real descriptor location */ 591 return ring->buf + (index << LOG_TXBB_SIZE); 592 } 593 594 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 595 * 596 * It seems strange we do not simply use skb_copy_bits(). 597 * This would allow to inline all skbs iff skb->len <= inline_thold 598 * 599 * Note that caller already checked skb was not a gso packet 600 */ 601 static bool is_inline(int inline_thold, const struct sk_buff *skb, 602 const struct skb_shared_info *shinfo, 603 void **pfrag) 604 { 605 void *ptr; 606 607 if (skb->len > inline_thold || !inline_thold) 608 return false; 609 610 if (shinfo->nr_frags == 1) { 611 ptr = skb_frag_address_safe(&shinfo->frags[0]); 612 if (unlikely(!ptr)) 613 return false; 614 *pfrag = ptr; 615 return true; 616 } 617 if (shinfo->nr_frags) 618 return false; 619 return true; 620 } 621 622 static int inline_size(const struct sk_buff *skb) 623 { 624 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 625 <= MLX4_INLINE_ALIGN) 626 return ALIGN(skb->len + CTRL_SIZE + 627 sizeof(struct mlx4_wqe_inline_seg), 16); 628 else 629 return ALIGN(skb->len + CTRL_SIZE + 2 * 630 sizeof(struct mlx4_wqe_inline_seg), 16); 631 } 632 633 static int get_real_size(const struct sk_buff *skb, 634 const struct skb_shared_info *shinfo, 635 struct net_device *dev, 636 int *lso_header_size, 637 bool *inline_ok, 638 void **pfrag) 639 { 640 struct mlx4_en_priv *priv = netdev_priv(dev); 641 int real_size; 642 643 if (shinfo->gso_size) { 644 *inline_ok = false; 645 if (skb->encapsulation) 646 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 647 else 648 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 649 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 650 ALIGN(*lso_header_size + 4, DS_SIZE); 651 if (unlikely(*lso_header_size != skb_headlen(skb))) { 652 /* We add a segment for the skb linear buffer only if 653 * it contains data */ 654 if (*lso_header_size < skb_headlen(skb)) 655 real_size += DS_SIZE; 656 else { 657 if (netif_msg_tx_err(priv)) 658 en_warn(priv, "Non-linear headers\n"); 659 return 0; 660 } 661 } 662 } else { 663 *lso_header_size = 0; 664 *inline_ok = is_inline(priv->prof->inline_thold, skb, 665 shinfo, pfrag); 666 667 if (*inline_ok) 668 real_size = inline_size(skb); 669 else 670 real_size = CTRL_SIZE + 671 (shinfo->nr_frags + 1) * DS_SIZE; 672 } 673 674 return real_size; 675 } 676 677 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 678 const struct sk_buff *skb, 679 const struct skb_shared_info *shinfo, 680 void *fragptr) 681 { 682 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 683 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); 684 unsigned int hlen = skb_headlen(skb); 685 686 if (skb->len <= spc) { 687 if (likely(skb->len >= MIN_PKT_LEN)) { 688 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 689 } else { 690 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 691 memset(((void *)(inl + 1)) + skb->len, 0, 692 MIN_PKT_LEN - skb->len); 693 } 694 skb_copy_from_linear_data(skb, inl + 1, hlen); 695 if (shinfo->nr_frags) 696 memcpy(((void *)(inl + 1)) + hlen, fragptr, 697 skb_frag_size(&shinfo->frags[0])); 698 699 } else { 700 inl->byte_count = cpu_to_be32(1 << 31 | spc); 701 if (hlen <= spc) { 702 skb_copy_from_linear_data(skb, inl + 1, hlen); 703 if (hlen < spc) { 704 memcpy(((void *)(inl + 1)) + hlen, 705 fragptr, spc - hlen); 706 fragptr += spc - hlen; 707 } 708 inl = (void *) (inl + 1) + spc; 709 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 710 } else { 711 skb_copy_from_linear_data(skb, inl + 1, spc); 712 inl = (void *) (inl + 1) + spc; 713 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 714 hlen - spc); 715 if (shinfo->nr_frags) 716 memcpy(((void *)(inl + 1)) + hlen - spc, 717 fragptr, 718 skb_frag_size(&shinfo->frags[0])); 719 } 720 721 dma_wmb(); 722 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 723 } 724 } 725 726 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 727 struct net_device *sb_dev) 728 { 729 struct mlx4_en_priv *priv = netdev_priv(dev); 730 u16 rings_p_up = priv->num_tx_rings_p_up; 731 732 if (netdev_get_num_tc(dev)) 733 return netdev_pick_tx(dev, skb, NULL); 734 735 return netdev_pick_tx(dev, skb, NULL) % rings_p_up; 736 } 737 738 static void mlx4_bf_copy(void __iomem *dst, const void *src, 739 unsigned int bytecnt) 740 { 741 __iowrite64_copy(dst, src, bytecnt / 8); 742 } 743 744 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 745 { 746 wmb(); 747 /* Since there is no iowrite*_native() that writes the 748 * value as is, without byteswapping - using the one 749 * the doesn't do byteswapping in the relevant arch 750 * endianness. 751 */ 752 #if defined(__LITTLE_ENDIAN) 753 iowrite32( 754 #else 755 iowrite32be( 756 #endif 757 (__force u32)ring->doorbell_qpn, ring->doorbell_address); 758 } 759 760 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 761 struct mlx4_en_tx_desc *tx_desc, 762 union mlx4_wqe_qpn_vlan qpn_vlan, 763 int desc_size, int bf_index, 764 __be32 op_own, bool bf_ok, 765 bool send_doorbell) 766 { 767 tx_desc->ctrl.qpn_vlan = qpn_vlan; 768 769 if (bf_ok) { 770 op_own |= htonl((bf_index & 0xffff) << 8); 771 /* Ensure new descriptor hits memory 772 * before setting ownership of this descriptor to HW 773 */ 774 dma_wmb(); 775 tx_desc->ctrl.owner_opcode = op_own; 776 777 wmb(); 778 779 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 780 desc_size); 781 782 wmb(); 783 784 ring->bf.offset ^= ring->bf.buf_size; 785 } else { 786 /* Ensure new descriptor hits memory 787 * before setting ownership of this descriptor to HW 788 */ 789 dma_wmb(); 790 tx_desc->ctrl.owner_opcode = op_own; 791 if (send_doorbell) 792 mlx4_en_xmit_doorbell(ring); 793 else 794 ring->xmit_more++; 795 } 796 } 797 798 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, 799 struct skb_shared_info *shinfo, 800 struct mlx4_wqe_data_seg *data, 801 struct sk_buff *skb, 802 int lso_header_size, 803 __be32 mr_key, 804 struct mlx4_en_tx_info *tx_info) 805 { 806 struct device *ddev = priv->ddev; 807 dma_addr_t dma = 0; 808 u32 byte_count = 0; 809 int i_frag; 810 811 /* Map fragments if any */ 812 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 813 const skb_frag_t *frag = &shinfo->frags[i_frag]; 814 byte_count = skb_frag_size(frag); 815 dma = skb_frag_dma_map(ddev, frag, 816 0, byte_count, 817 DMA_TO_DEVICE); 818 if (dma_mapping_error(ddev, dma)) 819 goto tx_drop_unmap; 820 821 data->addr = cpu_to_be64(dma); 822 data->lkey = mr_key; 823 dma_wmb(); 824 data->byte_count = cpu_to_be32(byte_count); 825 --data; 826 } 827 828 /* Map linear part if needed */ 829 if (tx_info->linear) { 830 byte_count = skb_headlen(skb) - lso_header_size; 831 832 dma = dma_map_single(ddev, skb->data + 833 lso_header_size, byte_count, 834 DMA_TO_DEVICE); 835 if (dma_mapping_error(ddev, dma)) 836 goto tx_drop_unmap; 837 838 data->addr = cpu_to_be64(dma); 839 data->lkey = mr_key; 840 dma_wmb(); 841 data->byte_count = cpu_to_be32(byte_count); 842 } 843 /* tx completion can avoid cache line miss for common cases */ 844 tx_info->map0_dma = dma; 845 tx_info->map0_byte_count = byte_count; 846 847 return true; 848 849 tx_drop_unmap: 850 en_err(priv, "DMA mapping error\n"); 851 852 while (++i_frag < shinfo->nr_frags) { 853 ++data; 854 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), 855 be32_to_cpu(data->byte_count), 856 DMA_TO_DEVICE); 857 } 858 859 return false; 860 } 861 862 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 863 { 864 struct skb_shared_info *shinfo = skb_shinfo(skb); 865 struct mlx4_en_priv *priv = netdev_priv(dev); 866 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 867 struct mlx4_en_tx_ring *ring; 868 struct mlx4_en_tx_desc *tx_desc; 869 struct mlx4_wqe_data_seg *data; 870 struct mlx4_en_tx_info *tx_info; 871 u32 __maybe_unused ring_cons; 872 int tx_ind; 873 int nr_txbb; 874 int desc_size; 875 int real_size; 876 u32 index, bf_index; 877 __be32 op_own; 878 int lso_header_size; 879 void *fragptr = NULL; 880 bool bounce = false; 881 bool send_doorbell; 882 bool stop_queue; 883 bool inline_ok; 884 u8 data_offset; 885 bool bf_ok; 886 887 tx_ind = skb_get_queue_mapping(skb); 888 ring = priv->tx_ring[TX][tx_ind]; 889 890 if (unlikely(!priv->port_up)) 891 goto tx_drop; 892 893 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 894 &inline_ok, &fragptr); 895 if (unlikely(!real_size)) 896 goto tx_drop_count; 897 898 /* Align descriptor to TXBB size */ 899 desc_size = ALIGN(real_size, TXBB_SIZE); 900 nr_txbb = desc_size >> LOG_TXBB_SIZE; 901 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 902 if (netif_msg_tx_err(priv)) 903 en_warn(priv, "Oversized header or SG list\n"); 904 goto tx_drop_count; 905 } 906 907 bf_ok = ring->bf_enabled; 908 if (skb_vlan_tag_present(skb)) { 909 u16 vlan_proto; 910 911 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 912 vlan_proto = be16_to_cpu(skb->vlan_proto); 913 if (vlan_proto == ETH_P_8021AD) 914 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 915 else if (vlan_proto == ETH_P_8021Q) 916 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 917 else 918 qpn_vlan.ins_vlan = 0; 919 bf_ok = false; 920 } 921 922 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 923 924 /* Packet is good - grab an index and transmit it */ 925 index = ring->prod & ring->size_mask; 926 bf_index = ring->prod; 927 928 /* See if we have enough space for whole descriptor TXBB for setting 929 * SW ownership on next descriptor; if not, use a bounce buffer. */ 930 if (likely(index + nr_txbb <= ring->size)) 931 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 932 else { 933 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 934 bounce = true; 935 bf_ok = false; 936 } 937 938 /* Save skb in tx_info ring */ 939 tx_info = &ring->tx_info[index]; 940 tx_info->skb = skb; 941 tx_info->nr_txbb = nr_txbb; 942 943 if (!lso_header_size) { 944 data = &tx_desc->data; 945 data_offset = offsetof(struct mlx4_en_tx_desc, data); 946 } else { 947 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE); 948 949 data = (void *)&tx_desc->lso + lso_align; 950 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; 951 } 952 953 /* valid only for none inline segments */ 954 tx_info->data_offset = data_offset; 955 956 tx_info->inl = inline_ok; 957 958 tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; 959 960 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 961 data += tx_info->nr_maps - 1; 962 963 if (!tx_info->inl) 964 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, 965 lso_header_size, ring->mr_key, 966 tx_info)) 967 goto tx_drop_count; 968 969 /* 970 * For timestamping add flag to skb_shinfo and 971 * set flag for further reference 972 */ 973 tx_info->ts_requested = 0; 974 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 975 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 976 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 977 tx_info->ts_requested = 1; 978 } 979 980 /* Prepare ctrl segement apart opcode+ownership, which depends on 981 * whether LSO is used */ 982 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 983 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 984 if (!skb->encapsulation) 985 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 986 MLX4_WQE_CTRL_TCP_UDP_CSUM); 987 else 988 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 989 ring->tx_csum++; 990 } 991 992 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 993 struct ethhdr *ethh; 994 995 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 996 * so that VFs and PF can communicate with each other 997 */ 998 ethh = (struct ethhdr *)skb->data; 999 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 1000 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 1001 } 1002 1003 /* Handle LSO (TSO) packets */ 1004 if (lso_header_size) { 1005 int i; 1006 1007 /* Mark opcode as LSO */ 1008 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 1009 ((ring->prod & ring->size) ? 1010 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1011 1012 /* Fill in the LSO prefix */ 1013 tx_desc->lso.mss_hdr_size = cpu_to_be32( 1014 shinfo->gso_size << 16 | lso_header_size); 1015 1016 /* Copy headers; 1017 * note that we already verified that it is linear */ 1018 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 1019 1020 ring->tso_packets++; 1021 1022 i = shinfo->gso_segs; 1023 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 1024 ring->packets += i; 1025 } else { 1026 /* Normal (Non LSO) packet */ 1027 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1028 ((ring->prod & ring->size) ? 1029 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1030 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 1031 ring->packets++; 1032 } 1033 ring->bytes += tx_info->nr_bytes; 1034 1035 if (tx_info->inl) 1036 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 1037 1038 if (skb->encapsulation) { 1039 union { 1040 struct iphdr *v4; 1041 struct ipv6hdr *v6; 1042 unsigned char *hdr; 1043 } ip; 1044 u8 proto; 1045 1046 ip.hdr = skb_inner_network_header(skb); 1047 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1048 ip.v6->nexthdr; 1049 1050 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1051 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1052 else 1053 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1054 } 1055 1056 ring->prod += nr_txbb; 1057 1058 /* If we used a bounce buffer then copy descriptor back into place */ 1059 if (unlikely(bounce)) 1060 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1061 1062 skb_tx_timestamp(skb); 1063 1064 /* Check available TXBBs And 2K spare for prefetch */ 1065 stop_queue = mlx4_en_is_tx_ring_full(ring); 1066 if (unlikely(stop_queue)) { 1067 netif_tx_stop_queue(ring->tx_queue); 1068 ring->queue_stopped++; 1069 } 1070 1071 send_doorbell = __netdev_tx_sent_queue(ring->tx_queue, 1072 tx_info->nr_bytes, 1073 netdev_xmit_more()); 1074 1075 real_size = (real_size / 16) & 0x3f; 1076 1077 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1078 1079 if (bf_ok) 1080 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1081 else 1082 qpn_vlan.fence_size = real_size; 1083 1084 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1085 op_own, bf_ok, send_doorbell); 1086 1087 if (unlikely(stop_queue)) { 1088 /* If queue was emptied after the if (stop_queue) , and before 1089 * the netif_tx_stop_queue() - need to wake the queue, 1090 * or else it will remain stopped forever. 1091 * Need a memory barrier to make sure ring->cons was not 1092 * updated before queue was stopped. 1093 */ 1094 smp_rmb(); 1095 1096 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1097 netif_tx_wake_queue(ring->tx_queue); 1098 ring->wake_queue++; 1099 } 1100 } 1101 return NETDEV_TX_OK; 1102 1103 tx_drop_count: 1104 ring->tx_dropped++; 1105 tx_drop: 1106 dev_kfree_skb_any(skb); 1107 return NETDEV_TX_OK; 1108 } 1109 1110 #define MLX4_EN_XDP_TX_NRTXBB 1 1111 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ 1112 / 16) & 0x3f) 1113 1114 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 1115 struct mlx4_en_tx_ring *ring) 1116 { 1117 int i; 1118 1119 for (i = 0; i < ring->size; i++) { 1120 struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; 1121 struct mlx4_en_tx_desc *tx_desc = ring->buf + 1122 (i << LOG_TXBB_SIZE); 1123 1124 tx_info->map0_byte_count = PAGE_SIZE; 1125 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; 1126 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); 1127 tx_info->ts_requested = 0; 1128 tx_info->nr_maps = 1; 1129 tx_info->linear = 1; 1130 tx_info->inl = 0; 1131 1132 tx_desc->data.lkey = ring->mr_key; 1133 tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; 1134 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1135 } 1136 } 1137 1138 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1139 struct mlx4_en_rx_alloc *frame, 1140 struct mlx4_en_priv *priv, unsigned int length, 1141 int tx_ind, bool *doorbell_pending) 1142 { 1143 struct mlx4_en_tx_desc *tx_desc; 1144 struct mlx4_en_tx_info *tx_info; 1145 struct mlx4_wqe_data_seg *data; 1146 struct mlx4_en_tx_ring *ring; 1147 dma_addr_t dma; 1148 __be32 op_own; 1149 int index; 1150 1151 if (unlikely(!priv->port_up)) 1152 goto tx_drop; 1153 1154 ring = priv->tx_ring[TX_XDP][tx_ind]; 1155 1156 if (unlikely(mlx4_en_is_tx_ring_full(ring))) 1157 goto tx_drop_count; 1158 1159 index = ring->prod & ring->size_mask; 1160 tx_info = &ring->tx_info[index]; 1161 1162 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 1163 data = &tx_desc->data; 1164 1165 dma = frame->dma; 1166 1167 tx_info->page = frame->page; 1168 frame->page = NULL; 1169 tx_info->map0_dma = dma; 1170 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1171 1172 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1173 length, DMA_TO_DEVICE); 1174 1175 data->addr = cpu_to_be64(dma + frame->page_offset); 1176 dma_wmb(); 1177 data->byte_count = cpu_to_be32(length); 1178 1179 /* tx completion can avoid cache line miss for common cases */ 1180 1181 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1182 ((ring->prod & ring->size) ? 1183 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1184 1185 rx_ring->xdp_tx++; 1186 1187 ring->prod += MLX4_EN_XDP_TX_NRTXBB; 1188 1189 /* Ensure new descriptor hits memory 1190 * before setting ownership of this descriptor to HW 1191 */ 1192 dma_wmb(); 1193 tx_desc->ctrl.owner_opcode = op_own; 1194 ring->xmit_more++; 1195 1196 *doorbell_pending = true; 1197 1198 return NETDEV_TX_OK; 1199 1200 tx_drop_count: 1201 rx_ring->xdp_tx_full++; 1202 *doorbell_pending = true; 1203 tx_drop: 1204 return NETDEV_TX_BUSY; 1205 } 1206