1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 61 if (!ring) { 62 en_err(priv, "Failed allocating TX ring\n"); 63 return -ENOMEM; 64 } 65 } 66 67 ring->size = size; 68 ring->size_mask = size - 1; 69 ring->stride = stride; 70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 71 72 tmp = size * sizeof(struct mlx4_en_tx_info); 73 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); 74 if (!ring->tx_info) { 75 ring->tx_info = vmalloc(tmp); 76 if (!ring->tx_info) { 77 err = -ENOMEM; 78 goto err_ring; 79 } 80 } 81 82 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 83 ring->tx_info, tmp); 84 85 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 86 if (!ring->bounce_buf) { 87 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 88 if (!ring->bounce_buf) { 89 err = -ENOMEM; 90 goto err_info; 91 } 92 } 93 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 94 95 /* Allocate HW buffers on provided NUMA node */ 96 set_dev_node(&mdev->dev->persist->pdev->dev, node); 97 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 99 if (err) { 100 en_err(priv, "Failed allocating hwq resources\n"); 101 goto err_bounce; 102 } 103 104 ring->buf = ring->wqres.buf.direct.buf; 105 106 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 107 ring, ring->buf, ring->size, ring->buf_size, 108 (unsigned long long) ring->wqres.buf.direct.map); 109 110 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 111 MLX4_RESERVE_ETH_BF_QP); 112 if (err) { 113 en_err(priv, "failed reserving qp for TX ring\n"); 114 goto err_hwq_res; 115 } 116 117 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); 118 if (err) { 119 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 120 goto err_reserve; 121 } 122 ring->qp.event = mlx4_en_sqp_event; 123 124 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 125 if (err) { 126 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 127 ring->bf.uar = &mdev->priv_uar; 128 ring->bf.uar->map = mdev->uar_map; 129 ring->bf_enabled = false; 130 ring->bf_alloced = false; 131 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 132 } else { 133 ring->bf_alloced = true; 134 ring->bf_enabled = !!(priv->pflags & 135 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 136 } 137 138 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 139 ring->queue_index = queue_index; 140 141 if (queue_index < priv->num_tx_rings_p_up) 142 cpumask_set_cpu(cpumask_local_spread(queue_index, 143 priv->mdev->dev->numa_node), 144 &ring->affinity_mask); 145 146 *pring = ring; 147 return 0; 148 149 err_reserve: 150 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 151 err_hwq_res: 152 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 153 err_bounce: 154 kfree(ring->bounce_buf); 155 ring->bounce_buf = NULL; 156 err_info: 157 kvfree(ring->tx_info); 158 ring->tx_info = NULL; 159 err_ring: 160 kfree(ring); 161 *pring = NULL; 162 return err; 163 } 164 165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 166 struct mlx4_en_tx_ring **pring) 167 { 168 struct mlx4_en_dev *mdev = priv->mdev; 169 struct mlx4_en_tx_ring *ring = *pring; 170 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 171 172 if (ring->bf_alloced) 173 mlx4_bf_free(mdev->dev, &ring->bf); 174 mlx4_qp_remove(mdev->dev, &ring->qp); 175 mlx4_qp_free(mdev->dev, &ring->qp); 176 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 177 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 178 kfree(ring->bounce_buf); 179 ring->bounce_buf = NULL; 180 kvfree(ring->tx_info); 181 ring->tx_info = NULL; 182 kfree(ring); 183 *pring = NULL; 184 } 185 186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 187 struct mlx4_en_tx_ring *ring, 188 int cq, int user_prio) 189 { 190 struct mlx4_en_dev *mdev = priv->mdev; 191 int err; 192 193 ring->cqn = cq; 194 ring->prod = 0; 195 ring->cons = 0xffffffff; 196 ring->last_nr_txbb = 1; 197 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 198 memset(ring->buf, 0, ring->buf_size); 199 ring->free_tx_desc = mlx4_en_free_tx_desc; 200 201 ring->qp_state = MLX4_QP_STATE_RST; 202 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); 203 ring->mr_key = cpu_to_be32(mdev->mr.key); 204 205 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 206 ring->cqn, user_prio, &ring->context); 207 if (ring->bf_alloced) 208 ring->context.usr_page = 209 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 210 ring->bf.uar->index)); 211 212 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 213 &ring->qp, &ring->qp_state); 214 if (!cpumask_empty(&ring->affinity_mask)) 215 netif_set_xps_queue(priv->dev, &ring->affinity_mask, 216 ring->queue_index); 217 218 return err; 219 } 220 221 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 222 struct mlx4_en_tx_ring *ring) 223 { 224 struct mlx4_en_dev *mdev = priv->mdev; 225 226 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 227 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 228 } 229 230 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 231 { 232 return ring->prod - ring->cons > ring->full_size; 233 } 234 235 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 236 struct mlx4_en_tx_ring *ring, int index, 237 u8 owner) 238 { 239 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 240 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 241 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 242 void *end = ring->buf + ring->buf_size; 243 __be32 *ptr = (__be32 *)tx_desc; 244 int i; 245 246 /* Optimize the common case when there are no wraparounds */ 247 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 248 /* Stamp the freed descriptor */ 249 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 250 i += STAMP_STRIDE) { 251 *ptr = stamp; 252 ptr += STAMP_DWORDS; 253 } 254 } else { 255 /* Stamp the freed descriptor */ 256 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 257 i += STAMP_STRIDE) { 258 *ptr = stamp; 259 ptr += STAMP_DWORDS; 260 if ((void *)ptr >= end) { 261 ptr = ring->buf; 262 stamp ^= cpu_to_be32(0x80000000); 263 } 264 } 265 } 266 } 267 268 269 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 270 struct mlx4_en_tx_ring *ring, 271 int index, u8 owner, u64 timestamp, 272 int napi_mode) 273 { 274 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 275 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 276 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 277 void *end = ring->buf + ring->buf_size; 278 struct sk_buff *skb = tx_info->skb; 279 int nr_maps = tx_info->nr_maps; 280 int i; 281 282 /* We do not touch skb here, so prefetch skb->users location 283 * to speedup consume_skb() 284 */ 285 prefetchw(&skb->users); 286 287 if (unlikely(timestamp)) { 288 struct skb_shared_hwtstamps hwts; 289 290 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 291 skb_tstamp_tx(skb, &hwts); 292 } 293 294 /* Optimize the common case when there are no wraparounds */ 295 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 296 if (!tx_info->inl) { 297 if (tx_info->linear) 298 dma_unmap_single(priv->ddev, 299 tx_info->map0_dma, 300 tx_info->map0_byte_count, 301 PCI_DMA_TODEVICE); 302 else 303 dma_unmap_page(priv->ddev, 304 tx_info->map0_dma, 305 tx_info->map0_byte_count, 306 PCI_DMA_TODEVICE); 307 for (i = 1; i < nr_maps; i++) { 308 data++; 309 dma_unmap_page(priv->ddev, 310 (dma_addr_t)be64_to_cpu(data->addr), 311 be32_to_cpu(data->byte_count), 312 PCI_DMA_TODEVICE); 313 } 314 } 315 } else { 316 if (!tx_info->inl) { 317 if ((void *) data >= end) { 318 data = ring->buf + ((void *)data - end); 319 } 320 321 if (tx_info->linear) 322 dma_unmap_single(priv->ddev, 323 tx_info->map0_dma, 324 tx_info->map0_byte_count, 325 PCI_DMA_TODEVICE); 326 else 327 dma_unmap_page(priv->ddev, 328 tx_info->map0_dma, 329 tx_info->map0_byte_count, 330 PCI_DMA_TODEVICE); 331 for (i = 1; i < nr_maps; i++) { 332 data++; 333 /* Check for wraparound before unmapping */ 334 if ((void *) data >= end) 335 data = ring->buf; 336 dma_unmap_page(priv->ddev, 337 (dma_addr_t)be64_to_cpu(data->addr), 338 be32_to_cpu(data->byte_count), 339 PCI_DMA_TODEVICE); 340 } 341 } 342 } 343 napi_consume_skb(skb, napi_mode); 344 345 return tx_info->nr_txbb; 346 } 347 348 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 349 struct mlx4_en_tx_ring *ring, 350 int index, u8 owner, u64 timestamp, 351 int napi_mode) 352 { 353 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 354 struct mlx4_en_rx_alloc frame = { 355 .page = tx_info->page, 356 .dma = tx_info->map0_dma, 357 .page_offset = 0, 358 .page_size = PAGE_SIZE, 359 }; 360 361 if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 362 dma_unmap_page(priv->ddev, tx_info->map0_dma, 363 PAGE_SIZE, priv->frag_info[0].dma_dir); 364 put_page(tx_info->page); 365 } 366 367 return tx_info->nr_txbb; 368 } 369 370 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 371 { 372 struct mlx4_en_priv *priv = netdev_priv(dev); 373 int cnt = 0; 374 375 /* Skip last polled descriptor */ 376 ring->cons += ring->last_nr_txbb; 377 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 378 ring->cons, ring->prod); 379 380 if ((u32) (ring->prod - ring->cons) > ring->size) { 381 if (netif_msg_tx_err(priv)) 382 en_warn(priv, "Tx consumer passed producer!\n"); 383 return 0; 384 } 385 386 while (ring->cons != ring->prod) { 387 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 388 ring->cons & ring->size_mask, 389 !!(ring->cons & ring->size), 0, 390 0 /* Non-NAPI caller */); 391 ring->cons += ring->last_nr_txbb; 392 cnt++; 393 } 394 395 netdev_tx_reset_queue(ring->tx_queue); 396 397 if (cnt) 398 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 399 400 return cnt; 401 } 402 403 static bool mlx4_en_process_tx_cq(struct net_device *dev, 404 struct mlx4_en_cq *cq, int napi_budget) 405 { 406 struct mlx4_en_priv *priv = netdev_priv(dev); 407 struct mlx4_cq *mcq = &cq->mcq; 408 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 409 struct mlx4_cqe *cqe; 410 u16 index; 411 u16 new_index, ring_index, stamp_index; 412 u32 txbbs_skipped = 0; 413 u32 txbbs_stamp = 0; 414 u32 cons_index = mcq->cons_index; 415 int size = cq->size; 416 u32 size_mask = ring->size_mask; 417 struct mlx4_cqe *buf = cq->buf; 418 u32 packets = 0; 419 u32 bytes = 0; 420 int factor = priv->cqe_factor; 421 int done = 0; 422 int budget = priv->tx_work_limit; 423 u32 last_nr_txbb; 424 u32 ring_cons; 425 426 if (!priv->port_up) 427 return true; 428 429 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 430 431 index = cons_index & size_mask; 432 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 433 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 434 ring_cons = ACCESS_ONCE(ring->cons); 435 ring_index = ring_cons & size_mask; 436 stamp_index = ring_index; 437 438 /* Process all completed CQEs */ 439 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 440 cons_index & size) && (done < budget)) { 441 /* 442 * make sure we read the CQE after we read the 443 * ownership bit 444 */ 445 dma_rmb(); 446 447 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 448 MLX4_CQE_OPCODE_ERROR)) { 449 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 450 451 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 452 cqe_err->vendor_err_syndrome, 453 cqe_err->syndrome); 454 } 455 456 /* Skip over last polled CQE */ 457 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 458 459 do { 460 u64 timestamp = 0; 461 462 txbbs_skipped += last_nr_txbb; 463 ring_index = (ring_index + last_nr_txbb) & size_mask; 464 465 if (unlikely(ring->tx_info[ring_index].ts_requested)) 466 timestamp = mlx4_en_get_cqe_ts(cqe); 467 468 /* free next descriptor */ 469 last_nr_txbb = ring->free_tx_desc( 470 priv, ring, ring_index, 471 !!((ring_cons + txbbs_skipped) & 472 ring->size), timestamp, napi_budget); 473 474 mlx4_en_stamp_wqe(priv, ring, stamp_index, 475 !!((ring_cons + txbbs_stamp) & 476 ring->size)); 477 stamp_index = ring_index; 478 txbbs_stamp = txbbs_skipped; 479 packets++; 480 bytes += ring->tx_info[ring_index].nr_bytes; 481 } while ((++done < budget) && (ring_index != new_index)); 482 483 ++cons_index; 484 index = cons_index & size_mask; 485 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 486 } 487 488 489 /* 490 * To prevent CQ overflow we first update CQ consumer and only then 491 * the ring consumer. 492 */ 493 mcq->cons_index = cons_index; 494 mlx4_cq_set_ci(mcq); 495 wmb(); 496 497 /* we want to dirty this cache line once */ 498 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 499 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 500 501 if (ring->free_tx_desc == mlx4_en_recycle_tx_desc) 502 return done < budget; 503 504 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 505 506 /* Wakeup Tx queue if this stopped, and ring is not full. 507 */ 508 if (netif_tx_queue_stopped(ring->tx_queue) && 509 !mlx4_en_is_tx_ring_full(ring)) { 510 netif_tx_wake_queue(ring->tx_queue); 511 ring->wake_queue++; 512 } 513 return done < budget; 514 } 515 516 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 517 { 518 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 519 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 520 521 if (likely(priv->port_up)) 522 napi_schedule_irqoff(&cq->napi); 523 else 524 mlx4_en_arm_cq(priv, cq); 525 } 526 527 /* TX CQ polling - called by NAPI */ 528 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 529 { 530 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 531 struct net_device *dev = cq->dev; 532 struct mlx4_en_priv *priv = netdev_priv(dev); 533 int clean_complete; 534 535 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 536 if (!clean_complete) 537 return budget; 538 539 napi_complete(napi); 540 mlx4_en_arm_cq(priv, cq); 541 542 return 0; 543 } 544 545 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 546 struct mlx4_en_tx_ring *ring, 547 u32 index, 548 unsigned int desc_size) 549 { 550 u32 copy = (ring->size - index) * TXBB_SIZE; 551 int i; 552 553 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 554 if ((i & (TXBB_SIZE - 1)) == 0) 555 wmb(); 556 557 *((u32 *) (ring->buf + i)) = 558 *((u32 *) (ring->bounce_buf + copy + i)); 559 } 560 561 for (i = copy - 4; i >= 4 ; i -= 4) { 562 if ((i & (TXBB_SIZE - 1)) == 0) 563 wmb(); 564 565 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 566 *((u32 *) (ring->bounce_buf + i)); 567 } 568 569 /* Return real descriptor location */ 570 return ring->buf + index * TXBB_SIZE; 571 } 572 573 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 574 * 575 * It seems strange we do not simply use skb_copy_bits(). 576 * This would allow to inline all skbs iff skb->len <= inline_thold 577 * 578 * Note that caller already checked skb was not a gso packet 579 */ 580 static bool is_inline(int inline_thold, const struct sk_buff *skb, 581 const struct skb_shared_info *shinfo, 582 void **pfrag) 583 { 584 void *ptr; 585 586 if (skb->len > inline_thold || !inline_thold) 587 return false; 588 589 if (shinfo->nr_frags == 1) { 590 ptr = skb_frag_address_safe(&shinfo->frags[0]); 591 if (unlikely(!ptr)) 592 return false; 593 *pfrag = ptr; 594 return true; 595 } 596 if (shinfo->nr_frags) 597 return false; 598 return true; 599 } 600 601 static int inline_size(const struct sk_buff *skb) 602 { 603 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 604 <= MLX4_INLINE_ALIGN) 605 return ALIGN(skb->len + CTRL_SIZE + 606 sizeof(struct mlx4_wqe_inline_seg), 16); 607 else 608 return ALIGN(skb->len + CTRL_SIZE + 2 * 609 sizeof(struct mlx4_wqe_inline_seg), 16); 610 } 611 612 static int get_real_size(const struct sk_buff *skb, 613 const struct skb_shared_info *shinfo, 614 struct net_device *dev, 615 int *lso_header_size, 616 bool *inline_ok, 617 void **pfrag) 618 { 619 struct mlx4_en_priv *priv = netdev_priv(dev); 620 int real_size; 621 622 if (shinfo->gso_size) { 623 *inline_ok = false; 624 if (skb->encapsulation) 625 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 626 else 627 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 628 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 629 ALIGN(*lso_header_size + 4, DS_SIZE); 630 if (unlikely(*lso_header_size != skb_headlen(skb))) { 631 /* We add a segment for the skb linear buffer only if 632 * it contains data */ 633 if (*lso_header_size < skb_headlen(skb)) 634 real_size += DS_SIZE; 635 else { 636 if (netif_msg_tx_err(priv)) 637 en_warn(priv, "Non-linear headers\n"); 638 return 0; 639 } 640 } 641 } else { 642 *lso_header_size = 0; 643 *inline_ok = is_inline(priv->prof->inline_thold, skb, 644 shinfo, pfrag); 645 646 if (*inline_ok) 647 real_size = inline_size(skb); 648 else 649 real_size = CTRL_SIZE + 650 (shinfo->nr_frags + 1) * DS_SIZE; 651 } 652 653 return real_size; 654 } 655 656 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 657 const struct sk_buff *skb, 658 const struct skb_shared_info *shinfo, 659 void *fragptr) 660 { 661 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 662 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 663 unsigned int hlen = skb_headlen(skb); 664 665 if (skb->len <= spc) { 666 if (likely(skb->len >= MIN_PKT_LEN)) { 667 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 668 } else { 669 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 670 memset(((void *)(inl + 1)) + skb->len, 0, 671 MIN_PKT_LEN - skb->len); 672 } 673 skb_copy_from_linear_data(skb, inl + 1, hlen); 674 if (shinfo->nr_frags) 675 memcpy(((void *)(inl + 1)) + hlen, fragptr, 676 skb_frag_size(&shinfo->frags[0])); 677 678 } else { 679 inl->byte_count = cpu_to_be32(1 << 31 | spc); 680 if (hlen <= spc) { 681 skb_copy_from_linear_data(skb, inl + 1, hlen); 682 if (hlen < spc) { 683 memcpy(((void *)(inl + 1)) + hlen, 684 fragptr, spc - hlen); 685 fragptr += spc - hlen; 686 } 687 inl = (void *) (inl + 1) + spc; 688 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 689 } else { 690 skb_copy_from_linear_data(skb, inl + 1, spc); 691 inl = (void *) (inl + 1) + spc; 692 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 693 hlen - spc); 694 if (shinfo->nr_frags) 695 memcpy(((void *)(inl + 1)) + hlen - spc, 696 fragptr, 697 skb_frag_size(&shinfo->frags[0])); 698 } 699 700 dma_wmb(); 701 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 702 } 703 } 704 705 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 706 void *accel_priv, select_queue_fallback_t fallback) 707 { 708 struct mlx4_en_priv *priv = netdev_priv(dev); 709 u16 rings_p_up = priv->num_tx_rings_p_up; 710 u8 up = 0; 711 712 if (dev->num_tc) 713 return skb_tx_hash(dev, skb); 714 715 if (skb_vlan_tag_present(skb)) 716 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; 717 718 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 719 } 720 721 static void mlx4_bf_copy(void __iomem *dst, const void *src, 722 unsigned int bytecnt) 723 { 724 __iowrite64_copy(dst, src, bytecnt / 8); 725 } 726 727 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 728 { 729 wmb(); 730 /* Since there is no iowrite*_native() that writes the 731 * value as is, without byteswapping - using the one 732 * the doesn't do byteswapping in the relevant arch 733 * endianness. 734 */ 735 #if defined(__LITTLE_ENDIAN) 736 iowrite32( 737 #else 738 iowrite32be( 739 #endif 740 ring->doorbell_qpn, 741 ring->bf.uar->map + MLX4_SEND_DOORBELL); 742 } 743 744 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 745 struct mlx4_en_tx_desc *tx_desc, 746 union mlx4_wqe_qpn_vlan qpn_vlan, 747 int desc_size, int bf_index, 748 __be32 op_own, bool bf_ok, 749 bool send_doorbell) 750 { 751 tx_desc->ctrl.qpn_vlan = qpn_vlan; 752 753 if (bf_ok) { 754 op_own |= htonl((bf_index & 0xffff) << 8); 755 /* Ensure new descriptor hits memory 756 * before setting ownership of this descriptor to HW 757 */ 758 dma_wmb(); 759 tx_desc->ctrl.owner_opcode = op_own; 760 761 wmb(); 762 763 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 764 desc_size); 765 766 wmb(); 767 768 ring->bf.offset ^= ring->bf.buf_size; 769 } else { 770 /* Ensure new descriptor hits memory 771 * before setting ownership of this descriptor to HW 772 */ 773 dma_wmb(); 774 tx_desc->ctrl.owner_opcode = op_own; 775 if (send_doorbell) 776 mlx4_en_xmit_doorbell(ring); 777 else 778 ring->xmit_more++; 779 } 780 } 781 782 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 783 { 784 struct skb_shared_info *shinfo = skb_shinfo(skb); 785 struct mlx4_en_priv *priv = netdev_priv(dev); 786 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 787 struct device *ddev = priv->ddev; 788 struct mlx4_en_tx_ring *ring; 789 struct mlx4_en_tx_desc *tx_desc; 790 struct mlx4_wqe_data_seg *data; 791 struct mlx4_en_tx_info *tx_info; 792 int tx_ind = 0; 793 int nr_txbb; 794 int desc_size; 795 int real_size; 796 u32 index, bf_index; 797 __be32 op_own; 798 u16 vlan_proto = 0; 799 int i_frag; 800 int lso_header_size; 801 void *fragptr = NULL; 802 bool bounce = false; 803 bool send_doorbell; 804 bool stop_queue; 805 bool inline_ok; 806 u32 ring_cons; 807 bool bf_ok; 808 809 tx_ind = skb_get_queue_mapping(skb); 810 ring = priv->tx_ring[tx_ind]; 811 812 if (!priv->port_up) 813 goto tx_drop; 814 815 /* fetch ring->cons far ahead before needing it to avoid stall */ 816 ring_cons = ACCESS_ONCE(ring->cons); 817 818 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 819 &inline_ok, &fragptr); 820 if (unlikely(!real_size)) 821 goto tx_drop_count; 822 823 /* Align descriptor to TXBB size */ 824 desc_size = ALIGN(real_size, TXBB_SIZE); 825 nr_txbb = desc_size / TXBB_SIZE; 826 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 827 if (netif_msg_tx_err(priv)) 828 en_warn(priv, "Oversized header or SG list\n"); 829 goto tx_drop_count; 830 } 831 832 bf_ok = ring->bf_enabled; 833 if (skb_vlan_tag_present(skb)) { 834 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 835 vlan_proto = be16_to_cpu(skb->vlan_proto); 836 if (vlan_proto == ETH_P_8021AD) 837 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 838 else if (vlan_proto == ETH_P_8021Q) 839 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 840 else 841 qpn_vlan.ins_vlan = 0; 842 bf_ok = false; 843 } 844 845 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 846 847 /* Track current inflight packets for performance analysis */ 848 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 849 (u32)(ring->prod - ring_cons - 1)); 850 851 /* Packet is good - grab an index and transmit it */ 852 index = ring->prod & ring->size_mask; 853 bf_index = ring->prod; 854 855 /* See if we have enough space for whole descriptor TXBB for setting 856 * SW ownership on next descriptor; if not, use a bounce buffer. */ 857 if (likely(index + nr_txbb <= ring->size)) 858 tx_desc = ring->buf + index * TXBB_SIZE; 859 else { 860 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 861 bounce = true; 862 bf_ok = false; 863 } 864 865 /* Save skb in tx_info ring */ 866 tx_info = &ring->tx_info[index]; 867 tx_info->skb = skb; 868 tx_info->nr_txbb = nr_txbb; 869 870 data = &tx_desc->data; 871 if (lso_header_size) 872 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 873 DS_SIZE)); 874 875 /* valid only for none inline segments */ 876 tx_info->data_offset = (void *)data - (void *)tx_desc; 877 878 tx_info->inl = inline_ok; 879 880 tx_info->linear = (lso_header_size < skb_headlen(skb) && 881 !inline_ok) ? 1 : 0; 882 883 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 884 data += tx_info->nr_maps - 1; 885 886 if (!tx_info->inl) { 887 dma_addr_t dma = 0; 888 u32 byte_count = 0; 889 890 /* Map fragments if any */ 891 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 892 const struct skb_frag_struct *frag; 893 894 frag = &shinfo->frags[i_frag]; 895 byte_count = skb_frag_size(frag); 896 dma = skb_frag_dma_map(ddev, frag, 897 0, byte_count, 898 DMA_TO_DEVICE); 899 if (dma_mapping_error(ddev, dma)) 900 goto tx_drop_unmap; 901 902 data->addr = cpu_to_be64(dma); 903 data->lkey = ring->mr_key; 904 dma_wmb(); 905 data->byte_count = cpu_to_be32(byte_count); 906 --data; 907 } 908 909 /* Map linear part if needed */ 910 if (tx_info->linear) { 911 byte_count = skb_headlen(skb) - lso_header_size; 912 913 dma = dma_map_single(ddev, skb->data + 914 lso_header_size, byte_count, 915 PCI_DMA_TODEVICE); 916 if (dma_mapping_error(ddev, dma)) 917 goto tx_drop_unmap; 918 919 data->addr = cpu_to_be64(dma); 920 data->lkey = ring->mr_key; 921 dma_wmb(); 922 data->byte_count = cpu_to_be32(byte_count); 923 } 924 /* tx completion can avoid cache line miss for common cases */ 925 tx_info->map0_dma = dma; 926 tx_info->map0_byte_count = byte_count; 927 } 928 929 /* 930 * For timestamping add flag to skb_shinfo and 931 * set flag for further reference 932 */ 933 tx_info->ts_requested = 0; 934 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 935 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 936 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 937 tx_info->ts_requested = 1; 938 } 939 940 /* Prepare ctrl segement apart opcode+ownership, which depends on 941 * whether LSO is used */ 942 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 943 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 944 if (!skb->encapsulation) 945 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 946 MLX4_WQE_CTRL_TCP_UDP_CSUM); 947 else 948 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 949 ring->tx_csum++; 950 } 951 952 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 953 struct ethhdr *ethh; 954 955 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 956 * so that VFs and PF can communicate with each other 957 */ 958 ethh = (struct ethhdr *)skb->data; 959 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 960 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 961 } 962 963 /* Handle LSO (TSO) packets */ 964 if (lso_header_size) { 965 int i; 966 967 /* Mark opcode as LSO */ 968 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 969 ((ring->prod & ring->size) ? 970 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 971 972 /* Fill in the LSO prefix */ 973 tx_desc->lso.mss_hdr_size = cpu_to_be32( 974 shinfo->gso_size << 16 | lso_header_size); 975 976 /* Copy headers; 977 * note that we already verified that it is linear */ 978 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 979 980 ring->tso_packets++; 981 982 i = ((skb->len - lso_header_size) / shinfo->gso_size) + 983 !!((skb->len - lso_header_size) % shinfo->gso_size); 984 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 985 ring->packets += i; 986 } else { 987 /* Normal (Non LSO) packet */ 988 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 989 ((ring->prod & ring->size) ? 990 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 991 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 992 ring->packets++; 993 } 994 ring->bytes += tx_info->nr_bytes; 995 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 996 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 997 998 if (tx_info->inl) 999 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 1000 1001 if (skb->encapsulation) { 1002 union { 1003 struct iphdr *v4; 1004 struct ipv6hdr *v6; 1005 unsigned char *hdr; 1006 } ip; 1007 u8 proto; 1008 1009 ip.hdr = skb_inner_network_header(skb); 1010 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1011 ip.v6->nexthdr; 1012 1013 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1014 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1015 else 1016 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1017 } 1018 1019 ring->prod += nr_txbb; 1020 1021 /* If we used a bounce buffer then copy descriptor back into place */ 1022 if (unlikely(bounce)) 1023 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1024 1025 skb_tx_timestamp(skb); 1026 1027 /* Check available TXBBs And 2K spare for prefetch */ 1028 stop_queue = mlx4_en_is_tx_ring_full(ring); 1029 if (unlikely(stop_queue)) { 1030 netif_tx_stop_queue(ring->tx_queue); 1031 ring->queue_stopped++; 1032 } 1033 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 1034 1035 real_size = (real_size / 16) & 0x3f; 1036 1037 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1038 1039 if (bf_ok) 1040 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1041 else 1042 qpn_vlan.fence_size = real_size; 1043 1044 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1045 op_own, bf_ok, send_doorbell); 1046 1047 if (unlikely(stop_queue)) { 1048 /* If queue was emptied after the if (stop_queue) , and before 1049 * the netif_tx_stop_queue() - need to wake the queue, 1050 * or else it will remain stopped forever. 1051 * Need a memory barrier to make sure ring->cons was not 1052 * updated before queue was stopped. 1053 */ 1054 smp_rmb(); 1055 1056 ring_cons = ACCESS_ONCE(ring->cons); 1057 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1058 netif_tx_wake_queue(ring->tx_queue); 1059 ring->wake_queue++; 1060 } 1061 } 1062 return NETDEV_TX_OK; 1063 1064 tx_drop_unmap: 1065 en_err(priv, "DMA mapping error\n"); 1066 1067 while (++i_frag < shinfo->nr_frags) { 1068 ++data; 1069 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 1070 be32_to_cpu(data->byte_count), 1071 PCI_DMA_TODEVICE); 1072 } 1073 1074 tx_drop_count: 1075 ring->tx_dropped++; 1076 tx_drop: 1077 dev_kfree_skb_any(skb); 1078 return NETDEV_TX_OK; 1079 } 1080 1081 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_alloc *frame, 1082 struct net_device *dev, unsigned int length, 1083 int tx_ind, int *doorbell_pending) 1084 { 1085 struct mlx4_en_priv *priv = netdev_priv(dev); 1086 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 1087 struct mlx4_en_tx_ring *ring; 1088 struct mlx4_en_tx_desc *tx_desc; 1089 struct mlx4_wqe_data_seg *data; 1090 struct mlx4_en_tx_info *tx_info; 1091 int index, bf_index; 1092 bool send_doorbell; 1093 int nr_txbb = 1; 1094 bool stop_queue; 1095 dma_addr_t dma; 1096 int real_size; 1097 __be32 op_own; 1098 u32 ring_cons; 1099 bool bf_ok; 1100 1101 BUILD_BUG_ON_MSG(ALIGN(CTRL_SIZE + DS_SIZE, TXBB_SIZE) != TXBB_SIZE, 1102 "mlx4_en_xmit_frame requires minimum size tx desc"); 1103 1104 ring = priv->tx_ring[tx_ind]; 1105 1106 if (!priv->port_up) 1107 goto tx_drop; 1108 1109 if (mlx4_en_is_tx_ring_full(ring)) 1110 goto tx_drop_count; 1111 1112 /* fetch ring->cons far ahead before needing it to avoid stall */ 1113 ring_cons = READ_ONCE(ring->cons); 1114 1115 index = ring->prod & ring->size_mask; 1116 tx_info = &ring->tx_info[index]; 1117 1118 bf_ok = ring->bf_enabled; 1119 1120 /* Track current inflight packets for performance analysis */ 1121 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1122 (u32)(ring->prod - ring_cons - 1)); 1123 1124 bf_index = ring->prod; 1125 tx_desc = ring->buf + index * TXBB_SIZE; 1126 data = &tx_desc->data; 1127 1128 dma = frame->dma; 1129 1130 tx_info->page = frame->page; 1131 frame->page = NULL; 1132 tx_info->map0_dma = dma; 1133 tx_info->map0_byte_count = length; 1134 tx_info->nr_txbb = nr_txbb; 1135 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1136 tx_info->data_offset = (void *)data - (void *)tx_desc; 1137 tx_info->ts_requested = 0; 1138 tx_info->nr_maps = 1; 1139 tx_info->linear = 1; 1140 tx_info->inl = 0; 1141 1142 dma_sync_single_for_device(priv->ddev, dma, length, PCI_DMA_TODEVICE); 1143 1144 data->addr = cpu_to_be64(dma); 1145 data->lkey = ring->mr_key; 1146 dma_wmb(); 1147 data->byte_count = cpu_to_be32(length); 1148 1149 /* tx completion can avoid cache line miss for common cases */ 1150 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1151 1152 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1153 ((ring->prod & ring->size) ? 1154 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1155 1156 ring->packets++; 1157 ring->bytes += tx_info->nr_bytes; 1158 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1159 1160 ring->prod += nr_txbb; 1161 1162 stop_queue = mlx4_en_is_tx_ring_full(ring); 1163 send_doorbell = stop_queue || 1164 *doorbell_pending > MLX4_EN_DOORBELL_BUDGET; 1165 bf_ok &= send_doorbell; 1166 1167 real_size = ((CTRL_SIZE + nr_txbb * DS_SIZE) / 16) & 0x3f; 1168 1169 if (bf_ok) 1170 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1171 else 1172 qpn_vlan.fence_size = real_size; 1173 1174 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, bf_index, 1175 op_own, bf_ok, send_doorbell); 1176 *doorbell_pending = send_doorbell ? 0 : *doorbell_pending + 1; 1177 1178 return NETDEV_TX_OK; 1179 1180 tx_drop_count: 1181 ring->tx_dropped++; 1182 tx_drop: 1183 return NETDEV_TX_BUSY; 1184 } 1185