1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #include <asm/page.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
43 #include <linux/ip.h>
44 #include <linux/ipv6.h>
45 #include <linux/indirect_call_wrapper.h>
46 #include <net/ipv6.h>
47 
48 #include "mlx4_en.h"
49 
50 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
51 			   struct mlx4_en_tx_ring **pring, u32 size,
52 			   u16 stride, int node, int queue_index)
53 {
54 	struct mlx4_en_dev *mdev = priv->mdev;
55 	struct mlx4_en_tx_ring *ring;
56 	int tmp;
57 	int err;
58 
59 	ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
60 	if (!ring) {
61 		en_err(priv, "Failed allocating TX ring\n");
62 		return -ENOMEM;
63 	}
64 
65 	ring->size = size;
66 	ring->size_mask = size - 1;
67 	ring->sp_stride = stride;
68 	ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
69 
70 	tmp = size * sizeof(struct mlx4_en_tx_info);
71 	ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node);
72 	if (!ring->tx_info) {
73 		err = -ENOMEM;
74 		goto err_ring;
75 	}
76 
77 	en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
78 		 ring->tx_info, tmp);
79 
80 	ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
81 	if (!ring->bounce_buf) {
82 		ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
83 		if (!ring->bounce_buf) {
84 			err = -ENOMEM;
85 			goto err_info;
86 		}
87 	}
88 	ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
89 
90 	/* Allocate HW buffers on provided NUMA node */
91 	set_dev_node(&mdev->dev->persist->pdev->dev, node);
92 	err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
93 	set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
94 	if (err) {
95 		en_err(priv, "Failed allocating hwq resources\n");
96 		goto err_bounce;
97 	}
98 
99 	ring->buf = ring->sp_wqres.buf.direct.buf;
100 
101 	en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
102 	       ring, ring->buf, ring->size, ring->buf_size,
103 	       (unsigned long long) ring->sp_wqres.buf.direct.map);
104 
105 	err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
106 				    MLX4_RESERVE_ETH_BF_QP,
107 				    MLX4_RES_USAGE_DRIVER);
108 	if (err) {
109 		en_err(priv, "failed reserving qp for TX ring\n");
110 		goto err_hwq_res;
111 	}
112 
113 	err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp);
114 	if (err) {
115 		en_err(priv, "Failed allocating qp %d\n", ring->qpn);
116 		goto err_reserve;
117 	}
118 	ring->sp_qp.event = mlx4_en_sqp_event;
119 
120 	err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
121 	if (err) {
122 		en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
123 		ring->bf.uar = &mdev->priv_uar;
124 		ring->bf.uar->map = mdev->uar_map;
125 		ring->bf_enabled = false;
126 		ring->bf_alloced = false;
127 		priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
128 	} else {
129 		ring->bf_alloced = true;
130 		ring->bf_enabled = !!(priv->pflags &
131 				      MLX4_EN_PRIV_FLAGS_BLUEFLAME);
132 	}
133 	ring->doorbell_address = ring->bf.uar->map + MLX4_SEND_DOORBELL;
134 
135 	ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
136 	ring->queue_index = queue_index;
137 
138 	if (queue_index < priv->num_tx_rings_p_up)
139 		cpumask_set_cpu(cpumask_local_spread(queue_index,
140 						     priv->mdev->dev->numa_node),
141 				&ring->sp_affinity_mask);
142 
143 	*pring = ring;
144 	return 0;
145 
146 err_reserve:
147 	mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
148 err_hwq_res:
149 	mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
150 err_bounce:
151 	kfree(ring->bounce_buf);
152 	ring->bounce_buf = NULL;
153 err_info:
154 	kvfree(ring->tx_info);
155 	ring->tx_info = NULL;
156 err_ring:
157 	kfree(ring);
158 	*pring = NULL;
159 	return err;
160 }
161 
162 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
163 			     struct mlx4_en_tx_ring **pring)
164 {
165 	struct mlx4_en_dev *mdev = priv->mdev;
166 	struct mlx4_en_tx_ring *ring = *pring;
167 	en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
168 
169 	if (ring->bf_alloced)
170 		mlx4_bf_free(mdev->dev, &ring->bf);
171 	mlx4_qp_remove(mdev->dev, &ring->sp_qp);
172 	mlx4_qp_free(mdev->dev, &ring->sp_qp);
173 	mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
174 	mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
175 	kfree(ring->bounce_buf);
176 	ring->bounce_buf = NULL;
177 	kvfree(ring->tx_info);
178 	ring->tx_info = NULL;
179 	kfree(ring);
180 	*pring = NULL;
181 }
182 
183 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
184 			     struct mlx4_en_tx_ring *ring,
185 			     int cq, int user_prio)
186 {
187 	struct mlx4_en_dev *mdev = priv->mdev;
188 	int err;
189 
190 	ring->sp_cqn = cq;
191 	ring->prod = 0;
192 	ring->cons = 0xffffffff;
193 	ring->last_nr_txbb = 1;
194 	memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
195 	memset(ring->buf, 0, ring->buf_size);
196 	ring->free_tx_desc = mlx4_en_free_tx_desc;
197 
198 	ring->sp_qp_state = MLX4_QP_STATE_RST;
199 	ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
200 	ring->mr_key = cpu_to_be32(mdev->mr.key);
201 
202 	mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
203 				ring->sp_cqn, user_prio, &ring->sp_context);
204 	if (ring->bf_alloced)
205 		ring->sp_context.usr_page =
206 			cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
207 							 ring->bf.uar->index));
208 
209 	err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
210 			       &ring->sp_qp, &ring->sp_qp_state);
211 	if (!cpumask_empty(&ring->sp_affinity_mask))
212 		netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
213 				    ring->queue_index);
214 
215 	return err;
216 }
217 
218 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
219 				struct mlx4_en_tx_ring *ring)
220 {
221 	struct mlx4_en_dev *mdev = priv->mdev;
222 
223 	mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
224 		       MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
225 }
226 
227 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
228 {
229 	return ring->prod - ring->cons > ring->full_size;
230 }
231 
232 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
233 			      struct mlx4_en_tx_ring *ring, int index,
234 			      u8 owner)
235 {
236 	__be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
237 	struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
238 	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
239 	void *end = ring->buf + ring->buf_size;
240 	__be32 *ptr = (__be32 *)tx_desc;
241 	int i;
242 
243 	/* Optimize the common case when there are no wraparounds */
244 	if (likely((void *)tx_desc +
245 		   (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
246 		/* Stamp the freed descriptor */
247 		for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
248 		     i += STAMP_STRIDE) {
249 			*ptr = stamp;
250 			ptr += STAMP_DWORDS;
251 		}
252 	} else {
253 		/* Stamp the freed descriptor */
254 		for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
255 		     i += STAMP_STRIDE) {
256 			*ptr = stamp;
257 			ptr += STAMP_DWORDS;
258 			if ((void *)ptr >= end) {
259 				ptr = ring->buf;
260 				stamp ^= cpu_to_be32(0x80000000);
261 			}
262 		}
263 	}
264 }
265 
266 INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
267 						   struct mlx4_en_tx_ring *ring,
268 						   int index, u64 timestamp,
269 						   int napi_mode));
270 
271 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
272 			 struct mlx4_en_tx_ring *ring,
273 			 int index, u64 timestamp,
274 			 int napi_mode)
275 {
276 	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
277 	struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
278 	struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
279 	void *end = ring->buf + ring->buf_size;
280 	struct sk_buff *skb = tx_info->skb;
281 	int nr_maps = tx_info->nr_maps;
282 	int i;
283 
284 	/* We do not touch skb here, so prefetch skb->users location
285 	 * to speedup consume_skb()
286 	 */
287 	prefetchw(&skb->users);
288 
289 	if (unlikely(timestamp)) {
290 		struct skb_shared_hwtstamps hwts;
291 
292 		mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
293 		skb_tstamp_tx(skb, &hwts);
294 	}
295 
296 	if (!tx_info->inl) {
297 		if (tx_info->linear)
298 			dma_unmap_single(priv->ddev,
299 					 tx_info->map0_dma,
300 					 tx_info->map0_byte_count,
301 					 DMA_TO_DEVICE);
302 		else
303 			dma_unmap_page(priv->ddev,
304 				       tx_info->map0_dma,
305 				       tx_info->map0_byte_count,
306 				       DMA_TO_DEVICE);
307 		/* Optimize the common case when there are no wraparounds */
308 		if (likely((void *)tx_desc +
309 			   (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
310 			for (i = 1; i < nr_maps; i++) {
311 				data++;
312 				dma_unmap_page(priv->ddev,
313 					(dma_addr_t)be64_to_cpu(data->addr),
314 					be32_to_cpu(data->byte_count),
315 					DMA_TO_DEVICE);
316 			}
317 		} else {
318 			if ((void *)data >= end)
319 				data = ring->buf + ((void *)data - end);
320 
321 			for (i = 1; i < nr_maps; i++) {
322 				data++;
323 				/* Check for wraparound before unmapping */
324 				if ((void *) data >= end)
325 					data = ring->buf;
326 				dma_unmap_page(priv->ddev,
327 					(dma_addr_t)be64_to_cpu(data->addr),
328 					be32_to_cpu(data->byte_count),
329 					DMA_TO_DEVICE);
330 			}
331 		}
332 	}
333 	napi_consume_skb(skb, napi_mode);
334 
335 	return tx_info->nr_txbb;
336 }
337 
338 INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
339 						      struct mlx4_en_tx_ring *ring,
340 						      int index, u64 timestamp,
341 						      int napi_mode));
342 
343 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
344 			    struct mlx4_en_tx_ring *ring,
345 			    int index, u64 timestamp,
346 			    int napi_mode)
347 {
348 	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
349 	struct mlx4_en_rx_alloc frame = {
350 		.page = tx_info->page,
351 		.dma = tx_info->map0_dma,
352 	};
353 
354 	if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) {
355 		dma_unmap_page(priv->ddev, tx_info->map0_dma,
356 			       PAGE_SIZE, priv->dma_dir);
357 		put_page(tx_info->page);
358 	}
359 
360 	return tx_info->nr_txbb;
361 }
362 
363 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
364 {
365 	struct mlx4_en_priv *priv = netdev_priv(dev);
366 	int cnt = 0;
367 
368 	/* Skip last polled descriptor */
369 	ring->cons += ring->last_nr_txbb;
370 	en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
371 		 ring->cons, ring->prod);
372 
373 	if ((u32) (ring->prod - ring->cons) > ring->size) {
374 		if (netif_msg_tx_err(priv))
375 			en_warn(priv, "Tx consumer passed producer!\n");
376 		return 0;
377 	}
378 
379 	while (ring->cons != ring->prod) {
380 		ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
381 						ring->cons & ring->size_mask,
382 						0, 0 /* Non-NAPI caller */);
383 		ring->cons += ring->last_nr_txbb;
384 		cnt++;
385 	}
386 
387 	if (ring->tx_queue)
388 		netdev_tx_reset_queue(ring->tx_queue);
389 
390 	if (cnt)
391 		en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
392 
393 	return cnt;
394 }
395 
396 static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe,
397 				   u16 cqe_index, struct mlx4_en_tx_ring *ring)
398 {
399 	struct mlx4_en_dev *mdev = priv->mdev;
400 	struct mlx4_en_tx_info *tx_info;
401 	struct mlx4_en_tx_desc *tx_desc;
402 	u16 wqe_index;
403 	int desc_size;
404 
405 	en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n",
406 	       ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome);
407 	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe),
408 		       false);
409 
410 	wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask;
411 	tx_info = &ring->tx_info[wqe_index];
412 	desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE;
413 	en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn,
414 	       wqe_index, desc_size);
415 	tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE);
416 	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false);
417 
418 	if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state))
419 		return;
420 
421 	en_err(priv, "Scheduling port restart\n");
422 	queue_work(mdev->workqueue, &priv->restart_task);
423 }
424 
425 int mlx4_en_process_tx_cq(struct net_device *dev,
426 			  struct mlx4_en_cq *cq, int napi_budget)
427 {
428 	struct mlx4_en_priv *priv = netdev_priv(dev);
429 	struct mlx4_cq *mcq = &cq->mcq;
430 	struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
431 	struct mlx4_cqe *cqe;
432 	u16 index, ring_index, stamp_index;
433 	u32 txbbs_skipped = 0;
434 	u32 txbbs_stamp = 0;
435 	u32 cons_index = mcq->cons_index;
436 	int size = cq->size;
437 	u32 size_mask = ring->size_mask;
438 	struct mlx4_cqe *buf = cq->buf;
439 	u32 packets = 0;
440 	u32 bytes = 0;
441 	int factor = priv->cqe_factor;
442 	int done = 0;
443 	int budget = priv->tx_work_limit;
444 	u32 last_nr_txbb;
445 	u32 ring_cons;
446 
447 	if (unlikely(!priv->port_up))
448 		return 0;
449 
450 	netdev_txq_bql_complete_prefetchw(ring->tx_queue);
451 
452 	index = cons_index & size_mask;
453 	cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
454 	last_nr_txbb = READ_ONCE(ring->last_nr_txbb);
455 	ring_cons = READ_ONCE(ring->cons);
456 	ring_index = ring_cons & size_mask;
457 	stamp_index = ring_index;
458 
459 	/* Process all completed CQEs */
460 	while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
461 			cons_index & size) && (done < budget)) {
462 		u16 new_index;
463 
464 		/*
465 		 * make sure we read the CQE after we read the
466 		 * ownership bit
467 		 */
468 		dma_rmb();
469 
470 		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
471 			     MLX4_CQE_OPCODE_ERROR))
472 			if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state))
473 				mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index,
474 						       ring);
475 
476 		/* Skip over last polled CQE */
477 		new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
478 
479 		do {
480 			u64 timestamp = 0;
481 
482 			txbbs_skipped += last_nr_txbb;
483 			ring_index = (ring_index + last_nr_txbb) & size_mask;
484 
485 			if (unlikely(ring->tx_info[ring_index].ts_requested))
486 				timestamp = mlx4_en_get_cqe_ts(cqe);
487 
488 			/* free next descriptor */
489 			last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc,
490 						       mlx4_en_free_tx_desc,
491 						       mlx4_en_recycle_tx_desc,
492 					priv, ring, ring_index,
493 					timestamp, napi_budget);
494 
495 			mlx4_en_stamp_wqe(priv, ring, stamp_index,
496 					  !!((ring_cons + txbbs_stamp) &
497 						ring->size));
498 			stamp_index = ring_index;
499 			txbbs_stamp = txbbs_skipped;
500 			packets++;
501 			bytes += ring->tx_info[ring_index].nr_bytes;
502 		} while ((++done < budget) && (ring_index != new_index));
503 
504 		++cons_index;
505 		index = cons_index & size_mask;
506 		cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
507 	}
508 
509 	/*
510 	 * To prevent CQ overflow we first update CQ consumer and only then
511 	 * the ring consumer.
512 	 */
513 	mcq->cons_index = cons_index;
514 	mlx4_cq_set_ci(mcq);
515 	wmb();
516 
517 	/* we want to dirty this cache line once */
518 	WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb);
519 	WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped);
520 
521 	if (cq->type == TX_XDP)
522 		return done;
523 
524 	netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
525 
526 	/* Wakeup Tx queue if this stopped, and ring is not full.
527 	 */
528 	if (netif_tx_queue_stopped(ring->tx_queue) &&
529 	    !mlx4_en_is_tx_ring_full(ring)) {
530 		netif_tx_wake_queue(ring->tx_queue);
531 		ring->wake_queue++;
532 	}
533 
534 	return done;
535 }
536 
537 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
538 {
539 	struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
540 	struct mlx4_en_priv *priv = netdev_priv(cq->dev);
541 
542 	if (likely(priv->port_up))
543 		napi_schedule_irqoff(&cq->napi);
544 	else
545 		mlx4_en_arm_cq(priv, cq);
546 }
547 
548 /* TX CQ polling - called by NAPI */
549 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
550 {
551 	struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
552 	struct net_device *dev = cq->dev;
553 	struct mlx4_en_priv *priv = netdev_priv(dev);
554 	int work_done;
555 
556 	work_done = mlx4_en_process_tx_cq(dev, cq, budget);
557 	if (work_done >= budget)
558 		return budget;
559 
560 	if (napi_complete_done(napi, work_done))
561 		mlx4_en_arm_cq(priv, cq);
562 
563 	return 0;
564 }
565 
566 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
567 						      struct mlx4_en_tx_ring *ring,
568 						      u32 index,
569 						      unsigned int desc_size)
570 {
571 	u32 copy = (ring->size - index) << LOG_TXBB_SIZE;
572 	int i;
573 
574 	for (i = desc_size - copy - 4; i >= 0; i -= 4) {
575 		if ((i & (TXBB_SIZE - 1)) == 0)
576 			wmb();
577 
578 		*((u32 *) (ring->buf + i)) =
579 			*((u32 *) (ring->bounce_buf + copy + i));
580 	}
581 
582 	for (i = copy - 4; i >= 4 ; i -= 4) {
583 		if ((i & (TXBB_SIZE - 1)) == 0)
584 			wmb();
585 
586 		*((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) =
587 			*((u32 *) (ring->bounce_buf + i));
588 	}
589 
590 	/* Return real descriptor location */
591 	return ring->buf + (index << LOG_TXBB_SIZE);
592 }
593 
594 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
595  *
596  * It seems strange we do not simply use skb_copy_bits().
597  * This would allow to inline all skbs iff skb->len <= inline_thold
598  *
599  * Note that caller already checked skb was not a gso packet
600  */
601 static bool is_inline(int inline_thold, const struct sk_buff *skb,
602 		      const struct skb_shared_info *shinfo,
603 		      void **pfrag)
604 {
605 	void *ptr;
606 
607 	if (skb->len > inline_thold || !inline_thold)
608 		return false;
609 
610 	if (shinfo->nr_frags == 1) {
611 		ptr = skb_frag_address_safe(&shinfo->frags[0]);
612 		if (unlikely(!ptr))
613 			return false;
614 		*pfrag = ptr;
615 		return true;
616 	}
617 	if (shinfo->nr_frags)
618 		return false;
619 	return true;
620 }
621 
622 static int inline_size(const struct sk_buff *skb)
623 {
624 	if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
625 	    <= MLX4_INLINE_ALIGN)
626 		return ALIGN(skb->len + CTRL_SIZE +
627 			     sizeof(struct mlx4_wqe_inline_seg), 16);
628 	else
629 		return ALIGN(skb->len + CTRL_SIZE + 2 *
630 			     sizeof(struct mlx4_wqe_inline_seg), 16);
631 }
632 
633 static int get_real_size(const struct sk_buff *skb,
634 			 const struct skb_shared_info *shinfo,
635 			 struct net_device *dev,
636 			 int *lso_header_size,
637 			 bool *inline_ok,
638 			 void **pfrag,
639 			 int *hopbyhop)
640 {
641 	struct mlx4_en_priv *priv = netdev_priv(dev);
642 	int real_size;
643 
644 	if (shinfo->gso_size) {
645 		*inline_ok = false;
646 		*hopbyhop = 0;
647 		if (skb->encapsulation) {
648 			*lso_header_size = skb_inner_tcp_all_headers(skb);
649 		} else {
650 			/* Detects large IPV6 TCP packets and prepares for removal of
651 			 * HBH header that has been pushed by ip6_xmit(),
652 			 * mainly so that tcpdump can dissect them.
653 			 */
654 			if (ipv6_has_hopopt_jumbo(skb))
655 				*hopbyhop = sizeof(struct hop_jumbo_hdr);
656 			*lso_header_size = skb_tcp_all_headers(skb);
657 		}
658 		real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
659 			ALIGN(*lso_header_size - *hopbyhop + 4, DS_SIZE);
660 		if (unlikely(*lso_header_size != skb_headlen(skb))) {
661 			/* We add a segment for the skb linear buffer only if
662 			 * it contains data */
663 			if (*lso_header_size < skb_headlen(skb))
664 				real_size += DS_SIZE;
665 			else {
666 				if (netif_msg_tx_err(priv))
667 					en_warn(priv, "Non-linear headers\n");
668 				return 0;
669 			}
670 		}
671 	} else {
672 		*lso_header_size = 0;
673 		*inline_ok = is_inline(priv->prof->inline_thold, skb,
674 				       shinfo, pfrag);
675 
676 		if (*inline_ok)
677 			real_size = inline_size(skb);
678 		else
679 			real_size = CTRL_SIZE +
680 				    (shinfo->nr_frags + 1) * DS_SIZE;
681 	}
682 
683 	return real_size;
684 }
685 
686 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
687 			     const struct sk_buff *skb,
688 			     const struct skb_shared_info *shinfo,
689 			     void *fragptr)
690 {
691 	struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
692 	int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl);
693 	unsigned int hlen = skb_headlen(skb);
694 
695 	if (skb->len <= spc) {
696 		if (likely(skb->len >= MIN_PKT_LEN)) {
697 			inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
698 		} else {
699 			inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
700 			memset(((void *)(inl + 1)) + skb->len, 0,
701 			       MIN_PKT_LEN - skb->len);
702 		}
703 		skb_copy_from_linear_data(skb, inl + 1, hlen);
704 		if (shinfo->nr_frags)
705 			memcpy(((void *)(inl + 1)) + hlen, fragptr,
706 			       skb_frag_size(&shinfo->frags[0]));
707 
708 	} else {
709 		inl->byte_count = cpu_to_be32(1 << 31 | spc);
710 		if (hlen <= spc) {
711 			skb_copy_from_linear_data(skb, inl + 1, hlen);
712 			if (hlen < spc) {
713 				memcpy(((void *)(inl + 1)) + hlen,
714 				       fragptr, spc - hlen);
715 				fragptr +=  spc - hlen;
716 			}
717 			inl = (void *) (inl + 1) + spc;
718 			memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
719 		} else {
720 			skb_copy_from_linear_data(skb, inl + 1, spc);
721 			inl = (void *) (inl + 1) + spc;
722 			skb_copy_from_linear_data_offset(skb, spc, inl + 1,
723 							 hlen - spc);
724 			if (shinfo->nr_frags)
725 				memcpy(((void *)(inl + 1)) + hlen - spc,
726 				       fragptr,
727 				       skb_frag_size(&shinfo->frags[0]));
728 		}
729 
730 		dma_wmb();
731 		inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
732 	}
733 }
734 
735 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
736 			 struct net_device *sb_dev)
737 {
738 	struct mlx4_en_priv *priv = netdev_priv(dev);
739 	u16 rings_p_up = priv->num_tx_rings_p_up;
740 
741 	if (netdev_get_num_tc(dev))
742 		return netdev_pick_tx(dev, skb, NULL);
743 
744 	return netdev_pick_tx(dev, skb, NULL) % rings_p_up;
745 }
746 
747 static void mlx4_bf_copy(void __iomem *dst, const void *src,
748 			 unsigned int bytecnt)
749 {
750 	__iowrite64_copy(dst, src, bytecnt / 8);
751 }
752 
753 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
754 {
755 	wmb();
756 	/* Since there is no iowrite*_native() that writes the
757 	 * value as is, without byteswapping - using the one
758 	 * the doesn't do byteswapping in the relevant arch
759 	 * endianness.
760 	 */
761 #if defined(__LITTLE_ENDIAN)
762 	iowrite32(
763 #else
764 	iowrite32be(
765 #endif
766 		  (__force u32)ring->doorbell_qpn, ring->doorbell_address);
767 }
768 
769 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
770 				  struct mlx4_en_tx_desc *tx_desc,
771 				  union mlx4_wqe_qpn_vlan qpn_vlan,
772 				  int desc_size, int bf_index,
773 				  __be32 op_own, bool bf_ok,
774 				  bool send_doorbell)
775 {
776 	tx_desc->ctrl.qpn_vlan = qpn_vlan;
777 
778 	if (bf_ok) {
779 		op_own |= htonl((bf_index & 0xffff) << 8);
780 		/* Ensure new descriptor hits memory
781 		 * before setting ownership of this descriptor to HW
782 		 */
783 		dma_wmb();
784 		tx_desc->ctrl.owner_opcode = op_own;
785 
786 		wmb();
787 
788 		mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
789 			     desc_size);
790 
791 		wmb();
792 
793 		ring->bf.offset ^= ring->bf.buf_size;
794 	} else {
795 		/* Ensure new descriptor hits memory
796 		 * before setting ownership of this descriptor to HW
797 		 */
798 		dma_wmb();
799 		tx_desc->ctrl.owner_opcode = op_own;
800 		if (send_doorbell)
801 			mlx4_en_xmit_doorbell(ring);
802 		else
803 			ring->xmit_more++;
804 	}
805 }
806 
807 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv,
808 				  struct skb_shared_info *shinfo,
809 				  struct mlx4_wqe_data_seg *data,
810 				  struct sk_buff *skb,
811 				  int lso_header_size,
812 				  __be32 mr_key,
813 				  struct mlx4_en_tx_info *tx_info)
814 {
815 	struct device *ddev = priv->ddev;
816 	dma_addr_t dma = 0;
817 	u32 byte_count = 0;
818 	int i_frag;
819 
820 	/* Map fragments if any */
821 	for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
822 		const skb_frag_t *frag = &shinfo->frags[i_frag];
823 		byte_count = skb_frag_size(frag);
824 		dma = skb_frag_dma_map(ddev, frag,
825 				       0, byte_count,
826 				       DMA_TO_DEVICE);
827 		if (dma_mapping_error(ddev, dma))
828 			goto tx_drop_unmap;
829 
830 		data->addr = cpu_to_be64(dma);
831 		data->lkey = mr_key;
832 		dma_wmb();
833 		data->byte_count = cpu_to_be32(byte_count);
834 		--data;
835 	}
836 
837 	/* Map linear part if needed */
838 	if (tx_info->linear) {
839 		byte_count = skb_headlen(skb) - lso_header_size;
840 
841 		dma = dma_map_single(ddev, skb->data +
842 				     lso_header_size, byte_count,
843 				     DMA_TO_DEVICE);
844 		if (dma_mapping_error(ddev, dma))
845 			goto tx_drop_unmap;
846 
847 		data->addr = cpu_to_be64(dma);
848 		data->lkey = mr_key;
849 		dma_wmb();
850 		data->byte_count = cpu_to_be32(byte_count);
851 	}
852 	/* tx completion can avoid cache line miss for common cases */
853 	tx_info->map0_dma = dma;
854 	tx_info->map0_byte_count = byte_count;
855 
856 	return true;
857 
858 tx_drop_unmap:
859 	en_err(priv, "DMA mapping error\n");
860 
861 	while (++i_frag < shinfo->nr_frags) {
862 		++data;
863 		dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr),
864 			       be32_to_cpu(data->byte_count),
865 			       DMA_TO_DEVICE);
866 	}
867 
868 	return false;
869 }
870 
871 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
872 {
873 	struct skb_shared_info *shinfo = skb_shinfo(skb);
874 	struct mlx4_en_priv *priv = netdev_priv(dev);
875 	union mlx4_wqe_qpn_vlan	qpn_vlan = {};
876 	struct mlx4_en_tx_ring *ring;
877 	struct mlx4_en_tx_desc *tx_desc;
878 	struct mlx4_wqe_data_seg *data;
879 	struct mlx4_en_tx_info *tx_info;
880 	u32 __maybe_unused ring_cons;
881 	int tx_ind;
882 	int nr_txbb;
883 	int desc_size;
884 	int real_size;
885 	u32 index, bf_index;
886 	struct ipv6hdr *h6;
887 	__be32 op_own;
888 	int lso_header_size;
889 	void *fragptr = NULL;
890 	bool bounce = false;
891 	bool send_doorbell;
892 	bool stop_queue;
893 	bool inline_ok;
894 	u8 data_offset;
895 	int hopbyhop;
896 	bool bf_ok;
897 
898 	tx_ind = skb_get_queue_mapping(skb);
899 	ring = priv->tx_ring[TX][tx_ind];
900 
901 	if (unlikely(!priv->port_up))
902 		goto tx_drop;
903 
904 	real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
905 				  &inline_ok, &fragptr, &hopbyhop);
906 	if (unlikely(!real_size))
907 		goto tx_drop_count;
908 
909 	/* Align descriptor to TXBB size */
910 	desc_size = ALIGN(real_size, TXBB_SIZE);
911 	nr_txbb = desc_size >> LOG_TXBB_SIZE;
912 	if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
913 		if (netif_msg_tx_err(priv))
914 			en_warn(priv, "Oversized header or SG list\n");
915 		goto tx_drop_count;
916 	}
917 
918 	bf_ok = ring->bf_enabled;
919 	if (skb_vlan_tag_present(skb)) {
920 		u16 vlan_proto;
921 
922 		qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
923 		vlan_proto = be16_to_cpu(skb->vlan_proto);
924 		if (vlan_proto == ETH_P_8021AD)
925 			qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
926 		else if (vlan_proto == ETH_P_8021Q)
927 			qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
928 		else
929 			qpn_vlan.ins_vlan = 0;
930 		bf_ok = false;
931 	}
932 
933 	netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
934 
935 	/* Packet is good - grab an index and transmit it */
936 	index = ring->prod & ring->size_mask;
937 	bf_index = ring->prod;
938 
939 	/* See if we have enough space for whole descriptor TXBB for setting
940 	 * SW ownership on next descriptor; if not, use a bounce buffer. */
941 	if (likely(index + nr_txbb <= ring->size))
942 		tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
943 	else {
944 		tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
945 		bounce = true;
946 		bf_ok = false;
947 	}
948 
949 	/* Save skb in tx_info ring */
950 	tx_info = &ring->tx_info[index];
951 	tx_info->skb = skb;
952 	tx_info->nr_txbb = nr_txbb;
953 
954 	if (!lso_header_size) {
955 		data = &tx_desc->data;
956 		data_offset = offsetof(struct mlx4_en_tx_desc, data);
957 	} else {
958 		int lso_align = ALIGN(lso_header_size - hopbyhop + 4, DS_SIZE);
959 
960 		data = (void *)&tx_desc->lso + lso_align;
961 		data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align;
962 	}
963 
964 	/* valid only for none inline segments */
965 	tx_info->data_offset = data_offset;
966 
967 	tx_info->inl = inline_ok;
968 
969 	tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok;
970 
971 	tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
972 	data += tx_info->nr_maps - 1;
973 
974 	if (!tx_info->inl)
975 		if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb,
976 					   lso_header_size, ring->mr_key,
977 					   tx_info))
978 			goto tx_drop_count;
979 
980 	/*
981 	 * For timestamping add flag to skb_shinfo and
982 	 * set flag for further reference
983 	 */
984 	tx_info->ts_requested = 0;
985 	if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
986 		     shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
987 		shinfo->tx_flags |= SKBTX_IN_PROGRESS;
988 		tx_info->ts_requested = 1;
989 	}
990 
991 	/* Prepare ctrl segement apart opcode+ownership, which depends on
992 	 * whether LSO is used */
993 	tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
994 	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
995 		if (!skb->encapsulation)
996 			tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
997 								 MLX4_WQE_CTRL_TCP_UDP_CSUM);
998 		else
999 			tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
1000 		ring->tx_csum++;
1001 	}
1002 
1003 	if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
1004 		struct ethhdr *ethh;
1005 
1006 		/* Copy dst mac address to wqe. This allows loopback in eSwitch,
1007 		 * so that VFs and PF can communicate with each other
1008 		 */
1009 		ethh = (struct ethhdr *)skb->data;
1010 		tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
1011 		tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
1012 	}
1013 
1014 	/* Handle LSO (TSO) packets */
1015 	if (lso_header_size) {
1016 		int i;
1017 
1018 		/* Mark opcode as LSO */
1019 		op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
1020 			((ring->prod & ring->size) ?
1021 				cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1022 
1023 		lso_header_size -= hopbyhop;
1024 		/* Fill in the LSO prefix */
1025 		tx_desc->lso.mss_hdr_size = cpu_to_be32(
1026 			shinfo->gso_size << 16 | lso_header_size);
1027 
1028 
1029 		if (unlikely(hopbyhop)) {
1030 			/* remove the HBH header.
1031 			 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
1032 			 */
1033 			memcpy(tx_desc->lso.header, skb->data, ETH_HLEN + sizeof(*h6));
1034 			h6 = (struct ipv6hdr *)((char *)tx_desc->lso.header + ETH_HLEN);
1035 			h6->nexthdr = IPPROTO_TCP;
1036 			/* Copy the TCP header after the IPv6 one */
1037 			memcpy(h6 + 1,
1038 			       skb->data + ETH_HLEN + sizeof(*h6) +
1039 					sizeof(struct hop_jumbo_hdr),
1040 			       tcp_hdrlen(skb));
1041 			/* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
1042 		} else {
1043 			/* Copy headers;
1044 			 * note that we already verified that it is linear
1045 			 */
1046 			memcpy(tx_desc->lso.header, skb->data, lso_header_size);
1047 		}
1048 		ring->tso_packets++;
1049 
1050 		i = shinfo->gso_segs;
1051 		tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
1052 		ring->packets += i;
1053 	} else {
1054 		/* Normal (Non LSO) packet */
1055 		op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1056 			((ring->prod & ring->size) ?
1057 			 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1058 		tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
1059 		ring->packets++;
1060 	}
1061 	ring->bytes += tx_info->nr_bytes;
1062 
1063 	if (tx_info->inl)
1064 		build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1065 
1066 	if (skb->encapsulation) {
1067 		union {
1068 			struct iphdr *v4;
1069 			struct ipv6hdr *v6;
1070 			unsigned char *hdr;
1071 		} ip;
1072 		u8 proto;
1073 
1074 		ip.hdr = skb_inner_network_header(skb);
1075 		proto = (ip.v4->version == 4) ? ip.v4->protocol :
1076 						ip.v6->nexthdr;
1077 
1078 		if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1079 			op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1080 		else
1081 			op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1082 	}
1083 
1084 	ring->prod += nr_txbb;
1085 
1086 	/* If we used a bounce buffer then copy descriptor back into place */
1087 	if (unlikely(bounce))
1088 		tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1089 
1090 	skb_tx_timestamp(skb);
1091 
1092 	/* Check available TXBBs And 2K spare for prefetch */
1093 	stop_queue = mlx4_en_is_tx_ring_full(ring);
1094 	if (unlikely(stop_queue)) {
1095 		netif_tx_stop_queue(ring->tx_queue);
1096 		ring->queue_stopped++;
1097 	}
1098 
1099 	send_doorbell = __netdev_tx_sent_queue(ring->tx_queue,
1100 					       tx_info->nr_bytes,
1101 					       netdev_xmit_more());
1102 
1103 	real_size = (real_size / 16) & 0x3f;
1104 
1105 	bf_ok &= desc_size <= MAX_BF && send_doorbell;
1106 
1107 	if (bf_ok)
1108 		qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1109 	else
1110 		qpn_vlan.fence_size = real_size;
1111 
1112 	mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1113 			      op_own, bf_ok, send_doorbell);
1114 
1115 	if (unlikely(stop_queue)) {
1116 		/* If queue was emptied after the if (stop_queue) , and before
1117 		 * the netif_tx_stop_queue() - need to wake the queue,
1118 		 * or else it will remain stopped forever.
1119 		 * Need a memory barrier to make sure ring->cons was not
1120 		 * updated before queue was stopped.
1121 		 */
1122 		smp_rmb();
1123 
1124 		if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1125 			netif_tx_wake_queue(ring->tx_queue);
1126 			ring->wake_queue++;
1127 		}
1128 	}
1129 	return NETDEV_TX_OK;
1130 
1131 tx_drop_count:
1132 	ring->tx_dropped++;
1133 tx_drop:
1134 	dev_kfree_skb_any(skb);
1135 	return NETDEV_TX_OK;
1136 }
1137 
1138 #define MLX4_EN_XDP_TX_NRTXBB  1
1139 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \
1140 				 / 16) & 0x3f)
1141 
1142 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
1143 				    struct mlx4_en_tx_ring *ring)
1144 {
1145 	int i;
1146 
1147 	for (i = 0; i < ring->size; i++) {
1148 		struct mlx4_en_tx_info *tx_info = &ring->tx_info[i];
1149 		struct mlx4_en_tx_desc *tx_desc = ring->buf +
1150 			(i << LOG_TXBB_SIZE);
1151 
1152 		tx_info->map0_byte_count = PAGE_SIZE;
1153 		tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB;
1154 		tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data);
1155 		tx_info->ts_requested = 0;
1156 		tx_info->nr_maps = 1;
1157 		tx_info->linear = 1;
1158 		tx_info->inl = 0;
1159 
1160 		tx_desc->data.lkey = ring->mr_key;
1161 		tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ;
1162 		tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1163 	}
1164 }
1165 
1166 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1167 			       struct mlx4_en_rx_alloc *frame,
1168 			       struct mlx4_en_priv *priv, unsigned int length,
1169 			       int tx_ind, bool *doorbell_pending)
1170 {
1171 	struct mlx4_en_tx_desc *tx_desc;
1172 	struct mlx4_en_tx_info *tx_info;
1173 	struct mlx4_wqe_data_seg *data;
1174 	struct mlx4_en_tx_ring *ring;
1175 	dma_addr_t dma;
1176 	__be32 op_own;
1177 	int index;
1178 
1179 	if (unlikely(!priv->port_up))
1180 		goto tx_drop;
1181 
1182 	ring = priv->tx_ring[TX_XDP][tx_ind];
1183 
1184 	if (unlikely(mlx4_en_is_tx_ring_full(ring)))
1185 		goto tx_drop_count;
1186 
1187 	index = ring->prod & ring->size_mask;
1188 	tx_info = &ring->tx_info[index];
1189 
1190 	tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
1191 	data = &tx_desc->data;
1192 
1193 	dma = frame->dma;
1194 
1195 	tx_info->page = frame->page;
1196 	frame->page = NULL;
1197 	tx_info->map0_dma = dma;
1198 	tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1199 
1200 	dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1201 					 length, DMA_TO_DEVICE);
1202 
1203 	data->addr = cpu_to_be64(dma + frame->page_offset);
1204 	dma_wmb();
1205 	data->byte_count = cpu_to_be32(length);
1206 
1207 	/* tx completion can avoid cache line miss for common cases */
1208 
1209 	op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1210 		((ring->prod & ring->size) ?
1211 		 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1212 
1213 	rx_ring->xdp_tx++;
1214 
1215 	ring->prod += MLX4_EN_XDP_TX_NRTXBB;
1216 
1217 	/* Ensure new descriptor hits memory
1218 	 * before setting ownership of this descriptor to HW
1219 	 */
1220 	dma_wmb();
1221 	tx_desc->ctrl.owner_opcode = op_own;
1222 	ring->xmit_more++;
1223 
1224 	*doorbell_pending = true;
1225 
1226 	return NETDEV_TX_OK;
1227 
1228 tx_drop_count:
1229 	rx_ring->xdp_tx_full++;
1230 	*doorbell_pending = true;
1231 tx_drop:
1232 	return NETDEV_TX_BUSY;
1233 }
1234