1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 61 if (!ring) { 62 en_err(priv, "Failed allocating TX ring\n"); 63 return -ENOMEM; 64 } 65 } 66 67 ring->size = size; 68 ring->size_mask = size - 1; 69 ring->sp_stride = stride; 70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 71 72 tmp = size * sizeof(struct mlx4_en_tx_info); 73 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); 74 if (!ring->tx_info) { 75 err = -ENOMEM; 76 goto err_ring; 77 } 78 79 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 80 ring->tx_info, tmp); 81 82 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 83 if (!ring->bounce_buf) { 84 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 85 if (!ring->bounce_buf) { 86 err = -ENOMEM; 87 goto err_info; 88 } 89 } 90 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 91 92 /* Allocate HW buffers on provided NUMA node */ 93 set_dev_node(&mdev->dev->persist->pdev->dev, node); 94 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 95 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 96 if (err) { 97 en_err(priv, "Failed allocating hwq resources\n"); 98 goto err_bounce; 99 } 100 101 ring->buf = ring->sp_wqres.buf.direct.buf; 102 103 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 104 ring, ring->buf, ring->size, ring->buf_size, 105 (unsigned long long) ring->sp_wqres.buf.direct.map); 106 107 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 108 MLX4_RESERVE_ETH_BF_QP); 109 if (err) { 110 en_err(priv, "failed reserving qp for TX ring\n"); 111 goto err_hwq_res; 112 } 113 114 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); 115 if (err) { 116 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 117 goto err_reserve; 118 } 119 ring->sp_qp.event = mlx4_en_sqp_event; 120 121 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 122 if (err) { 123 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 124 ring->bf.uar = &mdev->priv_uar; 125 ring->bf.uar->map = mdev->uar_map; 126 ring->bf_enabled = false; 127 ring->bf_alloced = false; 128 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 129 } else { 130 ring->bf_alloced = true; 131 ring->bf_enabled = !!(priv->pflags & 132 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 133 } 134 135 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 136 ring->queue_index = queue_index; 137 138 if (queue_index < priv->num_tx_rings_p_up) 139 cpumask_set_cpu(cpumask_local_spread(queue_index, 140 priv->mdev->dev->numa_node), 141 &ring->sp_affinity_mask); 142 143 *pring = ring; 144 return 0; 145 146 err_reserve: 147 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 148 err_hwq_res: 149 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 150 err_bounce: 151 kfree(ring->bounce_buf); 152 ring->bounce_buf = NULL; 153 err_info: 154 kvfree(ring->tx_info); 155 ring->tx_info = NULL; 156 err_ring: 157 kfree(ring); 158 *pring = NULL; 159 return err; 160 } 161 162 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 163 struct mlx4_en_tx_ring **pring) 164 { 165 struct mlx4_en_dev *mdev = priv->mdev; 166 struct mlx4_en_tx_ring *ring = *pring; 167 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 168 169 if (ring->bf_alloced) 170 mlx4_bf_free(mdev->dev, &ring->bf); 171 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 172 mlx4_qp_free(mdev->dev, &ring->sp_qp); 173 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 174 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 175 kfree(ring->bounce_buf); 176 ring->bounce_buf = NULL; 177 kvfree(ring->tx_info); 178 ring->tx_info = NULL; 179 kfree(ring); 180 *pring = NULL; 181 } 182 183 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 184 struct mlx4_en_tx_ring *ring, 185 int cq, int user_prio) 186 { 187 struct mlx4_en_dev *mdev = priv->mdev; 188 int err; 189 190 ring->sp_cqn = cq; 191 ring->prod = 0; 192 ring->cons = 0xffffffff; 193 ring->last_nr_txbb = 1; 194 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 195 memset(ring->buf, 0, ring->buf_size); 196 ring->free_tx_desc = mlx4_en_free_tx_desc; 197 198 ring->sp_qp_state = MLX4_QP_STATE_RST; 199 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 200 ring->mr_key = cpu_to_be32(mdev->mr.key); 201 202 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 203 ring->sp_cqn, user_prio, &ring->sp_context); 204 if (ring->bf_alloced) 205 ring->sp_context.usr_page = 206 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 207 ring->bf.uar->index)); 208 209 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 210 &ring->sp_qp, &ring->sp_qp_state); 211 if (!cpumask_empty(&ring->sp_affinity_mask)) 212 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 213 ring->queue_index); 214 215 return err; 216 } 217 218 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 219 struct mlx4_en_tx_ring *ring) 220 { 221 struct mlx4_en_dev *mdev = priv->mdev; 222 223 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 224 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 225 } 226 227 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 228 { 229 return ring->prod - ring->cons > ring->full_size; 230 } 231 232 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 233 struct mlx4_en_tx_ring *ring, int index, 234 u8 owner) 235 { 236 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 237 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 238 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 239 void *end = ring->buf + ring->buf_size; 240 __be32 *ptr = (__be32 *)tx_desc; 241 int i; 242 243 /* Optimize the common case when there are no wraparounds */ 244 if (likely((void *)tx_desc + 245 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 246 /* Stamp the freed descriptor */ 247 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 248 i += STAMP_STRIDE) { 249 *ptr = stamp; 250 ptr += STAMP_DWORDS; 251 } 252 } else { 253 /* Stamp the freed descriptor */ 254 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 255 i += STAMP_STRIDE) { 256 *ptr = stamp; 257 ptr += STAMP_DWORDS; 258 if ((void *)ptr >= end) { 259 ptr = ring->buf; 260 stamp ^= cpu_to_be32(0x80000000); 261 } 262 } 263 } 264 } 265 266 267 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 268 struct mlx4_en_tx_ring *ring, 269 int index, u64 timestamp, 270 int napi_mode) 271 { 272 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 273 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 274 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 275 void *end = ring->buf + ring->buf_size; 276 struct sk_buff *skb = tx_info->skb; 277 int nr_maps = tx_info->nr_maps; 278 int i; 279 280 /* We do not touch skb here, so prefetch skb->users location 281 * to speedup consume_skb() 282 */ 283 prefetchw(&skb->users); 284 285 if (unlikely(timestamp)) { 286 struct skb_shared_hwtstamps hwts; 287 288 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 289 skb_tstamp_tx(skb, &hwts); 290 } 291 292 if (!tx_info->inl) { 293 if (tx_info->linear) 294 dma_unmap_single(priv->ddev, 295 tx_info->map0_dma, 296 tx_info->map0_byte_count, 297 PCI_DMA_TODEVICE); 298 else 299 dma_unmap_page(priv->ddev, 300 tx_info->map0_dma, 301 tx_info->map0_byte_count, 302 PCI_DMA_TODEVICE); 303 /* Optimize the common case when there are no wraparounds */ 304 if (likely((void *)tx_desc + 305 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 306 for (i = 1; i < nr_maps; i++) { 307 data++; 308 dma_unmap_page(priv->ddev, 309 (dma_addr_t)be64_to_cpu(data->addr), 310 be32_to_cpu(data->byte_count), 311 PCI_DMA_TODEVICE); 312 } 313 } else { 314 if ((void *)data >= end) 315 data = ring->buf + ((void *)data - end); 316 317 for (i = 1; i < nr_maps; i++) { 318 data++; 319 /* Check for wraparound before unmapping */ 320 if ((void *) data >= end) 321 data = ring->buf; 322 dma_unmap_page(priv->ddev, 323 (dma_addr_t)be64_to_cpu(data->addr), 324 be32_to_cpu(data->byte_count), 325 PCI_DMA_TODEVICE); 326 } 327 } 328 } 329 napi_consume_skb(skb, napi_mode); 330 331 return tx_info->nr_txbb; 332 } 333 334 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 335 struct mlx4_en_tx_ring *ring, 336 int index, u64 timestamp, 337 int napi_mode) 338 { 339 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 340 struct mlx4_en_rx_alloc frame = { 341 .page = tx_info->page, 342 .dma = tx_info->map0_dma, 343 }; 344 345 if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 346 dma_unmap_page(priv->ddev, tx_info->map0_dma, 347 PAGE_SIZE, priv->dma_dir); 348 put_page(tx_info->page); 349 } 350 351 return tx_info->nr_txbb; 352 } 353 354 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 355 { 356 struct mlx4_en_priv *priv = netdev_priv(dev); 357 int cnt = 0; 358 359 /* Skip last polled descriptor */ 360 ring->cons += ring->last_nr_txbb; 361 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 362 ring->cons, ring->prod); 363 364 if ((u32) (ring->prod - ring->cons) > ring->size) { 365 if (netif_msg_tx_err(priv)) 366 en_warn(priv, "Tx consumer passed producer!\n"); 367 return 0; 368 } 369 370 while (ring->cons != ring->prod) { 371 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 372 ring->cons & ring->size_mask, 373 0, 0 /* Non-NAPI caller */); 374 ring->cons += ring->last_nr_txbb; 375 cnt++; 376 } 377 378 if (ring->tx_queue) 379 netdev_tx_reset_queue(ring->tx_queue); 380 381 if (cnt) 382 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 383 384 return cnt; 385 } 386 387 bool mlx4_en_process_tx_cq(struct net_device *dev, 388 struct mlx4_en_cq *cq, int napi_budget) 389 { 390 struct mlx4_en_priv *priv = netdev_priv(dev); 391 struct mlx4_cq *mcq = &cq->mcq; 392 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 393 struct mlx4_cqe *cqe; 394 u16 index, ring_index, stamp_index; 395 u32 txbbs_skipped = 0; 396 u32 txbbs_stamp = 0; 397 u32 cons_index = mcq->cons_index; 398 int size = cq->size; 399 u32 size_mask = ring->size_mask; 400 struct mlx4_cqe *buf = cq->buf; 401 u32 packets = 0; 402 u32 bytes = 0; 403 int factor = priv->cqe_factor; 404 int done = 0; 405 int budget = priv->tx_work_limit; 406 u32 last_nr_txbb; 407 u32 ring_cons; 408 409 if (unlikely(!priv->port_up)) 410 return true; 411 412 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 413 414 index = cons_index & size_mask; 415 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 416 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 417 ring_cons = ACCESS_ONCE(ring->cons); 418 ring_index = ring_cons & size_mask; 419 stamp_index = ring_index; 420 421 /* Process all completed CQEs */ 422 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 423 cons_index & size) && (done < budget)) { 424 u16 new_index; 425 426 /* 427 * make sure we read the CQE after we read the 428 * ownership bit 429 */ 430 dma_rmb(); 431 432 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 433 MLX4_CQE_OPCODE_ERROR)) { 434 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 435 436 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 437 cqe_err->vendor_err_syndrome, 438 cqe_err->syndrome); 439 } 440 441 /* Skip over last polled CQE */ 442 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 443 444 do { 445 u64 timestamp = 0; 446 447 txbbs_skipped += last_nr_txbb; 448 ring_index = (ring_index + last_nr_txbb) & size_mask; 449 450 if (unlikely(ring->tx_info[ring_index].ts_requested)) 451 timestamp = mlx4_en_get_cqe_ts(cqe); 452 453 /* free next descriptor */ 454 last_nr_txbb = ring->free_tx_desc( 455 priv, ring, ring_index, 456 timestamp, napi_budget); 457 458 mlx4_en_stamp_wqe(priv, ring, stamp_index, 459 !!((ring_cons + txbbs_stamp) & 460 ring->size)); 461 stamp_index = ring_index; 462 txbbs_stamp = txbbs_skipped; 463 packets++; 464 bytes += ring->tx_info[ring_index].nr_bytes; 465 } while ((++done < budget) && (ring_index != new_index)); 466 467 ++cons_index; 468 index = cons_index & size_mask; 469 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 470 } 471 472 /* 473 * To prevent CQ overflow we first update CQ consumer and only then 474 * the ring consumer. 475 */ 476 mcq->cons_index = cons_index; 477 mlx4_cq_set_ci(mcq); 478 wmb(); 479 480 /* we want to dirty this cache line once */ 481 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 482 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 483 484 if (cq->type == TX_XDP) 485 return done < budget; 486 487 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 488 489 /* Wakeup Tx queue if this stopped, and ring is not full. 490 */ 491 if (netif_tx_queue_stopped(ring->tx_queue) && 492 !mlx4_en_is_tx_ring_full(ring)) { 493 netif_tx_wake_queue(ring->tx_queue); 494 ring->wake_queue++; 495 } 496 497 return done < budget; 498 } 499 500 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 501 { 502 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 503 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 504 505 if (likely(priv->port_up)) 506 napi_schedule_irqoff(&cq->napi); 507 else 508 mlx4_en_arm_cq(priv, cq); 509 } 510 511 /* TX CQ polling - called by NAPI */ 512 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 513 { 514 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 515 struct net_device *dev = cq->dev; 516 struct mlx4_en_priv *priv = netdev_priv(dev); 517 bool clean_complete; 518 519 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 520 if (!clean_complete) 521 return budget; 522 523 napi_complete(napi); 524 mlx4_en_arm_cq(priv, cq); 525 526 return 0; 527 } 528 529 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 530 struct mlx4_en_tx_ring *ring, 531 u32 index, 532 unsigned int desc_size) 533 { 534 u32 copy = (ring->size - index) << LOG_TXBB_SIZE; 535 int i; 536 537 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 538 if ((i & (TXBB_SIZE - 1)) == 0) 539 wmb(); 540 541 *((u32 *) (ring->buf + i)) = 542 *((u32 *) (ring->bounce_buf + copy + i)); 543 } 544 545 for (i = copy - 4; i >= 4 ; i -= 4) { 546 if ((i & (TXBB_SIZE - 1)) == 0) 547 wmb(); 548 549 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = 550 *((u32 *) (ring->bounce_buf + i)); 551 } 552 553 /* Return real descriptor location */ 554 return ring->buf + (index << LOG_TXBB_SIZE); 555 } 556 557 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 558 * 559 * It seems strange we do not simply use skb_copy_bits(). 560 * This would allow to inline all skbs iff skb->len <= inline_thold 561 * 562 * Note that caller already checked skb was not a gso packet 563 */ 564 static bool is_inline(int inline_thold, const struct sk_buff *skb, 565 const struct skb_shared_info *shinfo, 566 void **pfrag) 567 { 568 void *ptr; 569 570 if (skb->len > inline_thold || !inline_thold) 571 return false; 572 573 if (shinfo->nr_frags == 1) { 574 ptr = skb_frag_address_safe(&shinfo->frags[0]); 575 if (unlikely(!ptr)) 576 return false; 577 *pfrag = ptr; 578 return true; 579 } 580 if (shinfo->nr_frags) 581 return false; 582 return true; 583 } 584 585 static int inline_size(const struct sk_buff *skb) 586 { 587 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 588 <= MLX4_INLINE_ALIGN) 589 return ALIGN(skb->len + CTRL_SIZE + 590 sizeof(struct mlx4_wqe_inline_seg), 16); 591 else 592 return ALIGN(skb->len + CTRL_SIZE + 2 * 593 sizeof(struct mlx4_wqe_inline_seg), 16); 594 } 595 596 static int get_real_size(const struct sk_buff *skb, 597 const struct skb_shared_info *shinfo, 598 struct net_device *dev, 599 int *lso_header_size, 600 bool *inline_ok, 601 void **pfrag) 602 { 603 struct mlx4_en_priv *priv = netdev_priv(dev); 604 int real_size; 605 606 if (shinfo->gso_size) { 607 *inline_ok = false; 608 if (skb->encapsulation) 609 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 610 else 611 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 612 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 613 ALIGN(*lso_header_size + 4, DS_SIZE); 614 if (unlikely(*lso_header_size != skb_headlen(skb))) { 615 /* We add a segment for the skb linear buffer only if 616 * it contains data */ 617 if (*lso_header_size < skb_headlen(skb)) 618 real_size += DS_SIZE; 619 else { 620 if (netif_msg_tx_err(priv)) 621 en_warn(priv, "Non-linear headers\n"); 622 return 0; 623 } 624 } 625 } else { 626 *lso_header_size = 0; 627 *inline_ok = is_inline(priv->prof->inline_thold, skb, 628 shinfo, pfrag); 629 630 if (*inline_ok) 631 real_size = inline_size(skb); 632 else 633 real_size = CTRL_SIZE + 634 (shinfo->nr_frags + 1) * DS_SIZE; 635 } 636 637 return real_size; 638 } 639 640 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 641 const struct sk_buff *skb, 642 const struct skb_shared_info *shinfo, 643 void *fragptr) 644 { 645 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 646 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 647 unsigned int hlen = skb_headlen(skb); 648 649 if (skb->len <= spc) { 650 if (likely(skb->len >= MIN_PKT_LEN)) { 651 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 652 } else { 653 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 654 memset(((void *)(inl + 1)) + skb->len, 0, 655 MIN_PKT_LEN - skb->len); 656 } 657 skb_copy_from_linear_data(skb, inl + 1, hlen); 658 if (shinfo->nr_frags) 659 memcpy(((void *)(inl + 1)) + hlen, fragptr, 660 skb_frag_size(&shinfo->frags[0])); 661 662 } else { 663 inl->byte_count = cpu_to_be32(1 << 31 | spc); 664 if (hlen <= spc) { 665 skb_copy_from_linear_data(skb, inl + 1, hlen); 666 if (hlen < spc) { 667 memcpy(((void *)(inl + 1)) + hlen, 668 fragptr, spc - hlen); 669 fragptr += spc - hlen; 670 } 671 inl = (void *) (inl + 1) + spc; 672 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 673 } else { 674 skb_copy_from_linear_data(skb, inl + 1, spc); 675 inl = (void *) (inl + 1) + spc; 676 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 677 hlen - spc); 678 if (shinfo->nr_frags) 679 memcpy(((void *)(inl + 1)) + hlen - spc, 680 fragptr, 681 skb_frag_size(&shinfo->frags[0])); 682 } 683 684 dma_wmb(); 685 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 686 } 687 } 688 689 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 690 void *accel_priv, select_queue_fallback_t fallback) 691 { 692 struct mlx4_en_priv *priv = netdev_priv(dev); 693 u16 rings_p_up = priv->num_tx_rings_p_up; 694 695 if (netdev_get_num_tc(dev)) 696 return skb_tx_hash(dev, skb); 697 698 return fallback(dev, skb) % rings_p_up; 699 } 700 701 static void mlx4_bf_copy(void __iomem *dst, const void *src, 702 unsigned int bytecnt) 703 { 704 __iowrite64_copy(dst, src, bytecnt / 8); 705 } 706 707 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 708 { 709 wmb(); 710 /* Since there is no iowrite*_native() that writes the 711 * value as is, without byteswapping - using the one 712 * the doesn't do byteswapping in the relevant arch 713 * endianness. 714 */ 715 #if defined(__LITTLE_ENDIAN) 716 iowrite32( 717 #else 718 iowrite32be( 719 #endif 720 ring->doorbell_qpn, 721 ring->bf.uar->map + MLX4_SEND_DOORBELL); 722 } 723 724 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 725 struct mlx4_en_tx_desc *tx_desc, 726 union mlx4_wqe_qpn_vlan qpn_vlan, 727 int desc_size, int bf_index, 728 __be32 op_own, bool bf_ok, 729 bool send_doorbell) 730 { 731 tx_desc->ctrl.qpn_vlan = qpn_vlan; 732 733 if (bf_ok) { 734 op_own |= htonl((bf_index & 0xffff) << 8); 735 /* Ensure new descriptor hits memory 736 * before setting ownership of this descriptor to HW 737 */ 738 dma_wmb(); 739 tx_desc->ctrl.owner_opcode = op_own; 740 741 wmb(); 742 743 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 744 desc_size); 745 746 wmb(); 747 748 ring->bf.offset ^= ring->bf.buf_size; 749 } else { 750 /* Ensure new descriptor hits memory 751 * before setting ownership of this descriptor to HW 752 */ 753 dma_wmb(); 754 tx_desc->ctrl.owner_opcode = op_own; 755 if (send_doorbell) 756 mlx4_en_xmit_doorbell(ring); 757 else 758 ring->xmit_more++; 759 } 760 } 761 762 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, 763 struct skb_shared_info *shinfo, 764 struct mlx4_wqe_data_seg *data, 765 struct sk_buff *skb, 766 int lso_header_size, 767 __be32 mr_key, 768 struct mlx4_en_tx_info *tx_info) 769 { 770 struct device *ddev = priv->ddev; 771 dma_addr_t dma = 0; 772 u32 byte_count = 0; 773 int i_frag; 774 775 /* Map fragments if any */ 776 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 777 const struct skb_frag_struct *frag; 778 779 frag = &shinfo->frags[i_frag]; 780 byte_count = skb_frag_size(frag); 781 dma = skb_frag_dma_map(ddev, frag, 782 0, byte_count, 783 DMA_TO_DEVICE); 784 if (dma_mapping_error(ddev, dma)) 785 goto tx_drop_unmap; 786 787 data->addr = cpu_to_be64(dma); 788 data->lkey = mr_key; 789 dma_wmb(); 790 data->byte_count = cpu_to_be32(byte_count); 791 --data; 792 } 793 794 /* Map linear part if needed */ 795 if (tx_info->linear) { 796 byte_count = skb_headlen(skb) - lso_header_size; 797 798 dma = dma_map_single(ddev, skb->data + 799 lso_header_size, byte_count, 800 PCI_DMA_TODEVICE); 801 if (dma_mapping_error(ddev, dma)) 802 goto tx_drop_unmap; 803 804 data->addr = cpu_to_be64(dma); 805 data->lkey = mr_key; 806 dma_wmb(); 807 data->byte_count = cpu_to_be32(byte_count); 808 } 809 /* tx completion can avoid cache line miss for common cases */ 810 tx_info->map0_dma = dma; 811 tx_info->map0_byte_count = byte_count; 812 813 return true; 814 815 tx_drop_unmap: 816 en_err(priv, "DMA mapping error\n"); 817 818 while (++i_frag < shinfo->nr_frags) { 819 ++data; 820 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), 821 be32_to_cpu(data->byte_count), 822 PCI_DMA_TODEVICE); 823 } 824 825 return false; 826 } 827 828 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 829 { 830 struct skb_shared_info *shinfo = skb_shinfo(skb); 831 struct mlx4_en_priv *priv = netdev_priv(dev); 832 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 833 struct mlx4_en_tx_ring *ring; 834 struct mlx4_en_tx_desc *tx_desc; 835 struct mlx4_wqe_data_seg *data; 836 struct mlx4_en_tx_info *tx_info; 837 int tx_ind; 838 int nr_txbb; 839 int desc_size; 840 int real_size; 841 u32 index, bf_index; 842 __be32 op_own; 843 int lso_header_size; 844 void *fragptr = NULL; 845 bool bounce = false; 846 bool send_doorbell; 847 bool stop_queue; 848 bool inline_ok; 849 u8 data_offset; 850 u32 ring_cons; 851 bool bf_ok; 852 853 tx_ind = skb_get_queue_mapping(skb); 854 ring = priv->tx_ring[TX][tx_ind]; 855 856 if (unlikely(!priv->port_up)) 857 goto tx_drop; 858 859 /* fetch ring->cons far ahead before needing it to avoid stall */ 860 ring_cons = ACCESS_ONCE(ring->cons); 861 862 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 863 &inline_ok, &fragptr); 864 if (unlikely(!real_size)) 865 goto tx_drop_count; 866 867 /* Align descriptor to TXBB size */ 868 desc_size = ALIGN(real_size, TXBB_SIZE); 869 nr_txbb = desc_size >> LOG_TXBB_SIZE; 870 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 871 if (netif_msg_tx_err(priv)) 872 en_warn(priv, "Oversized header or SG list\n"); 873 goto tx_drop_count; 874 } 875 876 bf_ok = ring->bf_enabled; 877 if (skb_vlan_tag_present(skb)) { 878 u16 vlan_proto; 879 880 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 881 vlan_proto = be16_to_cpu(skb->vlan_proto); 882 if (vlan_proto == ETH_P_8021AD) 883 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 884 else if (vlan_proto == ETH_P_8021Q) 885 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 886 else 887 qpn_vlan.ins_vlan = 0; 888 bf_ok = false; 889 } 890 891 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 892 893 /* Track current inflight packets for performance analysis */ 894 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 895 (u32)(ring->prod - ring_cons - 1)); 896 897 /* Packet is good - grab an index and transmit it */ 898 index = ring->prod & ring->size_mask; 899 bf_index = ring->prod; 900 901 /* See if we have enough space for whole descriptor TXBB for setting 902 * SW ownership on next descriptor; if not, use a bounce buffer. */ 903 if (likely(index + nr_txbb <= ring->size)) 904 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 905 else { 906 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 907 bounce = true; 908 bf_ok = false; 909 } 910 911 /* Save skb in tx_info ring */ 912 tx_info = &ring->tx_info[index]; 913 tx_info->skb = skb; 914 tx_info->nr_txbb = nr_txbb; 915 916 if (!lso_header_size) { 917 data = &tx_desc->data; 918 data_offset = offsetof(struct mlx4_en_tx_desc, data); 919 } else { 920 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE); 921 922 data = (void *)&tx_desc->lso + lso_align; 923 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; 924 } 925 926 /* valid only for none inline segments */ 927 tx_info->data_offset = data_offset; 928 929 tx_info->inl = inline_ok; 930 931 tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; 932 933 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 934 data += tx_info->nr_maps - 1; 935 936 if (!tx_info->inl) 937 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, 938 lso_header_size, ring->mr_key, 939 tx_info)) 940 goto tx_drop_count; 941 942 /* 943 * For timestamping add flag to skb_shinfo and 944 * set flag for further reference 945 */ 946 tx_info->ts_requested = 0; 947 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 948 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 949 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 950 tx_info->ts_requested = 1; 951 } 952 953 /* Prepare ctrl segement apart opcode+ownership, which depends on 954 * whether LSO is used */ 955 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 956 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 957 if (!skb->encapsulation) 958 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 959 MLX4_WQE_CTRL_TCP_UDP_CSUM); 960 else 961 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 962 ring->tx_csum++; 963 } 964 965 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 966 struct ethhdr *ethh; 967 968 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 969 * so that VFs and PF can communicate with each other 970 */ 971 ethh = (struct ethhdr *)skb->data; 972 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 973 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 974 } 975 976 /* Handle LSO (TSO) packets */ 977 if (lso_header_size) { 978 int i; 979 980 /* Mark opcode as LSO */ 981 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 982 ((ring->prod & ring->size) ? 983 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 984 985 /* Fill in the LSO prefix */ 986 tx_desc->lso.mss_hdr_size = cpu_to_be32( 987 shinfo->gso_size << 16 | lso_header_size); 988 989 /* Copy headers; 990 * note that we already verified that it is linear */ 991 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 992 993 ring->tso_packets++; 994 995 i = shinfo->gso_segs; 996 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 997 ring->packets += i; 998 } else { 999 /* Normal (Non LSO) packet */ 1000 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1001 ((ring->prod & ring->size) ? 1002 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1003 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 1004 ring->packets++; 1005 } 1006 ring->bytes += tx_info->nr_bytes; 1007 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 1008 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 1009 1010 if (tx_info->inl) 1011 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 1012 1013 if (skb->encapsulation) { 1014 union { 1015 struct iphdr *v4; 1016 struct ipv6hdr *v6; 1017 unsigned char *hdr; 1018 } ip; 1019 u8 proto; 1020 1021 ip.hdr = skb_inner_network_header(skb); 1022 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1023 ip.v6->nexthdr; 1024 1025 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1026 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1027 else 1028 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1029 } 1030 1031 ring->prod += nr_txbb; 1032 1033 /* If we used a bounce buffer then copy descriptor back into place */ 1034 if (unlikely(bounce)) 1035 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1036 1037 skb_tx_timestamp(skb); 1038 1039 /* Check available TXBBs And 2K spare for prefetch */ 1040 stop_queue = mlx4_en_is_tx_ring_full(ring); 1041 if (unlikely(stop_queue)) { 1042 netif_tx_stop_queue(ring->tx_queue); 1043 ring->queue_stopped++; 1044 } 1045 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 1046 1047 real_size = (real_size / 16) & 0x3f; 1048 1049 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1050 1051 if (bf_ok) 1052 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1053 else 1054 qpn_vlan.fence_size = real_size; 1055 1056 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1057 op_own, bf_ok, send_doorbell); 1058 1059 if (unlikely(stop_queue)) { 1060 /* If queue was emptied after the if (stop_queue) , and before 1061 * the netif_tx_stop_queue() - need to wake the queue, 1062 * or else it will remain stopped forever. 1063 * Need a memory barrier to make sure ring->cons was not 1064 * updated before queue was stopped. 1065 */ 1066 smp_rmb(); 1067 1068 ring_cons = ACCESS_ONCE(ring->cons); 1069 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1070 netif_tx_wake_queue(ring->tx_queue); 1071 ring->wake_queue++; 1072 } 1073 } 1074 return NETDEV_TX_OK; 1075 1076 tx_drop_count: 1077 ring->tx_dropped++; 1078 tx_drop: 1079 dev_kfree_skb_any(skb); 1080 return NETDEV_TX_OK; 1081 } 1082 1083 #define MLX4_EN_XDP_TX_NRTXBB 1 1084 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ 1085 / 16) & 0x3f) 1086 1087 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1088 struct mlx4_en_rx_alloc *frame, 1089 struct net_device *dev, unsigned int length, 1090 int tx_ind, bool *doorbell_pending) 1091 { 1092 struct mlx4_en_priv *priv = netdev_priv(dev); 1093 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 1094 struct mlx4_en_tx_desc *tx_desc; 1095 struct mlx4_en_tx_info *tx_info; 1096 struct mlx4_wqe_data_seg *data; 1097 struct mlx4_en_tx_ring *ring; 1098 dma_addr_t dma; 1099 __be32 op_own; 1100 int index; 1101 1102 if (unlikely(!priv->port_up)) 1103 goto tx_drop; 1104 1105 ring = priv->tx_ring[TX_XDP][tx_ind]; 1106 1107 if (unlikely(mlx4_en_is_tx_ring_full(ring))) 1108 goto tx_drop_count; 1109 1110 index = ring->prod & ring->size_mask; 1111 tx_info = &ring->tx_info[index]; 1112 1113 /* Track current inflight packets for performance analysis */ 1114 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1115 (u32)(ring->prod - READ_ONCE(ring->cons) - 1)); 1116 1117 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 1118 data = &tx_desc->data; 1119 1120 dma = frame->dma; 1121 1122 tx_info->page = frame->page; 1123 frame->page = NULL; 1124 tx_info->map0_dma = dma; 1125 tx_info->map0_byte_count = PAGE_SIZE; 1126 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; 1127 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1128 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); 1129 tx_info->ts_requested = 0; 1130 tx_info->nr_maps = 1; 1131 tx_info->linear = 1; 1132 tx_info->inl = 0; 1133 1134 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1135 length, PCI_DMA_TODEVICE); 1136 1137 data->addr = cpu_to_be64(dma + frame->page_offset); 1138 data->lkey = ring->mr_key; 1139 dma_wmb(); 1140 data->byte_count = cpu_to_be32(length); 1141 1142 /* tx completion can avoid cache line miss for common cases */ 1143 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1144 1145 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1146 ((ring->prod & ring->size) ? 1147 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1148 1149 rx_ring->xdp_tx++; 1150 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1151 1152 ring->prod += MLX4_EN_XDP_TX_NRTXBB; 1153 1154 qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; 1155 1156 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, 0, 1157 op_own, false, false); 1158 *doorbell_pending = true; 1159 1160 return NETDEV_TX_OK; 1161 1162 tx_drop_count: 1163 rx_ring->xdp_tx_full++; 1164 *doorbell_pending = true; 1165 tx_drop: 1166 return NETDEV_TX_BUSY; 1167 } 1168