1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 61 if (!ring) { 62 en_err(priv, "Failed allocating TX ring\n"); 63 return -ENOMEM; 64 } 65 } 66 67 ring->size = size; 68 ring->size_mask = size - 1; 69 ring->sp_stride = stride; 70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 71 72 tmp = size * sizeof(struct mlx4_en_tx_info); 73 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); 74 if (!ring->tx_info) { 75 ring->tx_info = vmalloc(tmp); 76 if (!ring->tx_info) { 77 err = -ENOMEM; 78 goto err_ring; 79 } 80 } 81 82 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 83 ring->tx_info, tmp); 84 85 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 86 if (!ring->bounce_buf) { 87 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 88 if (!ring->bounce_buf) { 89 err = -ENOMEM; 90 goto err_info; 91 } 92 } 93 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 94 95 /* Allocate HW buffers on provided NUMA node */ 96 set_dev_node(&mdev->dev->persist->pdev->dev, node); 97 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 99 if (err) { 100 en_err(priv, "Failed allocating hwq resources\n"); 101 goto err_bounce; 102 } 103 104 ring->buf = ring->sp_wqres.buf.direct.buf; 105 106 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 107 ring, ring->buf, ring->size, ring->buf_size, 108 (unsigned long long) ring->sp_wqres.buf.direct.map); 109 110 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 111 MLX4_RESERVE_ETH_BF_QP); 112 if (err) { 113 en_err(priv, "failed reserving qp for TX ring\n"); 114 goto err_hwq_res; 115 } 116 117 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp, GFP_KERNEL); 118 if (err) { 119 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 120 goto err_reserve; 121 } 122 ring->sp_qp.event = mlx4_en_sqp_event; 123 124 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 125 if (err) { 126 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 127 ring->bf.uar = &mdev->priv_uar; 128 ring->bf.uar->map = mdev->uar_map; 129 ring->bf_enabled = false; 130 ring->bf_alloced = false; 131 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 132 } else { 133 ring->bf_alloced = true; 134 ring->bf_enabled = !!(priv->pflags & 135 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 136 } 137 138 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 139 ring->queue_index = queue_index; 140 141 if (queue_index < priv->num_tx_rings_p_up) 142 cpumask_set_cpu(cpumask_local_spread(queue_index, 143 priv->mdev->dev->numa_node), 144 &ring->sp_affinity_mask); 145 146 *pring = ring; 147 return 0; 148 149 err_reserve: 150 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 151 err_hwq_res: 152 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 153 err_bounce: 154 kfree(ring->bounce_buf); 155 ring->bounce_buf = NULL; 156 err_info: 157 kvfree(ring->tx_info); 158 ring->tx_info = NULL; 159 err_ring: 160 kfree(ring); 161 *pring = NULL; 162 return err; 163 } 164 165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 166 struct mlx4_en_tx_ring **pring) 167 { 168 struct mlx4_en_dev *mdev = priv->mdev; 169 struct mlx4_en_tx_ring *ring = *pring; 170 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 171 172 if (ring->bf_alloced) 173 mlx4_bf_free(mdev->dev, &ring->bf); 174 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 175 mlx4_qp_free(mdev->dev, &ring->sp_qp); 176 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 177 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 178 kfree(ring->bounce_buf); 179 ring->bounce_buf = NULL; 180 kvfree(ring->tx_info); 181 ring->tx_info = NULL; 182 kfree(ring); 183 *pring = NULL; 184 } 185 186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 187 struct mlx4_en_tx_ring *ring, 188 int cq, int user_prio) 189 { 190 struct mlx4_en_dev *mdev = priv->mdev; 191 int err; 192 193 ring->sp_cqn = cq; 194 ring->prod = 0; 195 ring->cons = 0xffffffff; 196 ring->last_nr_txbb = 1; 197 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 198 memset(ring->buf, 0, ring->buf_size); 199 ring->free_tx_desc = mlx4_en_free_tx_desc; 200 201 ring->sp_qp_state = MLX4_QP_STATE_RST; 202 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 203 ring->mr_key = cpu_to_be32(mdev->mr.key); 204 205 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 206 ring->sp_cqn, user_prio, &ring->sp_context); 207 if (ring->bf_alloced) 208 ring->sp_context.usr_page = 209 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 210 ring->bf.uar->index)); 211 212 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 213 &ring->sp_qp, &ring->sp_qp_state); 214 if (!cpumask_empty(&ring->sp_affinity_mask)) 215 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 216 ring->queue_index); 217 218 return err; 219 } 220 221 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 222 struct mlx4_en_tx_ring *ring) 223 { 224 struct mlx4_en_dev *mdev = priv->mdev; 225 226 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 227 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 228 } 229 230 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 231 { 232 return ring->prod - ring->cons > ring->full_size; 233 } 234 235 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 236 struct mlx4_en_tx_ring *ring, int index, 237 u8 owner) 238 { 239 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 240 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 241 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 242 void *end = ring->buf + ring->buf_size; 243 __be32 *ptr = (__be32 *)tx_desc; 244 int i; 245 246 /* Optimize the common case when there are no wraparounds */ 247 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 248 /* Stamp the freed descriptor */ 249 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 250 i += STAMP_STRIDE) { 251 *ptr = stamp; 252 ptr += STAMP_DWORDS; 253 } 254 } else { 255 /* Stamp the freed descriptor */ 256 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 257 i += STAMP_STRIDE) { 258 *ptr = stamp; 259 ptr += STAMP_DWORDS; 260 if ((void *)ptr >= end) { 261 ptr = ring->buf; 262 stamp ^= cpu_to_be32(0x80000000); 263 } 264 } 265 } 266 } 267 268 269 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 270 struct mlx4_en_tx_ring *ring, 271 int index, u8 owner, u64 timestamp, 272 int napi_mode) 273 { 274 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 275 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 276 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 277 void *end = ring->buf + ring->buf_size; 278 struct sk_buff *skb = tx_info->skb; 279 int nr_maps = tx_info->nr_maps; 280 int i; 281 282 /* We do not touch skb here, so prefetch skb->users location 283 * to speedup consume_skb() 284 */ 285 prefetchw(&skb->users); 286 287 if (unlikely(timestamp)) { 288 struct skb_shared_hwtstamps hwts; 289 290 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 291 skb_tstamp_tx(skb, &hwts); 292 } 293 294 /* Optimize the common case when there are no wraparounds */ 295 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 296 if (!tx_info->inl) { 297 if (tx_info->linear) 298 dma_unmap_single(priv->ddev, 299 tx_info->map0_dma, 300 tx_info->map0_byte_count, 301 PCI_DMA_TODEVICE); 302 else 303 dma_unmap_page(priv->ddev, 304 tx_info->map0_dma, 305 tx_info->map0_byte_count, 306 PCI_DMA_TODEVICE); 307 for (i = 1; i < nr_maps; i++) { 308 data++; 309 dma_unmap_page(priv->ddev, 310 (dma_addr_t)be64_to_cpu(data->addr), 311 be32_to_cpu(data->byte_count), 312 PCI_DMA_TODEVICE); 313 } 314 } 315 } else { 316 if (!tx_info->inl) { 317 if ((void *) data >= end) { 318 data = ring->buf + ((void *)data - end); 319 } 320 321 if (tx_info->linear) 322 dma_unmap_single(priv->ddev, 323 tx_info->map0_dma, 324 tx_info->map0_byte_count, 325 PCI_DMA_TODEVICE); 326 else 327 dma_unmap_page(priv->ddev, 328 tx_info->map0_dma, 329 tx_info->map0_byte_count, 330 PCI_DMA_TODEVICE); 331 for (i = 1; i < nr_maps; i++) { 332 data++; 333 /* Check for wraparound before unmapping */ 334 if ((void *) data >= end) 335 data = ring->buf; 336 dma_unmap_page(priv->ddev, 337 (dma_addr_t)be64_to_cpu(data->addr), 338 be32_to_cpu(data->byte_count), 339 PCI_DMA_TODEVICE); 340 } 341 } 342 } 343 napi_consume_skb(skb, napi_mode); 344 345 return tx_info->nr_txbb; 346 } 347 348 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 349 struct mlx4_en_tx_ring *ring, 350 int index, u8 owner, u64 timestamp, 351 int napi_mode) 352 { 353 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 354 struct mlx4_en_rx_alloc frame = { 355 .page = tx_info->page, 356 .dma = tx_info->map0_dma, 357 }; 358 359 if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 360 dma_unmap_page(priv->ddev, tx_info->map0_dma, 361 PAGE_SIZE, priv->dma_dir); 362 put_page(tx_info->page); 363 } 364 365 return tx_info->nr_txbb; 366 } 367 368 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 369 { 370 struct mlx4_en_priv *priv = netdev_priv(dev); 371 int cnt = 0; 372 373 /* Skip last polled descriptor */ 374 ring->cons += ring->last_nr_txbb; 375 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 376 ring->cons, ring->prod); 377 378 if ((u32) (ring->prod - ring->cons) > ring->size) { 379 if (netif_msg_tx_err(priv)) 380 en_warn(priv, "Tx consumer passed producer!\n"); 381 return 0; 382 } 383 384 while (ring->cons != ring->prod) { 385 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 386 ring->cons & ring->size_mask, 387 !!(ring->cons & ring->size), 0, 388 0 /* Non-NAPI caller */); 389 ring->cons += ring->last_nr_txbb; 390 cnt++; 391 } 392 393 if (ring->tx_queue) 394 netdev_tx_reset_queue(ring->tx_queue); 395 396 if (cnt) 397 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 398 399 return cnt; 400 } 401 402 static bool mlx4_en_process_tx_cq(struct net_device *dev, 403 struct mlx4_en_cq *cq, int napi_budget) 404 { 405 struct mlx4_en_priv *priv = netdev_priv(dev); 406 struct mlx4_cq *mcq = &cq->mcq; 407 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 408 struct mlx4_cqe *cqe; 409 u16 index; 410 u16 new_index, ring_index, stamp_index; 411 u32 txbbs_skipped = 0; 412 u32 txbbs_stamp = 0; 413 u32 cons_index = mcq->cons_index; 414 int size = cq->size; 415 u32 size_mask = ring->size_mask; 416 struct mlx4_cqe *buf = cq->buf; 417 u32 packets = 0; 418 u32 bytes = 0; 419 int factor = priv->cqe_factor; 420 int done = 0; 421 int budget = priv->tx_work_limit; 422 u32 last_nr_txbb; 423 u32 ring_cons; 424 425 if (!priv->port_up) 426 return true; 427 428 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 429 430 index = cons_index & size_mask; 431 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 432 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 433 ring_cons = ACCESS_ONCE(ring->cons); 434 ring_index = ring_cons & size_mask; 435 stamp_index = ring_index; 436 437 /* Process all completed CQEs */ 438 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 439 cons_index & size) && (done < budget)) { 440 /* 441 * make sure we read the CQE after we read the 442 * ownership bit 443 */ 444 dma_rmb(); 445 446 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 447 MLX4_CQE_OPCODE_ERROR)) { 448 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 449 450 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 451 cqe_err->vendor_err_syndrome, 452 cqe_err->syndrome); 453 } 454 455 /* Skip over last polled CQE */ 456 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 457 458 do { 459 u64 timestamp = 0; 460 461 txbbs_skipped += last_nr_txbb; 462 ring_index = (ring_index + last_nr_txbb) & size_mask; 463 464 if (unlikely(ring->tx_info[ring_index].ts_requested)) 465 timestamp = mlx4_en_get_cqe_ts(cqe); 466 467 /* free next descriptor */ 468 last_nr_txbb = ring->free_tx_desc( 469 priv, ring, ring_index, 470 !!((ring_cons + txbbs_skipped) & 471 ring->size), timestamp, napi_budget); 472 473 mlx4_en_stamp_wqe(priv, ring, stamp_index, 474 !!((ring_cons + txbbs_stamp) & 475 ring->size)); 476 stamp_index = ring_index; 477 txbbs_stamp = txbbs_skipped; 478 packets++; 479 bytes += ring->tx_info[ring_index].nr_bytes; 480 } while ((++done < budget) && (ring_index != new_index)); 481 482 ++cons_index; 483 index = cons_index & size_mask; 484 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 485 } 486 487 488 /* 489 * To prevent CQ overflow we first update CQ consumer and only then 490 * the ring consumer. 491 */ 492 mcq->cons_index = cons_index; 493 mlx4_cq_set_ci(mcq); 494 wmb(); 495 496 /* we want to dirty this cache line once */ 497 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 498 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 499 500 if (ring->free_tx_desc == mlx4_en_recycle_tx_desc) 501 return done < budget; 502 503 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 504 505 /* Wakeup Tx queue if this stopped, and ring is not full. 506 */ 507 if (netif_tx_queue_stopped(ring->tx_queue) && 508 !mlx4_en_is_tx_ring_full(ring)) { 509 netif_tx_wake_queue(ring->tx_queue); 510 ring->wake_queue++; 511 } 512 return done < budget; 513 } 514 515 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 516 { 517 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 518 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 519 520 if (likely(priv->port_up)) 521 napi_schedule_irqoff(&cq->napi); 522 else 523 mlx4_en_arm_cq(priv, cq); 524 } 525 526 /* TX CQ polling - called by NAPI */ 527 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 528 { 529 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 530 struct net_device *dev = cq->dev; 531 struct mlx4_en_priv *priv = netdev_priv(dev); 532 int clean_complete; 533 534 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 535 if (!clean_complete) 536 return budget; 537 538 napi_complete(napi); 539 mlx4_en_arm_cq(priv, cq); 540 541 return 0; 542 } 543 544 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 545 struct mlx4_en_tx_ring *ring, 546 u32 index, 547 unsigned int desc_size) 548 { 549 u32 copy = (ring->size - index) * TXBB_SIZE; 550 int i; 551 552 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 553 if ((i & (TXBB_SIZE - 1)) == 0) 554 wmb(); 555 556 *((u32 *) (ring->buf + i)) = 557 *((u32 *) (ring->bounce_buf + copy + i)); 558 } 559 560 for (i = copy - 4; i >= 4 ; i -= 4) { 561 if ((i & (TXBB_SIZE - 1)) == 0) 562 wmb(); 563 564 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 565 *((u32 *) (ring->bounce_buf + i)); 566 } 567 568 /* Return real descriptor location */ 569 return ring->buf + index * TXBB_SIZE; 570 } 571 572 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 573 * 574 * It seems strange we do not simply use skb_copy_bits(). 575 * This would allow to inline all skbs iff skb->len <= inline_thold 576 * 577 * Note that caller already checked skb was not a gso packet 578 */ 579 static bool is_inline(int inline_thold, const struct sk_buff *skb, 580 const struct skb_shared_info *shinfo, 581 void **pfrag) 582 { 583 void *ptr; 584 585 if (skb->len > inline_thold || !inline_thold) 586 return false; 587 588 if (shinfo->nr_frags == 1) { 589 ptr = skb_frag_address_safe(&shinfo->frags[0]); 590 if (unlikely(!ptr)) 591 return false; 592 *pfrag = ptr; 593 return true; 594 } 595 if (shinfo->nr_frags) 596 return false; 597 return true; 598 } 599 600 static int inline_size(const struct sk_buff *skb) 601 { 602 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 603 <= MLX4_INLINE_ALIGN) 604 return ALIGN(skb->len + CTRL_SIZE + 605 sizeof(struct mlx4_wqe_inline_seg), 16); 606 else 607 return ALIGN(skb->len + CTRL_SIZE + 2 * 608 sizeof(struct mlx4_wqe_inline_seg), 16); 609 } 610 611 static int get_real_size(const struct sk_buff *skb, 612 const struct skb_shared_info *shinfo, 613 struct net_device *dev, 614 int *lso_header_size, 615 bool *inline_ok, 616 void **pfrag) 617 { 618 struct mlx4_en_priv *priv = netdev_priv(dev); 619 int real_size; 620 621 if (shinfo->gso_size) { 622 *inline_ok = false; 623 if (skb->encapsulation) 624 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 625 else 626 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 627 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 628 ALIGN(*lso_header_size + 4, DS_SIZE); 629 if (unlikely(*lso_header_size != skb_headlen(skb))) { 630 /* We add a segment for the skb linear buffer only if 631 * it contains data */ 632 if (*lso_header_size < skb_headlen(skb)) 633 real_size += DS_SIZE; 634 else { 635 if (netif_msg_tx_err(priv)) 636 en_warn(priv, "Non-linear headers\n"); 637 return 0; 638 } 639 } 640 } else { 641 *lso_header_size = 0; 642 *inline_ok = is_inline(priv->prof->inline_thold, skb, 643 shinfo, pfrag); 644 645 if (*inline_ok) 646 real_size = inline_size(skb); 647 else 648 real_size = CTRL_SIZE + 649 (shinfo->nr_frags + 1) * DS_SIZE; 650 } 651 652 return real_size; 653 } 654 655 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 656 const struct sk_buff *skb, 657 const struct skb_shared_info *shinfo, 658 void *fragptr) 659 { 660 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 661 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 662 unsigned int hlen = skb_headlen(skb); 663 664 if (skb->len <= spc) { 665 if (likely(skb->len >= MIN_PKT_LEN)) { 666 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 667 } else { 668 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 669 memset(((void *)(inl + 1)) + skb->len, 0, 670 MIN_PKT_LEN - skb->len); 671 } 672 skb_copy_from_linear_data(skb, inl + 1, hlen); 673 if (shinfo->nr_frags) 674 memcpy(((void *)(inl + 1)) + hlen, fragptr, 675 skb_frag_size(&shinfo->frags[0])); 676 677 } else { 678 inl->byte_count = cpu_to_be32(1 << 31 | spc); 679 if (hlen <= spc) { 680 skb_copy_from_linear_data(skb, inl + 1, hlen); 681 if (hlen < spc) { 682 memcpy(((void *)(inl + 1)) + hlen, 683 fragptr, spc - hlen); 684 fragptr += spc - hlen; 685 } 686 inl = (void *) (inl + 1) + spc; 687 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 688 } else { 689 skb_copy_from_linear_data(skb, inl + 1, spc); 690 inl = (void *) (inl + 1) + spc; 691 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 692 hlen - spc); 693 if (shinfo->nr_frags) 694 memcpy(((void *)(inl + 1)) + hlen - spc, 695 fragptr, 696 skb_frag_size(&shinfo->frags[0])); 697 } 698 699 dma_wmb(); 700 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 701 } 702 } 703 704 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 705 void *accel_priv, select_queue_fallback_t fallback) 706 { 707 struct mlx4_en_priv *priv = netdev_priv(dev); 708 u16 rings_p_up = priv->num_tx_rings_p_up; 709 u8 up = 0; 710 711 if (netdev_get_num_tc(dev)) 712 return skb_tx_hash(dev, skb); 713 714 if (skb_vlan_tag_present(skb)) 715 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; 716 717 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 718 } 719 720 static void mlx4_bf_copy(void __iomem *dst, const void *src, 721 unsigned int bytecnt) 722 { 723 __iowrite64_copy(dst, src, bytecnt / 8); 724 } 725 726 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 727 { 728 wmb(); 729 /* Since there is no iowrite*_native() that writes the 730 * value as is, without byteswapping - using the one 731 * the doesn't do byteswapping in the relevant arch 732 * endianness. 733 */ 734 #if defined(__LITTLE_ENDIAN) 735 iowrite32( 736 #else 737 iowrite32be( 738 #endif 739 ring->doorbell_qpn, 740 ring->bf.uar->map + MLX4_SEND_DOORBELL); 741 } 742 743 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 744 struct mlx4_en_tx_desc *tx_desc, 745 union mlx4_wqe_qpn_vlan qpn_vlan, 746 int desc_size, int bf_index, 747 __be32 op_own, bool bf_ok, 748 bool send_doorbell) 749 { 750 tx_desc->ctrl.qpn_vlan = qpn_vlan; 751 752 if (bf_ok) { 753 op_own |= htonl((bf_index & 0xffff) << 8); 754 /* Ensure new descriptor hits memory 755 * before setting ownership of this descriptor to HW 756 */ 757 dma_wmb(); 758 tx_desc->ctrl.owner_opcode = op_own; 759 760 wmb(); 761 762 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 763 desc_size); 764 765 wmb(); 766 767 ring->bf.offset ^= ring->bf.buf_size; 768 } else { 769 /* Ensure new descriptor hits memory 770 * before setting ownership of this descriptor to HW 771 */ 772 dma_wmb(); 773 tx_desc->ctrl.owner_opcode = op_own; 774 if (send_doorbell) 775 mlx4_en_xmit_doorbell(ring); 776 else 777 ring->xmit_more++; 778 } 779 } 780 781 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 782 { 783 struct skb_shared_info *shinfo = skb_shinfo(skb); 784 struct mlx4_en_priv *priv = netdev_priv(dev); 785 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 786 struct device *ddev = priv->ddev; 787 struct mlx4_en_tx_ring *ring; 788 struct mlx4_en_tx_desc *tx_desc; 789 struct mlx4_wqe_data_seg *data; 790 struct mlx4_en_tx_info *tx_info; 791 int tx_ind = 0; 792 int nr_txbb; 793 int desc_size; 794 int real_size; 795 u32 index, bf_index; 796 __be32 op_own; 797 u16 vlan_proto = 0; 798 int i_frag; 799 int lso_header_size; 800 void *fragptr = NULL; 801 bool bounce = false; 802 bool send_doorbell; 803 bool stop_queue; 804 bool inline_ok; 805 u32 ring_cons; 806 bool bf_ok; 807 808 tx_ind = skb_get_queue_mapping(skb); 809 ring = priv->tx_ring[TX][tx_ind]; 810 811 if (!priv->port_up) 812 goto tx_drop; 813 814 /* fetch ring->cons far ahead before needing it to avoid stall */ 815 ring_cons = ACCESS_ONCE(ring->cons); 816 817 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 818 &inline_ok, &fragptr); 819 if (unlikely(!real_size)) 820 goto tx_drop_count; 821 822 /* Align descriptor to TXBB size */ 823 desc_size = ALIGN(real_size, TXBB_SIZE); 824 nr_txbb = desc_size / TXBB_SIZE; 825 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 826 if (netif_msg_tx_err(priv)) 827 en_warn(priv, "Oversized header or SG list\n"); 828 goto tx_drop_count; 829 } 830 831 bf_ok = ring->bf_enabled; 832 if (skb_vlan_tag_present(skb)) { 833 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 834 vlan_proto = be16_to_cpu(skb->vlan_proto); 835 if (vlan_proto == ETH_P_8021AD) 836 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 837 else if (vlan_proto == ETH_P_8021Q) 838 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 839 else 840 qpn_vlan.ins_vlan = 0; 841 bf_ok = false; 842 } 843 844 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 845 846 /* Track current inflight packets for performance analysis */ 847 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 848 (u32)(ring->prod - ring_cons - 1)); 849 850 /* Packet is good - grab an index and transmit it */ 851 index = ring->prod & ring->size_mask; 852 bf_index = ring->prod; 853 854 /* See if we have enough space for whole descriptor TXBB for setting 855 * SW ownership on next descriptor; if not, use a bounce buffer. */ 856 if (likely(index + nr_txbb <= ring->size)) 857 tx_desc = ring->buf + index * TXBB_SIZE; 858 else { 859 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 860 bounce = true; 861 bf_ok = false; 862 } 863 864 /* Save skb in tx_info ring */ 865 tx_info = &ring->tx_info[index]; 866 tx_info->skb = skb; 867 tx_info->nr_txbb = nr_txbb; 868 869 data = &tx_desc->data; 870 if (lso_header_size) 871 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 872 DS_SIZE)); 873 874 /* valid only for none inline segments */ 875 tx_info->data_offset = (void *)data - (void *)tx_desc; 876 877 tx_info->inl = inline_ok; 878 879 tx_info->linear = (lso_header_size < skb_headlen(skb) && 880 !inline_ok) ? 1 : 0; 881 882 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 883 data += tx_info->nr_maps - 1; 884 885 if (!tx_info->inl) { 886 dma_addr_t dma = 0; 887 u32 byte_count = 0; 888 889 /* Map fragments if any */ 890 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 891 const struct skb_frag_struct *frag; 892 893 frag = &shinfo->frags[i_frag]; 894 byte_count = skb_frag_size(frag); 895 dma = skb_frag_dma_map(ddev, frag, 896 0, byte_count, 897 DMA_TO_DEVICE); 898 if (dma_mapping_error(ddev, dma)) 899 goto tx_drop_unmap; 900 901 data->addr = cpu_to_be64(dma); 902 data->lkey = ring->mr_key; 903 dma_wmb(); 904 data->byte_count = cpu_to_be32(byte_count); 905 --data; 906 } 907 908 /* Map linear part if needed */ 909 if (tx_info->linear) { 910 byte_count = skb_headlen(skb) - lso_header_size; 911 912 dma = dma_map_single(ddev, skb->data + 913 lso_header_size, byte_count, 914 PCI_DMA_TODEVICE); 915 if (dma_mapping_error(ddev, dma)) 916 goto tx_drop_unmap; 917 918 data->addr = cpu_to_be64(dma); 919 data->lkey = ring->mr_key; 920 dma_wmb(); 921 data->byte_count = cpu_to_be32(byte_count); 922 } 923 /* tx completion can avoid cache line miss for common cases */ 924 tx_info->map0_dma = dma; 925 tx_info->map0_byte_count = byte_count; 926 } 927 928 /* 929 * For timestamping add flag to skb_shinfo and 930 * set flag for further reference 931 */ 932 tx_info->ts_requested = 0; 933 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 934 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 935 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 936 tx_info->ts_requested = 1; 937 } 938 939 /* Prepare ctrl segement apart opcode+ownership, which depends on 940 * whether LSO is used */ 941 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 942 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 943 if (!skb->encapsulation) 944 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 945 MLX4_WQE_CTRL_TCP_UDP_CSUM); 946 else 947 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 948 ring->tx_csum++; 949 } 950 951 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 952 struct ethhdr *ethh; 953 954 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 955 * so that VFs and PF can communicate with each other 956 */ 957 ethh = (struct ethhdr *)skb->data; 958 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 959 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 960 } 961 962 /* Handle LSO (TSO) packets */ 963 if (lso_header_size) { 964 int i; 965 966 /* Mark opcode as LSO */ 967 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 968 ((ring->prod & ring->size) ? 969 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 970 971 /* Fill in the LSO prefix */ 972 tx_desc->lso.mss_hdr_size = cpu_to_be32( 973 shinfo->gso_size << 16 | lso_header_size); 974 975 /* Copy headers; 976 * note that we already verified that it is linear */ 977 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 978 979 ring->tso_packets++; 980 981 i = shinfo->gso_segs; 982 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 983 ring->packets += i; 984 } else { 985 /* Normal (Non LSO) packet */ 986 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 987 ((ring->prod & ring->size) ? 988 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 989 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 990 ring->packets++; 991 } 992 ring->bytes += tx_info->nr_bytes; 993 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 994 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 995 996 if (tx_info->inl) 997 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 998 999 if (skb->encapsulation) { 1000 union { 1001 struct iphdr *v4; 1002 struct ipv6hdr *v6; 1003 unsigned char *hdr; 1004 } ip; 1005 u8 proto; 1006 1007 ip.hdr = skb_inner_network_header(skb); 1008 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1009 ip.v6->nexthdr; 1010 1011 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1012 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1013 else 1014 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1015 } 1016 1017 ring->prod += nr_txbb; 1018 1019 /* If we used a bounce buffer then copy descriptor back into place */ 1020 if (unlikely(bounce)) 1021 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1022 1023 skb_tx_timestamp(skb); 1024 1025 /* Check available TXBBs And 2K spare for prefetch */ 1026 stop_queue = mlx4_en_is_tx_ring_full(ring); 1027 if (unlikely(stop_queue)) { 1028 netif_tx_stop_queue(ring->tx_queue); 1029 ring->queue_stopped++; 1030 } 1031 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 1032 1033 real_size = (real_size / 16) & 0x3f; 1034 1035 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1036 1037 if (bf_ok) 1038 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1039 else 1040 qpn_vlan.fence_size = real_size; 1041 1042 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1043 op_own, bf_ok, send_doorbell); 1044 1045 if (unlikely(stop_queue)) { 1046 /* If queue was emptied after the if (stop_queue) , and before 1047 * the netif_tx_stop_queue() - need to wake the queue, 1048 * or else it will remain stopped forever. 1049 * Need a memory barrier to make sure ring->cons was not 1050 * updated before queue was stopped. 1051 */ 1052 smp_rmb(); 1053 1054 ring_cons = ACCESS_ONCE(ring->cons); 1055 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1056 netif_tx_wake_queue(ring->tx_queue); 1057 ring->wake_queue++; 1058 } 1059 } 1060 return NETDEV_TX_OK; 1061 1062 tx_drop_unmap: 1063 en_err(priv, "DMA mapping error\n"); 1064 1065 while (++i_frag < shinfo->nr_frags) { 1066 ++data; 1067 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 1068 be32_to_cpu(data->byte_count), 1069 PCI_DMA_TODEVICE); 1070 } 1071 1072 tx_drop_count: 1073 ring->tx_dropped++; 1074 tx_drop: 1075 dev_kfree_skb_any(skb); 1076 return NETDEV_TX_OK; 1077 } 1078 1079 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1080 struct mlx4_en_rx_alloc *frame, 1081 struct net_device *dev, unsigned int length, 1082 int tx_ind, int *doorbell_pending) 1083 { 1084 struct mlx4_en_priv *priv = netdev_priv(dev); 1085 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 1086 struct mlx4_en_tx_ring *ring; 1087 struct mlx4_en_tx_desc *tx_desc; 1088 struct mlx4_wqe_data_seg *data; 1089 struct mlx4_en_tx_info *tx_info; 1090 int index, bf_index; 1091 bool send_doorbell; 1092 int nr_txbb = 1; 1093 bool stop_queue; 1094 dma_addr_t dma; 1095 int real_size; 1096 __be32 op_own; 1097 u32 ring_cons; 1098 bool bf_ok; 1099 1100 BUILD_BUG_ON_MSG(ALIGN(CTRL_SIZE + DS_SIZE, TXBB_SIZE) != TXBB_SIZE, 1101 "mlx4_en_xmit_frame requires minimum size tx desc"); 1102 1103 ring = priv->tx_ring[TX_XDP][tx_ind]; 1104 1105 if (!priv->port_up) 1106 goto tx_drop; 1107 1108 if (mlx4_en_is_tx_ring_full(ring)) 1109 goto tx_drop_count; 1110 1111 /* fetch ring->cons far ahead before needing it to avoid stall */ 1112 ring_cons = READ_ONCE(ring->cons); 1113 1114 index = ring->prod & ring->size_mask; 1115 tx_info = &ring->tx_info[index]; 1116 1117 bf_ok = ring->bf_enabled; 1118 1119 /* Track current inflight packets for performance analysis */ 1120 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1121 (u32)(ring->prod - ring_cons - 1)); 1122 1123 bf_index = ring->prod; 1124 tx_desc = ring->buf + index * TXBB_SIZE; 1125 data = &tx_desc->data; 1126 1127 dma = frame->dma; 1128 1129 tx_info->page = frame->page; 1130 frame->page = NULL; 1131 tx_info->map0_dma = dma; 1132 tx_info->map0_byte_count = PAGE_SIZE; 1133 tx_info->nr_txbb = nr_txbb; 1134 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1135 tx_info->data_offset = (void *)data - (void *)tx_desc; 1136 tx_info->ts_requested = 0; 1137 tx_info->nr_maps = 1; 1138 tx_info->linear = 1; 1139 tx_info->inl = 0; 1140 1141 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1142 length, PCI_DMA_TODEVICE); 1143 1144 data->addr = cpu_to_be64(dma + frame->page_offset); 1145 data->lkey = ring->mr_key; 1146 dma_wmb(); 1147 data->byte_count = cpu_to_be32(length); 1148 1149 /* tx completion can avoid cache line miss for common cases */ 1150 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1151 1152 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1153 ((ring->prod & ring->size) ? 1154 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1155 1156 rx_ring->xdp_tx++; 1157 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1158 1159 ring->prod += nr_txbb; 1160 1161 stop_queue = mlx4_en_is_tx_ring_full(ring); 1162 send_doorbell = stop_queue || 1163 *doorbell_pending > MLX4_EN_DOORBELL_BUDGET; 1164 bf_ok &= send_doorbell; 1165 1166 real_size = ((CTRL_SIZE + nr_txbb * DS_SIZE) / 16) & 0x3f; 1167 1168 if (bf_ok) 1169 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1170 else 1171 qpn_vlan.fence_size = real_size; 1172 1173 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, bf_index, 1174 op_own, bf_ok, send_doorbell); 1175 *doorbell_pending = send_doorbell ? 0 : *doorbell_pending + 1; 1176 1177 return NETDEV_TX_OK; 1178 1179 tx_drop_count: 1180 rx_ring->xdp_tx_full++; 1181 tx_drop: 1182 return NETDEV_TX_BUSY; 1183 } 1184