1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/bpf.h> 36 #include <linux/bpf_trace.h> 37 #include <linux/mlx4/cq.h> 38 #include <linux/slab.h> 39 #include <linux/mlx4/qp.h> 40 #include <linux/skbuff.h> 41 #include <linux/rculist.h> 42 #include <linux/if_ether.h> 43 #include <linux/if_vlan.h> 44 #include <linux/vmalloc.h> 45 #include <linux/irq.h> 46 47 #if IS_ENABLED(CONFIG_IPV6) 48 #include <net/ip6_checksum.h> 49 #endif 50 51 #include "mlx4_en.h" 52 53 static int mlx4_alloc_page(struct mlx4_en_priv *priv, 54 struct mlx4_en_rx_alloc *frag, 55 gfp_t gfp) 56 { 57 struct page *page; 58 dma_addr_t dma; 59 60 page = alloc_page(gfp); 61 if (unlikely(!page)) 62 return -ENOMEM; 63 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir); 64 if (unlikely(dma_mapping_error(priv->ddev, dma))) { 65 __free_page(page); 66 return -ENOMEM; 67 } 68 frag->page = page; 69 frag->dma = dma; 70 frag->page_offset = priv->rx_headroom; 71 return 0; 72 } 73 74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 75 struct mlx4_en_rx_ring *ring, 76 struct mlx4_en_rx_desc *rx_desc, 77 struct mlx4_en_rx_alloc *frags, 78 gfp_t gfp) 79 { 80 int i; 81 82 for (i = 0; i < priv->num_frags; i++, frags++) { 83 if (!frags->page) { 84 if (mlx4_alloc_page(priv, frags, gfp)) 85 return -ENOMEM; 86 ring->rx_alloc_pages++; 87 } 88 rx_desc->data[i].addr = cpu_to_be64(frags->dma + 89 frags->page_offset); 90 } 91 return 0; 92 } 93 94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv, 95 struct mlx4_en_rx_alloc *frag) 96 { 97 if (frag->page) { 98 dma_unmap_page(priv->ddev, frag->dma, 99 PAGE_SIZE, priv->dma_dir); 100 __free_page(frag->page); 101 } 102 /* We need to clear all fields, otherwise a change of priv->log_rx_info 103 * could lead to see garbage later in frag->page. 104 */ 105 memset(frag, 0, sizeof(*frag)); 106 } 107 108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv, 109 struct mlx4_en_rx_ring *ring, int index) 110 { 111 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 112 int possible_frags; 113 int i; 114 115 /* Set size and memtype fields */ 116 for (i = 0; i < priv->num_frags; i++) { 117 rx_desc->data[i].byte_count = 118 cpu_to_be32(priv->frag_info[i].frag_size); 119 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 120 } 121 122 /* If the number of used fragments does not fill up the ring stride, 123 * remaining (unused) fragments must be padded with null address/size 124 * and a special memory key */ 125 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 126 for (i = priv->num_frags; i < possible_frags; i++) { 127 rx_desc->data[i].byte_count = 0; 128 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 129 rx_desc->data[i].addr = 0; 130 } 131 } 132 133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 134 struct mlx4_en_rx_ring *ring, int index, 135 gfp_t gfp) 136 { 137 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 138 struct mlx4_en_rx_alloc *frags = ring->rx_info + 139 (index << priv->log_rx_info); 140 if (ring->page_cache.index > 0) { 141 /* XDP uses a single page per frame */ 142 if (!frags->page) { 143 ring->page_cache.index--; 144 frags->page = ring->page_cache.buf[ring->page_cache.index].page; 145 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma; 146 } 147 frags->page_offset = XDP_PACKET_HEADROOM; 148 rx_desc->data[0].addr = cpu_to_be64(frags->dma + 149 XDP_PACKET_HEADROOM); 150 return 0; 151 } 152 153 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp); 154 } 155 156 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring) 157 { 158 return ring->prod == ring->cons; 159 } 160 161 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 162 { 163 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 164 } 165 166 /* slow path */ 167 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv, 168 struct mlx4_en_rx_ring *ring, 169 int index) 170 { 171 struct mlx4_en_rx_alloc *frags; 172 int nr; 173 174 frags = ring->rx_info + (index << priv->log_rx_info); 175 for (nr = 0; nr < priv->num_frags; nr++) { 176 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 177 mlx4_en_free_frag(priv, frags + nr); 178 } 179 } 180 181 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 182 { 183 struct mlx4_en_rx_ring *ring; 184 int ring_ind; 185 int buf_ind; 186 int new_size; 187 188 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 189 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 190 ring = priv->rx_ring[ring_ind]; 191 192 if (mlx4_en_prepare_rx_desc(priv, ring, 193 ring->actual_size, 194 GFP_KERNEL | __GFP_COLD)) { 195 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 196 en_err(priv, "Failed to allocate enough rx buffers\n"); 197 return -ENOMEM; 198 } else { 199 new_size = rounddown_pow_of_two(ring->actual_size); 200 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 201 ring->actual_size, new_size); 202 goto reduce_rings; 203 } 204 } 205 ring->actual_size++; 206 ring->prod++; 207 } 208 } 209 return 0; 210 211 reduce_rings: 212 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 213 ring = priv->rx_ring[ring_ind]; 214 while (ring->actual_size > new_size) { 215 ring->actual_size--; 216 ring->prod--; 217 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 218 } 219 } 220 221 return 0; 222 } 223 224 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 225 struct mlx4_en_rx_ring *ring) 226 { 227 int index; 228 229 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 230 ring->cons, ring->prod); 231 232 /* Unmap and free Rx buffers */ 233 for (index = 0; index < ring->size; index++) { 234 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 235 mlx4_en_free_rx_desc(priv, ring, index); 236 } 237 ring->cons = 0; 238 ring->prod = 0; 239 } 240 241 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 242 { 243 int i; 244 int num_of_eqs; 245 int num_rx_rings; 246 struct mlx4_dev *dev = mdev->dev; 247 248 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 249 num_of_eqs = max_t(int, MIN_RX_RINGS, 250 min_t(int, 251 mlx4_get_eqs_per_port(mdev->dev, i), 252 DEF_RX_RINGS)); 253 254 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 255 min_t(int, num_of_eqs, 256 netif_get_num_default_rss_queues()); 257 mdev->profile.prof[i].rx_ring_num = 258 rounddown_pow_of_two(num_rx_rings); 259 } 260 } 261 262 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 263 struct mlx4_en_rx_ring **pring, 264 u32 size, u16 stride, int node) 265 { 266 struct mlx4_en_dev *mdev = priv->mdev; 267 struct mlx4_en_rx_ring *ring; 268 int err = -ENOMEM; 269 int tmp; 270 271 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 272 if (!ring) { 273 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 274 if (!ring) { 275 en_err(priv, "Failed to allocate RX ring structure\n"); 276 return -ENOMEM; 277 } 278 } 279 280 ring->prod = 0; 281 ring->cons = 0; 282 ring->size = size; 283 ring->size_mask = size - 1; 284 ring->stride = stride; 285 ring->log_stride = ffs(ring->stride) - 1; 286 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 287 288 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 289 sizeof(struct mlx4_en_rx_alloc)); 290 ring->rx_info = vzalloc_node(tmp, node); 291 if (!ring->rx_info) { 292 ring->rx_info = vzalloc(tmp); 293 if (!ring->rx_info) { 294 err = -ENOMEM; 295 goto err_ring; 296 } 297 } 298 299 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 300 ring->rx_info, tmp); 301 302 /* Allocate HW buffers on provided NUMA node */ 303 set_dev_node(&mdev->dev->persist->pdev->dev, node); 304 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 305 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 306 if (err) 307 goto err_info; 308 309 ring->buf = ring->wqres.buf.direct.buf; 310 311 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 312 313 *pring = ring; 314 return 0; 315 316 err_info: 317 vfree(ring->rx_info); 318 ring->rx_info = NULL; 319 err_ring: 320 kfree(ring); 321 *pring = NULL; 322 323 return err; 324 } 325 326 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 327 { 328 struct mlx4_en_rx_ring *ring; 329 int i; 330 int ring_ind; 331 int err; 332 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 333 DS_SIZE * priv->num_frags); 334 335 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 336 ring = priv->rx_ring[ring_ind]; 337 338 ring->prod = 0; 339 ring->cons = 0; 340 ring->actual_size = 0; 341 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 342 343 ring->stride = stride; 344 if (ring->stride <= TXBB_SIZE) { 345 /* Stamp first unused send wqe */ 346 __be32 *ptr = (__be32 *)ring->buf; 347 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); 348 *ptr = stamp; 349 /* Move pointer to start of rx section */ 350 ring->buf += TXBB_SIZE; 351 } 352 353 ring->log_stride = ffs(ring->stride) - 1; 354 ring->buf_size = ring->size * ring->stride; 355 356 memset(ring->buf, 0, ring->buf_size); 357 mlx4_en_update_rx_prod_db(ring); 358 359 /* Initialize all descriptors */ 360 for (i = 0; i < ring->size; i++) 361 mlx4_en_init_rx_desc(priv, ring, i); 362 } 363 err = mlx4_en_fill_rx_buffers(priv); 364 if (err) 365 goto err_buffers; 366 367 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 368 ring = priv->rx_ring[ring_ind]; 369 370 ring->size_mask = ring->actual_size - 1; 371 mlx4_en_update_rx_prod_db(ring); 372 } 373 374 return 0; 375 376 err_buffers: 377 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 378 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 379 380 ring_ind = priv->rx_ring_num - 1; 381 while (ring_ind >= 0) { 382 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 383 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 384 ring_ind--; 385 } 386 return err; 387 } 388 389 /* We recover from out of memory by scheduling our napi poll 390 * function (mlx4_en_process_cq), which tries to allocate 391 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 392 */ 393 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 394 { 395 int ring; 396 397 if (!priv->port_up) 398 return; 399 400 for (ring = 0; ring < priv->rx_ring_num; ring++) { 401 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) { 402 local_bh_disable(); 403 napi_reschedule(&priv->rx_cq[ring]->napi); 404 local_bh_enable(); 405 } 406 } 407 } 408 409 /* When the rx ring is running in page-per-packet mode, a released frame can go 410 * directly into a small cache, to avoid unmapping or touching the page 411 * allocator. In bpf prog performance scenarios, buffers are either forwarded 412 * or dropped, never converted to skbs, so every page can come directly from 413 * this cache when it is sized to be a multiple of the napi budget. 414 */ 415 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 416 struct mlx4_en_rx_alloc *frame) 417 { 418 struct mlx4_en_page_cache *cache = &ring->page_cache; 419 420 if (cache->index >= MLX4_EN_CACHE_SIZE) 421 return false; 422 423 cache->buf[cache->index].page = frame->page; 424 cache->buf[cache->index].dma = frame->dma; 425 cache->index++; 426 return true; 427 } 428 429 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 430 struct mlx4_en_rx_ring **pring, 431 u32 size, u16 stride) 432 { 433 struct mlx4_en_dev *mdev = priv->mdev; 434 struct mlx4_en_rx_ring *ring = *pring; 435 struct bpf_prog *old_prog; 436 437 old_prog = rcu_dereference_protected( 438 ring->xdp_prog, 439 lockdep_is_held(&mdev->state_lock)); 440 if (old_prog) 441 bpf_prog_put(old_prog); 442 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 443 vfree(ring->rx_info); 444 ring->rx_info = NULL; 445 kfree(ring); 446 *pring = NULL; 447 } 448 449 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 450 struct mlx4_en_rx_ring *ring) 451 { 452 int i; 453 454 for (i = 0; i < ring->page_cache.index; i++) { 455 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma, 456 PAGE_SIZE, priv->dma_dir); 457 put_page(ring->page_cache.buf[i].page); 458 } 459 ring->page_cache.index = 0; 460 mlx4_en_free_rx_buf(priv, ring); 461 if (ring->stride <= TXBB_SIZE) 462 ring->buf -= TXBB_SIZE; 463 } 464 465 466 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 467 struct mlx4_en_rx_alloc *frags, 468 struct sk_buff *skb, 469 int length) 470 { 471 const struct mlx4_en_frag_info *frag_info = priv->frag_info; 472 unsigned int truesize = 0; 473 int nr, frag_size; 474 struct page *page; 475 dma_addr_t dma; 476 bool release; 477 478 /* Collect used fragments while replacing them in the HW descriptors */ 479 for (nr = 0;; frags++) { 480 frag_size = min_t(int, length, frag_info->frag_size); 481 482 page = frags->page; 483 if (unlikely(!page)) 484 goto fail; 485 486 dma = frags->dma; 487 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset, 488 frag_size, priv->dma_dir); 489 490 __skb_fill_page_desc(skb, nr, page, frags->page_offset, 491 frag_size); 492 493 truesize += frag_info->frag_stride; 494 if (frag_info->frag_stride == PAGE_SIZE / 2) { 495 frags->page_offset ^= PAGE_SIZE / 2; 496 release = page_count(page) != 1 || 497 page_is_pfmemalloc(page) || 498 page_to_nid(page) != numa_mem_id(); 499 } else { 500 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES); 501 502 frags->page_offset += sz_align; 503 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE; 504 } 505 if (release) { 506 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir); 507 frags->page = NULL; 508 } else { 509 page_ref_inc(page); 510 } 511 512 nr++; 513 length -= frag_size; 514 if (!length) 515 break; 516 frag_info++; 517 } 518 skb->truesize += truesize; 519 return nr; 520 521 fail: 522 while (nr > 0) { 523 nr--; 524 __skb_frag_unref(skb_shinfo(skb)->frags + nr); 525 } 526 return 0; 527 } 528 529 static void validate_loopback(struct mlx4_en_priv *priv, void *va) 530 { 531 const unsigned char *data = va + ETH_HLEN; 532 int i; 533 534 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) { 535 if (data[i] != (unsigned char)i) 536 return; 537 } 538 /* Loopback found */ 539 priv->loopback_ok = 1; 540 } 541 542 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 543 struct mlx4_en_rx_ring *ring) 544 { 545 u32 missing = ring->actual_size - (ring->prod - ring->cons); 546 547 /* Try to batch allocations, but not too much. */ 548 if (missing < 8) 549 return false; 550 do { 551 if (mlx4_en_prepare_rx_desc(priv, ring, 552 ring->prod & ring->size_mask, 553 GFP_ATOMIC | __GFP_COLD | 554 __GFP_MEMALLOC)) 555 break; 556 ring->prod++; 557 } while (--missing); 558 559 return true; 560 } 561 562 /* When hardware doesn't strip the vlan, we need to calculate the checksum 563 * over it and add it to the hardware's checksum calculation 564 */ 565 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 566 struct vlan_hdr *vlanh) 567 { 568 return csum_add(hw_checksum, *(__wsum *)vlanh); 569 } 570 571 /* Although the stack expects checksum which doesn't include the pseudo 572 * header, the HW adds it. To address that, we are subtracting the pseudo 573 * header checksum from the checksum value provided by the HW. 574 */ 575 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 576 struct iphdr *iph) 577 { 578 __u16 length_for_csum = 0; 579 __wsum csum_pseudo_header = 0; 580 581 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 582 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 583 length_for_csum, iph->protocol, 0); 584 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 585 } 586 587 #if IS_ENABLED(CONFIG_IPV6) 588 /* In IPv6 packets, besides subtracting the pseudo header checksum, 589 * we also compute/add the IP header checksum which 590 * is not added by the HW. 591 */ 592 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 593 struct ipv6hdr *ipv6h) 594 { 595 __wsum csum_pseudo_hdr = 0; 596 597 if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT || 598 ipv6h->nexthdr == IPPROTO_HOPOPTS)) 599 return -1; 600 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); 601 602 csum_pseudo_hdr = csum_partial(&ipv6h->saddr, 603 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); 604 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); 605 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); 606 607 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); 608 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); 609 return 0; 610 } 611 #endif 612 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 613 netdev_features_t dev_features) 614 { 615 __wsum hw_checksum = 0; 616 617 void *hdr = (u8 *)va + sizeof(struct ethhdr); 618 619 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 620 621 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && 622 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { 623 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 624 hdr += sizeof(struct vlan_hdr); 625 } 626 627 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) 628 get_fixed_ipv4_csum(hw_checksum, skb, hdr); 629 #if IS_ENABLED(CONFIG_IPV6) 630 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 631 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr))) 632 return -1; 633 #endif 634 return 0; 635 } 636 637 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 638 { 639 struct mlx4_en_priv *priv = netdev_priv(dev); 640 struct mlx4_en_dev *mdev = priv->mdev; 641 struct mlx4_cqe *cqe; 642 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; 643 struct mlx4_en_rx_alloc *frags; 644 struct bpf_prog *xdp_prog; 645 int doorbell_pending; 646 struct sk_buff *skb; 647 int index; 648 int nr; 649 unsigned int length; 650 int polled = 0; 651 int ip_summed; 652 int factor = priv->cqe_factor; 653 u64 timestamp; 654 bool l2_tunnel; 655 656 if (unlikely(!priv->port_up)) 657 return 0; 658 659 if (unlikely(budget <= 0)) 660 return polled; 661 662 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */ 663 rcu_read_lock(); 664 xdp_prog = rcu_dereference(ring->xdp_prog); 665 doorbell_pending = 0; 666 667 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 668 * descriptor offset can be deduced from the CQE index instead of 669 * reading 'cqe->index' */ 670 index = cq->mcq.cons_index & ring->size_mask; 671 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 672 673 /* Process all completed CQEs */ 674 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 675 cq->mcq.cons_index & cq->size)) { 676 void *va; 677 678 frags = ring->rx_info + (index << priv->log_rx_info); 679 va = page_address(frags[0].page) + frags[0].page_offset; 680 /* 681 * make sure we read the CQE after we read the ownership bit 682 */ 683 dma_rmb(); 684 685 /* Drop packet on bad receive or bad checksum */ 686 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 687 MLX4_CQE_OPCODE_ERROR)) { 688 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 689 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 690 ((struct mlx4_err_cqe *)cqe)->syndrome); 691 goto next; 692 } 693 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 694 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 695 goto next; 696 } 697 698 /* Check if we need to drop the packet if SRIOV is not enabled 699 * and not performing the selftest or flb disabled 700 */ 701 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 702 const struct ethhdr *ethh = va; 703 dma_addr_t dma; 704 /* Get pointer to first fragment since we haven't 705 * skb yet and cast it to ethhdr struct 706 */ 707 dma = frags[0].dma + frags[0].page_offset; 708 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 709 DMA_FROM_DEVICE); 710 711 if (is_multicast_ether_addr(ethh->h_dest)) { 712 struct mlx4_mac_entry *entry; 713 struct hlist_head *bucket; 714 unsigned int mac_hash; 715 716 /* Drop the packet, since HW loopback-ed it */ 717 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 718 bucket = &priv->mac_hash[mac_hash]; 719 hlist_for_each_entry_rcu(entry, bucket, hlist) { 720 if (ether_addr_equal_64bits(entry->mac, 721 ethh->h_source)) 722 goto next; 723 } 724 } 725 } 726 727 if (unlikely(priv->validate_loopback)) { 728 validate_loopback(priv, va); 729 goto next; 730 } 731 732 /* 733 * Packet is OK - process it. 734 */ 735 length = be32_to_cpu(cqe->byte_cnt); 736 length -= ring->fcs_del; 737 738 /* A bpf program gets first chance to drop the packet. It may 739 * read bytes but not past the end of the frag. 740 */ 741 if (xdp_prog) { 742 struct xdp_buff xdp; 743 dma_addr_t dma; 744 void *orig_data; 745 u32 act; 746 747 dma = frags[0].dma + frags[0].page_offset; 748 dma_sync_single_for_cpu(priv->ddev, dma, 749 priv->frag_info[0].frag_size, 750 DMA_FROM_DEVICE); 751 752 xdp.data_hard_start = va - frags[0].page_offset; 753 xdp.data = va; 754 xdp.data_end = xdp.data + length; 755 orig_data = xdp.data; 756 757 act = bpf_prog_run_xdp(xdp_prog, &xdp); 758 759 if (xdp.data != orig_data) { 760 length = xdp.data_end - xdp.data; 761 frags[0].page_offset = xdp.data - 762 xdp.data_hard_start; 763 va = xdp.data; 764 } 765 766 switch (act) { 767 case XDP_PASS: 768 break; 769 case XDP_TX: 770 if (likely(!mlx4_en_xmit_frame(ring, frags, dev, 771 length, cq->ring, 772 &doorbell_pending))) { 773 frags[0].page = NULL; 774 goto next; 775 } 776 trace_xdp_exception(dev, xdp_prog, act); 777 goto xdp_drop_no_cnt; /* Drop on xmit failure */ 778 default: 779 bpf_warn_invalid_xdp_action(act); 780 case XDP_ABORTED: 781 trace_xdp_exception(dev, xdp_prog, act); 782 case XDP_DROP: 783 ring->xdp_drop++; 784 xdp_drop_no_cnt: 785 goto next; 786 } 787 } 788 789 ring->bytes += length; 790 ring->packets++; 791 792 skb = napi_get_frags(&cq->napi); 793 if (!skb) 794 goto next; 795 796 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) { 797 timestamp = mlx4_en_get_cqe_ts(cqe); 798 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), 799 timestamp); 800 } 801 skb_record_rx_queue(skb, cq->ring); 802 803 if (likely(dev->features & NETIF_F_RXCSUM)) { 804 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 805 MLX4_CQE_STATUS_UDP)) { 806 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 807 cqe->checksum == cpu_to_be16(0xffff)) { 808 ip_summed = CHECKSUM_UNNECESSARY; 809 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 810 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 811 if (l2_tunnel) 812 skb->csum_level = 1; 813 ring->csum_ok++; 814 } else { 815 goto csum_none; 816 } 817 } else { 818 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 819 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 820 MLX4_CQE_STATUS_IPV6))) { 821 if (check_csum(cqe, skb, va, dev->features)) { 822 goto csum_none; 823 } else { 824 ip_summed = CHECKSUM_COMPLETE; 825 ring->csum_complete++; 826 } 827 } else { 828 goto csum_none; 829 } 830 } 831 } else { 832 csum_none: 833 ip_summed = CHECKSUM_NONE; 834 ring->csum_none++; 835 } 836 skb->ip_summed = ip_summed; 837 if (dev->features & NETIF_F_RXHASH) 838 skb_set_hash(skb, 839 be32_to_cpu(cqe->immed_rss_invalid), 840 (ip_summed == CHECKSUM_UNNECESSARY) ? 841 PKT_HASH_TYPE_L4 : 842 PKT_HASH_TYPE_L3); 843 844 845 if ((cqe->vlan_my_qpn & 846 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && 847 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 848 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 849 be16_to_cpu(cqe->sl_vid)); 850 else if ((cqe->vlan_my_qpn & 851 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) && 852 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) 853 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), 854 be16_to_cpu(cqe->sl_vid)); 855 856 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length); 857 if (likely(nr)) { 858 skb_shinfo(skb)->nr_frags = nr; 859 skb->len = length; 860 skb->data_len = length; 861 napi_gro_frags(&cq->napi); 862 } else { 863 skb->vlan_tci = 0; 864 skb_clear_hash(skb); 865 } 866 next: 867 ++cq->mcq.cons_index; 868 index = (cq->mcq.cons_index) & ring->size_mask; 869 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 870 if (++polled == budget) 871 break; 872 } 873 874 rcu_read_unlock(); 875 876 if (polled) { 877 if (doorbell_pending) 878 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]); 879 880 mlx4_cq_set_ci(&cq->mcq); 881 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 882 ring->cons = cq->mcq.cons_index; 883 } 884 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 885 886 if (mlx4_en_refill_rx_buffers(priv, ring)) 887 mlx4_en_update_rx_prod_db(ring); 888 889 return polled; 890 } 891 892 893 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 894 { 895 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 896 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 897 898 if (likely(priv->port_up)) 899 napi_schedule_irqoff(&cq->napi); 900 else 901 mlx4_en_arm_cq(priv, cq); 902 } 903 904 /* Rx CQ polling - called by NAPI */ 905 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 906 { 907 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 908 struct net_device *dev = cq->dev; 909 struct mlx4_en_priv *priv = netdev_priv(dev); 910 int done; 911 912 done = mlx4_en_process_rx_cq(dev, cq, budget); 913 914 /* If we used up all the quota - we're probably not done yet... */ 915 if (done == budget) { 916 const struct cpumask *aff; 917 struct irq_data *idata; 918 int cpu_curr; 919 920 INC_PERF_COUNTER(priv->pstats.napi_quota); 921 922 cpu_curr = smp_processor_id(); 923 idata = irq_desc_get_irq_data(cq->irq_desc); 924 aff = irq_data_get_affinity_mask(idata); 925 926 if (likely(cpumask_test_cpu(cpu_curr, aff))) 927 return budget; 928 929 /* Current cpu is not according to smp_irq_affinity - 930 * probably affinity changed. Need to stop this NAPI 931 * poll, and restart it on the right CPU. 932 * Try to avoid returning a too small value (like 0), 933 * to not fool net_rx_action() and its netdev_budget 934 */ 935 if (done) 936 done--; 937 } 938 /* Done for now */ 939 if (napi_complete_done(napi, done)) 940 mlx4_en_arm_cq(priv, cq); 941 return done; 942 } 943 944 void mlx4_en_calc_rx_buf(struct net_device *dev) 945 { 946 struct mlx4_en_priv *priv = netdev_priv(dev); 947 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); 948 int i = 0; 949 950 /* bpf requires buffers to be set up as 1 packet per page. 951 * This only works when num_frags == 1. 952 */ 953 if (priv->tx_ring_num[TX_XDP]) { 954 priv->frag_info[0].frag_size = eff_mtu; 955 /* This will gain efficient xdp frame recycling at the 956 * expense of more costly truesize accounting 957 */ 958 priv->frag_info[0].frag_stride = PAGE_SIZE; 959 priv->dma_dir = PCI_DMA_BIDIRECTIONAL; 960 priv->rx_headroom = XDP_PACKET_HEADROOM; 961 i = 1; 962 } else { 963 int frag_size_max = 2048, buf_size = 0; 964 965 /* should not happen, right ? */ 966 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048) 967 frag_size_max = PAGE_SIZE; 968 969 while (buf_size < eff_mtu) { 970 int frag_stride, frag_size = eff_mtu - buf_size; 971 int pad, nb; 972 973 if (i < MLX4_EN_MAX_RX_FRAGS - 1) 974 frag_size = min(frag_size, frag_size_max); 975 976 priv->frag_info[i].frag_size = frag_size; 977 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES); 978 /* We can only pack 2 1536-bytes frames in on 4K page 979 * Therefore, each frame would consume more bytes (truesize) 980 */ 981 nb = PAGE_SIZE / frag_stride; 982 pad = (PAGE_SIZE - nb * frag_stride) / nb; 983 pad &= ~(SMP_CACHE_BYTES - 1); 984 priv->frag_info[i].frag_stride = frag_stride + pad; 985 986 buf_size += frag_size; 987 i++; 988 } 989 priv->dma_dir = PCI_DMA_FROMDEVICE; 990 priv->rx_headroom = 0; 991 } 992 993 priv->num_frags = i; 994 priv->rx_skb_size = eff_mtu; 995 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 996 997 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 998 eff_mtu, priv->num_frags); 999 for (i = 0; i < priv->num_frags; i++) { 1000 en_err(priv, 1001 " frag:%d - size:%d stride:%d\n", 1002 i, 1003 priv->frag_info[i].frag_size, 1004 priv->frag_info[i].frag_stride); 1005 } 1006 } 1007 1008 /* RSS related functions */ 1009 1010 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1011 struct mlx4_en_rx_ring *ring, 1012 enum mlx4_qp_state *state, 1013 struct mlx4_qp *qp) 1014 { 1015 struct mlx4_en_dev *mdev = priv->mdev; 1016 struct mlx4_qp_context *context; 1017 int err = 0; 1018 1019 context = kmalloc(sizeof(*context), GFP_KERNEL); 1020 if (!context) 1021 return -ENOMEM; 1022 1023 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); 1024 if (err) { 1025 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1026 goto out; 1027 } 1028 qp->event = mlx4_en_sqp_event; 1029 1030 memset(context, 0, sizeof *context); 1031 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1032 qpn, ring->cqn, -1, context); 1033 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1034 1035 /* Cancel FCS removal if FW allows */ 1036 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1037 context->param3 |= cpu_to_be32(1 << 29); 1038 if (priv->dev->features & NETIF_F_RXFCS) 1039 ring->fcs_del = 0; 1040 else 1041 ring->fcs_del = ETH_FCS_LEN; 1042 } else 1043 ring->fcs_del = 0; 1044 1045 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1046 if (err) { 1047 mlx4_qp_remove(mdev->dev, qp); 1048 mlx4_qp_free(mdev->dev, qp); 1049 } 1050 mlx4_en_update_rx_prod_db(ring); 1051 out: 1052 kfree(context); 1053 return err; 1054 } 1055 1056 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1057 { 1058 int err; 1059 u32 qpn; 1060 1061 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1062 MLX4_RESERVE_A0_QP); 1063 if (err) { 1064 en_err(priv, "Failed reserving drop qpn\n"); 1065 return err; 1066 } 1067 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); 1068 if (err) { 1069 en_err(priv, "Failed allocating drop qp\n"); 1070 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1071 return err; 1072 } 1073 1074 return 0; 1075 } 1076 1077 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1078 { 1079 u32 qpn; 1080 1081 qpn = priv->drop_qp.qpn; 1082 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1083 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1084 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1085 } 1086 1087 /* Allocate rx qp's and configure them according to rss map */ 1088 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1089 { 1090 struct mlx4_en_dev *mdev = priv->mdev; 1091 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1092 struct mlx4_qp_context context; 1093 struct mlx4_rss_context *rss_context; 1094 int rss_rings; 1095 void *ptr; 1096 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1097 MLX4_RSS_TCP_IPV6); 1098 int i, qpn; 1099 int err = 0; 1100 int good_qps = 0; 1101 1102 en_dbg(DRV, priv, "Configuring rss steering\n"); 1103 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1104 priv->rx_ring_num, 1105 &rss_map->base_qpn, 0); 1106 if (err) { 1107 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1108 return err; 1109 } 1110 1111 for (i = 0; i < priv->rx_ring_num; i++) { 1112 qpn = rss_map->base_qpn + i; 1113 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1114 &rss_map->state[i], 1115 &rss_map->qps[i]); 1116 if (err) 1117 goto rss_err; 1118 1119 ++good_qps; 1120 } 1121 1122 /* Configure RSS indirection qp */ 1123 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); 1124 if (err) { 1125 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1126 goto rss_err; 1127 } 1128 rss_map->indir_qp.event = mlx4_en_sqp_event; 1129 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1130 priv->rx_ring[0]->cqn, -1, &context); 1131 1132 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1133 rss_rings = priv->rx_ring_num; 1134 else 1135 rss_rings = priv->prof->rss_rings; 1136 1137 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1138 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1139 rss_context = ptr; 1140 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1141 (rss_map->base_qpn)); 1142 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1143 if (priv->mdev->profile.udp_rss) { 1144 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1145 rss_context->base_qpn_udp = rss_context->default_qpn; 1146 } 1147 1148 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1149 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1150 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1151 } 1152 1153 rss_context->flags = rss_mask; 1154 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1155 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1156 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1157 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1158 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1159 memcpy(rss_context->rss_key, priv->rss_key, 1160 MLX4_EN_RSS_KEY_SIZE); 1161 } else { 1162 en_err(priv, "Unknown RSS hash function requested\n"); 1163 err = -EINVAL; 1164 goto indir_err; 1165 } 1166 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1167 &rss_map->indir_qp, &rss_map->indir_state); 1168 if (err) 1169 goto indir_err; 1170 1171 return 0; 1172 1173 indir_err: 1174 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1175 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1176 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1177 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1178 rss_err: 1179 for (i = 0; i < good_qps; i++) { 1180 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1181 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1182 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1183 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1184 } 1185 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1186 return err; 1187 } 1188 1189 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1190 { 1191 struct mlx4_en_dev *mdev = priv->mdev; 1192 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1193 int i; 1194 1195 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1196 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1197 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1198 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1199 1200 for (i = 0; i < priv->rx_ring_num; i++) { 1201 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1202 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1203 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1204 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1205 } 1206 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1207 } 1208