1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/rculist.h> 40 #include <linux/if_ether.h> 41 #include <linux/if_vlan.h> 42 #include <linux/vmalloc.h> 43 44 #include "mlx4_en.h" 45 46 static int mlx4_alloc_pages(struct mlx4_en_priv *priv, 47 struct mlx4_en_rx_alloc *page_alloc, 48 const struct mlx4_en_frag_info *frag_info, 49 gfp_t _gfp) 50 { 51 int order; 52 struct page *page; 53 dma_addr_t dma; 54 55 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { 56 gfp_t gfp = _gfp; 57 58 if (order) 59 gfp |= __GFP_COMP | __GFP_NOWARN; 60 page = alloc_pages(gfp, order); 61 if (likely(page)) 62 break; 63 if (--order < 0 || 64 ((PAGE_SIZE << order) < frag_info->frag_size)) 65 return -ENOMEM; 66 } 67 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, 68 PCI_DMA_FROMDEVICE); 69 if (dma_mapping_error(priv->ddev, dma)) { 70 put_page(page); 71 return -ENOMEM; 72 } 73 page_alloc->page_size = PAGE_SIZE << order; 74 page_alloc->page = page; 75 page_alloc->dma = dma; 76 page_alloc->page_offset = frag_info->frag_align; 77 /* Not doing get_page() for each frag is a big win 78 * on asymetric workloads. 79 */ 80 atomic_set(&page->_count, 81 page_alloc->page_size / frag_info->frag_stride); 82 return 0; 83 } 84 85 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 86 struct mlx4_en_rx_desc *rx_desc, 87 struct mlx4_en_rx_alloc *frags, 88 struct mlx4_en_rx_alloc *ring_alloc, 89 gfp_t gfp) 90 { 91 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 92 const struct mlx4_en_frag_info *frag_info; 93 struct page *page; 94 dma_addr_t dma; 95 int i; 96 97 for (i = 0; i < priv->num_frags; i++) { 98 frag_info = &priv->frag_info[i]; 99 page_alloc[i] = ring_alloc[i]; 100 page_alloc[i].page_offset += frag_info->frag_stride; 101 102 if (page_alloc[i].page_offset + frag_info->frag_stride <= 103 ring_alloc[i].page_size) 104 continue; 105 106 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) 107 goto out; 108 } 109 110 for (i = 0; i < priv->num_frags; i++) { 111 frags[i] = ring_alloc[i]; 112 dma = ring_alloc[i].dma + ring_alloc[i].page_offset; 113 ring_alloc[i] = page_alloc[i]; 114 rx_desc->data[i].addr = cpu_to_be64(dma); 115 } 116 117 return 0; 118 119 out: 120 while (i--) { 121 frag_info = &priv->frag_info[i]; 122 if (page_alloc[i].page != ring_alloc[i].page) { 123 dma_unmap_page(priv->ddev, page_alloc[i].dma, 124 page_alloc[i].page_size, PCI_DMA_FROMDEVICE); 125 page = page_alloc[i].page; 126 atomic_set(&page->_count, 1); 127 put_page(page); 128 } 129 } 130 return -ENOMEM; 131 } 132 133 static void mlx4_en_free_frag(struct mlx4_en_priv *priv, 134 struct mlx4_en_rx_alloc *frags, 135 int i) 136 { 137 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 138 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; 139 140 141 if (next_frag_end > frags[i].page_size) 142 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, 143 PCI_DMA_FROMDEVICE); 144 145 if (frags[i].page) 146 put_page(frags[i].page); 147 } 148 149 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, 150 struct mlx4_en_rx_ring *ring) 151 { 152 int i; 153 struct mlx4_en_rx_alloc *page_alloc; 154 155 for (i = 0; i < priv->num_frags; i++) { 156 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 157 158 if (mlx4_alloc_pages(priv, &ring->page_alloc[i], 159 frag_info, GFP_KERNEL)) 160 goto out; 161 } 162 return 0; 163 164 out: 165 while (i--) { 166 struct page *page; 167 168 page_alloc = &ring->page_alloc[i]; 169 dma_unmap_page(priv->ddev, page_alloc->dma, 170 page_alloc->page_size, PCI_DMA_FROMDEVICE); 171 page = page_alloc->page; 172 atomic_set(&page->_count, 1); 173 put_page(page); 174 page_alloc->page = NULL; 175 } 176 return -ENOMEM; 177 } 178 179 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, 180 struct mlx4_en_rx_ring *ring) 181 { 182 struct mlx4_en_rx_alloc *page_alloc; 183 int i; 184 185 for (i = 0; i < priv->num_frags; i++) { 186 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 187 188 page_alloc = &ring->page_alloc[i]; 189 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", 190 i, page_count(page_alloc->page)); 191 192 dma_unmap_page(priv->ddev, page_alloc->dma, 193 page_alloc->page_size, PCI_DMA_FROMDEVICE); 194 while (page_alloc->page_offset + frag_info->frag_stride < 195 page_alloc->page_size) { 196 put_page(page_alloc->page); 197 page_alloc->page_offset += frag_info->frag_stride; 198 } 199 page_alloc->page = NULL; 200 } 201 } 202 203 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, 204 struct mlx4_en_rx_ring *ring, int index) 205 { 206 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 207 int possible_frags; 208 int i; 209 210 /* Set size and memtype fields */ 211 for (i = 0; i < priv->num_frags; i++) { 212 rx_desc->data[i].byte_count = 213 cpu_to_be32(priv->frag_info[i].frag_size); 214 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 215 } 216 217 /* If the number of used fragments does not fill up the ring stride, 218 * remaining (unused) fragments must be padded with null address/size 219 * and a special memory key */ 220 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 221 for (i = priv->num_frags; i < possible_frags; i++) { 222 rx_desc->data[i].byte_count = 0; 223 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 224 rx_desc->data[i].addr = 0; 225 } 226 } 227 228 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 229 struct mlx4_en_rx_ring *ring, int index, 230 gfp_t gfp) 231 { 232 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 233 struct mlx4_en_rx_alloc *frags = ring->rx_info + 234 (index << priv->log_rx_info); 235 236 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); 237 } 238 239 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 240 { 241 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 242 } 243 244 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, 245 struct mlx4_en_rx_ring *ring, 246 int index) 247 { 248 struct mlx4_en_rx_alloc *frags; 249 int nr; 250 251 frags = ring->rx_info + (index << priv->log_rx_info); 252 for (nr = 0; nr < priv->num_frags; nr++) { 253 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 254 mlx4_en_free_frag(priv, frags, nr); 255 } 256 } 257 258 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 259 { 260 struct mlx4_en_rx_ring *ring; 261 int ring_ind; 262 int buf_ind; 263 int new_size; 264 265 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 266 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 267 ring = priv->rx_ring[ring_ind]; 268 269 if (mlx4_en_prepare_rx_desc(priv, ring, 270 ring->actual_size, 271 GFP_KERNEL)) { 272 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 273 en_err(priv, "Failed to allocate enough rx buffers\n"); 274 return -ENOMEM; 275 } else { 276 new_size = rounddown_pow_of_two(ring->actual_size); 277 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 278 ring->actual_size, new_size); 279 goto reduce_rings; 280 } 281 } 282 ring->actual_size++; 283 ring->prod++; 284 } 285 } 286 return 0; 287 288 reduce_rings: 289 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 290 ring = priv->rx_ring[ring_ind]; 291 while (ring->actual_size > new_size) { 292 ring->actual_size--; 293 ring->prod--; 294 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 295 } 296 } 297 298 return 0; 299 } 300 301 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 302 struct mlx4_en_rx_ring *ring) 303 { 304 int index; 305 306 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 307 ring->cons, ring->prod); 308 309 /* Unmap and free Rx buffers */ 310 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); 311 while (ring->cons != ring->prod) { 312 index = ring->cons & ring->size_mask; 313 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 314 mlx4_en_free_rx_desc(priv, ring, index); 315 ++ring->cons; 316 } 317 } 318 319 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 320 { 321 int i; 322 int num_of_eqs; 323 int num_rx_rings; 324 struct mlx4_dev *dev = mdev->dev; 325 326 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 327 if (!dev->caps.comp_pool) 328 num_of_eqs = max_t(int, MIN_RX_RINGS, 329 min_t(int, 330 dev->caps.num_comp_vectors, 331 DEF_RX_RINGS)); 332 else 333 num_of_eqs = min_t(int, MAX_MSIX_P_PORT, 334 dev->caps.comp_pool/ 335 dev->caps.num_ports) - 1; 336 337 num_rx_rings = min_t(int, num_of_eqs, 338 netif_get_num_default_rss_queues()); 339 mdev->profile.prof[i].rx_ring_num = 340 rounddown_pow_of_two(num_rx_rings); 341 } 342 } 343 344 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 345 struct mlx4_en_rx_ring **pring, 346 u32 size, u16 stride, int node) 347 { 348 struct mlx4_en_dev *mdev = priv->mdev; 349 struct mlx4_en_rx_ring *ring; 350 int err = -ENOMEM; 351 int tmp; 352 353 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 354 if (!ring) { 355 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 356 if (!ring) { 357 en_err(priv, "Failed to allocate RX ring structure\n"); 358 return -ENOMEM; 359 } 360 } 361 362 ring->prod = 0; 363 ring->cons = 0; 364 ring->size = size; 365 ring->size_mask = size - 1; 366 ring->stride = stride; 367 ring->log_stride = ffs(ring->stride) - 1; 368 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 369 370 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 371 sizeof(struct mlx4_en_rx_alloc)); 372 ring->rx_info = vmalloc_node(tmp, node); 373 if (!ring->rx_info) { 374 ring->rx_info = vmalloc(tmp); 375 if (!ring->rx_info) { 376 err = -ENOMEM; 377 goto err_ring; 378 } 379 } 380 381 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 382 ring->rx_info, tmp); 383 384 /* Allocate HW buffers on provided NUMA node */ 385 set_dev_node(&mdev->dev->pdev->dev, node); 386 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 387 ring->buf_size, 2 * PAGE_SIZE); 388 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 389 if (err) 390 goto err_info; 391 392 err = mlx4_en_map_buffer(&ring->wqres.buf); 393 if (err) { 394 en_err(priv, "Failed to map RX buffer\n"); 395 goto err_hwq; 396 } 397 ring->buf = ring->wqres.buf.direct.buf; 398 399 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 400 401 *pring = ring; 402 return 0; 403 404 err_hwq: 405 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 406 err_info: 407 vfree(ring->rx_info); 408 ring->rx_info = NULL; 409 err_ring: 410 kfree(ring); 411 *pring = NULL; 412 413 return err; 414 } 415 416 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 417 { 418 struct mlx4_en_rx_ring *ring; 419 int i; 420 int ring_ind; 421 int err; 422 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 423 DS_SIZE * priv->num_frags); 424 425 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 426 ring = priv->rx_ring[ring_ind]; 427 428 ring->prod = 0; 429 ring->cons = 0; 430 ring->actual_size = 0; 431 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 432 433 ring->stride = stride; 434 if (ring->stride <= TXBB_SIZE) 435 ring->buf += TXBB_SIZE; 436 437 ring->log_stride = ffs(ring->stride) - 1; 438 ring->buf_size = ring->size * ring->stride; 439 440 memset(ring->buf, 0, ring->buf_size); 441 mlx4_en_update_rx_prod_db(ring); 442 443 /* Initialize all descriptors */ 444 for (i = 0; i < ring->size; i++) 445 mlx4_en_init_rx_desc(priv, ring, i); 446 447 /* Initialize page allocators */ 448 err = mlx4_en_init_allocator(priv, ring); 449 if (err) { 450 en_err(priv, "Failed initializing ring allocator\n"); 451 if (ring->stride <= TXBB_SIZE) 452 ring->buf -= TXBB_SIZE; 453 ring_ind--; 454 goto err_allocator; 455 } 456 } 457 err = mlx4_en_fill_rx_buffers(priv); 458 if (err) 459 goto err_buffers; 460 461 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 462 ring = priv->rx_ring[ring_ind]; 463 464 ring->size_mask = ring->actual_size - 1; 465 mlx4_en_update_rx_prod_db(ring); 466 } 467 468 return 0; 469 470 err_buffers: 471 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 472 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 473 474 ring_ind = priv->rx_ring_num - 1; 475 err_allocator: 476 while (ring_ind >= 0) { 477 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 478 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 479 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); 480 ring_ind--; 481 } 482 return err; 483 } 484 485 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 486 struct mlx4_en_rx_ring **pring, 487 u32 size, u16 stride) 488 { 489 struct mlx4_en_dev *mdev = priv->mdev; 490 struct mlx4_en_rx_ring *ring = *pring; 491 492 mlx4_en_unmap_buffer(&ring->wqres.buf); 493 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 494 vfree(ring->rx_info); 495 ring->rx_info = NULL; 496 kfree(ring); 497 *pring = NULL; 498 #ifdef CONFIG_RFS_ACCEL 499 mlx4_en_cleanup_filters(priv); 500 #endif 501 } 502 503 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 504 struct mlx4_en_rx_ring *ring) 505 { 506 mlx4_en_free_rx_buf(priv, ring); 507 if (ring->stride <= TXBB_SIZE) 508 ring->buf -= TXBB_SIZE; 509 mlx4_en_destroy_allocator(priv, ring); 510 } 511 512 513 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 514 struct mlx4_en_rx_desc *rx_desc, 515 struct mlx4_en_rx_alloc *frags, 516 struct sk_buff *skb, 517 int length) 518 { 519 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; 520 struct mlx4_en_frag_info *frag_info; 521 int nr; 522 dma_addr_t dma; 523 524 /* Collect used fragments while replacing them in the HW descriptors */ 525 for (nr = 0; nr < priv->num_frags; nr++) { 526 frag_info = &priv->frag_info[nr]; 527 if (length <= frag_info->frag_prefix_size) 528 break; 529 if (!frags[nr].page) 530 goto fail; 531 532 dma = be64_to_cpu(rx_desc->data[nr].addr); 533 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, 534 DMA_FROM_DEVICE); 535 536 /* Save page reference in skb */ 537 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); 538 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); 539 skb_frags_rx[nr].page_offset = frags[nr].page_offset; 540 skb->truesize += frag_info->frag_stride; 541 frags[nr].page = NULL; 542 } 543 /* Adjust size of last fragment to match actual length */ 544 if (nr > 0) 545 skb_frag_size_set(&skb_frags_rx[nr - 1], 546 length - priv->frag_info[nr - 1].frag_prefix_size); 547 return nr; 548 549 fail: 550 while (nr > 0) { 551 nr--; 552 __skb_frag_unref(&skb_frags_rx[nr]); 553 } 554 return 0; 555 } 556 557 558 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, 559 struct mlx4_en_rx_desc *rx_desc, 560 struct mlx4_en_rx_alloc *frags, 561 unsigned int length) 562 { 563 struct sk_buff *skb; 564 void *va; 565 int used_frags; 566 dma_addr_t dma; 567 568 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); 569 if (!skb) { 570 en_dbg(RX_ERR, priv, "Failed allocating skb\n"); 571 return NULL; 572 } 573 skb_reserve(skb, NET_IP_ALIGN); 574 skb->len = length; 575 576 /* Get pointer to first fragment so we could copy the headers into the 577 * (linear part of the) skb */ 578 va = page_address(frags[0].page) + frags[0].page_offset; 579 580 if (length <= SMALL_PACKET_SIZE) { 581 /* We are copying all relevant data to the skb - temporarily 582 * sync buffers for the copy */ 583 dma = be64_to_cpu(rx_desc->data[0].addr); 584 dma_sync_single_for_cpu(priv->ddev, dma, length, 585 DMA_FROM_DEVICE); 586 skb_copy_to_linear_data(skb, va, length); 587 skb->tail += length; 588 } else { 589 /* Move relevant fragments to skb */ 590 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, 591 skb, length); 592 if (unlikely(!used_frags)) { 593 kfree_skb(skb); 594 return NULL; 595 } 596 skb_shinfo(skb)->nr_frags = used_frags; 597 598 /* Copy headers into the skb linear buffer */ 599 memcpy(skb->data, va, HEADER_COPY_SIZE); 600 skb->tail += HEADER_COPY_SIZE; 601 602 /* Skip headers in first fragment */ 603 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; 604 605 /* Adjust size of first fragment */ 606 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); 607 skb->data_len = length - HEADER_COPY_SIZE; 608 } 609 return skb; 610 } 611 612 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) 613 { 614 int i; 615 int offset = ETH_HLEN; 616 617 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { 618 if (*(skb->data + offset) != (unsigned char) (i & 0xff)) 619 goto out_loopback; 620 } 621 /* Loopback found */ 622 priv->loopback_ok = 1; 623 624 out_loopback: 625 dev_kfree_skb_any(skb); 626 } 627 628 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 629 struct mlx4_en_rx_ring *ring) 630 { 631 int index = ring->prod & ring->size_mask; 632 633 while ((u32) (ring->prod - ring->cons) < ring->actual_size) { 634 if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC)) 635 break; 636 ring->prod++; 637 index = ring->prod & ring->size_mask; 638 } 639 } 640 641 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 642 { 643 struct mlx4_en_priv *priv = netdev_priv(dev); 644 struct mlx4_en_dev *mdev = priv->mdev; 645 struct mlx4_cqe *cqe; 646 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; 647 struct mlx4_en_rx_alloc *frags; 648 struct mlx4_en_rx_desc *rx_desc; 649 struct sk_buff *skb; 650 int index; 651 int nr; 652 unsigned int length; 653 int polled = 0; 654 int ip_summed; 655 int factor = priv->cqe_factor; 656 u64 timestamp; 657 bool l2_tunnel; 658 659 if (!priv->port_up) 660 return 0; 661 662 if (budget <= 0) 663 return polled; 664 665 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 666 * descriptor offset can be deduced from the CQE index instead of 667 * reading 'cqe->index' */ 668 index = cq->mcq.cons_index & ring->size_mask; 669 cqe = &cq->buf[(index << factor) + factor]; 670 671 /* Process all completed CQEs */ 672 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 673 cq->mcq.cons_index & cq->size)) { 674 675 frags = ring->rx_info + (index << priv->log_rx_info); 676 rx_desc = ring->buf + (index << ring->log_stride); 677 678 /* 679 * make sure we read the CQE after we read the ownership bit 680 */ 681 rmb(); 682 683 /* Drop packet on bad receive or bad checksum */ 684 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 685 MLX4_CQE_OPCODE_ERROR)) { 686 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 687 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 688 ((struct mlx4_err_cqe *)cqe)->syndrome); 689 goto next; 690 } 691 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 692 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 693 goto next; 694 } 695 696 /* Check if we need to drop the packet if SRIOV is not enabled 697 * and not performing the selftest or flb disabled 698 */ 699 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 700 struct ethhdr *ethh; 701 dma_addr_t dma; 702 /* Get pointer to first fragment since we haven't 703 * skb yet and cast it to ethhdr struct 704 */ 705 dma = be64_to_cpu(rx_desc->data[0].addr); 706 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 707 DMA_FROM_DEVICE); 708 ethh = (struct ethhdr *)(page_address(frags[0].page) + 709 frags[0].page_offset); 710 711 if (is_multicast_ether_addr(ethh->h_dest)) { 712 struct mlx4_mac_entry *entry; 713 struct hlist_head *bucket; 714 unsigned int mac_hash; 715 716 /* Drop the packet, since HW loopback-ed it */ 717 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 718 bucket = &priv->mac_hash[mac_hash]; 719 rcu_read_lock(); 720 hlist_for_each_entry_rcu(entry, bucket, hlist) { 721 if (ether_addr_equal_64bits(entry->mac, 722 ethh->h_source)) { 723 rcu_read_unlock(); 724 goto next; 725 } 726 } 727 rcu_read_unlock(); 728 } 729 } 730 731 /* 732 * Packet is OK - process it. 733 */ 734 length = be32_to_cpu(cqe->byte_cnt); 735 length -= ring->fcs_del; 736 ring->bytes += length; 737 ring->packets++; 738 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 739 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 740 741 if (likely(dev->features & NETIF_F_RXCSUM)) { 742 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 743 (cqe->checksum == cpu_to_be16(0xffff))) { 744 ring->csum_ok++; 745 /* This packet is eligible for GRO if it is: 746 * - DIX Ethernet (type interpretation) 747 * - TCP/IP (v4) 748 * - without IP options 749 * - not an IP fragment 750 * - no LLS polling in progress 751 */ 752 if (!mlx4_en_cq_busy_polling(cq) && 753 (dev->features & NETIF_F_GRO)) { 754 struct sk_buff *gro_skb = napi_get_frags(&cq->napi); 755 if (!gro_skb) 756 goto next; 757 758 nr = mlx4_en_complete_rx_desc(priv, 759 rx_desc, frags, gro_skb, 760 length); 761 if (!nr) 762 goto next; 763 764 skb_shinfo(gro_skb)->nr_frags = nr; 765 gro_skb->len = length; 766 gro_skb->data_len = length; 767 gro_skb->ip_summed = CHECKSUM_UNNECESSARY; 768 769 if (l2_tunnel) 770 gro_skb->encapsulation = 1; 771 if ((cqe->vlan_my_qpn & 772 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && 773 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 774 u16 vid = be16_to_cpu(cqe->sl_vid); 775 776 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); 777 } 778 779 if (dev->features & NETIF_F_RXHASH) 780 skb_set_hash(gro_skb, 781 be32_to_cpu(cqe->immed_rss_invalid), 782 PKT_HASH_TYPE_L3); 783 784 skb_record_rx_queue(gro_skb, cq->ring); 785 786 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 787 timestamp = mlx4_en_get_cqe_ts(cqe); 788 mlx4_en_fill_hwtstamps(mdev, 789 skb_hwtstamps(gro_skb), 790 timestamp); 791 } 792 793 napi_gro_frags(&cq->napi); 794 goto next; 795 } 796 797 /* GRO not possible, complete processing here */ 798 ip_summed = CHECKSUM_UNNECESSARY; 799 } else { 800 ip_summed = CHECKSUM_NONE; 801 ring->csum_none++; 802 } 803 } else { 804 ip_summed = CHECKSUM_NONE; 805 ring->csum_none++; 806 } 807 808 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); 809 if (!skb) { 810 priv->stats.rx_dropped++; 811 goto next; 812 } 813 814 if (unlikely(priv->validate_loopback)) { 815 validate_loopback(priv, skb); 816 goto next; 817 } 818 819 skb->ip_summed = ip_summed; 820 skb->protocol = eth_type_trans(skb, dev); 821 skb_record_rx_queue(skb, cq->ring); 822 823 if (l2_tunnel) 824 skb->encapsulation = 1; 825 826 if (dev->features & NETIF_F_RXHASH) 827 skb_set_hash(skb, 828 be32_to_cpu(cqe->immed_rss_invalid), 829 PKT_HASH_TYPE_L3); 830 831 if ((be32_to_cpu(cqe->vlan_my_qpn) & 832 MLX4_CQE_VLAN_PRESENT_MASK) && 833 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 834 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); 835 836 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 837 timestamp = mlx4_en_get_cqe_ts(cqe); 838 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), 839 timestamp); 840 } 841 842 skb_mark_napi_id(skb, &cq->napi); 843 844 if (!mlx4_en_cq_busy_polling(cq)) 845 napi_gro_receive(&cq->napi, skb); 846 else 847 netif_receive_skb(skb); 848 849 next: 850 for (nr = 0; nr < priv->num_frags; nr++) 851 mlx4_en_free_frag(priv, frags, nr); 852 853 ++cq->mcq.cons_index; 854 index = (cq->mcq.cons_index) & ring->size_mask; 855 cqe = &cq->buf[(index << factor) + factor]; 856 if (++polled == budget) 857 goto out; 858 } 859 860 out: 861 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 862 mlx4_cq_set_ci(&cq->mcq); 863 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 864 ring->cons = cq->mcq.cons_index; 865 mlx4_en_refill_rx_buffers(priv, ring); 866 mlx4_en_update_rx_prod_db(ring); 867 return polled; 868 } 869 870 871 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 872 { 873 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 874 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 875 876 if (priv->port_up) 877 napi_schedule(&cq->napi); 878 else 879 mlx4_en_arm_cq(priv, cq); 880 } 881 882 /* Rx CQ polling - called by NAPI */ 883 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 884 { 885 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 886 struct net_device *dev = cq->dev; 887 struct mlx4_en_priv *priv = netdev_priv(dev); 888 int done; 889 890 if (!mlx4_en_cq_lock_napi(cq)) 891 return budget; 892 893 done = mlx4_en_process_rx_cq(dev, cq, budget); 894 895 mlx4_en_cq_unlock_napi(cq); 896 897 /* If we used up all the quota - we're probably not done yet... */ 898 if (done == budget) { 899 INC_PERF_COUNTER(priv->pstats.napi_quota); 900 if (unlikely(cq->mcq.irq_affinity_change)) { 901 cq->mcq.irq_affinity_change = false; 902 napi_complete(napi); 903 mlx4_en_arm_cq(priv, cq); 904 return 0; 905 } 906 } else { 907 /* Done for now */ 908 cq->mcq.irq_affinity_change = false; 909 napi_complete(napi); 910 mlx4_en_arm_cq(priv, cq); 911 } 912 return done; 913 } 914 915 static const int frag_sizes[] = { 916 FRAG_SZ0, 917 FRAG_SZ1, 918 FRAG_SZ2, 919 FRAG_SZ3 920 }; 921 922 void mlx4_en_calc_rx_buf(struct net_device *dev) 923 { 924 struct mlx4_en_priv *priv = netdev_priv(dev); 925 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; 926 int buf_size = 0; 927 int i = 0; 928 929 while (buf_size < eff_mtu) { 930 priv->frag_info[i].frag_size = 931 (eff_mtu > buf_size + frag_sizes[i]) ? 932 frag_sizes[i] : eff_mtu - buf_size; 933 priv->frag_info[i].frag_prefix_size = buf_size; 934 if (!i) { 935 priv->frag_info[i].frag_align = NET_IP_ALIGN; 936 priv->frag_info[i].frag_stride = 937 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); 938 } else { 939 priv->frag_info[i].frag_align = 0; 940 priv->frag_info[i].frag_stride = 941 ALIGN(frag_sizes[i], SMP_CACHE_BYTES); 942 } 943 buf_size += priv->frag_info[i].frag_size; 944 i++; 945 } 946 947 priv->num_frags = i; 948 priv->rx_skb_size = eff_mtu; 949 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 950 951 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 952 eff_mtu, priv->num_frags); 953 for (i = 0; i < priv->num_frags; i++) { 954 en_err(priv, 955 " frag:%d - size:%d prefix:%d align:%d stride:%d\n", 956 i, 957 priv->frag_info[i].frag_size, 958 priv->frag_info[i].frag_prefix_size, 959 priv->frag_info[i].frag_align, 960 priv->frag_info[i].frag_stride); 961 } 962 } 963 964 /* RSS related functions */ 965 966 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 967 struct mlx4_en_rx_ring *ring, 968 enum mlx4_qp_state *state, 969 struct mlx4_qp *qp) 970 { 971 struct mlx4_en_dev *mdev = priv->mdev; 972 struct mlx4_qp_context *context; 973 int err = 0; 974 975 context = kmalloc(sizeof(*context), GFP_KERNEL); 976 if (!context) 977 return -ENOMEM; 978 979 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); 980 if (err) { 981 en_err(priv, "Failed to allocate qp #%x\n", qpn); 982 goto out; 983 } 984 qp->event = mlx4_en_sqp_event; 985 986 memset(context, 0, sizeof *context); 987 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 988 qpn, ring->cqn, -1, context); 989 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 990 991 /* Cancel FCS removal if FW allows */ 992 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 993 context->param3 |= cpu_to_be32(1 << 29); 994 ring->fcs_del = ETH_FCS_LEN; 995 } else 996 ring->fcs_del = 0; 997 998 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 999 if (err) { 1000 mlx4_qp_remove(mdev->dev, qp); 1001 mlx4_qp_free(mdev->dev, qp); 1002 } 1003 mlx4_en_update_rx_prod_db(ring); 1004 out: 1005 kfree(context); 1006 return err; 1007 } 1008 1009 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1010 { 1011 int err; 1012 u32 qpn; 1013 1014 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); 1015 if (err) { 1016 en_err(priv, "Failed reserving drop qpn\n"); 1017 return err; 1018 } 1019 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); 1020 if (err) { 1021 en_err(priv, "Failed allocating drop qp\n"); 1022 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1023 return err; 1024 } 1025 1026 return 0; 1027 } 1028 1029 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1030 { 1031 u32 qpn; 1032 1033 qpn = priv->drop_qp.qpn; 1034 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1035 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1036 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1037 } 1038 1039 /* Allocate rx qp's and configure them according to rss map */ 1040 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1041 { 1042 struct mlx4_en_dev *mdev = priv->mdev; 1043 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1044 struct mlx4_qp_context context; 1045 struct mlx4_rss_context *rss_context; 1046 int rss_rings; 1047 void *ptr; 1048 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1049 MLX4_RSS_TCP_IPV6); 1050 int i, qpn; 1051 int err = 0; 1052 int good_qps = 0; 1053 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, 1054 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, 1055 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; 1056 1057 en_dbg(DRV, priv, "Configuring rss steering\n"); 1058 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1059 priv->rx_ring_num, 1060 &rss_map->base_qpn); 1061 if (err) { 1062 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1063 return err; 1064 } 1065 1066 for (i = 0; i < priv->rx_ring_num; i++) { 1067 qpn = rss_map->base_qpn + i; 1068 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1069 &rss_map->state[i], 1070 &rss_map->qps[i]); 1071 if (err) 1072 goto rss_err; 1073 1074 ++good_qps; 1075 } 1076 1077 /* Configure RSS indirection qp */ 1078 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); 1079 if (err) { 1080 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1081 goto rss_err; 1082 } 1083 rss_map->indir_qp.event = mlx4_en_sqp_event; 1084 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1085 priv->rx_ring[0]->cqn, -1, &context); 1086 1087 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1088 rss_rings = priv->rx_ring_num; 1089 else 1090 rss_rings = priv->prof->rss_rings; 1091 1092 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1093 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1094 rss_context = ptr; 1095 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1096 (rss_map->base_qpn)); 1097 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1098 if (priv->mdev->profile.udp_rss) { 1099 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1100 rss_context->base_qpn_udp = rss_context->default_qpn; 1101 } 1102 1103 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1104 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1105 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1106 } 1107 1108 rss_context->flags = rss_mask; 1109 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1110 for (i = 0; i < 10; i++) 1111 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); 1112 1113 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1114 &rss_map->indir_qp, &rss_map->indir_state); 1115 if (err) 1116 goto indir_err; 1117 1118 return 0; 1119 1120 indir_err: 1121 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1122 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1123 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1124 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1125 rss_err: 1126 for (i = 0; i < good_qps; i++) { 1127 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1128 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1129 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1130 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1131 } 1132 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1133 return err; 1134 } 1135 1136 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1137 { 1138 struct mlx4_en_dev *mdev = priv->mdev; 1139 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1140 int i; 1141 1142 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1143 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1144 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1145 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1146 1147 for (i = 0; i < priv->rx_ring_num; i++) { 1148 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1149 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1150 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1151 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1152 } 1153 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1154 } 1155