1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/slab.h> 36 #include <linux/mlx4/qp.h> 37 #include <linux/skbuff.h> 38 #include <linux/if_ether.h> 39 #include <linux/if_vlan.h> 40 #include <linux/vmalloc.h> 41 42 #include "mlx4_en.h" 43 44 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 45 struct mlx4_en_rx_desc *rx_desc, 46 struct mlx4_en_rx_alloc *frags, 47 struct mlx4_en_rx_alloc *ring_alloc) 48 { 49 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 50 struct mlx4_en_frag_info *frag_info; 51 struct page *page; 52 dma_addr_t dma; 53 int i; 54 55 for (i = 0; i < priv->num_frags; i++) { 56 frag_info = &priv->frag_info[i]; 57 if (ring_alloc[i].offset == frag_info->last_offset) { 58 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 59 MLX4_EN_ALLOC_ORDER); 60 if (!page) 61 goto out; 62 dma = dma_map_page(priv->ddev, page, 0, 63 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 64 if (dma_mapping_error(priv->ddev, dma)) { 65 put_page(page); 66 goto out; 67 } 68 page_alloc[i].page = page; 69 page_alloc[i].dma = dma; 70 page_alloc[i].offset = frag_info->frag_align; 71 } else { 72 page_alloc[i].page = ring_alloc[i].page; 73 get_page(ring_alloc[i].page); 74 page_alloc[i].dma = ring_alloc[i].dma; 75 page_alloc[i].offset = ring_alloc[i].offset + 76 frag_info->frag_stride; 77 } 78 } 79 80 for (i = 0; i < priv->num_frags; i++) { 81 frags[i] = ring_alloc[i]; 82 dma = ring_alloc[i].dma + ring_alloc[i].offset; 83 ring_alloc[i] = page_alloc[i]; 84 rx_desc->data[i].addr = cpu_to_be64(dma); 85 } 86 87 return 0; 88 89 90 out: 91 while (i--) { 92 frag_info = &priv->frag_info[i]; 93 if (ring_alloc[i].offset == frag_info->last_offset) 94 dma_unmap_page(priv->ddev, page_alloc[i].dma, 95 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 96 put_page(page_alloc[i].page); 97 } 98 return -ENOMEM; 99 } 100 101 static void mlx4_en_free_frag(struct mlx4_en_priv *priv, 102 struct mlx4_en_rx_alloc *frags, 103 int i) 104 { 105 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 106 107 if (frags[i].offset == frag_info->last_offset) { 108 dma_unmap_page(priv->ddev, frags[i].dma, MLX4_EN_ALLOC_SIZE, 109 PCI_DMA_FROMDEVICE); 110 } 111 if (frags[i].page) 112 put_page(frags[i].page); 113 } 114 115 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, 116 struct mlx4_en_rx_ring *ring) 117 { 118 struct mlx4_en_rx_alloc *page_alloc; 119 int i; 120 121 for (i = 0; i < priv->num_frags; i++) { 122 page_alloc = &ring->page_alloc[i]; 123 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 124 MLX4_EN_ALLOC_ORDER); 125 if (!page_alloc->page) 126 goto out; 127 128 page_alloc->dma = dma_map_page(priv->ddev, page_alloc->page, 0, 129 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 130 if (dma_mapping_error(priv->ddev, page_alloc->dma)) { 131 put_page(page_alloc->page); 132 page_alloc->page = NULL; 133 goto out; 134 } 135 page_alloc->offset = priv->frag_info[i].frag_align; 136 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", 137 i, page_alloc->page); 138 } 139 return 0; 140 141 out: 142 while (i--) { 143 page_alloc = &ring->page_alloc[i]; 144 dma_unmap_page(priv->ddev, page_alloc->dma, 145 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 146 put_page(page_alloc->page); 147 page_alloc->page = NULL; 148 } 149 return -ENOMEM; 150 } 151 152 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, 153 struct mlx4_en_rx_ring *ring) 154 { 155 struct mlx4_en_rx_alloc *page_alloc; 156 int i; 157 158 for (i = 0; i < priv->num_frags; i++) { 159 page_alloc = &ring->page_alloc[i]; 160 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", 161 i, page_count(page_alloc->page)); 162 163 dma_unmap_page(priv->ddev, page_alloc->dma, 164 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 165 put_page(page_alloc->page); 166 page_alloc->page = NULL; 167 } 168 } 169 170 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, 171 struct mlx4_en_rx_ring *ring, int index) 172 { 173 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 174 int possible_frags; 175 int i; 176 177 /* Set size and memtype fields */ 178 for (i = 0; i < priv->num_frags; i++) { 179 rx_desc->data[i].byte_count = 180 cpu_to_be32(priv->frag_info[i].frag_size); 181 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 182 } 183 184 /* If the number of used fragments does not fill up the ring stride, 185 * remaining (unused) fragments must be padded with null address/size 186 * and a special memory key */ 187 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 188 for (i = priv->num_frags; i < possible_frags; i++) { 189 rx_desc->data[i].byte_count = 0; 190 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 191 rx_desc->data[i].addr = 0; 192 } 193 } 194 195 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 196 struct mlx4_en_rx_ring *ring, int index) 197 { 198 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 199 struct mlx4_en_rx_alloc *frags = ring->rx_info + 200 (index << priv->log_rx_info); 201 202 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc); 203 } 204 205 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 206 { 207 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 208 } 209 210 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, 211 struct mlx4_en_rx_ring *ring, 212 int index) 213 { 214 struct mlx4_en_rx_alloc *frags; 215 int nr; 216 217 frags = ring->rx_info + (index << priv->log_rx_info); 218 for (nr = 0; nr < priv->num_frags; nr++) { 219 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 220 mlx4_en_free_frag(priv, frags, nr); 221 } 222 } 223 224 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 225 { 226 struct mlx4_en_rx_ring *ring; 227 int ring_ind; 228 int buf_ind; 229 int new_size; 230 231 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 232 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 233 ring = &priv->rx_ring[ring_ind]; 234 235 if (mlx4_en_prepare_rx_desc(priv, ring, 236 ring->actual_size)) { 237 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 238 en_err(priv, "Failed to allocate " 239 "enough rx buffers\n"); 240 return -ENOMEM; 241 } else { 242 new_size = rounddown_pow_of_two(ring->actual_size); 243 en_warn(priv, "Only %d buffers allocated " 244 "reducing ring size to %d", 245 ring->actual_size, new_size); 246 goto reduce_rings; 247 } 248 } 249 ring->actual_size++; 250 ring->prod++; 251 } 252 } 253 return 0; 254 255 reduce_rings: 256 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 257 ring = &priv->rx_ring[ring_ind]; 258 while (ring->actual_size > new_size) { 259 ring->actual_size--; 260 ring->prod--; 261 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 262 } 263 } 264 265 return 0; 266 } 267 268 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 269 struct mlx4_en_rx_ring *ring) 270 { 271 int index; 272 273 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 274 ring->cons, ring->prod); 275 276 /* Unmap and free Rx buffers */ 277 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); 278 while (ring->cons != ring->prod) { 279 index = ring->cons & ring->size_mask; 280 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 281 mlx4_en_free_rx_desc(priv, ring, index); 282 ++ring->cons; 283 } 284 } 285 286 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 287 struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 288 { 289 struct mlx4_en_dev *mdev = priv->mdev; 290 int err = -ENOMEM; 291 int tmp; 292 293 ring->prod = 0; 294 ring->cons = 0; 295 ring->size = size; 296 ring->size_mask = size - 1; 297 ring->stride = stride; 298 ring->log_stride = ffs(ring->stride) - 1; 299 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 300 301 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 302 sizeof(struct mlx4_en_rx_alloc)); 303 ring->rx_info = vmalloc(tmp); 304 if (!ring->rx_info) 305 return -ENOMEM; 306 307 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 308 ring->rx_info, tmp); 309 310 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 311 ring->buf_size, 2 * PAGE_SIZE); 312 if (err) 313 goto err_ring; 314 315 err = mlx4_en_map_buffer(&ring->wqres.buf); 316 if (err) { 317 en_err(priv, "Failed to map RX buffer\n"); 318 goto err_hwq; 319 } 320 ring->buf = ring->wqres.buf.direct.buf; 321 322 return 0; 323 324 err_hwq: 325 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 326 err_ring: 327 vfree(ring->rx_info); 328 ring->rx_info = NULL; 329 return err; 330 } 331 332 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 333 { 334 struct mlx4_en_rx_ring *ring; 335 int i; 336 int ring_ind; 337 int err; 338 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 339 DS_SIZE * priv->num_frags); 340 341 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 342 ring = &priv->rx_ring[ring_ind]; 343 344 ring->prod = 0; 345 ring->cons = 0; 346 ring->actual_size = 0; 347 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; 348 349 ring->stride = stride; 350 if (ring->stride <= TXBB_SIZE) 351 ring->buf += TXBB_SIZE; 352 353 ring->log_stride = ffs(ring->stride) - 1; 354 ring->buf_size = ring->size * ring->stride; 355 356 memset(ring->buf, 0, ring->buf_size); 357 mlx4_en_update_rx_prod_db(ring); 358 359 /* Initialize all descriptors */ 360 for (i = 0; i < ring->size; i++) 361 mlx4_en_init_rx_desc(priv, ring, i); 362 363 /* Initialize page allocators */ 364 err = mlx4_en_init_allocator(priv, ring); 365 if (err) { 366 en_err(priv, "Failed initializing ring allocator\n"); 367 if (ring->stride <= TXBB_SIZE) 368 ring->buf -= TXBB_SIZE; 369 ring_ind--; 370 goto err_allocator; 371 } 372 } 373 err = mlx4_en_fill_rx_buffers(priv); 374 if (err) 375 goto err_buffers; 376 377 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 378 ring = &priv->rx_ring[ring_ind]; 379 380 ring->size_mask = ring->actual_size - 1; 381 mlx4_en_update_rx_prod_db(ring); 382 } 383 384 return 0; 385 386 err_buffers: 387 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 388 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); 389 390 ring_ind = priv->rx_ring_num - 1; 391 err_allocator: 392 while (ring_ind >= 0) { 393 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) 394 priv->rx_ring[ring_ind].buf -= TXBB_SIZE; 395 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); 396 ring_ind--; 397 } 398 return err; 399 } 400 401 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 402 struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 403 { 404 struct mlx4_en_dev *mdev = priv->mdev; 405 406 mlx4_en_unmap_buffer(&ring->wqres.buf); 407 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 408 vfree(ring->rx_info); 409 ring->rx_info = NULL; 410 #ifdef CONFIG_RFS_ACCEL 411 mlx4_en_cleanup_filters(priv, ring); 412 #endif 413 } 414 415 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 416 struct mlx4_en_rx_ring *ring) 417 { 418 mlx4_en_free_rx_buf(priv, ring); 419 if (ring->stride <= TXBB_SIZE) 420 ring->buf -= TXBB_SIZE; 421 mlx4_en_destroy_allocator(priv, ring); 422 } 423 424 425 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 426 struct mlx4_en_rx_desc *rx_desc, 427 struct mlx4_en_rx_alloc *frags, 428 struct sk_buff *skb, 429 int length) 430 { 431 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; 432 struct mlx4_en_frag_info *frag_info; 433 int nr; 434 dma_addr_t dma; 435 436 /* Collect used fragments while replacing them in the HW descriptors */ 437 for (nr = 0; nr < priv->num_frags; nr++) { 438 frag_info = &priv->frag_info[nr]; 439 if (length <= frag_info->frag_prefix_size) 440 break; 441 if (!frags[nr].page) 442 goto fail; 443 444 dma = be64_to_cpu(rx_desc->data[nr].addr); 445 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, 446 DMA_FROM_DEVICE); 447 448 /* Save page reference in skb */ 449 get_page(frags[nr].page); 450 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); 451 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); 452 skb_frags_rx[nr].page_offset = frags[nr].offset; 453 skb->truesize += frag_info->frag_stride; 454 } 455 /* Adjust size of last fragment to match actual length */ 456 if (nr > 0) 457 skb_frag_size_set(&skb_frags_rx[nr - 1], 458 length - priv->frag_info[nr - 1].frag_prefix_size); 459 return nr; 460 461 fail: 462 while (nr > 0) { 463 nr--; 464 __skb_frag_unref(&skb_frags_rx[nr]); 465 } 466 return 0; 467 } 468 469 470 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, 471 struct mlx4_en_rx_desc *rx_desc, 472 struct mlx4_en_rx_alloc *frags, 473 unsigned int length) 474 { 475 struct sk_buff *skb; 476 void *va; 477 int used_frags; 478 dma_addr_t dma; 479 480 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); 481 if (!skb) { 482 en_dbg(RX_ERR, priv, "Failed allocating skb\n"); 483 return NULL; 484 } 485 skb_reserve(skb, NET_IP_ALIGN); 486 skb->len = length; 487 488 /* Get pointer to first fragment so we could copy the headers into the 489 * (linear part of the) skb */ 490 va = page_address(frags[0].page) + frags[0].offset; 491 492 if (length <= SMALL_PACKET_SIZE) { 493 /* We are copying all relevant data to the skb - temporarily 494 * sync buffers for the copy */ 495 dma = be64_to_cpu(rx_desc->data[0].addr); 496 dma_sync_single_for_cpu(priv->ddev, dma, length, 497 DMA_FROM_DEVICE); 498 skb_copy_to_linear_data(skb, va, length); 499 skb->tail += length; 500 } else { 501 /* Move relevant fragments to skb */ 502 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, 503 skb, length); 504 if (unlikely(!used_frags)) { 505 kfree_skb(skb); 506 return NULL; 507 } 508 skb_shinfo(skb)->nr_frags = used_frags; 509 510 /* Copy headers into the skb linear buffer */ 511 memcpy(skb->data, va, HEADER_COPY_SIZE); 512 skb->tail += HEADER_COPY_SIZE; 513 514 /* Skip headers in first fragment */ 515 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; 516 517 /* Adjust size of first fragment */ 518 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); 519 skb->data_len = length - HEADER_COPY_SIZE; 520 } 521 return skb; 522 } 523 524 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) 525 { 526 int i; 527 int offset = ETH_HLEN; 528 529 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { 530 if (*(skb->data + offset) != (unsigned char) (i & 0xff)) 531 goto out_loopback; 532 } 533 /* Loopback found */ 534 priv->loopback_ok = 1; 535 536 out_loopback: 537 dev_kfree_skb_any(skb); 538 } 539 540 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 541 struct mlx4_en_rx_ring *ring) 542 { 543 int index = ring->prod & ring->size_mask; 544 545 while ((u32) (ring->prod - ring->cons) < ring->actual_size) { 546 if (mlx4_en_prepare_rx_desc(priv, ring, index)) 547 break; 548 ring->prod++; 549 index = ring->prod & ring->size_mask; 550 } 551 } 552 553 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 554 { 555 struct mlx4_en_priv *priv = netdev_priv(dev); 556 struct mlx4_cqe *cqe; 557 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; 558 struct mlx4_en_rx_alloc *frags; 559 struct mlx4_en_rx_desc *rx_desc; 560 struct sk_buff *skb; 561 int index; 562 int nr; 563 unsigned int length; 564 int polled = 0; 565 int ip_summed; 566 struct ethhdr *ethh; 567 dma_addr_t dma; 568 u64 s_mac; 569 int factor = priv->cqe_factor; 570 571 if (!priv->port_up) 572 return 0; 573 574 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 575 * descriptor offset can be deduced from the CQE index instead of 576 * reading 'cqe->index' */ 577 index = cq->mcq.cons_index & ring->size_mask; 578 cqe = &cq->buf[(index << factor) + factor]; 579 580 /* Process all completed CQEs */ 581 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 582 cq->mcq.cons_index & cq->size)) { 583 584 frags = ring->rx_info + (index << priv->log_rx_info); 585 rx_desc = ring->buf + (index << ring->log_stride); 586 587 /* 588 * make sure we read the CQE after we read the ownership bit 589 */ 590 rmb(); 591 592 /* Drop packet on bad receive or bad checksum */ 593 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 594 MLX4_CQE_OPCODE_ERROR)) { 595 en_err(priv, "CQE completed in error - vendor " 596 "syndrom:%d syndrom:%d\n", 597 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, 598 ((struct mlx4_err_cqe *) cqe)->syndrome); 599 goto next; 600 } 601 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 602 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 603 goto next; 604 } 605 606 /* Get pointer to first fragment since we haven't skb yet and 607 * cast it to ethhdr struct */ 608 dma = be64_to_cpu(rx_desc->data[0].addr); 609 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 610 DMA_FROM_DEVICE); 611 ethh = (struct ethhdr *)(page_address(frags[0].page) + 612 frags[0].offset); 613 s_mac = mlx4_en_mac_to_u64(ethh->h_source); 614 615 /* If source MAC is equal to our own MAC and not performing 616 * the selftest or flb disabled - drop the packet */ 617 if (s_mac == priv->mac && 618 !((dev->features & NETIF_F_LOOPBACK) || 619 priv->validate_loopback)) 620 goto next; 621 622 /* 623 * Packet is OK - process it. 624 */ 625 length = be32_to_cpu(cqe->byte_cnt); 626 length -= ring->fcs_del; 627 ring->bytes += length; 628 ring->packets++; 629 630 if (likely(dev->features & NETIF_F_RXCSUM)) { 631 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 632 (cqe->checksum == cpu_to_be16(0xffff))) { 633 ring->csum_ok++; 634 /* This packet is eligible for GRO if it is: 635 * - DIX Ethernet (type interpretation) 636 * - TCP/IP (v4) 637 * - without IP options 638 * - not an IP fragment */ 639 if (dev->features & NETIF_F_GRO) { 640 struct sk_buff *gro_skb = napi_get_frags(&cq->napi); 641 if (!gro_skb) 642 goto next; 643 644 nr = mlx4_en_complete_rx_desc(priv, 645 rx_desc, frags, gro_skb, 646 length); 647 if (!nr) 648 goto next; 649 650 skb_shinfo(gro_skb)->nr_frags = nr; 651 gro_skb->len = length; 652 gro_skb->data_len = length; 653 gro_skb->ip_summed = CHECKSUM_UNNECESSARY; 654 655 if (cqe->vlan_my_qpn & 656 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) { 657 u16 vid = be16_to_cpu(cqe->sl_vid); 658 659 __vlan_hwaccel_put_tag(gro_skb, vid); 660 } 661 662 if (dev->features & NETIF_F_RXHASH) 663 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); 664 665 skb_record_rx_queue(gro_skb, cq->ring); 666 napi_gro_frags(&cq->napi); 667 668 goto next; 669 } 670 671 /* GRO not possible, complete processing here */ 672 ip_summed = CHECKSUM_UNNECESSARY; 673 } else { 674 ip_summed = CHECKSUM_NONE; 675 ring->csum_none++; 676 } 677 } else { 678 ip_summed = CHECKSUM_NONE; 679 ring->csum_none++; 680 } 681 682 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); 683 if (!skb) { 684 priv->stats.rx_dropped++; 685 goto next; 686 } 687 688 if (unlikely(priv->validate_loopback)) { 689 validate_loopback(priv, skb); 690 goto next; 691 } 692 693 skb->ip_summed = ip_summed; 694 skb->protocol = eth_type_trans(skb, dev); 695 skb_record_rx_queue(skb, cq->ring); 696 697 if (dev->features & NETIF_F_RXHASH) 698 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); 699 700 if (be32_to_cpu(cqe->vlan_my_qpn) & 701 MLX4_CQE_VLAN_PRESENT_MASK) 702 __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid)); 703 704 /* Push it up the stack */ 705 netif_receive_skb(skb); 706 707 next: 708 for (nr = 0; nr < priv->num_frags; nr++) 709 mlx4_en_free_frag(priv, frags, nr); 710 711 ++cq->mcq.cons_index; 712 index = (cq->mcq.cons_index) & ring->size_mask; 713 cqe = &cq->buf[(index << factor) + factor]; 714 if (++polled == budget) 715 goto out; 716 } 717 718 out: 719 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 720 mlx4_cq_set_ci(&cq->mcq); 721 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 722 ring->cons = cq->mcq.cons_index; 723 mlx4_en_refill_rx_buffers(priv, ring); 724 mlx4_en_update_rx_prod_db(ring); 725 return polled; 726 } 727 728 729 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 730 { 731 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 732 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 733 734 if (priv->port_up) 735 napi_schedule(&cq->napi); 736 else 737 mlx4_en_arm_cq(priv, cq); 738 } 739 740 /* Rx CQ polling - called by NAPI */ 741 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 742 { 743 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 744 struct net_device *dev = cq->dev; 745 struct mlx4_en_priv *priv = netdev_priv(dev); 746 int done; 747 748 done = mlx4_en_process_rx_cq(dev, cq, budget); 749 750 /* If we used up all the quota - we're probably not done yet... */ 751 if (done == budget) 752 INC_PERF_COUNTER(priv->pstats.napi_quota); 753 else { 754 /* Done for now */ 755 napi_complete(napi); 756 mlx4_en_arm_cq(priv, cq); 757 } 758 return done; 759 } 760 761 762 /* Calculate the last offset position that accommodates a full fragment 763 * (assuming fagment size = stride-align) */ 764 static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) 765 { 766 u16 res = MLX4_EN_ALLOC_SIZE % stride; 767 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; 768 769 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " 770 "res:%d offset:%d\n", stride, align, res, offset); 771 return offset; 772 } 773 774 775 static int frag_sizes[] = { 776 FRAG_SZ0, 777 FRAG_SZ1, 778 FRAG_SZ2, 779 FRAG_SZ3 780 }; 781 782 void mlx4_en_calc_rx_buf(struct net_device *dev) 783 { 784 struct mlx4_en_priv *priv = netdev_priv(dev); 785 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; 786 int buf_size = 0; 787 int i = 0; 788 789 while (buf_size < eff_mtu) { 790 priv->frag_info[i].frag_size = 791 (eff_mtu > buf_size + frag_sizes[i]) ? 792 frag_sizes[i] : eff_mtu - buf_size; 793 priv->frag_info[i].frag_prefix_size = buf_size; 794 if (!i) { 795 priv->frag_info[i].frag_align = NET_IP_ALIGN; 796 priv->frag_info[i].frag_stride = 797 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); 798 } else { 799 priv->frag_info[i].frag_align = 0; 800 priv->frag_info[i].frag_stride = 801 ALIGN(frag_sizes[i], SMP_CACHE_BYTES); 802 } 803 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( 804 priv, priv->frag_info[i].frag_stride, 805 priv->frag_info[i].frag_align); 806 buf_size += priv->frag_info[i].frag_size; 807 i++; 808 } 809 810 priv->num_frags = i; 811 priv->rx_skb_size = eff_mtu; 812 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 813 814 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " 815 "num_frags:%d):\n", eff_mtu, priv->num_frags); 816 for (i = 0; i < priv->num_frags; i++) { 817 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " 818 "stride:%d last_offset:%d\n", i, 819 priv->frag_info[i].frag_size, 820 priv->frag_info[i].frag_prefix_size, 821 priv->frag_info[i].frag_align, 822 priv->frag_info[i].frag_stride, 823 priv->frag_info[i].last_offset); 824 } 825 } 826 827 /* RSS related functions */ 828 829 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 830 struct mlx4_en_rx_ring *ring, 831 enum mlx4_qp_state *state, 832 struct mlx4_qp *qp) 833 { 834 struct mlx4_en_dev *mdev = priv->mdev; 835 struct mlx4_qp_context *context; 836 int err = 0; 837 838 context = kmalloc(sizeof *context , GFP_KERNEL); 839 if (!context) { 840 en_err(priv, "Failed to allocate qp context\n"); 841 return -ENOMEM; 842 } 843 844 err = mlx4_qp_alloc(mdev->dev, qpn, qp); 845 if (err) { 846 en_err(priv, "Failed to allocate qp #%x\n", qpn); 847 goto out; 848 } 849 qp->event = mlx4_en_sqp_event; 850 851 memset(context, 0, sizeof *context); 852 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 853 qpn, ring->cqn, -1, context); 854 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 855 856 /* Cancel FCS removal if FW allows */ 857 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 858 context->param3 |= cpu_to_be32(1 << 29); 859 ring->fcs_del = ETH_FCS_LEN; 860 } else 861 ring->fcs_del = 0; 862 863 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 864 if (err) { 865 mlx4_qp_remove(mdev->dev, qp); 866 mlx4_qp_free(mdev->dev, qp); 867 } 868 mlx4_en_update_rx_prod_db(ring); 869 out: 870 kfree(context); 871 return err; 872 } 873 874 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 875 { 876 int err; 877 u32 qpn; 878 879 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); 880 if (err) { 881 en_err(priv, "Failed reserving drop qpn\n"); 882 return err; 883 } 884 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); 885 if (err) { 886 en_err(priv, "Failed allocating drop qp\n"); 887 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 888 return err; 889 } 890 891 return 0; 892 } 893 894 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 895 { 896 u32 qpn; 897 898 qpn = priv->drop_qp.qpn; 899 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 900 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 901 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 902 } 903 904 /* Allocate rx qp's and configure them according to rss map */ 905 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 906 { 907 struct mlx4_en_dev *mdev = priv->mdev; 908 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 909 struct mlx4_qp_context context; 910 struct mlx4_rss_context *rss_context; 911 int rss_rings; 912 void *ptr; 913 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 914 MLX4_RSS_TCP_IPV6); 915 int i, qpn; 916 int err = 0; 917 int good_qps = 0; 918 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, 919 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, 920 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; 921 922 en_dbg(DRV, priv, "Configuring rss steering\n"); 923 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 924 priv->rx_ring_num, 925 &rss_map->base_qpn); 926 if (err) { 927 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 928 return err; 929 } 930 931 for (i = 0; i < priv->rx_ring_num; i++) { 932 qpn = rss_map->base_qpn + i; 933 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], 934 &rss_map->state[i], 935 &rss_map->qps[i]); 936 if (err) 937 goto rss_err; 938 939 ++good_qps; 940 } 941 942 /* Configure RSS indirection qp */ 943 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); 944 if (err) { 945 en_err(priv, "Failed to allocate RSS indirection QP\n"); 946 goto rss_err; 947 } 948 rss_map->indir_qp.event = mlx4_en_sqp_event; 949 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 950 priv->rx_ring[0].cqn, -1, &context); 951 952 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 953 rss_rings = priv->rx_ring_num; 954 else 955 rss_rings = priv->prof->rss_rings; 956 957 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 958 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 959 rss_context = ptr; 960 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 961 (rss_map->base_qpn)); 962 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 963 if (priv->mdev->profile.udp_rss) { 964 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 965 rss_context->base_qpn_udp = rss_context->default_qpn; 966 } 967 rss_context->flags = rss_mask; 968 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 969 for (i = 0; i < 10; i++) 970 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); 971 972 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 973 &rss_map->indir_qp, &rss_map->indir_state); 974 if (err) 975 goto indir_err; 976 977 return 0; 978 979 indir_err: 980 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 981 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 982 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 983 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 984 rss_err: 985 for (i = 0; i < good_qps; i++) { 986 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 987 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 988 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 989 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 990 } 991 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 992 return err; 993 } 994 995 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 996 { 997 struct mlx4_en_dev *mdev = priv->mdev; 998 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 999 int i; 1000 1001 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1002 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1003 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1004 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1005 1006 for (i = 0; i < priv->rx_ring_num; i++) { 1007 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1008 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1009 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1010 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1011 } 1012 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1013 } 1014