1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/slab.h> 36 #include <linux/mlx4/qp.h> 37 #include <linux/skbuff.h> 38 #include <linux/rculist.h> 39 #include <linux/if_ether.h> 40 #include <linux/if_vlan.h> 41 #include <linux/vmalloc.h> 42 43 #include "mlx4_en.h" 44 45 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 46 struct mlx4_en_rx_desc *rx_desc, 47 struct mlx4_en_rx_alloc *frags, 48 struct mlx4_en_rx_alloc *ring_alloc) 49 { 50 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 51 struct mlx4_en_frag_info *frag_info; 52 struct page *page; 53 dma_addr_t dma; 54 int i; 55 56 for (i = 0; i < priv->num_frags; i++) { 57 frag_info = &priv->frag_info[i]; 58 if (ring_alloc[i].offset == frag_info->last_offset) { 59 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 60 MLX4_EN_ALLOC_ORDER); 61 if (!page) 62 goto out; 63 dma = dma_map_page(priv->ddev, page, 0, 64 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 65 if (dma_mapping_error(priv->ddev, dma)) { 66 put_page(page); 67 goto out; 68 } 69 page_alloc[i].page = page; 70 page_alloc[i].dma = dma; 71 page_alloc[i].offset = frag_info->frag_align; 72 } else { 73 page_alloc[i].page = ring_alloc[i].page; 74 get_page(ring_alloc[i].page); 75 page_alloc[i].dma = ring_alloc[i].dma; 76 page_alloc[i].offset = ring_alloc[i].offset + 77 frag_info->frag_stride; 78 } 79 } 80 81 for (i = 0; i < priv->num_frags; i++) { 82 frags[i] = ring_alloc[i]; 83 dma = ring_alloc[i].dma + ring_alloc[i].offset; 84 ring_alloc[i] = page_alloc[i]; 85 rx_desc->data[i].addr = cpu_to_be64(dma); 86 } 87 88 return 0; 89 90 91 out: 92 while (i--) { 93 frag_info = &priv->frag_info[i]; 94 if (ring_alloc[i].offset == frag_info->last_offset) 95 dma_unmap_page(priv->ddev, page_alloc[i].dma, 96 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 97 put_page(page_alloc[i].page); 98 } 99 return -ENOMEM; 100 } 101 102 static void mlx4_en_free_frag(struct mlx4_en_priv *priv, 103 struct mlx4_en_rx_alloc *frags, 104 int i) 105 { 106 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 107 108 if (frags[i].offset == frag_info->last_offset) { 109 dma_unmap_page(priv->ddev, frags[i].dma, MLX4_EN_ALLOC_SIZE, 110 PCI_DMA_FROMDEVICE); 111 } 112 if (frags[i].page) 113 put_page(frags[i].page); 114 } 115 116 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, 117 struct mlx4_en_rx_ring *ring) 118 { 119 struct mlx4_en_rx_alloc *page_alloc; 120 int i; 121 122 for (i = 0; i < priv->num_frags; i++) { 123 page_alloc = &ring->page_alloc[i]; 124 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 125 MLX4_EN_ALLOC_ORDER); 126 if (!page_alloc->page) 127 goto out; 128 129 page_alloc->dma = dma_map_page(priv->ddev, page_alloc->page, 0, 130 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 131 if (dma_mapping_error(priv->ddev, page_alloc->dma)) { 132 put_page(page_alloc->page); 133 page_alloc->page = NULL; 134 goto out; 135 } 136 page_alloc->offset = priv->frag_info[i].frag_align; 137 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", 138 i, page_alloc->page); 139 } 140 return 0; 141 142 out: 143 while (i--) { 144 page_alloc = &ring->page_alloc[i]; 145 dma_unmap_page(priv->ddev, page_alloc->dma, 146 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 147 put_page(page_alloc->page); 148 page_alloc->page = NULL; 149 } 150 return -ENOMEM; 151 } 152 153 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, 154 struct mlx4_en_rx_ring *ring) 155 { 156 struct mlx4_en_rx_alloc *page_alloc; 157 int i; 158 159 for (i = 0; i < priv->num_frags; i++) { 160 page_alloc = &ring->page_alloc[i]; 161 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", 162 i, page_count(page_alloc->page)); 163 164 dma_unmap_page(priv->ddev, page_alloc->dma, 165 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 166 put_page(page_alloc->page); 167 page_alloc->page = NULL; 168 } 169 } 170 171 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, 172 struct mlx4_en_rx_ring *ring, int index) 173 { 174 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 175 int possible_frags; 176 int i; 177 178 /* Set size and memtype fields */ 179 for (i = 0; i < priv->num_frags; i++) { 180 rx_desc->data[i].byte_count = 181 cpu_to_be32(priv->frag_info[i].frag_size); 182 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 183 } 184 185 /* If the number of used fragments does not fill up the ring stride, 186 * remaining (unused) fragments must be padded with null address/size 187 * and a special memory key */ 188 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 189 for (i = priv->num_frags; i < possible_frags; i++) { 190 rx_desc->data[i].byte_count = 0; 191 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 192 rx_desc->data[i].addr = 0; 193 } 194 } 195 196 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 197 struct mlx4_en_rx_ring *ring, int index) 198 { 199 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 200 struct mlx4_en_rx_alloc *frags = ring->rx_info + 201 (index << priv->log_rx_info); 202 203 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc); 204 } 205 206 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 207 { 208 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 209 } 210 211 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, 212 struct mlx4_en_rx_ring *ring, 213 int index) 214 { 215 struct mlx4_en_rx_alloc *frags; 216 int nr; 217 218 frags = ring->rx_info + (index << priv->log_rx_info); 219 for (nr = 0; nr < priv->num_frags; nr++) { 220 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 221 mlx4_en_free_frag(priv, frags, nr); 222 } 223 } 224 225 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 226 { 227 struct mlx4_en_rx_ring *ring; 228 int ring_ind; 229 int buf_ind; 230 int new_size; 231 232 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 233 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 234 ring = &priv->rx_ring[ring_ind]; 235 236 if (mlx4_en_prepare_rx_desc(priv, ring, 237 ring->actual_size)) { 238 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 239 en_err(priv, "Failed to allocate " 240 "enough rx buffers\n"); 241 return -ENOMEM; 242 } else { 243 new_size = rounddown_pow_of_two(ring->actual_size); 244 en_warn(priv, "Only %d buffers allocated " 245 "reducing ring size to %d", 246 ring->actual_size, new_size); 247 goto reduce_rings; 248 } 249 } 250 ring->actual_size++; 251 ring->prod++; 252 } 253 } 254 return 0; 255 256 reduce_rings: 257 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 258 ring = &priv->rx_ring[ring_ind]; 259 while (ring->actual_size > new_size) { 260 ring->actual_size--; 261 ring->prod--; 262 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 263 } 264 } 265 266 return 0; 267 } 268 269 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 270 struct mlx4_en_rx_ring *ring) 271 { 272 int index; 273 274 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 275 ring->cons, ring->prod); 276 277 /* Unmap and free Rx buffers */ 278 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); 279 while (ring->cons != ring->prod) { 280 index = ring->cons & ring->size_mask; 281 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 282 mlx4_en_free_rx_desc(priv, ring, index); 283 ++ring->cons; 284 } 285 } 286 287 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 288 struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 289 { 290 struct mlx4_en_dev *mdev = priv->mdev; 291 int err = -ENOMEM; 292 int tmp; 293 294 ring->prod = 0; 295 ring->cons = 0; 296 ring->size = size; 297 ring->size_mask = size - 1; 298 ring->stride = stride; 299 ring->log_stride = ffs(ring->stride) - 1; 300 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 301 302 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 303 sizeof(struct mlx4_en_rx_alloc)); 304 ring->rx_info = vmalloc(tmp); 305 if (!ring->rx_info) 306 return -ENOMEM; 307 308 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 309 ring->rx_info, tmp); 310 311 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 312 ring->buf_size, 2 * PAGE_SIZE); 313 if (err) 314 goto err_ring; 315 316 err = mlx4_en_map_buffer(&ring->wqres.buf); 317 if (err) { 318 en_err(priv, "Failed to map RX buffer\n"); 319 goto err_hwq; 320 } 321 ring->buf = ring->wqres.buf.direct.buf; 322 323 return 0; 324 325 err_hwq: 326 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 327 err_ring: 328 vfree(ring->rx_info); 329 ring->rx_info = NULL; 330 return err; 331 } 332 333 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 334 { 335 struct mlx4_en_rx_ring *ring; 336 int i; 337 int ring_ind; 338 int err; 339 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 340 DS_SIZE * priv->num_frags); 341 342 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 343 ring = &priv->rx_ring[ring_ind]; 344 345 ring->prod = 0; 346 ring->cons = 0; 347 ring->actual_size = 0; 348 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; 349 350 ring->stride = stride; 351 if (ring->stride <= TXBB_SIZE) 352 ring->buf += TXBB_SIZE; 353 354 ring->log_stride = ffs(ring->stride) - 1; 355 ring->buf_size = ring->size * ring->stride; 356 357 memset(ring->buf, 0, ring->buf_size); 358 mlx4_en_update_rx_prod_db(ring); 359 360 /* Initialize all descriptors */ 361 for (i = 0; i < ring->size; i++) 362 mlx4_en_init_rx_desc(priv, ring, i); 363 364 /* Initialize page allocators */ 365 err = mlx4_en_init_allocator(priv, ring); 366 if (err) { 367 en_err(priv, "Failed initializing ring allocator\n"); 368 if (ring->stride <= TXBB_SIZE) 369 ring->buf -= TXBB_SIZE; 370 ring_ind--; 371 goto err_allocator; 372 } 373 } 374 err = mlx4_en_fill_rx_buffers(priv); 375 if (err) 376 goto err_buffers; 377 378 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 379 ring = &priv->rx_ring[ring_ind]; 380 381 ring->size_mask = ring->actual_size - 1; 382 mlx4_en_update_rx_prod_db(ring); 383 } 384 385 return 0; 386 387 err_buffers: 388 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 389 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); 390 391 ring_ind = priv->rx_ring_num - 1; 392 err_allocator: 393 while (ring_ind >= 0) { 394 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) 395 priv->rx_ring[ring_ind].buf -= TXBB_SIZE; 396 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); 397 ring_ind--; 398 } 399 return err; 400 } 401 402 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 403 struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 404 { 405 struct mlx4_en_dev *mdev = priv->mdev; 406 407 mlx4_en_unmap_buffer(&ring->wqres.buf); 408 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 409 vfree(ring->rx_info); 410 ring->rx_info = NULL; 411 #ifdef CONFIG_RFS_ACCEL 412 mlx4_en_cleanup_filters(priv, ring); 413 #endif 414 } 415 416 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 417 struct mlx4_en_rx_ring *ring) 418 { 419 mlx4_en_free_rx_buf(priv, ring); 420 if (ring->stride <= TXBB_SIZE) 421 ring->buf -= TXBB_SIZE; 422 mlx4_en_destroy_allocator(priv, ring); 423 } 424 425 426 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 427 struct mlx4_en_rx_desc *rx_desc, 428 struct mlx4_en_rx_alloc *frags, 429 struct sk_buff *skb, 430 int length) 431 { 432 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; 433 struct mlx4_en_frag_info *frag_info; 434 int nr; 435 dma_addr_t dma; 436 437 /* Collect used fragments while replacing them in the HW descriptors */ 438 for (nr = 0; nr < priv->num_frags; nr++) { 439 frag_info = &priv->frag_info[nr]; 440 if (length <= frag_info->frag_prefix_size) 441 break; 442 if (!frags[nr].page) 443 goto fail; 444 445 dma = be64_to_cpu(rx_desc->data[nr].addr); 446 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, 447 DMA_FROM_DEVICE); 448 449 /* Save page reference in skb */ 450 get_page(frags[nr].page); 451 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); 452 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); 453 skb_frags_rx[nr].page_offset = frags[nr].offset; 454 skb->truesize += frag_info->frag_stride; 455 } 456 /* Adjust size of last fragment to match actual length */ 457 if (nr > 0) 458 skb_frag_size_set(&skb_frags_rx[nr - 1], 459 length - priv->frag_info[nr - 1].frag_prefix_size); 460 return nr; 461 462 fail: 463 while (nr > 0) { 464 nr--; 465 __skb_frag_unref(&skb_frags_rx[nr]); 466 } 467 return 0; 468 } 469 470 471 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, 472 struct mlx4_en_rx_desc *rx_desc, 473 struct mlx4_en_rx_alloc *frags, 474 unsigned int length) 475 { 476 struct sk_buff *skb; 477 void *va; 478 int used_frags; 479 dma_addr_t dma; 480 481 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); 482 if (!skb) { 483 en_dbg(RX_ERR, priv, "Failed allocating skb\n"); 484 return NULL; 485 } 486 skb_reserve(skb, NET_IP_ALIGN); 487 skb->len = length; 488 489 /* Get pointer to first fragment so we could copy the headers into the 490 * (linear part of the) skb */ 491 va = page_address(frags[0].page) + frags[0].offset; 492 493 if (length <= SMALL_PACKET_SIZE) { 494 /* We are copying all relevant data to the skb - temporarily 495 * sync buffers for the copy */ 496 dma = be64_to_cpu(rx_desc->data[0].addr); 497 dma_sync_single_for_cpu(priv->ddev, dma, length, 498 DMA_FROM_DEVICE); 499 skb_copy_to_linear_data(skb, va, length); 500 skb->tail += length; 501 } else { 502 /* Move relevant fragments to skb */ 503 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, 504 skb, length); 505 if (unlikely(!used_frags)) { 506 kfree_skb(skb); 507 return NULL; 508 } 509 skb_shinfo(skb)->nr_frags = used_frags; 510 511 /* Copy headers into the skb linear buffer */ 512 memcpy(skb->data, va, HEADER_COPY_SIZE); 513 skb->tail += HEADER_COPY_SIZE; 514 515 /* Skip headers in first fragment */ 516 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; 517 518 /* Adjust size of first fragment */ 519 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); 520 skb->data_len = length - HEADER_COPY_SIZE; 521 } 522 return skb; 523 } 524 525 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) 526 { 527 int i; 528 int offset = ETH_HLEN; 529 530 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { 531 if (*(skb->data + offset) != (unsigned char) (i & 0xff)) 532 goto out_loopback; 533 } 534 /* Loopback found */ 535 priv->loopback_ok = 1; 536 537 out_loopback: 538 dev_kfree_skb_any(skb); 539 } 540 541 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 542 struct mlx4_en_rx_ring *ring) 543 { 544 int index = ring->prod & ring->size_mask; 545 546 while ((u32) (ring->prod - ring->cons) < ring->actual_size) { 547 if (mlx4_en_prepare_rx_desc(priv, ring, index)) 548 break; 549 ring->prod++; 550 index = ring->prod & ring->size_mask; 551 } 552 } 553 554 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 555 { 556 struct mlx4_en_priv *priv = netdev_priv(dev); 557 struct mlx4_cqe *cqe; 558 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; 559 struct mlx4_en_rx_alloc *frags; 560 struct mlx4_en_rx_desc *rx_desc; 561 struct sk_buff *skb; 562 int index; 563 int nr; 564 unsigned int length; 565 int polled = 0; 566 int ip_summed; 567 int factor = priv->cqe_factor; 568 569 if (!priv->port_up) 570 return 0; 571 572 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 573 * descriptor offset can be deduced from the CQE index instead of 574 * reading 'cqe->index' */ 575 index = cq->mcq.cons_index & ring->size_mask; 576 cqe = &cq->buf[(index << factor) + factor]; 577 578 /* Process all completed CQEs */ 579 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 580 cq->mcq.cons_index & cq->size)) { 581 582 frags = ring->rx_info + (index << priv->log_rx_info); 583 rx_desc = ring->buf + (index << ring->log_stride); 584 585 /* 586 * make sure we read the CQE after we read the ownership bit 587 */ 588 rmb(); 589 590 /* Drop packet on bad receive or bad checksum */ 591 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 592 MLX4_CQE_OPCODE_ERROR)) { 593 en_err(priv, "CQE completed in error - vendor " 594 "syndrom:%d syndrom:%d\n", 595 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, 596 ((struct mlx4_err_cqe *) cqe)->syndrome); 597 goto next; 598 } 599 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 600 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 601 goto next; 602 } 603 604 /* Check if we need to drop the packet if SRIOV is not enabled 605 * and not performing the selftest or flb disabled 606 */ 607 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 608 struct ethhdr *ethh; 609 dma_addr_t dma; 610 /* Get pointer to first fragment since we haven't 611 * skb yet and cast it to ethhdr struct 612 */ 613 dma = be64_to_cpu(rx_desc->data[0].addr); 614 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 615 DMA_FROM_DEVICE); 616 ethh = (struct ethhdr *)(page_address(frags[0].page) + 617 frags[0].offset); 618 619 if (is_multicast_ether_addr(ethh->h_dest)) { 620 struct mlx4_mac_entry *entry; 621 struct hlist_head *bucket; 622 unsigned int mac_hash; 623 624 /* Drop the packet, since HW loopback-ed it */ 625 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 626 bucket = &priv->mac_hash[mac_hash]; 627 rcu_read_lock(); 628 hlist_for_each_entry_rcu(entry, bucket, hlist) { 629 if (ether_addr_equal_64bits(entry->mac, 630 ethh->h_source)) { 631 rcu_read_unlock(); 632 goto next; 633 } 634 } 635 rcu_read_unlock(); 636 } 637 } 638 639 /* 640 * Packet is OK - process it. 641 */ 642 length = be32_to_cpu(cqe->byte_cnt); 643 length -= ring->fcs_del; 644 ring->bytes += length; 645 ring->packets++; 646 647 if (likely(dev->features & NETIF_F_RXCSUM)) { 648 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 649 (cqe->checksum == cpu_to_be16(0xffff))) { 650 ring->csum_ok++; 651 /* This packet is eligible for GRO if it is: 652 * - DIX Ethernet (type interpretation) 653 * - TCP/IP (v4) 654 * - without IP options 655 * - not an IP fragment */ 656 if (dev->features & NETIF_F_GRO) { 657 struct sk_buff *gro_skb = napi_get_frags(&cq->napi); 658 if (!gro_skb) 659 goto next; 660 661 nr = mlx4_en_complete_rx_desc(priv, 662 rx_desc, frags, gro_skb, 663 length); 664 if (!nr) 665 goto next; 666 667 skb_shinfo(gro_skb)->nr_frags = nr; 668 gro_skb->len = length; 669 gro_skb->data_len = length; 670 gro_skb->ip_summed = CHECKSUM_UNNECESSARY; 671 672 if (cqe->vlan_my_qpn & 673 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) { 674 u16 vid = be16_to_cpu(cqe->sl_vid); 675 676 __vlan_hwaccel_put_tag(gro_skb, vid); 677 } 678 679 if (dev->features & NETIF_F_RXHASH) 680 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); 681 682 skb_record_rx_queue(gro_skb, cq->ring); 683 napi_gro_frags(&cq->napi); 684 685 goto next; 686 } 687 688 /* GRO not possible, complete processing here */ 689 ip_summed = CHECKSUM_UNNECESSARY; 690 } else { 691 ip_summed = CHECKSUM_NONE; 692 ring->csum_none++; 693 } 694 } else { 695 ip_summed = CHECKSUM_NONE; 696 ring->csum_none++; 697 } 698 699 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); 700 if (!skb) { 701 priv->stats.rx_dropped++; 702 goto next; 703 } 704 705 if (unlikely(priv->validate_loopback)) { 706 validate_loopback(priv, skb); 707 goto next; 708 } 709 710 skb->ip_summed = ip_summed; 711 skb->protocol = eth_type_trans(skb, dev); 712 skb_record_rx_queue(skb, cq->ring); 713 714 if (dev->features & NETIF_F_RXHASH) 715 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); 716 717 if (be32_to_cpu(cqe->vlan_my_qpn) & 718 MLX4_CQE_VLAN_PRESENT_MASK) 719 __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid)); 720 721 /* Push it up the stack */ 722 netif_receive_skb(skb); 723 724 next: 725 for (nr = 0; nr < priv->num_frags; nr++) 726 mlx4_en_free_frag(priv, frags, nr); 727 728 ++cq->mcq.cons_index; 729 index = (cq->mcq.cons_index) & ring->size_mask; 730 cqe = &cq->buf[(index << factor) + factor]; 731 if (++polled == budget) 732 goto out; 733 } 734 735 out: 736 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 737 mlx4_cq_set_ci(&cq->mcq); 738 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 739 ring->cons = cq->mcq.cons_index; 740 mlx4_en_refill_rx_buffers(priv, ring); 741 mlx4_en_update_rx_prod_db(ring); 742 return polled; 743 } 744 745 746 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 747 { 748 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 749 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 750 751 if (priv->port_up) 752 napi_schedule(&cq->napi); 753 else 754 mlx4_en_arm_cq(priv, cq); 755 } 756 757 /* Rx CQ polling - called by NAPI */ 758 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 759 { 760 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 761 struct net_device *dev = cq->dev; 762 struct mlx4_en_priv *priv = netdev_priv(dev); 763 int done; 764 765 done = mlx4_en_process_rx_cq(dev, cq, budget); 766 767 /* If we used up all the quota - we're probably not done yet... */ 768 if (done == budget) 769 INC_PERF_COUNTER(priv->pstats.napi_quota); 770 else { 771 /* Done for now */ 772 napi_complete(napi); 773 mlx4_en_arm_cq(priv, cq); 774 } 775 return done; 776 } 777 778 779 /* Calculate the last offset position that accommodates a full fragment 780 * (assuming fagment size = stride-align) */ 781 static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) 782 { 783 u16 res = MLX4_EN_ALLOC_SIZE % stride; 784 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; 785 786 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " 787 "res:%d offset:%d\n", stride, align, res, offset); 788 return offset; 789 } 790 791 792 static int frag_sizes[] = { 793 FRAG_SZ0, 794 FRAG_SZ1, 795 FRAG_SZ2, 796 FRAG_SZ3 797 }; 798 799 void mlx4_en_calc_rx_buf(struct net_device *dev) 800 { 801 struct mlx4_en_priv *priv = netdev_priv(dev); 802 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; 803 int buf_size = 0; 804 int i = 0; 805 806 while (buf_size < eff_mtu) { 807 priv->frag_info[i].frag_size = 808 (eff_mtu > buf_size + frag_sizes[i]) ? 809 frag_sizes[i] : eff_mtu - buf_size; 810 priv->frag_info[i].frag_prefix_size = buf_size; 811 if (!i) { 812 priv->frag_info[i].frag_align = NET_IP_ALIGN; 813 priv->frag_info[i].frag_stride = 814 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); 815 } else { 816 priv->frag_info[i].frag_align = 0; 817 priv->frag_info[i].frag_stride = 818 ALIGN(frag_sizes[i], SMP_CACHE_BYTES); 819 } 820 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( 821 priv, priv->frag_info[i].frag_stride, 822 priv->frag_info[i].frag_align); 823 buf_size += priv->frag_info[i].frag_size; 824 i++; 825 } 826 827 priv->num_frags = i; 828 priv->rx_skb_size = eff_mtu; 829 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 830 831 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " 832 "num_frags:%d):\n", eff_mtu, priv->num_frags); 833 for (i = 0; i < priv->num_frags; i++) { 834 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " 835 "stride:%d last_offset:%d\n", i, 836 priv->frag_info[i].frag_size, 837 priv->frag_info[i].frag_prefix_size, 838 priv->frag_info[i].frag_align, 839 priv->frag_info[i].frag_stride, 840 priv->frag_info[i].last_offset); 841 } 842 } 843 844 /* RSS related functions */ 845 846 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 847 struct mlx4_en_rx_ring *ring, 848 enum mlx4_qp_state *state, 849 struct mlx4_qp *qp) 850 { 851 struct mlx4_en_dev *mdev = priv->mdev; 852 struct mlx4_qp_context *context; 853 int err = 0; 854 855 context = kmalloc(sizeof(*context), GFP_KERNEL); 856 if (!context) 857 return -ENOMEM; 858 859 err = mlx4_qp_alloc(mdev->dev, qpn, qp); 860 if (err) { 861 en_err(priv, "Failed to allocate qp #%x\n", qpn); 862 goto out; 863 } 864 qp->event = mlx4_en_sqp_event; 865 866 memset(context, 0, sizeof *context); 867 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 868 qpn, ring->cqn, -1, context); 869 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 870 871 /* Cancel FCS removal if FW allows */ 872 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 873 context->param3 |= cpu_to_be32(1 << 29); 874 ring->fcs_del = ETH_FCS_LEN; 875 } else 876 ring->fcs_del = 0; 877 878 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 879 if (err) { 880 mlx4_qp_remove(mdev->dev, qp); 881 mlx4_qp_free(mdev->dev, qp); 882 } 883 mlx4_en_update_rx_prod_db(ring); 884 out: 885 kfree(context); 886 return err; 887 } 888 889 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 890 { 891 int err; 892 u32 qpn; 893 894 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); 895 if (err) { 896 en_err(priv, "Failed reserving drop qpn\n"); 897 return err; 898 } 899 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); 900 if (err) { 901 en_err(priv, "Failed allocating drop qp\n"); 902 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 903 return err; 904 } 905 906 return 0; 907 } 908 909 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 910 { 911 u32 qpn; 912 913 qpn = priv->drop_qp.qpn; 914 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 915 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 916 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 917 } 918 919 /* Allocate rx qp's and configure them according to rss map */ 920 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 921 { 922 struct mlx4_en_dev *mdev = priv->mdev; 923 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 924 struct mlx4_qp_context context; 925 struct mlx4_rss_context *rss_context; 926 int rss_rings; 927 void *ptr; 928 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 929 MLX4_RSS_TCP_IPV6); 930 int i, qpn; 931 int err = 0; 932 int good_qps = 0; 933 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, 934 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, 935 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; 936 937 en_dbg(DRV, priv, "Configuring rss steering\n"); 938 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 939 priv->rx_ring_num, 940 &rss_map->base_qpn); 941 if (err) { 942 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 943 return err; 944 } 945 946 for (i = 0; i < priv->rx_ring_num; i++) { 947 qpn = rss_map->base_qpn + i; 948 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], 949 &rss_map->state[i], 950 &rss_map->qps[i]); 951 if (err) 952 goto rss_err; 953 954 ++good_qps; 955 } 956 957 /* Configure RSS indirection qp */ 958 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); 959 if (err) { 960 en_err(priv, "Failed to allocate RSS indirection QP\n"); 961 goto rss_err; 962 } 963 rss_map->indir_qp.event = mlx4_en_sqp_event; 964 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 965 priv->rx_ring[0].cqn, -1, &context); 966 967 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 968 rss_rings = priv->rx_ring_num; 969 else 970 rss_rings = priv->prof->rss_rings; 971 972 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 973 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 974 rss_context = ptr; 975 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 976 (rss_map->base_qpn)); 977 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 978 if (priv->mdev->profile.udp_rss) { 979 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 980 rss_context->base_qpn_udp = rss_context->default_qpn; 981 } 982 rss_context->flags = rss_mask; 983 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 984 for (i = 0; i < 10; i++) 985 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); 986 987 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 988 &rss_map->indir_qp, &rss_map->indir_state); 989 if (err) 990 goto indir_err; 991 992 return 0; 993 994 indir_err: 995 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 996 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 997 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 998 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 999 rss_err: 1000 for (i = 0; i < good_qps; i++) { 1001 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1002 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1003 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1004 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1005 } 1006 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1007 return err; 1008 } 1009 1010 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1011 { 1012 struct mlx4_en_dev *mdev = priv->mdev; 1013 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1014 int i; 1015 1016 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1017 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1018 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1019 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1020 1021 for (i = 0; i < priv->rx_ring_num; i++) { 1022 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1023 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1024 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1025 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1026 } 1027 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1028 } 1029