1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/rculist.h> 40 #include <linux/if_ether.h> 41 #include <linux/if_vlan.h> 42 #include <linux/vmalloc.h> 43 #include <linux/irq.h> 44 45 #if IS_ENABLED(CONFIG_IPV6) 46 #include <net/ip6_checksum.h> 47 #endif 48 49 #include "mlx4_en.h" 50 51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv, 52 struct mlx4_en_rx_alloc *page_alloc, 53 const struct mlx4_en_frag_info *frag_info, 54 gfp_t _gfp) 55 { 56 int order; 57 struct page *page; 58 dma_addr_t dma; 59 60 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { 61 gfp_t gfp = _gfp; 62 63 if (order) 64 gfp |= __GFP_COMP | __GFP_NOWARN; 65 page = alloc_pages(gfp, order); 66 if (likely(page)) 67 break; 68 if (--order < 0 || 69 ((PAGE_SIZE << order) < frag_info->frag_size)) 70 return -ENOMEM; 71 } 72 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, 73 PCI_DMA_FROMDEVICE); 74 if (dma_mapping_error(priv->ddev, dma)) { 75 put_page(page); 76 return -ENOMEM; 77 } 78 page_alloc->page_size = PAGE_SIZE << order; 79 page_alloc->page = page; 80 page_alloc->dma = dma; 81 page_alloc->page_offset = 0; 82 /* Not doing get_page() for each frag is a big win 83 * on asymetric workloads. Note we can not use atomic_set(). 84 */ 85 atomic_add(page_alloc->page_size / frag_info->frag_stride - 1, 86 &page->_count); 87 return 0; 88 } 89 90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 91 struct mlx4_en_rx_desc *rx_desc, 92 struct mlx4_en_rx_alloc *frags, 93 struct mlx4_en_rx_alloc *ring_alloc, 94 gfp_t gfp) 95 { 96 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 97 const struct mlx4_en_frag_info *frag_info; 98 struct page *page; 99 dma_addr_t dma; 100 int i; 101 102 for (i = 0; i < priv->num_frags; i++) { 103 frag_info = &priv->frag_info[i]; 104 page_alloc[i] = ring_alloc[i]; 105 page_alloc[i].page_offset += frag_info->frag_stride; 106 107 if (page_alloc[i].page_offset + frag_info->frag_stride <= 108 ring_alloc[i].page_size) 109 continue; 110 111 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) 112 goto out; 113 } 114 115 for (i = 0; i < priv->num_frags; i++) { 116 frags[i] = ring_alloc[i]; 117 dma = ring_alloc[i].dma + ring_alloc[i].page_offset; 118 ring_alloc[i] = page_alloc[i]; 119 rx_desc->data[i].addr = cpu_to_be64(dma); 120 } 121 122 return 0; 123 124 out: 125 while (i--) { 126 if (page_alloc[i].page != ring_alloc[i].page) { 127 dma_unmap_page(priv->ddev, page_alloc[i].dma, 128 page_alloc[i].page_size, PCI_DMA_FROMDEVICE); 129 page = page_alloc[i].page; 130 atomic_set(&page->_count, 1); 131 put_page(page); 132 } 133 } 134 return -ENOMEM; 135 } 136 137 static void mlx4_en_free_frag(struct mlx4_en_priv *priv, 138 struct mlx4_en_rx_alloc *frags, 139 int i) 140 { 141 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 142 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; 143 144 145 if (next_frag_end > frags[i].page_size) 146 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, 147 PCI_DMA_FROMDEVICE); 148 149 if (frags[i].page) 150 put_page(frags[i].page); 151 } 152 153 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, 154 struct mlx4_en_rx_ring *ring) 155 { 156 int i; 157 struct mlx4_en_rx_alloc *page_alloc; 158 159 for (i = 0; i < priv->num_frags; i++) { 160 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 161 162 if (mlx4_alloc_pages(priv, &ring->page_alloc[i], 163 frag_info, GFP_KERNEL | __GFP_COLD)) 164 goto out; 165 166 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", 167 i, ring->page_alloc[i].page_size, 168 atomic_read(&ring->page_alloc[i].page->_count)); 169 } 170 return 0; 171 172 out: 173 while (i--) { 174 struct page *page; 175 176 page_alloc = &ring->page_alloc[i]; 177 dma_unmap_page(priv->ddev, page_alloc->dma, 178 page_alloc->page_size, PCI_DMA_FROMDEVICE); 179 page = page_alloc->page; 180 atomic_set(&page->_count, 1); 181 put_page(page); 182 page_alloc->page = NULL; 183 } 184 return -ENOMEM; 185 } 186 187 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, 188 struct mlx4_en_rx_ring *ring) 189 { 190 struct mlx4_en_rx_alloc *page_alloc; 191 int i; 192 193 for (i = 0; i < priv->num_frags; i++) { 194 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 195 196 page_alloc = &ring->page_alloc[i]; 197 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", 198 i, page_count(page_alloc->page)); 199 200 dma_unmap_page(priv->ddev, page_alloc->dma, 201 page_alloc->page_size, PCI_DMA_FROMDEVICE); 202 while (page_alloc->page_offset + frag_info->frag_stride < 203 page_alloc->page_size) { 204 put_page(page_alloc->page); 205 page_alloc->page_offset += frag_info->frag_stride; 206 } 207 page_alloc->page = NULL; 208 } 209 } 210 211 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, 212 struct mlx4_en_rx_ring *ring, int index) 213 { 214 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 215 int possible_frags; 216 int i; 217 218 /* Set size and memtype fields */ 219 for (i = 0; i < priv->num_frags; i++) { 220 rx_desc->data[i].byte_count = 221 cpu_to_be32(priv->frag_info[i].frag_size); 222 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 223 } 224 225 /* If the number of used fragments does not fill up the ring stride, 226 * remaining (unused) fragments must be padded with null address/size 227 * and a special memory key */ 228 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 229 for (i = priv->num_frags; i < possible_frags; i++) { 230 rx_desc->data[i].byte_count = 0; 231 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 232 rx_desc->data[i].addr = 0; 233 } 234 } 235 236 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 237 struct mlx4_en_rx_ring *ring, int index, 238 gfp_t gfp) 239 { 240 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 241 struct mlx4_en_rx_alloc *frags = ring->rx_info + 242 (index << priv->log_rx_info); 243 244 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); 245 } 246 247 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) 248 { 249 BUG_ON((u32)(ring->prod - ring->cons) > ring->actual_size); 250 return ring->prod == ring->cons; 251 } 252 253 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 254 { 255 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 256 } 257 258 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, 259 struct mlx4_en_rx_ring *ring, 260 int index) 261 { 262 struct mlx4_en_rx_alloc *frags; 263 int nr; 264 265 frags = ring->rx_info + (index << priv->log_rx_info); 266 for (nr = 0; nr < priv->num_frags; nr++) { 267 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 268 mlx4_en_free_frag(priv, frags, nr); 269 } 270 } 271 272 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 273 { 274 struct mlx4_en_rx_ring *ring; 275 int ring_ind; 276 int buf_ind; 277 int new_size; 278 279 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 280 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 281 ring = priv->rx_ring[ring_ind]; 282 283 if (mlx4_en_prepare_rx_desc(priv, ring, 284 ring->actual_size, 285 GFP_KERNEL | __GFP_COLD)) { 286 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 287 en_err(priv, "Failed to allocate enough rx buffers\n"); 288 return -ENOMEM; 289 } else { 290 new_size = rounddown_pow_of_two(ring->actual_size); 291 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 292 ring->actual_size, new_size); 293 goto reduce_rings; 294 } 295 } 296 ring->actual_size++; 297 ring->prod++; 298 } 299 } 300 return 0; 301 302 reduce_rings: 303 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 304 ring = priv->rx_ring[ring_ind]; 305 while (ring->actual_size > new_size) { 306 ring->actual_size--; 307 ring->prod--; 308 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 309 } 310 } 311 312 return 0; 313 } 314 315 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 316 struct mlx4_en_rx_ring *ring) 317 { 318 int index; 319 320 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 321 ring->cons, ring->prod); 322 323 /* Unmap and free Rx buffers */ 324 while (!mlx4_en_is_ring_empty(ring)) { 325 index = ring->cons & ring->size_mask; 326 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 327 mlx4_en_free_rx_desc(priv, ring, index); 328 ++ring->cons; 329 } 330 } 331 332 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 333 { 334 int i; 335 int num_of_eqs; 336 int num_rx_rings; 337 struct mlx4_dev *dev = mdev->dev; 338 339 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 340 num_of_eqs = max_t(int, MIN_RX_RINGS, 341 min_t(int, 342 mlx4_get_eqs_per_port(mdev->dev, i), 343 DEF_RX_RINGS)); 344 345 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 346 min_t(int, num_of_eqs, 347 netif_get_num_default_rss_queues()); 348 mdev->profile.prof[i].rx_ring_num = 349 rounddown_pow_of_two(num_rx_rings); 350 } 351 } 352 353 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 354 struct mlx4_en_rx_ring **pring, 355 u32 size, u16 stride, int node) 356 { 357 struct mlx4_en_dev *mdev = priv->mdev; 358 struct mlx4_en_rx_ring *ring; 359 int err = -ENOMEM; 360 int tmp; 361 362 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 363 if (!ring) { 364 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 365 if (!ring) { 366 en_err(priv, "Failed to allocate RX ring structure\n"); 367 return -ENOMEM; 368 } 369 } 370 371 ring->prod = 0; 372 ring->cons = 0; 373 ring->size = size; 374 ring->size_mask = size - 1; 375 ring->stride = stride; 376 ring->log_stride = ffs(ring->stride) - 1; 377 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 378 379 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 380 sizeof(struct mlx4_en_rx_alloc)); 381 ring->rx_info = vmalloc_node(tmp, node); 382 if (!ring->rx_info) { 383 ring->rx_info = vmalloc(tmp); 384 if (!ring->rx_info) { 385 err = -ENOMEM; 386 goto err_ring; 387 } 388 } 389 390 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 391 ring->rx_info, tmp); 392 393 /* Allocate HW buffers on provided NUMA node */ 394 set_dev_node(&mdev->dev->persist->pdev->dev, node); 395 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 396 ring->buf_size, 2 * PAGE_SIZE); 397 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 398 if (err) 399 goto err_info; 400 401 err = mlx4_en_map_buffer(&ring->wqres.buf); 402 if (err) { 403 en_err(priv, "Failed to map RX buffer\n"); 404 goto err_hwq; 405 } 406 ring->buf = ring->wqres.buf.direct.buf; 407 408 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 409 410 *pring = ring; 411 return 0; 412 413 err_hwq: 414 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 415 err_info: 416 vfree(ring->rx_info); 417 ring->rx_info = NULL; 418 err_ring: 419 kfree(ring); 420 *pring = NULL; 421 422 return err; 423 } 424 425 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 426 { 427 struct mlx4_en_rx_ring *ring; 428 int i; 429 int ring_ind; 430 int err; 431 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 432 DS_SIZE * priv->num_frags); 433 434 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 435 ring = priv->rx_ring[ring_ind]; 436 437 ring->prod = 0; 438 ring->cons = 0; 439 ring->actual_size = 0; 440 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 441 442 ring->stride = stride; 443 if (ring->stride <= TXBB_SIZE) 444 ring->buf += TXBB_SIZE; 445 446 ring->log_stride = ffs(ring->stride) - 1; 447 ring->buf_size = ring->size * ring->stride; 448 449 memset(ring->buf, 0, ring->buf_size); 450 mlx4_en_update_rx_prod_db(ring); 451 452 /* Initialize all descriptors */ 453 for (i = 0; i < ring->size; i++) 454 mlx4_en_init_rx_desc(priv, ring, i); 455 456 /* Initialize page allocators */ 457 err = mlx4_en_init_allocator(priv, ring); 458 if (err) { 459 en_err(priv, "Failed initializing ring allocator\n"); 460 if (ring->stride <= TXBB_SIZE) 461 ring->buf -= TXBB_SIZE; 462 ring_ind--; 463 goto err_allocator; 464 } 465 } 466 err = mlx4_en_fill_rx_buffers(priv); 467 if (err) 468 goto err_buffers; 469 470 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 471 ring = priv->rx_ring[ring_ind]; 472 473 ring->size_mask = ring->actual_size - 1; 474 mlx4_en_update_rx_prod_db(ring); 475 } 476 477 return 0; 478 479 err_buffers: 480 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 481 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 482 483 ring_ind = priv->rx_ring_num - 1; 484 err_allocator: 485 while (ring_ind >= 0) { 486 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 487 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 488 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); 489 ring_ind--; 490 } 491 return err; 492 } 493 494 /* We recover from out of memory by scheduling our napi poll 495 * function (mlx4_en_process_cq), which tries to allocate 496 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 497 */ 498 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 499 { 500 int ring; 501 502 if (!priv->port_up) 503 return; 504 505 for (ring = 0; ring < priv->rx_ring_num; ring++) { 506 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) 507 napi_reschedule(&priv->rx_cq[ring]->napi); 508 } 509 } 510 511 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 512 struct mlx4_en_rx_ring **pring, 513 u32 size, u16 stride) 514 { 515 struct mlx4_en_dev *mdev = priv->mdev; 516 struct mlx4_en_rx_ring *ring = *pring; 517 518 mlx4_en_unmap_buffer(&ring->wqres.buf); 519 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 520 vfree(ring->rx_info); 521 ring->rx_info = NULL; 522 kfree(ring); 523 *pring = NULL; 524 #ifdef CONFIG_RFS_ACCEL 525 mlx4_en_cleanup_filters(priv); 526 #endif 527 } 528 529 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 530 struct mlx4_en_rx_ring *ring) 531 { 532 mlx4_en_free_rx_buf(priv, ring); 533 if (ring->stride <= TXBB_SIZE) 534 ring->buf -= TXBB_SIZE; 535 mlx4_en_destroy_allocator(priv, ring); 536 } 537 538 539 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 540 struct mlx4_en_rx_desc *rx_desc, 541 struct mlx4_en_rx_alloc *frags, 542 struct sk_buff *skb, 543 int length) 544 { 545 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; 546 struct mlx4_en_frag_info *frag_info; 547 int nr; 548 dma_addr_t dma; 549 550 /* Collect used fragments while replacing them in the HW descriptors */ 551 for (nr = 0; nr < priv->num_frags; nr++) { 552 frag_info = &priv->frag_info[nr]; 553 if (length <= frag_info->frag_prefix_size) 554 break; 555 if (!frags[nr].page) 556 goto fail; 557 558 dma = be64_to_cpu(rx_desc->data[nr].addr); 559 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, 560 DMA_FROM_DEVICE); 561 562 /* Save page reference in skb */ 563 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); 564 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); 565 skb_frags_rx[nr].page_offset = frags[nr].page_offset; 566 skb->truesize += frag_info->frag_stride; 567 frags[nr].page = NULL; 568 } 569 /* Adjust size of last fragment to match actual length */ 570 if (nr > 0) 571 skb_frag_size_set(&skb_frags_rx[nr - 1], 572 length - priv->frag_info[nr - 1].frag_prefix_size); 573 return nr; 574 575 fail: 576 while (nr > 0) { 577 nr--; 578 __skb_frag_unref(&skb_frags_rx[nr]); 579 } 580 return 0; 581 } 582 583 584 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, 585 struct mlx4_en_rx_desc *rx_desc, 586 struct mlx4_en_rx_alloc *frags, 587 unsigned int length) 588 { 589 struct sk_buff *skb; 590 void *va; 591 int used_frags; 592 dma_addr_t dma; 593 594 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); 595 if (!skb) { 596 en_dbg(RX_ERR, priv, "Failed allocating skb\n"); 597 return NULL; 598 } 599 skb_reserve(skb, NET_IP_ALIGN); 600 skb->len = length; 601 602 /* Get pointer to first fragment so we could copy the headers into the 603 * (linear part of the) skb */ 604 va = page_address(frags[0].page) + frags[0].page_offset; 605 606 if (length <= SMALL_PACKET_SIZE) { 607 /* We are copying all relevant data to the skb - temporarily 608 * sync buffers for the copy */ 609 dma = be64_to_cpu(rx_desc->data[0].addr); 610 dma_sync_single_for_cpu(priv->ddev, dma, length, 611 DMA_FROM_DEVICE); 612 skb_copy_to_linear_data(skb, va, length); 613 skb->tail += length; 614 } else { 615 unsigned int pull_len; 616 617 /* Move relevant fragments to skb */ 618 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, 619 skb, length); 620 if (unlikely(!used_frags)) { 621 kfree_skb(skb); 622 return NULL; 623 } 624 skb_shinfo(skb)->nr_frags = used_frags; 625 626 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); 627 /* Copy headers into the skb linear buffer */ 628 memcpy(skb->data, va, pull_len); 629 skb->tail += pull_len; 630 631 /* Skip headers in first fragment */ 632 skb_shinfo(skb)->frags[0].page_offset += pull_len; 633 634 /* Adjust size of first fragment */ 635 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); 636 skb->data_len = length - pull_len; 637 } 638 return skb; 639 } 640 641 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) 642 { 643 int i; 644 int offset = ETH_HLEN; 645 646 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { 647 if (*(skb->data + offset) != (unsigned char) (i & 0xff)) 648 goto out_loopback; 649 } 650 /* Loopback found */ 651 priv->loopback_ok = 1; 652 653 out_loopback: 654 dev_kfree_skb_any(skb); 655 } 656 657 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 658 struct mlx4_en_rx_ring *ring) 659 { 660 int index = ring->prod & ring->size_mask; 661 662 while ((u32) (ring->prod - ring->cons) < ring->actual_size) { 663 if (mlx4_en_prepare_rx_desc(priv, ring, index, 664 GFP_ATOMIC | __GFP_COLD)) 665 break; 666 ring->prod++; 667 index = ring->prod & ring->size_mask; 668 } 669 } 670 671 /* When hardware doesn't strip the vlan, we need to calculate the checksum 672 * over it and add it to the hardware's checksum calculation 673 */ 674 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 675 struct vlan_hdr *vlanh) 676 { 677 return csum_add(hw_checksum, *(__wsum *)vlanh); 678 } 679 680 /* Although the stack expects checksum which doesn't include the pseudo 681 * header, the HW adds it. To address that, we are subtracting the pseudo 682 * header checksum from the checksum value provided by the HW. 683 */ 684 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 685 struct iphdr *iph) 686 { 687 __u16 length_for_csum = 0; 688 __wsum csum_pseudo_header = 0; 689 690 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 691 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 692 length_for_csum, iph->protocol, 0); 693 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 694 } 695 696 #if IS_ENABLED(CONFIG_IPV6) 697 /* In IPv6 packets, besides subtracting the pseudo header checksum, 698 * we also compute/add the IP header checksum which 699 * is not added by the HW. 700 */ 701 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 702 struct ipv6hdr *ipv6h) 703 { 704 __wsum csum_pseudo_hdr = 0; 705 706 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) 707 return -1; 708 hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8)); 709 710 csum_pseudo_hdr = csum_partial(&ipv6h->saddr, 711 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); 712 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); 713 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); 714 715 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); 716 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); 717 return 0; 718 } 719 #endif 720 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 721 netdev_features_t dev_features) 722 { 723 __wsum hw_checksum = 0; 724 725 void *hdr = (u8 *)va + sizeof(struct ethhdr); 726 727 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 728 729 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK) && 730 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { 731 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 732 hdr += sizeof(struct vlan_hdr); 733 } 734 735 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) 736 get_fixed_ipv4_csum(hw_checksum, skb, hdr); 737 #if IS_ENABLED(CONFIG_IPV6) 738 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 739 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) 740 return -1; 741 #endif 742 return 0; 743 } 744 745 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 746 { 747 struct mlx4_en_priv *priv = netdev_priv(dev); 748 struct mlx4_en_dev *mdev = priv->mdev; 749 struct mlx4_cqe *cqe; 750 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; 751 struct mlx4_en_rx_alloc *frags; 752 struct mlx4_en_rx_desc *rx_desc; 753 struct sk_buff *skb; 754 int index; 755 int nr; 756 unsigned int length; 757 int polled = 0; 758 int ip_summed; 759 int factor = priv->cqe_factor; 760 u64 timestamp; 761 bool l2_tunnel; 762 763 if (!priv->port_up) 764 return 0; 765 766 if (budget <= 0) 767 return polled; 768 769 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 770 * descriptor offset can be deduced from the CQE index instead of 771 * reading 'cqe->index' */ 772 index = cq->mcq.cons_index & ring->size_mask; 773 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 774 775 /* Process all completed CQEs */ 776 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 777 cq->mcq.cons_index & cq->size)) { 778 779 frags = ring->rx_info + (index << priv->log_rx_info); 780 rx_desc = ring->buf + (index << ring->log_stride); 781 782 /* 783 * make sure we read the CQE after we read the ownership bit 784 */ 785 dma_rmb(); 786 787 /* Drop packet on bad receive or bad checksum */ 788 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 789 MLX4_CQE_OPCODE_ERROR)) { 790 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 791 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 792 ((struct mlx4_err_cqe *)cqe)->syndrome); 793 goto next; 794 } 795 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 796 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 797 goto next; 798 } 799 800 /* Check if we need to drop the packet if SRIOV is not enabled 801 * and not performing the selftest or flb disabled 802 */ 803 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 804 struct ethhdr *ethh; 805 dma_addr_t dma; 806 /* Get pointer to first fragment since we haven't 807 * skb yet and cast it to ethhdr struct 808 */ 809 dma = be64_to_cpu(rx_desc->data[0].addr); 810 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 811 DMA_FROM_DEVICE); 812 ethh = (struct ethhdr *)(page_address(frags[0].page) + 813 frags[0].page_offset); 814 815 if (is_multicast_ether_addr(ethh->h_dest)) { 816 struct mlx4_mac_entry *entry; 817 struct hlist_head *bucket; 818 unsigned int mac_hash; 819 820 /* Drop the packet, since HW loopback-ed it */ 821 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 822 bucket = &priv->mac_hash[mac_hash]; 823 rcu_read_lock(); 824 hlist_for_each_entry_rcu(entry, bucket, hlist) { 825 if (ether_addr_equal_64bits(entry->mac, 826 ethh->h_source)) { 827 rcu_read_unlock(); 828 goto next; 829 } 830 } 831 rcu_read_unlock(); 832 } 833 } 834 835 /* 836 * Packet is OK - process it. 837 */ 838 length = be32_to_cpu(cqe->byte_cnt); 839 length -= ring->fcs_del; 840 ring->bytes += length; 841 ring->packets++; 842 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 843 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 844 845 if (likely(dev->features & NETIF_F_RXCSUM)) { 846 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 847 MLX4_CQE_STATUS_UDP)) { 848 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 849 cqe->checksum == cpu_to_be16(0xffff)) { 850 ip_summed = CHECKSUM_UNNECESSARY; 851 ring->csum_ok++; 852 } else { 853 ip_summed = CHECKSUM_NONE; 854 ring->csum_none++; 855 } 856 } else { 857 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 858 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 859 MLX4_CQE_STATUS_IPV6))) { 860 ip_summed = CHECKSUM_COMPLETE; 861 ring->csum_complete++; 862 } else { 863 ip_summed = CHECKSUM_NONE; 864 ring->csum_none++; 865 } 866 } 867 } else { 868 ip_summed = CHECKSUM_NONE; 869 ring->csum_none++; 870 } 871 872 /* This packet is eligible for GRO if it is: 873 * - DIX Ethernet (type interpretation) 874 * - TCP/IP (v4) 875 * - without IP options 876 * - not an IP fragment 877 * - no LLS polling in progress 878 */ 879 if (!mlx4_en_cq_busy_polling(cq) && 880 (dev->features & NETIF_F_GRO)) { 881 struct sk_buff *gro_skb = napi_get_frags(&cq->napi); 882 if (!gro_skb) 883 goto next; 884 885 nr = mlx4_en_complete_rx_desc(priv, 886 rx_desc, frags, gro_skb, 887 length); 888 if (!nr) 889 goto next; 890 891 if (ip_summed == CHECKSUM_COMPLETE) { 892 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); 893 if (check_csum(cqe, gro_skb, va, 894 dev->features)) { 895 ip_summed = CHECKSUM_NONE; 896 ring->csum_none++; 897 ring->csum_complete--; 898 } 899 } 900 901 skb_shinfo(gro_skb)->nr_frags = nr; 902 gro_skb->len = length; 903 gro_skb->data_len = length; 904 gro_skb->ip_summed = ip_summed; 905 906 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) 907 gro_skb->csum_level = 1; 908 909 if ((cqe->vlan_my_qpn & 910 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && 911 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 912 u16 vid = be16_to_cpu(cqe->sl_vid); 913 914 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); 915 } 916 917 if (dev->features & NETIF_F_RXHASH) 918 skb_set_hash(gro_skb, 919 be32_to_cpu(cqe->immed_rss_invalid), 920 PKT_HASH_TYPE_L3); 921 922 skb_record_rx_queue(gro_skb, cq->ring); 923 skb_mark_napi_id(gro_skb, &cq->napi); 924 925 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 926 timestamp = mlx4_en_get_cqe_ts(cqe); 927 mlx4_en_fill_hwtstamps(mdev, 928 skb_hwtstamps(gro_skb), 929 timestamp); 930 } 931 932 napi_gro_frags(&cq->napi); 933 goto next; 934 } 935 936 /* GRO not possible, complete processing here */ 937 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); 938 if (!skb) { 939 priv->stats.rx_dropped++; 940 goto next; 941 } 942 943 if (unlikely(priv->validate_loopback)) { 944 validate_loopback(priv, skb); 945 goto next; 946 } 947 948 if (ip_summed == CHECKSUM_COMPLETE) { 949 if (check_csum(cqe, skb, skb->data, dev->features)) { 950 ip_summed = CHECKSUM_NONE; 951 ring->csum_complete--; 952 ring->csum_none++; 953 } 954 } 955 956 skb->ip_summed = ip_summed; 957 skb->protocol = eth_type_trans(skb, dev); 958 skb_record_rx_queue(skb, cq->ring); 959 960 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) 961 skb->csum_level = 1; 962 963 if (dev->features & NETIF_F_RXHASH) 964 skb_set_hash(skb, 965 be32_to_cpu(cqe->immed_rss_invalid), 966 PKT_HASH_TYPE_L3); 967 968 if ((be32_to_cpu(cqe->vlan_my_qpn) & 969 MLX4_CQE_VLAN_PRESENT_MASK) && 970 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 971 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); 972 973 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 974 timestamp = mlx4_en_get_cqe_ts(cqe); 975 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), 976 timestamp); 977 } 978 979 skb_mark_napi_id(skb, &cq->napi); 980 981 if (!mlx4_en_cq_busy_polling(cq)) 982 napi_gro_receive(&cq->napi, skb); 983 else 984 netif_receive_skb(skb); 985 986 next: 987 for (nr = 0; nr < priv->num_frags; nr++) 988 mlx4_en_free_frag(priv, frags, nr); 989 990 ++cq->mcq.cons_index; 991 index = (cq->mcq.cons_index) & ring->size_mask; 992 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 993 if (++polled == budget) 994 goto out; 995 } 996 997 out: 998 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 999 mlx4_cq_set_ci(&cq->mcq); 1000 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 1001 ring->cons = cq->mcq.cons_index; 1002 mlx4_en_refill_rx_buffers(priv, ring); 1003 mlx4_en_update_rx_prod_db(ring); 1004 return polled; 1005 } 1006 1007 1008 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 1009 { 1010 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 1011 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 1012 1013 if (likely(priv->port_up)) 1014 napi_schedule_irqoff(&cq->napi); 1015 else 1016 mlx4_en_arm_cq(priv, cq); 1017 } 1018 1019 /* Rx CQ polling - called by NAPI */ 1020 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 1021 { 1022 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 1023 struct net_device *dev = cq->dev; 1024 struct mlx4_en_priv *priv = netdev_priv(dev); 1025 int done; 1026 1027 if (!mlx4_en_cq_lock_napi(cq)) 1028 return budget; 1029 1030 done = mlx4_en_process_rx_cq(dev, cq, budget); 1031 1032 mlx4_en_cq_unlock_napi(cq); 1033 1034 /* If we used up all the quota - we're probably not done yet... */ 1035 if (done == budget) { 1036 int cpu_curr; 1037 const struct cpumask *aff; 1038 1039 INC_PERF_COUNTER(priv->pstats.napi_quota); 1040 1041 cpu_curr = smp_processor_id(); 1042 aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; 1043 1044 if (likely(cpumask_test_cpu(cpu_curr, aff))) 1045 return budget; 1046 1047 /* Current cpu is not according to smp_irq_affinity - 1048 * probably affinity changed. need to stop this NAPI 1049 * poll, and restart it on the right CPU 1050 */ 1051 done = 0; 1052 } 1053 /* Done for now */ 1054 napi_complete_done(napi, done); 1055 mlx4_en_arm_cq(priv, cq); 1056 return done; 1057 } 1058 1059 static const int frag_sizes[] = { 1060 FRAG_SZ0, 1061 FRAG_SZ1, 1062 FRAG_SZ2, 1063 FRAG_SZ3 1064 }; 1065 1066 void mlx4_en_calc_rx_buf(struct net_device *dev) 1067 { 1068 struct mlx4_en_priv *priv = netdev_priv(dev); 1069 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; 1070 int buf_size = 0; 1071 int i = 0; 1072 1073 while (buf_size < eff_mtu) { 1074 priv->frag_info[i].frag_size = 1075 (eff_mtu > buf_size + frag_sizes[i]) ? 1076 frag_sizes[i] : eff_mtu - buf_size; 1077 priv->frag_info[i].frag_prefix_size = buf_size; 1078 priv->frag_info[i].frag_stride = 1079 ALIGN(priv->frag_info[i].frag_size, 1080 SMP_CACHE_BYTES); 1081 buf_size += priv->frag_info[i].frag_size; 1082 i++; 1083 } 1084 1085 priv->num_frags = i; 1086 priv->rx_skb_size = eff_mtu; 1087 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 1088 1089 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 1090 eff_mtu, priv->num_frags); 1091 for (i = 0; i < priv->num_frags; i++) { 1092 en_err(priv, 1093 " frag:%d - size:%d prefix:%d stride:%d\n", 1094 i, 1095 priv->frag_info[i].frag_size, 1096 priv->frag_info[i].frag_prefix_size, 1097 priv->frag_info[i].frag_stride); 1098 } 1099 } 1100 1101 /* RSS related functions */ 1102 1103 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1104 struct mlx4_en_rx_ring *ring, 1105 enum mlx4_qp_state *state, 1106 struct mlx4_qp *qp) 1107 { 1108 struct mlx4_en_dev *mdev = priv->mdev; 1109 struct mlx4_qp_context *context; 1110 int err = 0; 1111 1112 context = kmalloc(sizeof(*context), GFP_KERNEL); 1113 if (!context) 1114 return -ENOMEM; 1115 1116 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); 1117 if (err) { 1118 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1119 goto out; 1120 } 1121 qp->event = mlx4_en_sqp_event; 1122 1123 memset(context, 0, sizeof *context); 1124 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1125 qpn, ring->cqn, -1, context); 1126 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1127 1128 /* Cancel FCS removal if FW allows */ 1129 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1130 context->param3 |= cpu_to_be32(1 << 29); 1131 if (priv->dev->features & NETIF_F_RXFCS) 1132 ring->fcs_del = 0; 1133 else 1134 ring->fcs_del = ETH_FCS_LEN; 1135 } else 1136 ring->fcs_del = 0; 1137 1138 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1139 if (err) { 1140 mlx4_qp_remove(mdev->dev, qp); 1141 mlx4_qp_free(mdev->dev, qp); 1142 } 1143 mlx4_en_update_rx_prod_db(ring); 1144 out: 1145 kfree(context); 1146 return err; 1147 } 1148 1149 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1150 { 1151 int err; 1152 u32 qpn; 1153 1154 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1155 MLX4_RESERVE_A0_QP); 1156 if (err) { 1157 en_err(priv, "Failed reserving drop qpn\n"); 1158 return err; 1159 } 1160 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); 1161 if (err) { 1162 en_err(priv, "Failed allocating drop qp\n"); 1163 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1164 return err; 1165 } 1166 1167 return 0; 1168 } 1169 1170 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1171 { 1172 u32 qpn; 1173 1174 qpn = priv->drop_qp.qpn; 1175 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1176 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1177 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1178 } 1179 1180 /* Allocate rx qp's and configure them according to rss map */ 1181 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1182 { 1183 struct mlx4_en_dev *mdev = priv->mdev; 1184 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1185 struct mlx4_qp_context context; 1186 struct mlx4_rss_context *rss_context; 1187 int rss_rings; 1188 void *ptr; 1189 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1190 MLX4_RSS_TCP_IPV6); 1191 int i, qpn; 1192 int err = 0; 1193 int good_qps = 0; 1194 1195 en_dbg(DRV, priv, "Configuring rss steering\n"); 1196 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1197 priv->rx_ring_num, 1198 &rss_map->base_qpn, 0); 1199 if (err) { 1200 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1201 return err; 1202 } 1203 1204 for (i = 0; i < priv->rx_ring_num; i++) { 1205 qpn = rss_map->base_qpn + i; 1206 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1207 &rss_map->state[i], 1208 &rss_map->qps[i]); 1209 if (err) 1210 goto rss_err; 1211 1212 ++good_qps; 1213 } 1214 1215 /* Configure RSS indirection qp */ 1216 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); 1217 if (err) { 1218 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1219 goto rss_err; 1220 } 1221 rss_map->indir_qp.event = mlx4_en_sqp_event; 1222 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1223 priv->rx_ring[0]->cqn, -1, &context); 1224 1225 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1226 rss_rings = priv->rx_ring_num; 1227 else 1228 rss_rings = priv->prof->rss_rings; 1229 1230 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1231 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1232 rss_context = ptr; 1233 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1234 (rss_map->base_qpn)); 1235 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1236 if (priv->mdev->profile.udp_rss) { 1237 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1238 rss_context->base_qpn_udp = rss_context->default_qpn; 1239 } 1240 1241 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1242 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1243 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1244 } 1245 1246 rss_context->flags = rss_mask; 1247 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1248 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1249 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1250 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1251 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1252 memcpy(rss_context->rss_key, priv->rss_key, 1253 MLX4_EN_RSS_KEY_SIZE); 1254 netdev_rss_key_fill(rss_context->rss_key, 1255 MLX4_EN_RSS_KEY_SIZE); 1256 } else { 1257 en_err(priv, "Unknown RSS hash function requested\n"); 1258 err = -EINVAL; 1259 goto indir_err; 1260 } 1261 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1262 &rss_map->indir_qp, &rss_map->indir_state); 1263 if (err) 1264 goto indir_err; 1265 1266 return 0; 1267 1268 indir_err: 1269 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1270 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1271 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1272 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1273 rss_err: 1274 for (i = 0; i < good_qps; i++) { 1275 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1276 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1277 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1278 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1279 } 1280 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1281 return err; 1282 } 1283 1284 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1285 { 1286 struct mlx4_en_dev *mdev = priv->mdev; 1287 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1288 int i; 1289 1290 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1291 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1292 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1293 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1294 1295 for (i = 0; i < priv->rx_ring_num; i++) { 1296 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1297 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1298 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1299 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1300 } 1301 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1302 } 1303