1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/rculist.h> 40 #include <linux/if_ether.h> 41 #include <linux/if_vlan.h> 42 #include <linux/vmalloc.h> 43 #include <linux/irq.h> 44 45 #if IS_ENABLED(CONFIG_IPV6) 46 #include <net/ip6_checksum.h> 47 #endif 48 49 #include "mlx4_en.h" 50 51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv, 52 struct mlx4_en_rx_alloc *page_alloc, 53 const struct mlx4_en_frag_info *frag_info, 54 gfp_t _gfp) 55 { 56 int order; 57 struct page *page; 58 dma_addr_t dma; 59 60 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { 61 gfp_t gfp = _gfp; 62 63 if (order) 64 gfp |= __GFP_COMP | __GFP_NOWARN; 65 page = alloc_pages(gfp, order); 66 if (likely(page)) 67 break; 68 if (--order < 0 || 69 ((PAGE_SIZE << order) < frag_info->frag_size)) 70 return -ENOMEM; 71 } 72 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, 73 PCI_DMA_FROMDEVICE); 74 if (dma_mapping_error(priv->ddev, dma)) { 75 put_page(page); 76 return -ENOMEM; 77 } 78 page_alloc->page_size = PAGE_SIZE << order; 79 page_alloc->page = page; 80 page_alloc->dma = dma; 81 page_alloc->page_offset = 0; 82 /* Not doing get_page() for each frag is a big win 83 * on asymetric workloads. Note we can not use atomic_set(). 84 */ 85 atomic_add(page_alloc->page_size / frag_info->frag_stride - 1, 86 &page->_count); 87 return 0; 88 } 89 90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 91 struct mlx4_en_rx_desc *rx_desc, 92 struct mlx4_en_rx_alloc *frags, 93 struct mlx4_en_rx_alloc *ring_alloc, 94 gfp_t gfp) 95 { 96 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 97 const struct mlx4_en_frag_info *frag_info; 98 struct page *page; 99 dma_addr_t dma; 100 int i; 101 102 for (i = 0; i < priv->num_frags; i++) { 103 frag_info = &priv->frag_info[i]; 104 page_alloc[i] = ring_alloc[i]; 105 page_alloc[i].page_offset += frag_info->frag_stride; 106 107 if (page_alloc[i].page_offset + frag_info->frag_stride <= 108 ring_alloc[i].page_size) 109 continue; 110 111 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) 112 goto out; 113 } 114 115 for (i = 0; i < priv->num_frags; i++) { 116 frags[i] = ring_alloc[i]; 117 dma = ring_alloc[i].dma + ring_alloc[i].page_offset; 118 ring_alloc[i] = page_alloc[i]; 119 rx_desc->data[i].addr = cpu_to_be64(dma); 120 } 121 122 return 0; 123 124 out: 125 while (i--) { 126 if (page_alloc[i].page != ring_alloc[i].page) { 127 dma_unmap_page(priv->ddev, page_alloc[i].dma, 128 page_alloc[i].page_size, PCI_DMA_FROMDEVICE); 129 page = page_alloc[i].page; 130 atomic_set(&page->_count, 1); 131 put_page(page); 132 } 133 } 134 return -ENOMEM; 135 } 136 137 static void mlx4_en_free_frag(struct mlx4_en_priv *priv, 138 struct mlx4_en_rx_alloc *frags, 139 int i) 140 { 141 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 142 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; 143 144 145 if (next_frag_end > frags[i].page_size) 146 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, 147 PCI_DMA_FROMDEVICE); 148 149 if (frags[i].page) 150 put_page(frags[i].page); 151 } 152 153 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, 154 struct mlx4_en_rx_ring *ring) 155 { 156 int i; 157 struct mlx4_en_rx_alloc *page_alloc; 158 159 for (i = 0; i < priv->num_frags; i++) { 160 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 161 162 if (mlx4_alloc_pages(priv, &ring->page_alloc[i], 163 frag_info, GFP_KERNEL | __GFP_COLD)) 164 goto out; 165 166 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", 167 i, ring->page_alloc[i].page_size, 168 atomic_read(&ring->page_alloc[i].page->_count)); 169 } 170 return 0; 171 172 out: 173 while (i--) { 174 struct page *page; 175 176 page_alloc = &ring->page_alloc[i]; 177 dma_unmap_page(priv->ddev, page_alloc->dma, 178 page_alloc->page_size, PCI_DMA_FROMDEVICE); 179 page = page_alloc->page; 180 atomic_set(&page->_count, 1); 181 put_page(page); 182 page_alloc->page = NULL; 183 } 184 return -ENOMEM; 185 } 186 187 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, 188 struct mlx4_en_rx_ring *ring) 189 { 190 struct mlx4_en_rx_alloc *page_alloc; 191 int i; 192 193 for (i = 0; i < priv->num_frags; i++) { 194 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; 195 196 page_alloc = &ring->page_alloc[i]; 197 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", 198 i, page_count(page_alloc->page)); 199 200 dma_unmap_page(priv->ddev, page_alloc->dma, 201 page_alloc->page_size, PCI_DMA_FROMDEVICE); 202 while (page_alloc->page_offset + frag_info->frag_stride < 203 page_alloc->page_size) { 204 put_page(page_alloc->page); 205 page_alloc->page_offset += frag_info->frag_stride; 206 } 207 page_alloc->page = NULL; 208 } 209 } 210 211 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, 212 struct mlx4_en_rx_ring *ring, int index) 213 { 214 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 215 int possible_frags; 216 int i; 217 218 /* Set size and memtype fields */ 219 for (i = 0; i < priv->num_frags; i++) { 220 rx_desc->data[i].byte_count = 221 cpu_to_be32(priv->frag_info[i].frag_size); 222 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 223 } 224 225 /* If the number of used fragments does not fill up the ring stride, 226 * remaining (unused) fragments must be padded with null address/size 227 * and a special memory key */ 228 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 229 for (i = priv->num_frags; i < possible_frags; i++) { 230 rx_desc->data[i].byte_count = 0; 231 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 232 rx_desc->data[i].addr = 0; 233 } 234 } 235 236 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 237 struct mlx4_en_rx_ring *ring, int index, 238 gfp_t gfp) 239 { 240 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); 241 struct mlx4_en_rx_alloc *frags = ring->rx_info + 242 (index << priv->log_rx_info); 243 244 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); 245 } 246 247 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) 248 { 249 BUG_ON((u32)(ring->prod - ring->cons) > ring->actual_size); 250 return ring->prod == ring->cons; 251 } 252 253 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 254 { 255 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 256 } 257 258 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, 259 struct mlx4_en_rx_ring *ring, 260 int index) 261 { 262 struct mlx4_en_rx_alloc *frags; 263 int nr; 264 265 frags = ring->rx_info + (index << priv->log_rx_info); 266 for (nr = 0; nr < priv->num_frags; nr++) { 267 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 268 mlx4_en_free_frag(priv, frags, nr); 269 } 270 } 271 272 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 273 { 274 struct mlx4_en_rx_ring *ring; 275 int ring_ind; 276 int buf_ind; 277 int new_size; 278 279 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 280 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 281 ring = priv->rx_ring[ring_ind]; 282 283 if (mlx4_en_prepare_rx_desc(priv, ring, 284 ring->actual_size, 285 GFP_KERNEL | __GFP_COLD)) { 286 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 287 en_err(priv, "Failed to allocate enough rx buffers\n"); 288 return -ENOMEM; 289 } else { 290 new_size = rounddown_pow_of_two(ring->actual_size); 291 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 292 ring->actual_size, new_size); 293 goto reduce_rings; 294 } 295 } 296 ring->actual_size++; 297 ring->prod++; 298 } 299 } 300 return 0; 301 302 reduce_rings: 303 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 304 ring = priv->rx_ring[ring_ind]; 305 while (ring->actual_size > new_size) { 306 ring->actual_size--; 307 ring->prod--; 308 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 309 } 310 } 311 312 return 0; 313 } 314 315 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 316 struct mlx4_en_rx_ring *ring) 317 { 318 int index; 319 320 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 321 ring->cons, ring->prod); 322 323 /* Unmap and free Rx buffers */ 324 while (!mlx4_en_is_ring_empty(ring)) { 325 index = ring->cons & ring->size_mask; 326 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 327 mlx4_en_free_rx_desc(priv, ring, index); 328 ++ring->cons; 329 } 330 } 331 332 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 333 { 334 int i; 335 int num_of_eqs; 336 int num_rx_rings; 337 struct mlx4_dev *dev = mdev->dev; 338 339 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 340 if (!dev->caps.comp_pool) 341 num_of_eqs = max_t(int, MIN_RX_RINGS, 342 min_t(int, 343 dev->caps.num_comp_vectors, 344 DEF_RX_RINGS)); 345 else 346 num_of_eqs = min_t(int, MAX_MSIX_P_PORT, 347 dev->caps.comp_pool/ 348 dev->caps.num_ports) - 1; 349 350 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 351 min_t(int, num_of_eqs, 352 netif_get_num_default_rss_queues()); 353 mdev->profile.prof[i].rx_ring_num = 354 rounddown_pow_of_two(num_rx_rings); 355 } 356 } 357 358 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 359 struct mlx4_en_rx_ring **pring, 360 u32 size, u16 stride, int node) 361 { 362 struct mlx4_en_dev *mdev = priv->mdev; 363 struct mlx4_en_rx_ring *ring; 364 int err = -ENOMEM; 365 int tmp; 366 367 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 368 if (!ring) { 369 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 370 if (!ring) { 371 en_err(priv, "Failed to allocate RX ring structure\n"); 372 return -ENOMEM; 373 } 374 } 375 376 ring->prod = 0; 377 ring->cons = 0; 378 ring->size = size; 379 ring->size_mask = size - 1; 380 ring->stride = stride; 381 ring->log_stride = ffs(ring->stride) - 1; 382 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 383 384 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 385 sizeof(struct mlx4_en_rx_alloc)); 386 ring->rx_info = vmalloc_node(tmp, node); 387 if (!ring->rx_info) { 388 ring->rx_info = vmalloc(tmp); 389 if (!ring->rx_info) { 390 err = -ENOMEM; 391 goto err_ring; 392 } 393 } 394 395 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 396 ring->rx_info, tmp); 397 398 /* Allocate HW buffers on provided NUMA node */ 399 set_dev_node(&mdev->dev->persist->pdev->dev, node); 400 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 401 ring->buf_size, 2 * PAGE_SIZE); 402 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 403 if (err) 404 goto err_info; 405 406 err = mlx4_en_map_buffer(&ring->wqres.buf); 407 if (err) { 408 en_err(priv, "Failed to map RX buffer\n"); 409 goto err_hwq; 410 } 411 ring->buf = ring->wqres.buf.direct.buf; 412 413 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 414 415 *pring = ring; 416 return 0; 417 418 err_hwq: 419 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 420 err_info: 421 vfree(ring->rx_info); 422 ring->rx_info = NULL; 423 err_ring: 424 kfree(ring); 425 *pring = NULL; 426 427 return err; 428 } 429 430 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 431 { 432 struct mlx4_en_rx_ring *ring; 433 int i; 434 int ring_ind; 435 int err; 436 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 437 DS_SIZE * priv->num_frags); 438 439 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 440 ring = priv->rx_ring[ring_ind]; 441 442 ring->prod = 0; 443 ring->cons = 0; 444 ring->actual_size = 0; 445 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 446 447 ring->stride = stride; 448 if (ring->stride <= TXBB_SIZE) 449 ring->buf += TXBB_SIZE; 450 451 ring->log_stride = ffs(ring->stride) - 1; 452 ring->buf_size = ring->size * ring->stride; 453 454 memset(ring->buf, 0, ring->buf_size); 455 mlx4_en_update_rx_prod_db(ring); 456 457 /* Initialize all descriptors */ 458 for (i = 0; i < ring->size; i++) 459 mlx4_en_init_rx_desc(priv, ring, i); 460 461 /* Initialize page allocators */ 462 err = mlx4_en_init_allocator(priv, ring); 463 if (err) { 464 en_err(priv, "Failed initializing ring allocator\n"); 465 if (ring->stride <= TXBB_SIZE) 466 ring->buf -= TXBB_SIZE; 467 ring_ind--; 468 goto err_allocator; 469 } 470 } 471 err = mlx4_en_fill_rx_buffers(priv); 472 if (err) 473 goto err_buffers; 474 475 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 476 ring = priv->rx_ring[ring_ind]; 477 478 ring->size_mask = ring->actual_size - 1; 479 mlx4_en_update_rx_prod_db(ring); 480 } 481 482 return 0; 483 484 err_buffers: 485 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 486 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 487 488 ring_ind = priv->rx_ring_num - 1; 489 err_allocator: 490 while (ring_ind >= 0) { 491 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 492 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 493 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); 494 ring_ind--; 495 } 496 return err; 497 } 498 499 /* We recover from out of memory by scheduling our napi poll 500 * function (mlx4_en_process_cq), which tries to allocate 501 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 502 */ 503 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 504 { 505 int ring; 506 507 if (!priv->port_up) 508 return; 509 510 for (ring = 0; ring < priv->rx_ring_num; ring++) { 511 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) 512 napi_reschedule(&priv->rx_cq[ring]->napi); 513 } 514 } 515 516 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 517 struct mlx4_en_rx_ring **pring, 518 u32 size, u16 stride) 519 { 520 struct mlx4_en_dev *mdev = priv->mdev; 521 struct mlx4_en_rx_ring *ring = *pring; 522 523 mlx4_en_unmap_buffer(&ring->wqres.buf); 524 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 525 vfree(ring->rx_info); 526 ring->rx_info = NULL; 527 kfree(ring); 528 *pring = NULL; 529 #ifdef CONFIG_RFS_ACCEL 530 mlx4_en_cleanup_filters(priv); 531 #endif 532 } 533 534 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 535 struct mlx4_en_rx_ring *ring) 536 { 537 mlx4_en_free_rx_buf(priv, ring); 538 if (ring->stride <= TXBB_SIZE) 539 ring->buf -= TXBB_SIZE; 540 mlx4_en_destroy_allocator(priv, ring); 541 } 542 543 544 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 545 struct mlx4_en_rx_desc *rx_desc, 546 struct mlx4_en_rx_alloc *frags, 547 struct sk_buff *skb, 548 int length) 549 { 550 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; 551 struct mlx4_en_frag_info *frag_info; 552 int nr; 553 dma_addr_t dma; 554 555 /* Collect used fragments while replacing them in the HW descriptors */ 556 for (nr = 0; nr < priv->num_frags; nr++) { 557 frag_info = &priv->frag_info[nr]; 558 if (length <= frag_info->frag_prefix_size) 559 break; 560 if (!frags[nr].page) 561 goto fail; 562 563 dma = be64_to_cpu(rx_desc->data[nr].addr); 564 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, 565 DMA_FROM_DEVICE); 566 567 /* Save page reference in skb */ 568 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); 569 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); 570 skb_frags_rx[nr].page_offset = frags[nr].page_offset; 571 skb->truesize += frag_info->frag_stride; 572 frags[nr].page = NULL; 573 } 574 /* Adjust size of last fragment to match actual length */ 575 if (nr > 0) 576 skb_frag_size_set(&skb_frags_rx[nr - 1], 577 length - priv->frag_info[nr - 1].frag_prefix_size); 578 return nr; 579 580 fail: 581 while (nr > 0) { 582 nr--; 583 __skb_frag_unref(&skb_frags_rx[nr]); 584 } 585 return 0; 586 } 587 588 589 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, 590 struct mlx4_en_rx_desc *rx_desc, 591 struct mlx4_en_rx_alloc *frags, 592 unsigned int length) 593 { 594 struct sk_buff *skb; 595 void *va; 596 int used_frags; 597 dma_addr_t dma; 598 599 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); 600 if (!skb) { 601 en_dbg(RX_ERR, priv, "Failed allocating skb\n"); 602 return NULL; 603 } 604 skb_reserve(skb, NET_IP_ALIGN); 605 skb->len = length; 606 607 /* Get pointer to first fragment so we could copy the headers into the 608 * (linear part of the) skb */ 609 va = page_address(frags[0].page) + frags[0].page_offset; 610 611 if (length <= SMALL_PACKET_SIZE) { 612 /* We are copying all relevant data to the skb - temporarily 613 * sync buffers for the copy */ 614 dma = be64_to_cpu(rx_desc->data[0].addr); 615 dma_sync_single_for_cpu(priv->ddev, dma, length, 616 DMA_FROM_DEVICE); 617 skb_copy_to_linear_data(skb, va, length); 618 skb->tail += length; 619 } else { 620 unsigned int pull_len; 621 622 /* Move relevant fragments to skb */ 623 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, 624 skb, length); 625 if (unlikely(!used_frags)) { 626 kfree_skb(skb); 627 return NULL; 628 } 629 skb_shinfo(skb)->nr_frags = used_frags; 630 631 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); 632 /* Copy headers into the skb linear buffer */ 633 memcpy(skb->data, va, pull_len); 634 skb->tail += pull_len; 635 636 /* Skip headers in first fragment */ 637 skb_shinfo(skb)->frags[0].page_offset += pull_len; 638 639 /* Adjust size of first fragment */ 640 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); 641 skb->data_len = length - pull_len; 642 } 643 return skb; 644 } 645 646 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) 647 { 648 int i; 649 int offset = ETH_HLEN; 650 651 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { 652 if (*(skb->data + offset) != (unsigned char) (i & 0xff)) 653 goto out_loopback; 654 } 655 /* Loopback found */ 656 priv->loopback_ok = 1; 657 658 out_loopback: 659 dev_kfree_skb_any(skb); 660 } 661 662 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 663 struct mlx4_en_rx_ring *ring) 664 { 665 int index = ring->prod & ring->size_mask; 666 667 while ((u32) (ring->prod - ring->cons) < ring->actual_size) { 668 if (mlx4_en_prepare_rx_desc(priv, ring, index, 669 GFP_ATOMIC | __GFP_COLD)) 670 break; 671 ring->prod++; 672 index = ring->prod & ring->size_mask; 673 } 674 } 675 676 /* When hardware doesn't strip the vlan, we need to calculate the checksum 677 * over it and add it to the hardware's checksum calculation 678 */ 679 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 680 struct vlan_hdr *vlanh) 681 { 682 return csum_add(hw_checksum, *(__wsum *)vlanh); 683 } 684 685 /* Although the stack expects checksum which doesn't include the pseudo 686 * header, the HW adds it. To address that, we are subtracting the pseudo 687 * header checksum from the checksum value provided by the HW. 688 */ 689 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 690 struct iphdr *iph) 691 { 692 __u16 length_for_csum = 0; 693 __wsum csum_pseudo_header = 0; 694 695 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 696 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 697 length_for_csum, iph->protocol, 0); 698 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 699 } 700 701 #if IS_ENABLED(CONFIG_IPV6) 702 /* In IPv6 packets, besides subtracting the pseudo header checksum, 703 * we also compute/add the IP header checksum which 704 * is not added by the HW. 705 */ 706 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 707 struct ipv6hdr *ipv6h) 708 { 709 __wsum csum_pseudo_hdr = 0; 710 711 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) 712 return -1; 713 hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8)); 714 715 csum_pseudo_hdr = csum_partial(&ipv6h->saddr, 716 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); 717 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); 718 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); 719 720 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); 721 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); 722 return 0; 723 } 724 #endif 725 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 726 int hwtstamp_rx_filter) 727 { 728 __wsum hw_checksum = 0; 729 730 void *hdr = (u8 *)va + sizeof(struct ethhdr); 731 732 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 733 734 if (((struct ethhdr *)va)->h_proto == htons(ETH_P_8021Q) && 735 hwtstamp_rx_filter != HWTSTAMP_FILTER_NONE) { 736 /* next protocol non IPv4 or IPv6 */ 737 if (((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto 738 != htons(ETH_P_IP) && 739 ((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto 740 != htons(ETH_P_IPV6)) 741 return -1; 742 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 743 hdr += sizeof(struct vlan_hdr); 744 } 745 746 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) 747 get_fixed_ipv4_csum(hw_checksum, skb, hdr); 748 #if IS_ENABLED(CONFIG_IPV6) 749 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 750 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) 751 return -1; 752 #endif 753 return 0; 754 } 755 756 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 757 { 758 struct mlx4_en_priv *priv = netdev_priv(dev); 759 struct mlx4_en_dev *mdev = priv->mdev; 760 struct mlx4_cqe *cqe; 761 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; 762 struct mlx4_en_rx_alloc *frags; 763 struct mlx4_en_rx_desc *rx_desc; 764 struct sk_buff *skb; 765 int index; 766 int nr; 767 unsigned int length; 768 int polled = 0; 769 int ip_summed; 770 int factor = priv->cqe_factor; 771 u64 timestamp; 772 bool l2_tunnel; 773 774 if (!priv->port_up) 775 return 0; 776 777 if (budget <= 0) 778 return polled; 779 780 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 781 * descriptor offset can be deduced from the CQE index instead of 782 * reading 'cqe->index' */ 783 index = cq->mcq.cons_index & ring->size_mask; 784 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 785 786 /* Process all completed CQEs */ 787 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 788 cq->mcq.cons_index & cq->size)) { 789 790 frags = ring->rx_info + (index << priv->log_rx_info); 791 rx_desc = ring->buf + (index << ring->log_stride); 792 793 /* 794 * make sure we read the CQE after we read the ownership bit 795 */ 796 dma_rmb(); 797 798 /* Drop packet on bad receive or bad checksum */ 799 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 800 MLX4_CQE_OPCODE_ERROR)) { 801 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 802 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 803 ((struct mlx4_err_cqe *)cqe)->syndrome); 804 goto next; 805 } 806 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 807 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 808 goto next; 809 } 810 811 /* Check if we need to drop the packet if SRIOV is not enabled 812 * and not performing the selftest or flb disabled 813 */ 814 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 815 struct ethhdr *ethh; 816 dma_addr_t dma; 817 /* Get pointer to first fragment since we haven't 818 * skb yet and cast it to ethhdr struct 819 */ 820 dma = be64_to_cpu(rx_desc->data[0].addr); 821 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 822 DMA_FROM_DEVICE); 823 ethh = (struct ethhdr *)(page_address(frags[0].page) + 824 frags[0].page_offset); 825 826 if (is_multicast_ether_addr(ethh->h_dest)) { 827 struct mlx4_mac_entry *entry; 828 struct hlist_head *bucket; 829 unsigned int mac_hash; 830 831 /* Drop the packet, since HW loopback-ed it */ 832 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 833 bucket = &priv->mac_hash[mac_hash]; 834 rcu_read_lock(); 835 hlist_for_each_entry_rcu(entry, bucket, hlist) { 836 if (ether_addr_equal_64bits(entry->mac, 837 ethh->h_source)) { 838 rcu_read_unlock(); 839 goto next; 840 } 841 } 842 rcu_read_unlock(); 843 } 844 } 845 846 /* 847 * Packet is OK - process it. 848 */ 849 length = be32_to_cpu(cqe->byte_cnt); 850 length -= ring->fcs_del; 851 ring->bytes += length; 852 ring->packets++; 853 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 854 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 855 856 if (likely(dev->features & NETIF_F_RXCSUM)) { 857 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 858 MLX4_CQE_STATUS_UDP)) { 859 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 860 cqe->checksum == cpu_to_be16(0xffff)) { 861 ip_summed = CHECKSUM_UNNECESSARY; 862 ring->csum_ok++; 863 } else { 864 ip_summed = CHECKSUM_NONE; 865 ring->csum_none++; 866 } 867 } else { 868 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 869 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 870 MLX4_CQE_STATUS_IPV6))) { 871 ip_summed = CHECKSUM_COMPLETE; 872 ring->csum_complete++; 873 } else { 874 ip_summed = CHECKSUM_NONE; 875 ring->csum_none++; 876 } 877 } 878 } else { 879 ip_summed = CHECKSUM_NONE; 880 ring->csum_none++; 881 } 882 883 /* This packet is eligible for GRO if it is: 884 * - DIX Ethernet (type interpretation) 885 * - TCP/IP (v4) 886 * - without IP options 887 * - not an IP fragment 888 * - no LLS polling in progress 889 */ 890 if (!mlx4_en_cq_busy_polling(cq) && 891 (dev->features & NETIF_F_GRO)) { 892 struct sk_buff *gro_skb = napi_get_frags(&cq->napi); 893 if (!gro_skb) 894 goto next; 895 896 nr = mlx4_en_complete_rx_desc(priv, 897 rx_desc, frags, gro_skb, 898 length); 899 if (!nr) 900 goto next; 901 902 if (ip_summed == CHECKSUM_COMPLETE) { 903 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); 904 if (check_csum(cqe, gro_skb, va, ring->hwtstamp_rx_filter)) { 905 ip_summed = CHECKSUM_NONE; 906 ring->csum_none++; 907 ring->csum_complete--; 908 } 909 } 910 911 skb_shinfo(gro_skb)->nr_frags = nr; 912 gro_skb->len = length; 913 gro_skb->data_len = length; 914 gro_skb->ip_summed = ip_summed; 915 916 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) 917 gro_skb->csum_level = 1; 918 919 if ((cqe->vlan_my_qpn & 920 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && 921 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 922 u16 vid = be16_to_cpu(cqe->sl_vid); 923 924 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); 925 } 926 927 if (dev->features & NETIF_F_RXHASH) 928 skb_set_hash(gro_skb, 929 be32_to_cpu(cqe->immed_rss_invalid), 930 PKT_HASH_TYPE_L3); 931 932 skb_record_rx_queue(gro_skb, cq->ring); 933 skb_mark_napi_id(gro_skb, &cq->napi); 934 935 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 936 timestamp = mlx4_en_get_cqe_ts(cqe); 937 mlx4_en_fill_hwtstamps(mdev, 938 skb_hwtstamps(gro_skb), 939 timestamp); 940 } 941 942 napi_gro_frags(&cq->napi); 943 goto next; 944 } 945 946 /* GRO not possible, complete processing here */ 947 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); 948 if (!skb) { 949 priv->stats.rx_dropped++; 950 goto next; 951 } 952 953 if (unlikely(priv->validate_loopback)) { 954 validate_loopback(priv, skb); 955 goto next; 956 } 957 958 if (ip_summed == CHECKSUM_COMPLETE) { 959 if (check_csum(cqe, skb, skb->data, ring->hwtstamp_rx_filter)) { 960 ip_summed = CHECKSUM_NONE; 961 ring->csum_complete--; 962 ring->csum_none++; 963 } 964 } 965 966 skb->ip_summed = ip_summed; 967 skb->protocol = eth_type_trans(skb, dev); 968 skb_record_rx_queue(skb, cq->ring); 969 970 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) 971 skb->csum_level = 1; 972 973 if (dev->features & NETIF_F_RXHASH) 974 skb_set_hash(skb, 975 be32_to_cpu(cqe->immed_rss_invalid), 976 PKT_HASH_TYPE_L3); 977 978 if ((be32_to_cpu(cqe->vlan_my_qpn) & 979 MLX4_CQE_VLAN_PRESENT_MASK) && 980 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 981 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); 982 983 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { 984 timestamp = mlx4_en_get_cqe_ts(cqe); 985 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), 986 timestamp); 987 } 988 989 skb_mark_napi_id(skb, &cq->napi); 990 991 if (!mlx4_en_cq_busy_polling(cq)) 992 napi_gro_receive(&cq->napi, skb); 993 else 994 netif_receive_skb(skb); 995 996 next: 997 for (nr = 0; nr < priv->num_frags; nr++) 998 mlx4_en_free_frag(priv, frags, nr); 999 1000 ++cq->mcq.cons_index; 1001 index = (cq->mcq.cons_index) & ring->size_mask; 1002 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 1003 if (++polled == budget) 1004 goto out; 1005 } 1006 1007 out: 1008 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 1009 mlx4_cq_set_ci(&cq->mcq); 1010 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 1011 ring->cons = cq->mcq.cons_index; 1012 mlx4_en_refill_rx_buffers(priv, ring); 1013 mlx4_en_update_rx_prod_db(ring); 1014 return polled; 1015 } 1016 1017 1018 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 1019 { 1020 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 1021 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 1022 1023 if (likely(priv->port_up)) 1024 napi_schedule_irqoff(&cq->napi); 1025 else 1026 mlx4_en_arm_cq(priv, cq); 1027 } 1028 1029 /* Rx CQ polling - called by NAPI */ 1030 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 1031 { 1032 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 1033 struct net_device *dev = cq->dev; 1034 struct mlx4_en_priv *priv = netdev_priv(dev); 1035 int done; 1036 1037 if (!mlx4_en_cq_lock_napi(cq)) 1038 return budget; 1039 1040 done = mlx4_en_process_rx_cq(dev, cq, budget); 1041 1042 mlx4_en_cq_unlock_napi(cq); 1043 1044 /* If we used up all the quota - we're probably not done yet... */ 1045 if (done == budget) { 1046 int cpu_curr; 1047 const struct cpumask *aff; 1048 1049 INC_PERF_COUNTER(priv->pstats.napi_quota); 1050 1051 cpu_curr = smp_processor_id(); 1052 aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; 1053 1054 if (likely(cpumask_test_cpu(cpu_curr, aff))) 1055 return budget; 1056 1057 /* Current cpu is not according to smp_irq_affinity - 1058 * probably affinity changed. need to stop this NAPI 1059 * poll, and restart it on the right CPU 1060 */ 1061 done = 0; 1062 } 1063 /* Done for now */ 1064 napi_complete_done(napi, done); 1065 mlx4_en_arm_cq(priv, cq); 1066 return done; 1067 } 1068 1069 static const int frag_sizes[] = { 1070 FRAG_SZ0, 1071 FRAG_SZ1, 1072 FRAG_SZ2, 1073 FRAG_SZ3 1074 }; 1075 1076 void mlx4_en_calc_rx_buf(struct net_device *dev) 1077 { 1078 struct mlx4_en_priv *priv = netdev_priv(dev); 1079 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; 1080 int buf_size = 0; 1081 int i = 0; 1082 1083 while (buf_size < eff_mtu) { 1084 priv->frag_info[i].frag_size = 1085 (eff_mtu > buf_size + frag_sizes[i]) ? 1086 frag_sizes[i] : eff_mtu - buf_size; 1087 priv->frag_info[i].frag_prefix_size = buf_size; 1088 priv->frag_info[i].frag_stride = 1089 ALIGN(priv->frag_info[i].frag_size, 1090 SMP_CACHE_BYTES); 1091 buf_size += priv->frag_info[i].frag_size; 1092 i++; 1093 } 1094 1095 priv->num_frags = i; 1096 priv->rx_skb_size = eff_mtu; 1097 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 1098 1099 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 1100 eff_mtu, priv->num_frags); 1101 for (i = 0; i < priv->num_frags; i++) { 1102 en_err(priv, 1103 " frag:%d - size:%d prefix:%d stride:%d\n", 1104 i, 1105 priv->frag_info[i].frag_size, 1106 priv->frag_info[i].frag_prefix_size, 1107 priv->frag_info[i].frag_stride); 1108 } 1109 } 1110 1111 /* RSS related functions */ 1112 1113 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1114 struct mlx4_en_rx_ring *ring, 1115 enum mlx4_qp_state *state, 1116 struct mlx4_qp *qp) 1117 { 1118 struct mlx4_en_dev *mdev = priv->mdev; 1119 struct mlx4_qp_context *context; 1120 int err = 0; 1121 1122 context = kmalloc(sizeof(*context), GFP_KERNEL); 1123 if (!context) 1124 return -ENOMEM; 1125 1126 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); 1127 if (err) { 1128 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1129 goto out; 1130 } 1131 qp->event = mlx4_en_sqp_event; 1132 1133 memset(context, 0, sizeof *context); 1134 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1135 qpn, ring->cqn, -1, context); 1136 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1137 1138 /* Cancel FCS removal if FW allows */ 1139 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1140 context->param3 |= cpu_to_be32(1 << 29); 1141 if (priv->dev->features & NETIF_F_RXFCS) 1142 ring->fcs_del = 0; 1143 else 1144 ring->fcs_del = ETH_FCS_LEN; 1145 } else 1146 ring->fcs_del = 0; 1147 1148 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1149 if (err) { 1150 mlx4_qp_remove(mdev->dev, qp); 1151 mlx4_qp_free(mdev->dev, qp); 1152 } 1153 mlx4_en_update_rx_prod_db(ring); 1154 out: 1155 kfree(context); 1156 return err; 1157 } 1158 1159 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1160 { 1161 int err; 1162 u32 qpn; 1163 1164 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1165 MLX4_RESERVE_A0_QP); 1166 if (err) { 1167 en_err(priv, "Failed reserving drop qpn\n"); 1168 return err; 1169 } 1170 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); 1171 if (err) { 1172 en_err(priv, "Failed allocating drop qp\n"); 1173 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1174 return err; 1175 } 1176 1177 return 0; 1178 } 1179 1180 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1181 { 1182 u32 qpn; 1183 1184 qpn = priv->drop_qp.qpn; 1185 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1186 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1187 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1188 } 1189 1190 /* Allocate rx qp's and configure them according to rss map */ 1191 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1192 { 1193 struct mlx4_en_dev *mdev = priv->mdev; 1194 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1195 struct mlx4_qp_context context; 1196 struct mlx4_rss_context *rss_context; 1197 int rss_rings; 1198 void *ptr; 1199 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1200 MLX4_RSS_TCP_IPV6); 1201 int i, qpn; 1202 int err = 0; 1203 int good_qps = 0; 1204 1205 en_dbg(DRV, priv, "Configuring rss steering\n"); 1206 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1207 priv->rx_ring_num, 1208 &rss_map->base_qpn, 0); 1209 if (err) { 1210 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1211 return err; 1212 } 1213 1214 for (i = 0; i < priv->rx_ring_num; i++) { 1215 qpn = rss_map->base_qpn + i; 1216 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1217 &rss_map->state[i], 1218 &rss_map->qps[i]); 1219 if (err) 1220 goto rss_err; 1221 1222 ++good_qps; 1223 } 1224 1225 /* Configure RSS indirection qp */ 1226 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); 1227 if (err) { 1228 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1229 goto rss_err; 1230 } 1231 rss_map->indir_qp.event = mlx4_en_sqp_event; 1232 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1233 priv->rx_ring[0]->cqn, -1, &context); 1234 1235 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1236 rss_rings = priv->rx_ring_num; 1237 else 1238 rss_rings = priv->prof->rss_rings; 1239 1240 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1241 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1242 rss_context = ptr; 1243 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1244 (rss_map->base_qpn)); 1245 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1246 if (priv->mdev->profile.udp_rss) { 1247 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1248 rss_context->base_qpn_udp = rss_context->default_qpn; 1249 } 1250 1251 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1252 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1253 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1254 } 1255 1256 rss_context->flags = rss_mask; 1257 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1258 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1259 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1260 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1261 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1262 memcpy(rss_context->rss_key, priv->rss_key, 1263 MLX4_EN_RSS_KEY_SIZE); 1264 netdev_rss_key_fill(rss_context->rss_key, 1265 MLX4_EN_RSS_KEY_SIZE); 1266 } else { 1267 en_err(priv, "Unknown RSS hash function requested\n"); 1268 err = -EINVAL; 1269 goto indir_err; 1270 } 1271 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1272 &rss_map->indir_qp, &rss_map->indir_state); 1273 if (err) 1274 goto indir_err; 1275 1276 return 0; 1277 1278 indir_err: 1279 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1280 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1281 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1282 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1283 rss_err: 1284 for (i = 0; i < good_qps; i++) { 1285 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1286 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1287 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1288 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1289 } 1290 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1291 return err; 1292 } 1293 1294 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1295 { 1296 struct mlx4_en_dev *mdev = priv->mdev; 1297 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1298 int i; 1299 1300 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1301 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); 1302 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); 1303 mlx4_qp_free(mdev->dev, &rss_map->indir_qp); 1304 1305 for (i = 0; i < priv->rx_ring_num; i++) { 1306 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1307 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1308 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1309 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1310 } 1311 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1312 } 1313