1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/bpf.h> 36 #include <linux/bpf_trace.h> 37 #include <linux/mlx4/cq.h> 38 #include <linux/slab.h> 39 #include <linux/mlx4/qp.h> 40 #include <linux/skbuff.h> 41 #include <linux/rculist.h> 42 #include <linux/if_ether.h> 43 #include <linux/if_vlan.h> 44 #include <linux/vmalloc.h> 45 #include <linux/irq.h> 46 47 #if IS_ENABLED(CONFIG_IPV6) 48 #include <net/ip6_checksum.h> 49 #endif 50 51 #include "mlx4_en.h" 52 53 static int mlx4_alloc_page(struct mlx4_en_priv *priv, 54 struct mlx4_en_rx_alloc *frag, 55 gfp_t gfp) 56 { 57 struct page *page; 58 dma_addr_t dma; 59 60 page = alloc_page(gfp); 61 if (unlikely(!page)) 62 return -ENOMEM; 63 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir); 64 if (unlikely(dma_mapping_error(priv->ddev, dma))) { 65 __free_page(page); 66 return -ENOMEM; 67 } 68 frag->page = page; 69 frag->dma = dma; 70 frag->page_offset = priv->rx_headroom; 71 return 0; 72 } 73 74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 75 struct mlx4_en_rx_ring *ring, 76 struct mlx4_en_rx_desc *rx_desc, 77 struct mlx4_en_rx_alloc *frags, 78 gfp_t gfp) 79 { 80 int i; 81 82 for (i = 0; i < priv->num_frags; i++, frags++) { 83 if (!frags->page) { 84 if (mlx4_alloc_page(priv, frags, gfp)) 85 return -ENOMEM; 86 ring->rx_alloc_pages++; 87 } 88 rx_desc->data[i].addr = cpu_to_be64(frags->dma + 89 frags->page_offset); 90 } 91 return 0; 92 } 93 94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv, 95 struct mlx4_en_rx_alloc *frag) 96 { 97 if (frag->page) { 98 dma_unmap_page(priv->ddev, frag->dma, 99 PAGE_SIZE, priv->dma_dir); 100 __free_page(frag->page); 101 } 102 /* We need to clear all fields, otherwise a change of priv->log_rx_info 103 * could lead to see garbage later in frag->page. 104 */ 105 memset(frag, 0, sizeof(*frag)); 106 } 107 108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv, 109 struct mlx4_en_rx_ring *ring, int index) 110 { 111 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 112 int possible_frags; 113 int i; 114 115 /* Set size and memtype fields */ 116 for (i = 0; i < priv->num_frags; i++) { 117 rx_desc->data[i].byte_count = 118 cpu_to_be32(priv->frag_info[i].frag_size); 119 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 120 } 121 122 /* If the number of used fragments does not fill up the ring stride, 123 * remaining (unused) fragments must be padded with null address/size 124 * and a special memory key */ 125 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 126 for (i = priv->num_frags; i < possible_frags; i++) { 127 rx_desc->data[i].byte_count = 0; 128 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 129 rx_desc->data[i].addr = 0; 130 } 131 } 132 133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 134 struct mlx4_en_rx_ring *ring, int index, 135 gfp_t gfp) 136 { 137 struct mlx4_en_rx_desc *rx_desc = ring->buf + 138 (index << ring->log_stride); 139 struct mlx4_en_rx_alloc *frags = ring->rx_info + 140 (index << priv->log_rx_info); 141 if (likely(ring->page_cache.index > 0)) { 142 /* XDP uses a single page per frame */ 143 if (!frags->page) { 144 ring->page_cache.index--; 145 frags->page = ring->page_cache.buf[ring->page_cache.index].page; 146 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma; 147 } 148 frags->page_offset = XDP_PACKET_HEADROOM; 149 rx_desc->data[0].addr = cpu_to_be64(frags->dma + 150 XDP_PACKET_HEADROOM); 151 return 0; 152 } 153 154 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp); 155 } 156 157 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring) 158 { 159 return ring->prod == ring->cons; 160 } 161 162 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 163 { 164 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 165 } 166 167 /* slow path */ 168 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv, 169 struct mlx4_en_rx_ring *ring, 170 int index) 171 { 172 struct mlx4_en_rx_alloc *frags; 173 int nr; 174 175 frags = ring->rx_info + (index << priv->log_rx_info); 176 for (nr = 0; nr < priv->num_frags; nr++) { 177 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 178 mlx4_en_free_frag(priv, frags + nr); 179 } 180 } 181 182 /* Function not in fast-path */ 183 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 184 { 185 struct mlx4_en_rx_ring *ring; 186 int ring_ind; 187 int buf_ind; 188 int new_size; 189 190 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 191 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 192 ring = priv->rx_ring[ring_ind]; 193 194 if (mlx4_en_prepare_rx_desc(priv, ring, 195 ring->actual_size, 196 GFP_KERNEL | __GFP_COLD)) { 197 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 198 en_err(priv, "Failed to allocate enough rx buffers\n"); 199 return -ENOMEM; 200 } else { 201 new_size = rounddown_pow_of_two(ring->actual_size); 202 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 203 ring->actual_size, new_size); 204 goto reduce_rings; 205 } 206 } 207 ring->actual_size++; 208 ring->prod++; 209 } 210 } 211 return 0; 212 213 reduce_rings: 214 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 215 ring = priv->rx_ring[ring_ind]; 216 while (ring->actual_size > new_size) { 217 ring->actual_size--; 218 ring->prod--; 219 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 220 } 221 } 222 223 return 0; 224 } 225 226 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 227 struct mlx4_en_rx_ring *ring) 228 { 229 int index; 230 231 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 232 ring->cons, ring->prod); 233 234 /* Unmap and free Rx buffers */ 235 for (index = 0; index < ring->size; index++) { 236 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 237 mlx4_en_free_rx_desc(priv, ring, index); 238 } 239 ring->cons = 0; 240 ring->prod = 0; 241 } 242 243 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 244 { 245 int i; 246 int num_of_eqs; 247 int num_rx_rings; 248 struct mlx4_dev *dev = mdev->dev; 249 250 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 251 num_of_eqs = max_t(int, MIN_RX_RINGS, 252 min_t(int, 253 mlx4_get_eqs_per_port(mdev->dev, i), 254 DEF_RX_RINGS)); 255 256 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 257 min_t(int, num_of_eqs, 258 netif_get_num_default_rss_queues()); 259 mdev->profile.prof[i].rx_ring_num = 260 rounddown_pow_of_two(num_rx_rings); 261 } 262 } 263 264 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 265 struct mlx4_en_rx_ring **pring, 266 u32 size, u16 stride, int node) 267 { 268 struct mlx4_en_dev *mdev = priv->mdev; 269 struct mlx4_en_rx_ring *ring; 270 int err = -ENOMEM; 271 int tmp; 272 273 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 274 if (!ring) { 275 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 276 if (!ring) { 277 en_err(priv, "Failed to allocate RX ring structure\n"); 278 return -ENOMEM; 279 } 280 } 281 282 ring->prod = 0; 283 ring->cons = 0; 284 ring->size = size; 285 ring->size_mask = size - 1; 286 ring->stride = stride; 287 ring->log_stride = ffs(ring->stride) - 1; 288 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 289 290 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 291 sizeof(struct mlx4_en_rx_alloc)); 292 ring->rx_info = vzalloc_node(tmp, node); 293 if (!ring->rx_info) { 294 ring->rx_info = vzalloc(tmp); 295 if (!ring->rx_info) { 296 err = -ENOMEM; 297 goto err_ring; 298 } 299 } 300 301 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 302 ring->rx_info, tmp); 303 304 /* Allocate HW buffers on provided NUMA node */ 305 set_dev_node(&mdev->dev->persist->pdev->dev, node); 306 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 307 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 308 if (err) 309 goto err_info; 310 311 ring->buf = ring->wqres.buf.direct.buf; 312 313 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 314 315 *pring = ring; 316 return 0; 317 318 err_info: 319 vfree(ring->rx_info); 320 ring->rx_info = NULL; 321 err_ring: 322 kfree(ring); 323 *pring = NULL; 324 325 return err; 326 } 327 328 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 329 { 330 struct mlx4_en_rx_ring *ring; 331 int i; 332 int ring_ind; 333 int err; 334 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 335 DS_SIZE * priv->num_frags); 336 337 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 338 ring = priv->rx_ring[ring_ind]; 339 340 ring->prod = 0; 341 ring->cons = 0; 342 ring->actual_size = 0; 343 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 344 345 ring->stride = stride; 346 if (ring->stride <= TXBB_SIZE) { 347 /* Stamp first unused send wqe */ 348 __be32 *ptr = (__be32 *)ring->buf; 349 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); 350 *ptr = stamp; 351 /* Move pointer to start of rx section */ 352 ring->buf += TXBB_SIZE; 353 } 354 355 ring->log_stride = ffs(ring->stride) - 1; 356 ring->buf_size = ring->size * ring->stride; 357 358 memset(ring->buf, 0, ring->buf_size); 359 mlx4_en_update_rx_prod_db(ring); 360 361 /* Initialize all descriptors */ 362 for (i = 0; i < ring->size; i++) 363 mlx4_en_init_rx_desc(priv, ring, i); 364 } 365 err = mlx4_en_fill_rx_buffers(priv); 366 if (err) 367 goto err_buffers; 368 369 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 370 ring = priv->rx_ring[ring_ind]; 371 372 ring->size_mask = ring->actual_size - 1; 373 mlx4_en_update_rx_prod_db(ring); 374 } 375 376 return 0; 377 378 err_buffers: 379 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 380 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 381 382 ring_ind = priv->rx_ring_num - 1; 383 while (ring_ind >= 0) { 384 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 385 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 386 ring_ind--; 387 } 388 return err; 389 } 390 391 /* We recover from out of memory by scheduling our napi poll 392 * function (mlx4_en_process_cq), which tries to allocate 393 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 394 */ 395 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 396 { 397 int ring; 398 399 if (!priv->port_up) 400 return; 401 402 for (ring = 0; ring < priv->rx_ring_num; ring++) { 403 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) { 404 local_bh_disable(); 405 napi_reschedule(&priv->rx_cq[ring]->napi); 406 local_bh_enable(); 407 } 408 } 409 } 410 411 /* When the rx ring is running in page-per-packet mode, a released frame can go 412 * directly into a small cache, to avoid unmapping or touching the page 413 * allocator. In bpf prog performance scenarios, buffers are either forwarded 414 * or dropped, never converted to skbs, so every page can come directly from 415 * this cache when it is sized to be a multiple of the napi budget. 416 */ 417 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 418 struct mlx4_en_rx_alloc *frame) 419 { 420 struct mlx4_en_page_cache *cache = &ring->page_cache; 421 422 if (cache->index >= MLX4_EN_CACHE_SIZE) 423 return false; 424 425 cache->buf[cache->index].page = frame->page; 426 cache->buf[cache->index].dma = frame->dma; 427 cache->index++; 428 return true; 429 } 430 431 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 432 struct mlx4_en_rx_ring **pring, 433 u32 size, u16 stride) 434 { 435 struct mlx4_en_dev *mdev = priv->mdev; 436 struct mlx4_en_rx_ring *ring = *pring; 437 struct bpf_prog *old_prog; 438 439 old_prog = rcu_dereference_protected( 440 ring->xdp_prog, 441 lockdep_is_held(&mdev->state_lock)); 442 if (old_prog) 443 bpf_prog_put(old_prog); 444 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 445 vfree(ring->rx_info); 446 ring->rx_info = NULL; 447 kfree(ring); 448 *pring = NULL; 449 } 450 451 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 452 struct mlx4_en_rx_ring *ring) 453 { 454 int i; 455 456 for (i = 0; i < ring->page_cache.index; i++) { 457 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma, 458 PAGE_SIZE, priv->dma_dir); 459 put_page(ring->page_cache.buf[i].page); 460 } 461 ring->page_cache.index = 0; 462 mlx4_en_free_rx_buf(priv, ring); 463 if (ring->stride <= TXBB_SIZE) 464 ring->buf -= TXBB_SIZE; 465 } 466 467 468 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 469 struct mlx4_en_rx_alloc *frags, 470 struct sk_buff *skb, 471 int length) 472 { 473 const struct mlx4_en_frag_info *frag_info = priv->frag_info; 474 unsigned int truesize = 0; 475 int nr, frag_size; 476 struct page *page; 477 dma_addr_t dma; 478 bool release; 479 480 /* Collect used fragments while replacing them in the HW descriptors */ 481 for (nr = 0;; frags++) { 482 frag_size = min_t(int, length, frag_info->frag_size); 483 484 page = frags->page; 485 if (unlikely(!page)) 486 goto fail; 487 488 dma = frags->dma; 489 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset, 490 frag_size, priv->dma_dir); 491 492 __skb_fill_page_desc(skb, nr, page, frags->page_offset, 493 frag_size); 494 495 truesize += frag_info->frag_stride; 496 if (frag_info->frag_stride == PAGE_SIZE / 2) { 497 frags->page_offset ^= PAGE_SIZE / 2; 498 release = page_count(page) != 1 || 499 page_is_pfmemalloc(page) || 500 page_to_nid(page) != numa_mem_id(); 501 } else { 502 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES); 503 504 frags->page_offset += sz_align; 505 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE; 506 } 507 if (release) { 508 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir); 509 frags->page = NULL; 510 } else { 511 page_ref_inc(page); 512 } 513 514 nr++; 515 length -= frag_size; 516 if (!length) 517 break; 518 frag_info++; 519 } 520 skb->truesize += truesize; 521 return nr; 522 523 fail: 524 while (nr > 0) { 525 nr--; 526 __skb_frag_unref(skb_shinfo(skb)->frags + nr); 527 } 528 return 0; 529 } 530 531 static void validate_loopback(struct mlx4_en_priv *priv, void *va) 532 { 533 const unsigned char *data = va + ETH_HLEN; 534 int i; 535 536 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) { 537 if (data[i] != (unsigned char)i) 538 return; 539 } 540 /* Loopback found */ 541 priv->loopback_ok = 1; 542 } 543 544 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 545 struct mlx4_en_rx_ring *ring) 546 { 547 u32 missing = ring->actual_size - (ring->prod - ring->cons); 548 549 /* Try to batch allocations, but not too much. */ 550 if (missing < 8) 551 return; 552 do { 553 if (mlx4_en_prepare_rx_desc(priv, ring, 554 ring->prod & ring->size_mask, 555 GFP_ATOMIC | __GFP_COLD | 556 __GFP_MEMALLOC)) 557 break; 558 ring->prod++; 559 } while (likely(--missing)); 560 561 mlx4_en_update_rx_prod_db(ring); 562 } 563 564 /* When hardware doesn't strip the vlan, we need to calculate the checksum 565 * over it and add it to the hardware's checksum calculation 566 */ 567 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 568 struct vlan_hdr *vlanh) 569 { 570 return csum_add(hw_checksum, *(__wsum *)vlanh); 571 } 572 573 /* Although the stack expects checksum which doesn't include the pseudo 574 * header, the HW adds it. To address that, we are subtracting the pseudo 575 * header checksum from the checksum value provided by the HW. 576 */ 577 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 578 struct iphdr *iph) 579 { 580 __u16 length_for_csum = 0; 581 __wsum csum_pseudo_header = 0; 582 583 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 584 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 585 length_for_csum, iph->protocol, 0); 586 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 587 } 588 589 #if IS_ENABLED(CONFIG_IPV6) 590 /* In IPv6 packets, besides subtracting the pseudo header checksum, 591 * we also compute/add the IP header checksum which 592 * is not added by the HW. 593 */ 594 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 595 struct ipv6hdr *ipv6h) 596 { 597 __wsum csum_pseudo_hdr = 0; 598 599 if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT || 600 ipv6h->nexthdr == IPPROTO_HOPOPTS)) 601 return -1; 602 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); 603 604 csum_pseudo_hdr = csum_partial(&ipv6h->saddr, 605 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); 606 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); 607 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); 608 609 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); 610 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); 611 return 0; 612 } 613 #endif 614 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 615 netdev_features_t dev_features) 616 { 617 __wsum hw_checksum = 0; 618 619 void *hdr = (u8 *)va + sizeof(struct ethhdr); 620 621 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 622 623 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && 624 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { 625 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 626 hdr += sizeof(struct vlan_hdr); 627 } 628 629 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) 630 get_fixed_ipv4_csum(hw_checksum, skb, hdr); 631 #if IS_ENABLED(CONFIG_IPV6) 632 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 633 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr))) 634 return -1; 635 #endif 636 return 0; 637 } 638 639 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 640 { 641 struct mlx4_en_priv *priv = netdev_priv(dev); 642 int factor = priv->cqe_factor; 643 struct mlx4_en_rx_ring *ring; 644 struct bpf_prog *xdp_prog; 645 int cq_ring = cq->ring; 646 bool doorbell_pending; 647 struct mlx4_cqe *cqe; 648 int polled = 0; 649 int index; 650 651 if (unlikely(!priv->port_up)) 652 return 0; 653 654 if (unlikely(budget <= 0)) 655 return polled; 656 657 ring = priv->rx_ring[cq_ring]; 658 659 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */ 660 rcu_read_lock(); 661 xdp_prog = rcu_dereference(ring->xdp_prog); 662 doorbell_pending = 0; 663 664 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 665 * descriptor offset can be deduced from the CQE index instead of 666 * reading 'cqe->index' */ 667 index = cq->mcq.cons_index & ring->size_mask; 668 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 669 670 /* Process all completed CQEs */ 671 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 672 cq->mcq.cons_index & cq->size)) { 673 struct mlx4_en_rx_alloc *frags; 674 enum pkt_hash_types hash_type; 675 struct sk_buff *skb; 676 unsigned int length; 677 int ip_summed; 678 void *va; 679 int nr; 680 681 frags = ring->rx_info + (index << priv->log_rx_info); 682 va = page_address(frags[0].page) + frags[0].page_offset; 683 prefetchw(va); 684 /* 685 * make sure we read the CQE after we read the ownership bit 686 */ 687 dma_rmb(); 688 689 /* Drop packet on bad receive or bad checksum */ 690 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 691 MLX4_CQE_OPCODE_ERROR)) { 692 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 693 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 694 ((struct mlx4_err_cqe *)cqe)->syndrome); 695 goto next; 696 } 697 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 698 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 699 goto next; 700 } 701 702 /* Check if we need to drop the packet if SRIOV is not enabled 703 * and not performing the selftest or flb disabled 704 */ 705 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 706 const struct ethhdr *ethh = va; 707 dma_addr_t dma; 708 /* Get pointer to first fragment since we haven't 709 * skb yet and cast it to ethhdr struct 710 */ 711 dma = frags[0].dma + frags[0].page_offset; 712 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 713 DMA_FROM_DEVICE); 714 715 if (is_multicast_ether_addr(ethh->h_dest)) { 716 struct mlx4_mac_entry *entry; 717 struct hlist_head *bucket; 718 unsigned int mac_hash; 719 720 /* Drop the packet, since HW loopback-ed it */ 721 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 722 bucket = &priv->mac_hash[mac_hash]; 723 hlist_for_each_entry_rcu(entry, bucket, hlist) { 724 if (ether_addr_equal_64bits(entry->mac, 725 ethh->h_source)) 726 goto next; 727 } 728 } 729 } 730 731 if (unlikely(priv->validate_loopback)) { 732 validate_loopback(priv, va); 733 goto next; 734 } 735 736 /* 737 * Packet is OK - process it. 738 */ 739 length = be32_to_cpu(cqe->byte_cnt); 740 length -= ring->fcs_del; 741 742 /* A bpf program gets first chance to drop the packet. It may 743 * read bytes but not past the end of the frag. 744 */ 745 if (xdp_prog) { 746 struct xdp_buff xdp; 747 dma_addr_t dma; 748 void *orig_data; 749 u32 act; 750 751 dma = frags[0].dma + frags[0].page_offset; 752 dma_sync_single_for_cpu(priv->ddev, dma, 753 priv->frag_info[0].frag_size, 754 DMA_FROM_DEVICE); 755 756 xdp.data_hard_start = va - frags[0].page_offset; 757 xdp.data = va; 758 xdp.data_end = xdp.data + length; 759 orig_data = xdp.data; 760 761 act = bpf_prog_run_xdp(xdp_prog, &xdp); 762 763 if (xdp.data != orig_data) { 764 length = xdp.data_end - xdp.data; 765 frags[0].page_offset = xdp.data - 766 xdp.data_hard_start; 767 va = xdp.data; 768 } 769 770 switch (act) { 771 case XDP_PASS: 772 break; 773 case XDP_TX: 774 if (likely(!mlx4_en_xmit_frame(ring, frags, dev, 775 length, cq_ring, 776 &doorbell_pending))) { 777 frags[0].page = NULL; 778 goto next; 779 } 780 trace_xdp_exception(dev, xdp_prog, act); 781 goto xdp_drop_no_cnt; /* Drop on xmit failure */ 782 default: 783 bpf_warn_invalid_xdp_action(act); 784 case XDP_ABORTED: 785 trace_xdp_exception(dev, xdp_prog, act); 786 case XDP_DROP: 787 ring->xdp_drop++; 788 xdp_drop_no_cnt: 789 goto next; 790 } 791 } 792 793 ring->bytes += length; 794 ring->packets++; 795 796 skb = napi_get_frags(&cq->napi); 797 if (unlikely(!skb)) 798 goto next; 799 800 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) { 801 u64 timestamp = mlx4_en_get_cqe_ts(cqe); 802 803 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb), 804 timestamp); 805 } 806 skb_record_rx_queue(skb, cq_ring); 807 808 if (likely(dev->features & NETIF_F_RXCSUM)) { 809 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 810 MLX4_CQE_STATUS_UDP)) { 811 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 812 cqe->checksum == cpu_to_be16(0xffff)) { 813 bool l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 814 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 815 816 ip_summed = CHECKSUM_UNNECESSARY; 817 hash_type = PKT_HASH_TYPE_L4; 818 if (l2_tunnel) 819 skb->csum_level = 1; 820 ring->csum_ok++; 821 } else { 822 goto csum_none; 823 } 824 } else { 825 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 826 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 827 MLX4_CQE_STATUS_IPV6))) { 828 if (check_csum(cqe, skb, va, dev->features)) { 829 goto csum_none; 830 } else { 831 ip_summed = CHECKSUM_COMPLETE; 832 hash_type = PKT_HASH_TYPE_L3; 833 ring->csum_complete++; 834 } 835 } else { 836 goto csum_none; 837 } 838 } 839 } else { 840 csum_none: 841 ip_summed = CHECKSUM_NONE; 842 hash_type = PKT_HASH_TYPE_L3; 843 ring->csum_none++; 844 } 845 skb->ip_summed = ip_summed; 846 if (dev->features & NETIF_F_RXHASH) 847 skb_set_hash(skb, 848 be32_to_cpu(cqe->immed_rss_invalid), 849 hash_type); 850 851 if ((cqe->vlan_my_qpn & 852 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && 853 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 854 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 855 be16_to_cpu(cqe->sl_vid)); 856 else if ((cqe->vlan_my_qpn & 857 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) && 858 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) 859 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), 860 be16_to_cpu(cqe->sl_vid)); 861 862 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length); 863 if (likely(nr)) { 864 skb_shinfo(skb)->nr_frags = nr; 865 skb->len = length; 866 skb->data_len = length; 867 napi_gro_frags(&cq->napi); 868 } else { 869 skb->vlan_tci = 0; 870 skb_clear_hash(skb); 871 } 872 next: 873 ++cq->mcq.cons_index; 874 index = (cq->mcq.cons_index) & ring->size_mask; 875 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 876 if (unlikely(++polled == budget)) 877 break; 878 } 879 880 rcu_read_unlock(); 881 882 if (likely(polled)) { 883 if (doorbell_pending) { 884 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true; 885 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]); 886 } 887 888 mlx4_cq_set_ci(&cq->mcq); 889 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 890 ring->cons = cq->mcq.cons_index; 891 } 892 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 893 894 mlx4_en_refill_rx_buffers(priv, ring); 895 896 return polled; 897 } 898 899 900 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 901 { 902 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 903 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 904 905 if (likely(priv->port_up)) 906 napi_schedule_irqoff(&cq->napi); 907 else 908 mlx4_en_arm_cq(priv, cq); 909 } 910 911 /* Rx CQ polling - called by NAPI */ 912 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 913 { 914 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 915 struct net_device *dev = cq->dev; 916 struct mlx4_en_priv *priv = netdev_priv(dev); 917 struct mlx4_en_cq *xdp_tx_cq = NULL; 918 bool clean_complete = true; 919 int done; 920 921 if (priv->tx_ring_num[TX_XDP]) { 922 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring]; 923 if (xdp_tx_cq->xdp_busy) { 924 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq, 925 budget); 926 xdp_tx_cq->xdp_busy = !clean_complete; 927 } 928 } 929 930 done = mlx4_en_process_rx_cq(dev, cq, budget); 931 932 /* If we used up all the quota - we're probably not done yet... */ 933 if (done == budget || !clean_complete) { 934 const struct cpumask *aff; 935 struct irq_data *idata; 936 int cpu_curr; 937 938 /* in case we got here because of !clean_complete */ 939 done = budget; 940 941 INC_PERF_COUNTER(priv->pstats.napi_quota); 942 943 cpu_curr = smp_processor_id(); 944 idata = irq_desc_get_irq_data(cq->irq_desc); 945 aff = irq_data_get_affinity_mask(idata); 946 947 if (likely(cpumask_test_cpu(cpu_curr, aff))) 948 return budget; 949 950 /* Current cpu is not according to smp_irq_affinity - 951 * probably affinity changed. Need to stop this NAPI 952 * poll, and restart it on the right CPU. 953 * Try to avoid returning a too small value (like 0), 954 * to not fool net_rx_action() and its netdev_budget 955 */ 956 if (done) 957 done--; 958 } 959 /* Done for now */ 960 if (likely(napi_complete_done(napi, done))) 961 mlx4_en_arm_cq(priv, cq); 962 return done; 963 } 964 965 void mlx4_en_calc_rx_buf(struct net_device *dev) 966 { 967 struct mlx4_en_priv *priv = netdev_priv(dev); 968 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); 969 int i = 0; 970 971 /* bpf requires buffers to be set up as 1 packet per page. 972 * This only works when num_frags == 1. 973 */ 974 if (priv->tx_ring_num[TX_XDP]) { 975 priv->frag_info[0].frag_size = eff_mtu; 976 /* This will gain efficient xdp frame recycling at the 977 * expense of more costly truesize accounting 978 */ 979 priv->frag_info[0].frag_stride = PAGE_SIZE; 980 priv->dma_dir = PCI_DMA_BIDIRECTIONAL; 981 priv->rx_headroom = XDP_PACKET_HEADROOM; 982 i = 1; 983 } else { 984 int frag_size_max = 2048, buf_size = 0; 985 986 /* should not happen, right ? */ 987 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048) 988 frag_size_max = PAGE_SIZE; 989 990 while (buf_size < eff_mtu) { 991 int frag_stride, frag_size = eff_mtu - buf_size; 992 int pad, nb; 993 994 if (i < MLX4_EN_MAX_RX_FRAGS - 1) 995 frag_size = min(frag_size, frag_size_max); 996 997 priv->frag_info[i].frag_size = frag_size; 998 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES); 999 /* We can only pack 2 1536-bytes frames in on 4K page 1000 * Therefore, each frame would consume more bytes (truesize) 1001 */ 1002 nb = PAGE_SIZE / frag_stride; 1003 pad = (PAGE_SIZE - nb * frag_stride) / nb; 1004 pad &= ~(SMP_CACHE_BYTES - 1); 1005 priv->frag_info[i].frag_stride = frag_stride + pad; 1006 1007 buf_size += frag_size; 1008 i++; 1009 } 1010 priv->dma_dir = PCI_DMA_FROMDEVICE; 1011 priv->rx_headroom = 0; 1012 } 1013 1014 priv->num_frags = i; 1015 priv->rx_skb_size = eff_mtu; 1016 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 1017 1018 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 1019 eff_mtu, priv->num_frags); 1020 for (i = 0; i < priv->num_frags; i++) { 1021 en_dbg(DRV, 1022 priv, 1023 " frag:%d - size:%d stride:%d\n", 1024 i, 1025 priv->frag_info[i].frag_size, 1026 priv->frag_info[i].frag_stride); 1027 } 1028 } 1029 1030 /* RSS related functions */ 1031 1032 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1033 struct mlx4_en_rx_ring *ring, 1034 enum mlx4_qp_state *state, 1035 struct mlx4_qp *qp) 1036 { 1037 struct mlx4_en_dev *mdev = priv->mdev; 1038 struct mlx4_qp_context *context; 1039 int err = 0; 1040 1041 context = kmalloc(sizeof(*context), GFP_KERNEL); 1042 if (!context) 1043 return -ENOMEM; 1044 1045 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); 1046 if (err) { 1047 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1048 goto out; 1049 } 1050 qp->event = mlx4_en_sqp_event; 1051 1052 memset(context, 0, sizeof *context); 1053 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1054 qpn, ring->cqn, -1, context); 1055 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1056 1057 /* Cancel FCS removal if FW allows */ 1058 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1059 context->param3 |= cpu_to_be32(1 << 29); 1060 if (priv->dev->features & NETIF_F_RXFCS) 1061 ring->fcs_del = 0; 1062 else 1063 ring->fcs_del = ETH_FCS_LEN; 1064 } else 1065 ring->fcs_del = 0; 1066 1067 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1068 if (err) { 1069 mlx4_qp_remove(mdev->dev, qp); 1070 mlx4_qp_free(mdev->dev, qp); 1071 } 1072 mlx4_en_update_rx_prod_db(ring); 1073 out: 1074 kfree(context); 1075 return err; 1076 } 1077 1078 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1079 { 1080 int err; 1081 u32 qpn; 1082 1083 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1084 MLX4_RESERVE_A0_QP); 1085 if (err) { 1086 en_err(priv, "Failed reserving drop qpn\n"); 1087 return err; 1088 } 1089 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); 1090 if (err) { 1091 en_err(priv, "Failed allocating drop qp\n"); 1092 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1093 return err; 1094 } 1095 1096 return 0; 1097 } 1098 1099 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1100 { 1101 u32 qpn; 1102 1103 qpn = priv->drop_qp.qpn; 1104 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1105 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1106 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1107 } 1108 1109 /* Allocate rx qp's and configure them according to rss map */ 1110 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1111 { 1112 struct mlx4_en_dev *mdev = priv->mdev; 1113 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1114 struct mlx4_qp_context context; 1115 struct mlx4_rss_context *rss_context; 1116 int rss_rings; 1117 void *ptr; 1118 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1119 MLX4_RSS_TCP_IPV6); 1120 int i, qpn; 1121 int err = 0; 1122 int good_qps = 0; 1123 u8 flags; 1124 1125 en_dbg(DRV, priv, "Configuring rss steering\n"); 1126 1127 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0; 1128 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1129 priv->rx_ring_num, 1130 &rss_map->base_qpn, flags); 1131 if (err) { 1132 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1133 return err; 1134 } 1135 1136 for (i = 0; i < priv->rx_ring_num; i++) { 1137 qpn = rss_map->base_qpn + i; 1138 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1139 &rss_map->state[i], 1140 &rss_map->qps[i]); 1141 if (err) 1142 goto rss_err; 1143 1144 ++good_qps; 1145 } 1146 1147 if (priv->rx_ring_num == 1) { 1148 rss_map->indir_qp = &rss_map->qps[0]; 1149 priv->base_qpn = rss_map->indir_qp->qpn; 1150 en_info(priv, "Optimized Non-RSS steering\n"); 1151 return 0; 1152 } 1153 1154 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL); 1155 if (!rss_map->indir_qp) { 1156 err = -ENOMEM; 1157 goto rss_err; 1158 } 1159 1160 /* Configure RSS indirection qp */ 1161 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp, 1162 GFP_KERNEL); 1163 if (err) { 1164 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1165 goto rss_err; 1166 } 1167 1168 rss_map->indir_qp->event = mlx4_en_sqp_event; 1169 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1170 priv->rx_ring[0]->cqn, -1, &context); 1171 1172 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1173 rss_rings = priv->rx_ring_num; 1174 else 1175 rss_rings = priv->prof->rss_rings; 1176 1177 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1178 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1179 rss_context = ptr; 1180 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1181 (rss_map->base_qpn)); 1182 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1183 if (priv->mdev->profile.udp_rss) { 1184 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1185 rss_context->base_qpn_udp = rss_context->default_qpn; 1186 } 1187 1188 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1189 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1190 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1191 } 1192 1193 rss_context->flags = rss_mask; 1194 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1195 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1196 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1197 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1198 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1199 memcpy(rss_context->rss_key, priv->rss_key, 1200 MLX4_EN_RSS_KEY_SIZE); 1201 } else { 1202 en_err(priv, "Unknown RSS hash function requested\n"); 1203 err = -EINVAL; 1204 goto indir_err; 1205 } 1206 1207 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1208 rss_map->indir_qp, &rss_map->indir_state); 1209 if (err) 1210 goto indir_err; 1211 1212 return 0; 1213 1214 indir_err: 1215 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1216 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp); 1217 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1218 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1219 kfree(rss_map->indir_qp); 1220 rss_map->indir_qp = NULL; 1221 rss_err: 1222 for (i = 0; i < good_qps; i++) { 1223 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1224 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1225 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1226 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1227 } 1228 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1229 return err; 1230 } 1231 1232 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1233 { 1234 struct mlx4_en_dev *mdev = priv->mdev; 1235 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1236 int i; 1237 1238 if (priv->rx_ring_num > 1) { 1239 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1240 MLX4_QP_STATE_RST, NULL, 0, 0, 1241 rss_map->indir_qp); 1242 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1243 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1244 kfree(rss_map->indir_qp); 1245 rss_map->indir_qp = NULL; 1246 } 1247 1248 for (i = 0; i < priv->rx_ring_num; i++) { 1249 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1250 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1251 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1252 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1253 } 1254 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1255 } 1256