1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <net/busy_poll.h> 35 #include <linux/bpf.h> 36 #include <linux/bpf_trace.h> 37 #include <linux/mlx4/cq.h> 38 #include <linux/slab.h> 39 #include <linux/mlx4/qp.h> 40 #include <linux/skbuff.h> 41 #include <linux/rculist.h> 42 #include <linux/if_ether.h> 43 #include <linux/if_vlan.h> 44 #include <linux/vmalloc.h> 45 #include <linux/irq.h> 46 47 #if IS_ENABLED(CONFIG_IPV6) 48 #include <net/ip6_checksum.h> 49 #endif 50 51 #include "mlx4_en.h" 52 53 static int mlx4_alloc_page(struct mlx4_en_priv *priv, 54 struct mlx4_en_rx_alloc *frag, 55 gfp_t gfp) 56 { 57 struct page *page; 58 dma_addr_t dma; 59 60 page = alloc_page(gfp); 61 if (unlikely(!page)) 62 return -ENOMEM; 63 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir); 64 if (unlikely(dma_mapping_error(priv->ddev, dma))) { 65 __free_page(page); 66 return -ENOMEM; 67 } 68 frag->page = page; 69 frag->dma = dma; 70 frag->page_offset = priv->rx_headroom; 71 return 0; 72 } 73 74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 75 struct mlx4_en_rx_ring *ring, 76 struct mlx4_en_rx_desc *rx_desc, 77 struct mlx4_en_rx_alloc *frags, 78 gfp_t gfp) 79 { 80 int i; 81 82 for (i = 0; i < priv->num_frags; i++, frags++) { 83 if (!frags->page) { 84 if (mlx4_alloc_page(priv, frags, gfp)) 85 return -ENOMEM; 86 ring->rx_alloc_pages++; 87 } 88 rx_desc->data[i].addr = cpu_to_be64(frags->dma + 89 frags->page_offset); 90 } 91 return 0; 92 } 93 94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv, 95 struct mlx4_en_rx_alloc *frag) 96 { 97 if (frag->page) { 98 dma_unmap_page(priv->ddev, frag->dma, 99 PAGE_SIZE, priv->dma_dir); 100 __free_page(frag->page); 101 } 102 /* We need to clear all fields, otherwise a change of priv->log_rx_info 103 * could lead to see garbage later in frag->page. 104 */ 105 memset(frag, 0, sizeof(*frag)); 106 } 107 108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv, 109 struct mlx4_en_rx_ring *ring, int index) 110 { 111 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 112 int possible_frags; 113 int i; 114 115 /* Set size and memtype fields */ 116 for (i = 0; i < priv->num_frags; i++) { 117 rx_desc->data[i].byte_count = 118 cpu_to_be32(priv->frag_info[i].frag_size); 119 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 120 } 121 122 /* If the number of used fragments does not fill up the ring stride, 123 * remaining (unused) fragments must be padded with null address/size 124 * and a special memory key */ 125 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 126 for (i = priv->num_frags; i < possible_frags; i++) { 127 rx_desc->data[i].byte_count = 0; 128 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 129 rx_desc->data[i].addr = 0; 130 } 131 } 132 133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 134 struct mlx4_en_rx_ring *ring, int index, 135 gfp_t gfp) 136 { 137 struct mlx4_en_rx_desc *rx_desc = ring->buf + 138 (index << ring->log_stride); 139 struct mlx4_en_rx_alloc *frags = ring->rx_info + 140 (index << priv->log_rx_info); 141 if (likely(ring->page_cache.index > 0)) { 142 /* XDP uses a single page per frame */ 143 if (!frags->page) { 144 ring->page_cache.index--; 145 frags->page = ring->page_cache.buf[ring->page_cache.index].page; 146 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma; 147 } 148 frags->page_offset = XDP_PACKET_HEADROOM; 149 rx_desc->data[0].addr = cpu_to_be64(frags->dma + 150 XDP_PACKET_HEADROOM); 151 return 0; 152 } 153 154 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp); 155 } 156 157 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring) 158 { 159 return ring->prod == ring->cons; 160 } 161 162 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 163 { 164 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 165 } 166 167 /* slow path */ 168 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv, 169 struct mlx4_en_rx_ring *ring, 170 int index) 171 { 172 struct mlx4_en_rx_alloc *frags; 173 int nr; 174 175 frags = ring->rx_info + (index << priv->log_rx_info); 176 for (nr = 0; nr < priv->num_frags; nr++) { 177 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 178 mlx4_en_free_frag(priv, frags + nr); 179 } 180 } 181 182 /* Function not in fast-path */ 183 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 184 { 185 struct mlx4_en_rx_ring *ring; 186 int ring_ind; 187 int buf_ind; 188 int new_size; 189 190 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 191 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 192 ring = priv->rx_ring[ring_ind]; 193 194 if (mlx4_en_prepare_rx_desc(priv, ring, 195 ring->actual_size, 196 GFP_KERNEL)) { 197 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 198 en_err(priv, "Failed to allocate enough rx buffers\n"); 199 return -ENOMEM; 200 } else { 201 new_size = rounddown_pow_of_two(ring->actual_size); 202 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 203 ring->actual_size, new_size); 204 goto reduce_rings; 205 } 206 } 207 ring->actual_size++; 208 ring->prod++; 209 } 210 } 211 return 0; 212 213 reduce_rings: 214 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 215 ring = priv->rx_ring[ring_ind]; 216 while (ring->actual_size > new_size) { 217 ring->actual_size--; 218 ring->prod--; 219 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 220 } 221 } 222 223 return 0; 224 } 225 226 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 227 struct mlx4_en_rx_ring *ring) 228 { 229 int index; 230 231 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 232 ring->cons, ring->prod); 233 234 /* Unmap and free Rx buffers */ 235 for (index = 0; index < ring->size; index++) { 236 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 237 mlx4_en_free_rx_desc(priv, ring, index); 238 } 239 ring->cons = 0; 240 ring->prod = 0; 241 } 242 243 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 244 { 245 int i; 246 int num_of_eqs; 247 int num_rx_rings; 248 struct mlx4_dev *dev = mdev->dev; 249 250 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 251 num_of_eqs = max_t(int, MIN_RX_RINGS, 252 min_t(int, 253 mlx4_get_eqs_per_port(mdev->dev, i), 254 DEF_RX_RINGS)); 255 256 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 257 min_t(int, num_of_eqs, num_online_cpus()); 258 mdev->profile.prof[i].rx_ring_num = 259 rounddown_pow_of_two(num_rx_rings); 260 } 261 } 262 263 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 264 struct mlx4_en_rx_ring **pring, 265 u32 size, u16 stride, int node) 266 { 267 struct mlx4_en_dev *mdev = priv->mdev; 268 struct mlx4_en_rx_ring *ring; 269 int err = -ENOMEM; 270 int tmp; 271 272 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 273 if (!ring) { 274 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 275 if (!ring) { 276 en_err(priv, "Failed to allocate RX ring structure\n"); 277 return -ENOMEM; 278 } 279 } 280 281 ring->prod = 0; 282 ring->cons = 0; 283 ring->size = size; 284 ring->size_mask = size - 1; 285 ring->stride = stride; 286 ring->log_stride = ffs(ring->stride) - 1; 287 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 288 289 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 290 sizeof(struct mlx4_en_rx_alloc)); 291 ring->rx_info = vzalloc_node(tmp, node); 292 if (!ring->rx_info) { 293 ring->rx_info = vzalloc(tmp); 294 if (!ring->rx_info) { 295 err = -ENOMEM; 296 goto err_ring; 297 } 298 } 299 300 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 301 ring->rx_info, tmp); 302 303 /* Allocate HW buffers on provided NUMA node */ 304 set_dev_node(&mdev->dev->persist->pdev->dev, node); 305 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 306 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 307 if (err) 308 goto err_info; 309 310 ring->buf = ring->wqres.buf.direct.buf; 311 312 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 313 314 *pring = ring; 315 return 0; 316 317 err_info: 318 vfree(ring->rx_info); 319 ring->rx_info = NULL; 320 err_ring: 321 kfree(ring); 322 *pring = NULL; 323 324 return err; 325 } 326 327 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 328 { 329 struct mlx4_en_rx_ring *ring; 330 int i; 331 int ring_ind; 332 int err; 333 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 334 DS_SIZE * priv->num_frags); 335 336 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 337 ring = priv->rx_ring[ring_ind]; 338 339 ring->prod = 0; 340 ring->cons = 0; 341 ring->actual_size = 0; 342 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 343 344 ring->stride = stride; 345 if (ring->stride <= TXBB_SIZE) { 346 /* Stamp first unused send wqe */ 347 __be32 *ptr = (__be32 *)ring->buf; 348 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); 349 *ptr = stamp; 350 /* Move pointer to start of rx section */ 351 ring->buf += TXBB_SIZE; 352 } 353 354 ring->log_stride = ffs(ring->stride) - 1; 355 ring->buf_size = ring->size * ring->stride; 356 357 memset(ring->buf, 0, ring->buf_size); 358 mlx4_en_update_rx_prod_db(ring); 359 360 /* Initialize all descriptors */ 361 for (i = 0; i < ring->size; i++) 362 mlx4_en_init_rx_desc(priv, ring, i); 363 } 364 err = mlx4_en_fill_rx_buffers(priv); 365 if (err) 366 goto err_buffers; 367 368 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 369 ring = priv->rx_ring[ring_ind]; 370 371 ring->size_mask = ring->actual_size - 1; 372 mlx4_en_update_rx_prod_db(ring); 373 } 374 375 return 0; 376 377 err_buffers: 378 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 379 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 380 381 ring_ind = priv->rx_ring_num - 1; 382 while (ring_ind >= 0) { 383 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 384 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 385 ring_ind--; 386 } 387 return err; 388 } 389 390 /* We recover from out of memory by scheduling our napi poll 391 * function (mlx4_en_process_cq), which tries to allocate 392 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 393 */ 394 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 395 { 396 int ring; 397 398 if (!priv->port_up) 399 return; 400 401 for (ring = 0; ring < priv->rx_ring_num; ring++) { 402 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) { 403 local_bh_disable(); 404 napi_reschedule(&priv->rx_cq[ring]->napi); 405 local_bh_enable(); 406 } 407 } 408 } 409 410 /* When the rx ring is running in page-per-packet mode, a released frame can go 411 * directly into a small cache, to avoid unmapping or touching the page 412 * allocator. In bpf prog performance scenarios, buffers are either forwarded 413 * or dropped, never converted to skbs, so every page can come directly from 414 * this cache when it is sized to be a multiple of the napi budget. 415 */ 416 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 417 struct mlx4_en_rx_alloc *frame) 418 { 419 struct mlx4_en_page_cache *cache = &ring->page_cache; 420 421 if (cache->index >= MLX4_EN_CACHE_SIZE) 422 return false; 423 424 cache->buf[cache->index].page = frame->page; 425 cache->buf[cache->index].dma = frame->dma; 426 cache->index++; 427 return true; 428 } 429 430 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 431 struct mlx4_en_rx_ring **pring, 432 u32 size, u16 stride) 433 { 434 struct mlx4_en_dev *mdev = priv->mdev; 435 struct mlx4_en_rx_ring *ring = *pring; 436 struct bpf_prog *old_prog; 437 438 old_prog = rcu_dereference_protected( 439 ring->xdp_prog, 440 lockdep_is_held(&mdev->state_lock)); 441 if (old_prog) 442 bpf_prog_put(old_prog); 443 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 444 vfree(ring->rx_info); 445 ring->rx_info = NULL; 446 kfree(ring); 447 *pring = NULL; 448 } 449 450 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 451 struct mlx4_en_rx_ring *ring) 452 { 453 int i; 454 455 for (i = 0; i < ring->page_cache.index; i++) { 456 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma, 457 PAGE_SIZE, priv->dma_dir); 458 put_page(ring->page_cache.buf[i].page); 459 } 460 ring->page_cache.index = 0; 461 mlx4_en_free_rx_buf(priv, ring); 462 if (ring->stride <= TXBB_SIZE) 463 ring->buf -= TXBB_SIZE; 464 } 465 466 467 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 468 struct mlx4_en_rx_alloc *frags, 469 struct sk_buff *skb, 470 int length) 471 { 472 const struct mlx4_en_frag_info *frag_info = priv->frag_info; 473 unsigned int truesize = 0; 474 int nr, frag_size; 475 struct page *page; 476 dma_addr_t dma; 477 bool release; 478 479 /* Collect used fragments while replacing them in the HW descriptors */ 480 for (nr = 0;; frags++) { 481 frag_size = min_t(int, length, frag_info->frag_size); 482 483 page = frags->page; 484 if (unlikely(!page)) 485 goto fail; 486 487 dma = frags->dma; 488 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset, 489 frag_size, priv->dma_dir); 490 491 __skb_fill_page_desc(skb, nr, page, frags->page_offset, 492 frag_size); 493 494 truesize += frag_info->frag_stride; 495 if (frag_info->frag_stride == PAGE_SIZE / 2) { 496 frags->page_offset ^= PAGE_SIZE / 2; 497 release = page_count(page) != 1 || 498 page_is_pfmemalloc(page) || 499 page_to_nid(page) != numa_mem_id(); 500 } else { 501 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES); 502 503 frags->page_offset += sz_align; 504 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE; 505 } 506 if (release) { 507 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir); 508 frags->page = NULL; 509 } else { 510 page_ref_inc(page); 511 } 512 513 nr++; 514 length -= frag_size; 515 if (!length) 516 break; 517 frag_info++; 518 } 519 skb->truesize += truesize; 520 return nr; 521 522 fail: 523 while (nr > 0) { 524 nr--; 525 __skb_frag_unref(skb_shinfo(skb)->frags + nr); 526 } 527 return 0; 528 } 529 530 static void validate_loopback(struct mlx4_en_priv *priv, void *va) 531 { 532 const unsigned char *data = va + ETH_HLEN; 533 int i; 534 535 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) { 536 if (data[i] != (unsigned char)i) 537 return; 538 } 539 /* Loopback found */ 540 priv->loopback_ok = 1; 541 } 542 543 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 544 struct mlx4_en_rx_ring *ring) 545 { 546 u32 missing = ring->actual_size - (ring->prod - ring->cons); 547 548 /* Try to batch allocations, but not too much. */ 549 if (missing < 8) 550 return; 551 do { 552 if (mlx4_en_prepare_rx_desc(priv, ring, 553 ring->prod & ring->size_mask, 554 GFP_ATOMIC | __GFP_MEMALLOC)) 555 break; 556 ring->prod++; 557 } while (likely(--missing)); 558 559 mlx4_en_update_rx_prod_db(ring); 560 } 561 562 /* When hardware doesn't strip the vlan, we need to calculate the checksum 563 * over it and add it to the hardware's checksum calculation 564 */ 565 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 566 struct vlan_hdr *vlanh) 567 { 568 return csum_add(hw_checksum, *(__wsum *)vlanh); 569 } 570 571 /* Although the stack expects checksum which doesn't include the pseudo 572 * header, the HW adds it. To address that, we are subtracting the pseudo 573 * header checksum from the checksum value provided by the HW. 574 */ 575 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 576 struct iphdr *iph) 577 { 578 __u16 length_for_csum = 0; 579 __wsum csum_pseudo_header = 0; 580 __u8 ipproto = iph->protocol; 581 582 if (unlikely(ipproto == IPPROTO_SCTP)) 583 return -1; 584 585 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 586 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 587 length_for_csum, ipproto, 0); 588 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 589 return 0; 590 } 591 592 #if IS_ENABLED(CONFIG_IPV6) 593 /* In IPv6 packets, besides subtracting the pseudo header checksum, 594 * we also compute/add the IP header checksum which 595 * is not added by the HW. 596 */ 597 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 598 struct ipv6hdr *ipv6h) 599 { 600 __u8 nexthdr = ipv6h->nexthdr; 601 __wsum csum_pseudo_hdr = 0; 602 603 if (unlikely(nexthdr == IPPROTO_FRAGMENT || 604 nexthdr == IPPROTO_HOPOPTS || 605 nexthdr == IPPROTO_SCTP)) 606 return -1; 607 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(nexthdr)); 608 609 csum_pseudo_hdr = csum_partial(&ipv6h->saddr, 610 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); 611 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); 612 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, 613 (__force __wsum)htons(nexthdr)); 614 615 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); 616 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); 617 return 0; 618 } 619 #endif 620 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 621 netdev_features_t dev_features) 622 { 623 __wsum hw_checksum = 0; 624 625 void *hdr = (u8 *)va + sizeof(struct ethhdr); 626 627 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 628 629 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && 630 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { 631 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 632 hdr += sizeof(struct vlan_hdr); 633 } 634 635 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) 636 return get_fixed_ipv4_csum(hw_checksum, skb, hdr); 637 #if IS_ENABLED(CONFIG_IPV6) 638 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 639 return get_fixed_ipv6_csum(hw_checksum, skb, hdr); 640 #endif 641 return 0; 642 } 643 644 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 645 { 646 struct mlx4_en_priv *priv = netdev_priv(dev); 647 int factor = priv->cqe_factor; 648 struct mlx4_en_rx_ring *ring; 649 struct bpf_prog *xdp_prog; 650 int cq_ring = cq->ring; 651 bool doorbell_pending; 652 struct mlx4_cqe *cqe; 653 int polled = 0; 654 int index; 655 656 if (unlikely(!priv->port_up)) 657 return 0; 658 659 if (unlikely(budget <= 0)) 660 return polled; 661 662 ring = priv->rx_ring[cq_ring]; 663 664 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */ 665 rcu_read_lock(); 666 xdp_prog = rcu_dereference(ring->xdp_prog); 667 doorbell_pending = 0; 668 669 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 670 * descriptor offset can be deduced from the CQE index instead of 671 * reading 'cqe->index' */ 672 index = cq->mcq.cons_index & ring->size_mask; 673 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 674 675 /* Process all completed CQEs */ 676 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 677 cq->mcq.cons_index & cq->size)) { 678 struct mlx4_en_rx_alloc *frags; 679 enum pkt_hash_types hash_type; 680 struct sk_buff *skb; 681 unsigned int length; 682 int ip_summed; 683 void *va; 684 int nr; 685 686 frags = ring->rx_info + (index << priv->log_rx_info); 687 va = page_address(frags[0].page) + frags[0].page_offset; 688 prefetchw(va); 689 /* 690 * make sure we read the CQE after we read the ownership bit 691 */ 692 dma_rmb(); 693 694 /* Drop packet on bad receive or bad checksum */ 695 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 696 MLX4_CQE_OPCODE_ERROR)) { 697 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", 698 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 699 ((struct mlx4_err_cqe *)cqe)->syndrome); 700 goto next; 701 } 702 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 703 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 704 goto next; 705 } 706 707 /* Check if we need to drop the packet if SRIOV is not enabled 708 * and not performing the selftest or flb disabled 709 */ 710 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 711 const struct ethhdr *ethh = va; 712 dma_addr_t dma; 713 /* Get pointer to first fragment since we haven't 714 * skb yet and cast it to ethhdr struct 715 */ 716 dma = frags[0].dma + frags[0].page_offset; 717 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 718 DMA_FROM_DEVICE); 719 720 if (is_multicast_ether_addr(ethh->h_dest)) { 721 struct mlx4_mac_entry *entry; 722 struct hlist_head *bucket; 723 unsigned int mac_hash; 724 725 /* Drop the packet, since HW loopback-ed it */ 726 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 727 bucket = &priv->mac_hash[mac_hash]; 728 hlist_for_each_entry_rcu(entry, bucket, hlist) { 729 if (ether_addr_equal_64bits(entry->mac, 730 ethh->h_source)) 731 goto next; 732 } 733 } 734 } 735 736 if (unlikely(priv->validate_loopback)) { 737 validate_loopback(priv, va); 738 goto next; 739 } 740 741 /* 742 * Packet is OK - process it. 743 */ 744 length = be32_to_cpu(cqe->byte_cnt); 745 length -= ring->fcs_del; 746 747 /* A bpf program gets first chance to drop the packet. It may 748 * read bytes but not past the end of the frag. 749 */ 750 if (xdp_prog) { 751 struct xdp_buff xdp; 752 dma_addr_t dma; 753 void *orig_data; 754 u32 act; 755 756 dma = frags[0].dma + frags[0].page_offset; 757 dma_sync_single_for_cpu(priv->ddev, dma, 758 priv->frag_info[0].frag_size, 759 DMA_FROM_DEVICE); 760 761 xdp.data_hard_start = va - frags[0].page_offset; 762 xdp.data = va; 763 xdp_set_data_meta_invalid(&xdp); 764 xdp.data_end = xdp.data + length; 765 orig_data = xdp.data; 766 767 act = bpf_prog_run_xdp(xdp_prog, &xdp); 768 769 if (xdp.data != orig_data) { 770 length = xdp.data_end - xdp.data; 771 frags[0].page_offset = xdp.data - 772 xdp.data_hard_start; 773 va = xdp.data; 774 } 775 776 switch (act) { 777 case XDP_PASS: 778 break; 779 case XDP_TX: 780 if (likely(!mlx4_en_xmit_frame(ring, frags, priv, 781 length, cq_ring, 782 &doorbell_pending))) { 783 frags[0].page = NULL; 784 goto next; 785 } 786 trace_xdp_exception(dev, xdp_prog, act); 787 goto xdp_drop_no_cnt; /* Drop on xmit failure */ 788 default: 789 bpf_warn_invalid_xdp_action(act); 790 case XDP_ABORTED: 791 trace_xdp_exception(dev, xdp_prog, act); 792 case XDP_DROP: 793 ring->xdp_drop++; 794 xdp_drop_no_cnt: 795 goto next; 796 } 797 } 798 799 ring->bytes += length; 800 ring->packets++; 801 802 skb = napi_get_frags(&cq->napi); 803 if (unlikely(!skb)) 804 goto next; 805 806 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) { 807 u64 timestamp = mlx4_en_get_cqe_ts(cqe); 808 809 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb), 810 timestamp); 811 } 812 skb_record_rx_queue(skb, cq_ring); 813 814 if (likely(dev->features & NETIF_F_RXCSUM)) { 815 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 816 MLX4_CQE_STATUS_UDP)) { 817 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 818 cqe->checksum == cpu_to_be16(0xffff)) { 819 bool l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 820 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 821 822 ip_summed = CHECKSUM_UNNECESSARY; 823 hash_type = PKT_HASH_TYPE_L4; 824 if (l2_tunnel) 825 skb->csum_level = 1; 826 ring->csum_ok++; 827 } else { 828 goto csum_none; 829 } 830 } else { 831 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 832 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 833 MLX4_CQE_STATUS_IPV6))) { 834 if (check_csum(cqe, skb, va, dev->features)) { 835 goto csum_none; 836 } else { 837 ip_summed = CHECKSUM_COMPLETE; 838 hash_type = PKT_HASH_TYPE_L3; 839 ring->csum_complete++; 840 } 841 } else { 842 goto csum_none; 843 } 844 } 845 } else { 846 csum_none: 847 ip_summed = CHECKSUM_NONE; 848 hash_type = PKT_HASH_TYPE_L3; 849 ring->csum_none++; 850 } 851 skb->ip_summed = ip_summed; 852 if (dev->features & NETIF_F_RXHASH) 853 skb_set_hash(skb, 854 be32_to_cpu(cqe->immed_rss_invalid), 855 hash_type); 856 857 if ((cqe->vlan_my_qpn & 858 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && 859 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 860 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 861 be16_to_cpu(cqe->sl_vid)); 862 else if ((cqe->vlan_my_qpn & 863 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) && 864 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) 865 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), 866 be16_to_cpu(cqe->sl_vid)); 867 868 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length); 869 if (likely(nr)) { 870 skb_shinfo(skb)->nr_frags = nr; 871 skb->len = length; 872 skb->data_len = length; 873 napi_gro_frags(&cq->napi); 874 } else { 875 skb->vlan_tci = 0; 876 skb_clear_hash(skb); 877 } 878 next: 879 ++cq->mcq.cons_index; 880 index = (cq->mcq.cons_index) & ring->size_mask; 881 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 882 if (unlikely(++polled == budget)) 883 break; 884 } 885 886 rcu_read_unlock(); 887 888 if (likely(polled)) { 889 if (doorbell_pending) { 890 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true; 891 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]); 892 } 893 894 mlx4_cq_set_ci(&cq->mcq); 895 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 896 ring->cons = cq->mcq.cons_index; 897 } 898 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); 899 900 mlx4_en_refill_rx_buffers(priv, ring); 901 902 return polled; 903 } 904 905 906 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 907 { 908 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 909 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 910 911 if (likely(priv->port_up)) 912 napi_schedule_irqoff(&cq->napi); 913 else 914 mlx4_en_arm_cq(priv, cq); 915 } 916 917 /* Rx CQ polling - called by NAPI */ 918 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 919 { 920 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 921 struct net_device *dev = cq->dev; 922 struct mlx4_en_priv *priv = netdev_priv(dev); 923 struct mlx4_en_cq *xdp_tx_cq = NULL; 924 bool clean_complete = true; 925 int done; 926 927 if (priv->tx_ring_num[TX_XDP]) { 928 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring]; 929 if (xdp_tx_cq->xdp_busy) { 930 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq, 931 budget); 932 xdp_tx_cq->xdp_busy = !clean_complete; 933 } 934 } 935 936 done = mlx4_en_process_rx_cq(dev, cq, budget); 937 938 /* If we used up all the quota - we're probably not done yet... */ 939 if (done == budget || !clean_complete) { 940 const struct cpumask *aff; 941 struct irq_data *idata; 942 int cpu_curr; 943 944 /* in case we got here because of !clean_complete */ 945 done = budget; 946 947 INC_PERF_COUNTER(priv->pstats.napi_quota); 948 949 cpu_curr = smp_processor_id(); 950 idata = irq_desc_get_irq_data(cq->irq_desc); 951 aff = irq_data_get_affinity_mask(idata); 952 953 if (likely(cpumask_test_cpu(cpu_curr, aff))) 954 return budget; 955 956 /* Current cpu is not according to smp_irq_affinity - 957 * probably affinity changed. Need to stop this NAPI 958 * poll, and restart it on the right CPU. 959 * Try to avoid returning a too small value (like 0), 960 * to not fool net_rx_action() and its netdev_budget 961 */ 962 if (done) 963 done--; 964 } 965 /* Done for now */ 966 if (likely(napi_complete_done(napi, done))) 967 mlx4_en_arm_cq(priv, cq); 968 return done; 969 } 970 971 void mlx4_en_calc_rx_buf(struct net_device *dev) 972 { 973 struct mlx4_en_priv *priv = netdev_priv(dev); 974 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); 975 int i = 0; 976 977 /* bpf requires buffers to be set up as 1 packet per page. 978 * This only works when num_frags == 1. 979 */ 980 if (priv->tx_ring_num[TX_XDP]) { 981 priv->frag_info[0].frag_size = eff_mtu; 982 /* This will gain efficient xdp frame recycling at the 983 * expense of more costly truesize accounting 984 */ 985 priv->frag_info[0].frag_stride = PAGE_SIZE; 986 priv->dma_dir = PCI_DMA_BIDIRECTIONAL; 987 priv->rx_headroom = XDP_PACKET_HEADROOM; 988 i = 1; 989 } else { 990 int frag_size_max = 2048, buf_size = 0; 991 992 /* should not happen, right ? */ 993 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048) 994 frag_size_max = PAGE_SIZE; 995 996 while (buf_size < eff_mtu) { 997 int frag_stride, frag_size = eff_mtu - buf_size; 998 int pad, nb; 999 1000 if (i < MLX4_EN_MAX_RX_FRAGS - 1) 1001 frag_size = min(frag_size, frag_size_max); 1002 1003 priv->frag_info[i].frag_size = frag_size; 1004 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES); 1005 /* We can only pack 2 1536-bytes frames in on 4K page 1006 * Therefore, each frame would consume more bytes (truesize) 1007 */ 1008 nb = PAGE_SIZE / frag_stride; 1009 pad = (PAGE_SIZE - nb * frag_stride) / nb; 1010 pad &= ~(SMP_CACHE_BYTES - 1); 1011 priv->frag_info[i].frag_stride = frag_stride + pad; 1012 1013 buf_size += frag_size; 1014 i++; 1015 } 1016 priv->dma_dir = PCI_DMA_FROMDEVICE; 1017 priv->rx_headroom = 0; 1018 } 1019 1020 priv->num_frags = i; 1021 priv->rx_skb_size = eff_mtu; 1022 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 1023 1024 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 1025 eff_mtu, priv->num_frags); 1026 for (i = 0; i < priv->num_frags; i++) { 1027 en_dbg(DRV, 1028 priv, 1029 " frag:%d - size:%d stride:%d\n", 1030 i, 1031 priv->frag_info[i].frag_size, 1032 priv->frag_info[i].frag_stride); 1033 } 1034 } 1035 1036 /* RSS related functions */ 1037 1038 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1039 struct mlx4_en_rx_ring *ring, 1040 enum mlx4_qp_state *state, 1041 struct mlx4_qp *qp) 1042 { 1043 struct mlx4_en_dev *mdev = priv->mdev; 1044 struct mlx4_qp_context *context; 1045 int err = 0; 1046 1047 context = kmalloc(sizeof(*context), GFP_KERNEL); 1048 if (!context) 1049 return -ENOMEM; 1050 1051 err = mlx4_qp_alloc(mdev->dev, qpn, qp); 1052 if (err) { 1053 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1054 goto out; 1055 } 1056 qp->event = mlx4_en_sqp_event; 1057 1058 memset(context, 0, sizeof(*context)); 1059 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1060 qpn, ring->cqn, -1, context); 1061 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1062 1063 /* Cancel FCS removal if FW allows */ 1064 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1065 context->param3 |= cpu_to_be32(1 << 29); 1066 if (priv->dev->features & NETIF_F_RXFCS) 1067 ring->fcs_del = 0; 1068 else 1069 ring->fcs_del = ETH_FCS_LEN; 1070 } else 1071 ring->fcs_del = 0; 1072 1073 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1074 if (err) { 1075 mlx4_qp_remove(mdev->dev, qp); 1076 mlx4_qp_free(mdev->dev, qp); 1077 } 1078 mlx4_en_update_rx_prod_db(ring); 1079 out: 1080 kfree(context); 1081 return err; 1082 } 1083 1084 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1085 { 1086 int err; 1087 u32 qpn; 1088 1089 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1090 MLX4_RESERVE_A0_QP, 1091 MLX4_RES_USAGE_DRIVER); 1092 if (err) { 1093 en_err(priv, "Failed reserving drop qpn\n"); 1094 return err; 1095 } 1096 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); 1097 if (err) { 1098 en_err(priv, "Failed allocating drop qp\n"); 1099 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1100 return err; 1101 } 1102 1103 return 0; 1104 } 1105 1106 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1107 { 1108 u32 qpn; 1109 1110 qpn = priv->drop_qp.qpn; 1111 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1112 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1113 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1114 } 1115 1116 /* Allocate rx qp's and configure them according to rss map */ 1117 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1118 { 1119 struct mlx4_en_dev *mdev = priv->mdev; 1120 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1121 struct mlx4_qp_context context; 1122 struct mlx4_rss_context *rss_context; 1123 int rss_rings; 1124 void *ptr; 1125 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1126 MLX4_RSS_TCP_IPV6); 1127 int i, qpn; 1128 int err = 0; 1129 int good_qps = 0; 1130 u8 flags; 1131 1132 en_dbg(DRV, priv, "Configuring rss steering\n"); 1133 1134 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0; 1135 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1136 priv->rx_ring_num, 1137 &rss_map->base_qpn, flags, 1138 MLX4_RES_USAGE_DRIVER); 1139 if (err) { 1140 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1141 return err; 1142 } 1143 1144 for (i = 0; i < priv->rx_ring_num; i++) { 1145 qpn = rss_map->base_qpn + i; 1146 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1147 &rss_map->state[i], 1148 &rss_map->qps[i]); 1149 if (err) 1150 goto rss_err; 1151 1152 ++good_qps; 1153 } 1154 1155 if (priv->rx_ring_num == 1) { 1156 rss_map->indir_qp = &rss_map->qps[0]; 1157 priv->base_qpn = rss_map->indir_qp->qpn; 1158 en_info(priv, "Optimized Non-RSS steering\n"); 1159 return 0; 1160 } 1161 1162 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL); 1163 if (!rss_map->indir_qp) { 1164 err = -ENOMEM; 1165 goto rss_err; 1166 } 1167 1168 /* Configure RSS indirection qp */ 1169 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp); 1170 if (err) { 1171 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1172 goto rss_err; 1173 } 1174 1175 rss_map->indir_qp->event = mlx4_en_sqp_event; 1176 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1177 priv->rx_ring[0]->cqn, -1, &context); 1178 1179 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1180 rss_rings = priv->rx_ring_num; 1181 else 1182 rss_rings = priv->prof->rss_rings; 1183 1184 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1185 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1186 rss_context = ptr; 1187 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1188 (rss_map->base_qpn)); 1189 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1190 if (priv->mdev->profile.udp_rss) { 1191 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1192 rss_context->base_qpn_udp = rss_context->default_qpn; 1193 } 1194 1195 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1196 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1197 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1198 } 1199 1200 rss_context->flags = rss_mask; 1201 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1202 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1203 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1204 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1205 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1206 memcpy(rss_context->rss_key, priv->rss_key, 1207 MLX4_EN_RSS_KEY_SIZE); 1208 } else { 1209 en_err(priv, "Unknown RSS hash function requested\n"); 1210 err = -EINVAL; 1211 goto indir_err; 1212 } 1213 1214 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1215 rss_map->indir_qp, &rss_map->indir_state); 1216 if (err) 1217 goto indir_err; 1218 1219 return 0; 1220 1221 indir_err: 1222 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1223 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp); 1224 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1225 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1226 kfree(rss_map->indir_qp); 1227 rss_map->indir_qp = NULL; 1228 rss_err: 1229 for (i = 0; i < good_qps; i++) { 1230 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1231 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1232 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1233 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1234 } 1235 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1236 return err; 1237 } 1238 1239 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1240 { 1241 struct mlx4_en_dev *mdev = priv->mdev; 1242 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1243 int i; 1244 1245 if (priv->rx_ring_num > 1) { 1246 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1247 MLX4_QP_STATE_RST, NULL, 0, 0, 1248 rss_map->indir_qp); 1249 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1250 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1251 kfree(rss_map->indir_qp); 1252 rss_map->indir_qp = NULL; 1253 } 1254 1255 for (i = 0; i < priv->rx_ring_num; i++) { 1256 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1257 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1258 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1259 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1260 } 1261 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1262 } 1263