1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 35 #include <linux/if_vlan.h> 36 37 #include <linux/mlx4/device.h> 38 #include <linux/mlx4/cmd.h> 39 40 #include "en_port.h" 41 #include "mlx4_en.h" 42 43 44 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv) 45 { 46 struct mlx4_cmd_mailbox *mailbox; 47 struct mlx4_set_vlan_fltr_mbox *filter; 48 int i; 49 int j; 50 int index = 0; 51 u32 entry; 52 int err = 0; 53 54 mailbox = mlx4_alloc_cmd_mailbox(dev); 55 if (IS_ERR(mailbox)) 56 return PTR_ERR(mailbox); 57 58 filter = mailbox->buf; 59 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) { 60 entry = 0; 61 for (j = 0; j < 32; j++) 62 if (test_bit(index++, priv->active_vlans)) 63 entry |= 1 << j; 64 filter->entry[i] = cpu_to_be32(entry); 65 } 66 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR, 67 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); 68 mlx4_free_cmd_mailbox(dev, mailbox); 69 return err; 70 } 71 72 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port) 73 { 74 struct mlx4_en_query_port_context *qport_context; 75 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]); 76 struct mlx4_en_port_state *state = &priv->port_state; 77 struct mlx4_cmd_mailbox *mailbox; 78 int err; 79 80 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 81 if (IS_ERR(mailbox)) 82 return PTR_ERR(mailbox); 83 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 84 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 85 MLX4_CMD_WRAPPED); 86 if (err) 87 goto out; 88 qport_context = mailbox->buf; 89 90 /* This command is always accessed from Ethtool context 91 * already synchronized, no need in locking */ 92 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK); 93 switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) { 94 case MLX4_EN_100M_SPEED: 95 state->link_speed = SPEED_100; 96 break; 97 case MLX4_EN_1G_SPEED: 98 state->link_speed = SPEED_1000; 99 break; 100 case MLX4_EN_10G_SPEED_XAUI: 101 case MLX4_EN_10G_SPEED_XFI: 102 state->link_speed = SPEED_10000; 103 break; 104 case MLX4_EN_20G_SPEED: 105 state->link_speed = SPEED_20000; 106 break; 107 case MLX4_EN_40G_SPEED: 108 state->link_speed = SPEED_40000; 109 break; 110 case MLX4_EN_56G_SPEED: 111 state->link_speed = SPEED_56000; 112 break; 113 default: 114 state->link_speed = -1; 115 break; 116 } 117 118 state->transceiver = qport_context->transceiver; 119 120 state->flags = 0; /* Reset and recalculate the port flags */ 121 state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ? 122 MLX4_EN_PORT_ANC : 0; 123 state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ? 124 MLX4_EN_PORT_ANE : 0; 125 126 out: 127 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 128 return err; 129 } 130 131 /* Each counter set is located in struct mlx4_en_stat_out_mbox 132 * with a const offset between its prio components. 133 * This function runs over a counter set and sum all of it's prio components. 134 */ 135 static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num) 136 { 137 __be64 *curr = start; 138 unsigned long ret = 0; 139 int i; 140 int offset = next - start; 141 142 for (i = 0; i < num; i++) { 143 ret += be64_to_cpu(*curr); 144 curr += offset; 145 } 146 147 return ret; 148 } 149 150 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) 151 { 152 struct mlx4_counter tmp_counter_stats; 153 struct mlx4_en_stat_out_mbox *mlx4_en_stats; 154 struct mlx4_en_stat_out_flow_control_mbox *flowstats; 155 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]); 156 struct net_device_stats *stats = &priv->stats; 157 struct mlx4_cmd_mailbox *mailbox; 158 u64 in_mod = reset << 8 | port; 159 int err; 160 int i, counter_index; 161 unsigned long sw_rx_dropped = 0; 162 163 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 164 if (IS_ERR(mailbox)) 165 return PTR_ERR(mailbox); 166 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0, 167 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B, 168 MLX4_CMD_WRAPPED); 169 if (err) 170 goto out; 171 172 mlx4_en_stats = mailbox->buf; 173 174 spin_lock_bh(&priv->stats_lock); 175 176 stats->rx_packets = 0; 177 stats->rx_bytes = 0; 178 priv->port_stats.rx_chksum_good = 0; 179 priv->port_stats.rx_chksum_none = 0; 180 priv->port_stats.rx_chksum_complete = 0; 181 for (i = 0; i < priv->rx_ring_num; i++) { 182 stats->rx_packets += priv->rx_ring[i]->packets; 183 stats->rx_bytes += priv->rx_ring[i]->bytes; 184 sw_rx_dropped += priv->rx_ring[i]->dropped; 185 priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok; 186 priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none; 187 priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete; 188 } 189 stats->tx_packets = 0; 190 stats->tx_bytes = 0; 191 priv->port_stats.tx_chksum_offload = 0; 192 priv->port_stats.queue_stopped = 0; 193 priv->port_stats.wake_queue = 0; 194 priv->port_stats.tso_packets = 0; 195 priv->port_stats.xmit_more = 0; 196 197 for (i = 0; i < priv->tx_ring_num; i++) { 198 const struct mlx4_en_tx_ring *ring = priv->tx_ring[i]; 199 200 stats->tx_packets += ring->packets; 201 stats->tx_bytes += ring->bytes; 202 priv->port_stats.tx_chksum_offload += ring->tx_csum; 203 priv->port_stats.queue_stopped += ring->queue_stopped; 204 priv->port_stats.wake_queue += ring->wake_queue; 205 priv->port_stats.tso_packets += ring->tso_packets; 206 priv->port_stats.xmit_more += ring->xmit_more; 207 } 208 if (mlx4_is_master(mdev->dev)) { 209 stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0, 210 &mlx4_en_stats->RTOT_prio_1, 211 NUM_PRIORITIES); 212 stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0, 213 &mlx4_en_stats->TTOT_prio_1, 214 NUM_PRIORITIES); 215 stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0, 216 &mlx4_en_stats->ROCT_prio_1, 217 NUM_PRIORITIES); 218 stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0, 219 &mlx4_en_stats->TOCT_prio_1, 220 NUM_PRIORITIES); 221 } 222 223 /* net device stats */ 224 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) + 225 be32_to_cpu(mlx4_en_stats->RJBBR) + 226 be32_to_cpu(mlx4_en_stats->RCRC) + 227 be32_to_cpu(mlx4_en_stats->RRUNT) + 228 be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) + 229 be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) + 230 be32_to_cpu(mlx4_en_stats->RSHORT) + 231 en_stats_adder(&mlx4_en_stats->RGIANT_prio_0, 232 &mlx4_en_stats->RGIANT_prio_1, 233 NUM_PRIORITIES); 234 stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0, 235 &mlx4_en_stats->TGIANT_prio_1, 236 NUM_PRIORITIES); 237 stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0, 238 &mlx4_en_stats->MCAST_prio_1, 239 NUM_PRIORITIES); 240 stats->collisions = 0; 241 stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP) + 242 sw_rx_dropped; 243 stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength); 244 stats->rx_over_errors = 0; 245 stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC); 246 stats->rx_frame_errors = 0; 247 stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw); 248 stats->rx_missed_errors = 0; 249 stats->tx_aborted_errors = 0; 250 stats->tx_carrier_errors = 0; 251 stats->tx_fifo_errors = 0; 252 stats->tx_heartbeat_errors = 0; 253 stats->tx_window_errors = 0; 254 stats->tx_dropped = be32_to_cpu(mlx4_en_stats->TDROP); 255 256 /* RX stats */ 257 priv->pkstats.rx_multicast_packets = stats->multicast; 258 priv->pkstats.rx_broadcast_packets = 259 en_stats_adder(&mlx4_en_stats->RBCAST_prio_0, 260 &mlx4_en_stats->RBCAST_prio_1, 261 NUM_PRIORITIES); 262 priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR); 263 priv->pkstats.rx_in_range_length_error = 264 be64_to_cpu(mlx4_en_stats->RInRangeLengthErr); 265 priv->pkstats.rx_out_range_length_error = 266 be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr); 267 268 /* Tx stats */ 269 priv->pkstats.tx_multicast_packets = 270 en_stats_adder(&mlx4_en_stats->TMCAST_prio_0, 271 &mlx4_en_stats->TMCAST_prio_1, 272 NUM_PRIORITIES); 273 priv->pkstats.tx_broadcast_packets = 274 en_stats_adder(&mlx4_en_stats->TBCAST_prio_0, 275 &mlx4_en_stats->TBCAST_prio_1, 276 NUM_PRIORITIES); 277 278 priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0); 279 priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0); 280 priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1); 281 priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1); 282 priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2); 283 priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2); 284 priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3); 285 priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3); 286 priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4); 287 priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4); 288 priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5); 289 priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5); 290 priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6); 291 priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6); 292 priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7); 293 priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7); 294 priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan); 295 priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan); 296 priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0); 297 priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0); 298 priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1); 299 priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1); 300 priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2); 301 priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2); 302 priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3); 303 priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3); 304 priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4); 305 priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4); 306 priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5); 307 priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5); 308 priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6); 309 priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6); 310 priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7); 311 priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7); 312 priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan); 313 priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan); 314 315 spin_unlock_bh(&priv->stats_lock); 316 317 memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats)); 318 counter_index = mlx4_get_default_counter_index(mdev->dev, port); 319 err = mlx4_get_counter_stats(mdev->dev, counter_index, 320 &tmp_counter_stats, reset); 321 322 /* 0xffs indicates invalid value */ 323 memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES); 324 325 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) { 326 memset(mailbox->buf, 0, 327 sizeof(*flowstats) * MLX4_NUM_PRIORITIES); 328 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, 329 in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL, 330 0, MLX4_CMD_DUMP_ETH_STATS, 331 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); 332 if (err) 333 goto out; 334 } 335 336 flowstats = mailbox->buf; 337 338 spin_lock_bh(&priv->stats_lock); 339 340 if (tmp_counter_stats.counter_mode == 0) { 341 priv->pf_stats.rx_bytes = be64_to_cpu(tmp_counter_stats.rx_bytes); 342 priv->pf_stats.tx_bytes = be64_to_cpu(tmp_counter_stats.tx_bytes); 343 priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames); 344 priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames); 345 } 346 347 for (i = 0; i < MLX4_NUM_PRIORITIES; i++) { 348 priv->rx_priority_flowstats[i].rx_pause = 349 be64_to_cpu(flowstats[i].rx_pause); 350 priv->rx_priority_flowstats[i].rx_pause_duration = 351 be64_to_cpu(flowstats[i].rx_pause_duration); 352 priv->rx_priority_flowstats[i].rx_pause_transition = 353 be64_to_cpu(flowstats[i].rx_pause_transition); 354 priv->tx_priority_flowstats[i].tx_pause = 355 be64_to_cpu(flowstats[i].tx_pause); 356 priv->tx_priority_flowstats[i].tx_pause_duration = 357 be64_to_cpu(flowstats[i].tx_pause_duration); 358 priv->tx_priority_flowstats[i].tx_pause_transition = 359 be64_to_cpu(flowstats[i].tx_pause_transition); 360 } 361 362 /* if pfc is not in use, all priorities counters have the same value */ 363 priv->rx_flowstats.rx_pause = 364 be64_to_cpu(flowstats[0].rx_pause); 365 priv->rx_flowstats.rx_pause_duration = 366 be64_to_cpu(flowstats[0].rx_pause_duration); 367 priv->rx_flowstats.rx_pause_transition = 368 be64_to_cpu(flowstats[0].rx_pause_transition); 369 priv->tx_flowstats.tx_pause = 370 be64_to_cpu(flowstats[0].tx_pause); 371 priv->tx_flowstats.tx_pause_duration = 372 be64_to_cpu(flowstats[0].tx_pause_duration); 373 priv->tx_flowstats.tx_pause_transition = 374 be64_to_cpu(flowstats[0].tx_pause_transition); 375 376 spin_unlock_bh(&priv->stats_lock); 377 378 out: 379 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 380 return err; 381 } 382 383